JP2013131070A - Apparatus, method, and program for supporting circuit design - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a circuit design support apparatus capable of supporting designing of a low power consumption circuit whose jitter value remains within a tolerance range even if source voltage fluctuates due to power source noise.SOLUTION: A circuit design support apparatus includes; a condition setting section 11 which sets target paths of a designing object, a signal cycle, and a tolerable jitter value based on user inputs; a voltage computation section 12 for computing average power source voltage, which is a period-average of power source voltage supplied to the target paths, and a maximum and minimum thereof; a cell setting section 14 for sequentially setting cell arrangement information in a manner which reduces driving capability of the target paths; a wiring length computation section 15 for computing wiring length information corresponding to a case where the difference between a first delay of the target paths, when the maximum average power source voltage is supplied, and a second delay of the target paths, when the minimum average power source voltage is supplied is the smallest; a jitter value computation section 16 for sequentially computing jitter values for the target paths corresponding to the arrangement information in order of descending driving capability based on the average power source voltage; and a determination section 17 for determining whether or not the jitter values exceed the tolerable jitter value.

Description

  The present invention relates to a circuit design support apparatus, and more particularly to a circuit design that takes jitter and power consumption into consideration.

  Since jitter caused by power supply noise causes an actual machine failure such as an error in communication between chips, various methods for reducing jitter have been considered. FIG. 1 is a diagram showing various jitter reduction methods. As shown in FIG. 1, the jitter reduction methods can be roughly divided into four methods. There are (1) a method for strengthening power supply wiring and (2) a method for reducing current consumption as methods for reducing noise sources (measures on the attacker side). There are (3) a method of directly reducing jitter and (4) a method of reducing jitter by reducing the influence of power supply noise.

  The present invention relates to (4) a method of reducing jitter by reducing the influence of power supply noise, and particularly to reducing jitter based on a path configuration. The following documents are disclosed as techniques related to the path configuration. Non-Patent Document 1 discloses a technique for minimizing path delay. FIG. 2 is a diagram regarding path delay in Non-Patent Document 1. Referring to FIG. 2, the relationship between the number of repeater insertions and the path delay is shown. Non-Patent Document 1 discloses how many stages of cells (repeaters) are inserted at equal intervals to minimize path delay for the purpose of minimizing path delay.

  Patent Document 1 (Japanese Patent Application Laid-Open No. 2011-8410) discloses a circuit design support apparatus that can perform circuit design of a signal path that is highly resistant to fluctuations in parameter conditions such as manufacturing variations and environmental variations. Is disclosed. This circuit design support device uses a delay time of a plurality of parameters from a delay time of a signal path under a predetermined condition of a plurality of parameters for each wiring length that can be taken as a wiring connecting a front circuit and a rear circuit in a signal path. It is characterized by comprising a calculating means for calculating the degree of influence of fluctuation of individual conditions on the delay time, and a determining means for determining signal path arrangement information based on the calculated degree of influence.

  1 is a method for directly reducing jitter (3), and the following documents are disclosed as techniques relating to the jitter reduction circuit. Patent Document 2 (Japanese Patent Laid-Open No. 2010-191644) discloses a semiconductor design support program that can reduce clock jitter. The semiconductor design support program includes an adjustment target circuit specifying unit, a noise period specifying unit, a delay time specifying unit, and an adjustment time determining unit. The adjustment target circuit designating unit designates a clock distribution circuit to be adjusted. The noise period specifying means specifies a noise period of a noise source that has an influence of periodic noise on the clock distribution circuit. The delay time specifying means specifies the propagation delay time of the clock distribution circuit. The adjustment time determining means determines the adjustment time so that the adjusted propagation delay time obtained by adding the adjustment time to the propagation delay time is a natural number multiple of the noise period. According to such a semiconductor design support program, it is said that a semiconductor device in which the jitter amount of the clock signal is reduced can be easily designed.

  Patent Document 3 (Japanese Patent Laid-Open No. 2010-39631) discloses an LSI design method in which logic cells are arranged in consideration of power supply voltage fluctuation due to power supply noise. This LSI design method obtains a voltage waveform at a plurality of points on a power supply line, obtains a minimum voltage from the voltage waveform, and expresses a spatial correlation of the minimum voltage with respect to a distance between two points among the plurality of points on the power supply line. The first correlation coefficient is obtained, and the arrangement of the plurality of logic cells is determined based on the first correlation coefficient.

  Japanese Patent Application Laid-Open No. 2008-227624 discloses a method for reducing the influence of power supply noise. This method of reducing the influence of power supply noise reduces the influence of power supply noise riding on the first signal propagating through the first signal line of the electronic circuit on the second signal propagating through the second signal line. A method of measuring noise of a specific frequency component in power supply noise that affects the second signal, and measuring the noise of the first or second signal according to the frequency of occurrence of noise of the measured specific frequency component. It is characterized by controlling the components. As a result, the influence of power supply noise generated in the second signal can be reduced.

  Japanese Patent Laid-Open No. 2007-193658 discloses a semiconductor device having a function of adjusting a clock delay value. The semiconductor device includes a clock distribution unit that distributes a clock output from an oscillation source to an internal circuit of the semiconductor device, a clock supply unit that supplies a clock to an external circuit, a clock that is supplied to the external circuit, and a clock distribution unit A phase difference detecting means for detecting a phase difference from the clock at the end of the clock, and a clock delay adjusting means for adjusting a delay of the clock output from the clock supply means based on the phase difference data detected by the phase difference detecting means; It is characterized by including. Such a semiconductor device can supply a stable clock signal because it does not affect the clock output to the outside even if the power supply fluctuates due to the operation of the internal block.

JP 2011-8410 A JP 2010-191644 A JP 2010-39631 A JP 2008-227624 A JP 2007-193658 A

G. Chen and E.M. G. Friedman, “Low-Power Repeaters Driving RC and RLC Interconnects With Delay and Bandwidth Constants,” IEEE Trans. VLSI SYSTEMS, VOL. 14, NO. 2, FEBRUARY 2006.

  In the method described in Non-Patent Document 1, since a repeater is inserted to minimize the path delay (cell delay + wiring delay), the ratio of the cell delay in the path delay increases. Although the wiring delay hardly changes even when the voltage changes, the cell delay tends to change based on the voltage change. Therefore, even if the path delay is minimized by inserting a repeater as in Non-Patent Document 1, it is likely to be affected by voltage fluctuation, and as a result, path delay fluctuation (jitter value) due to power supply noise becomes large. There is.

  In the following, means for solving the problems will be described using the reference numerals used in the embodiments for carrying out the invention in parentheses. This symbol is added to clarify the correspondence between the description of the claims and the description of the mode for carrying out the invention, and the technical scope of the invention described in the claims. Must not be used to interpret

A circuit design support device (1) according to the present invention includes a condition setting unit (23) that sets a target path (23) that is a design target for signal propagation, a signal cycle, and an allowable jitter value of a signal based on user input. 11), the average power supply voltage (VA _k ) _obtained by averaging the power supply voltage (V) supplied to the target path (23) every period (T), and the maximum value (VA _max ) of the average power supply voltage (VA _k ) ) And a minimum value (VA _min ), and the number of logical stages (n) of each of a plurality of cell types (CELL _i ) having different driving capabilities arranged as elements of the target path (23). _i ) is defined by arrangement information in the order of the cell setting unit (14) that sets the arrangement information in order so that the driving capability of the target path (23) decreases and the arrangement information having the highest driving capability. For the target path (23) _{(VA max)} and the first delay of the target path (23) when it is supplied, when the difference between the second delay target path (23) is minimized when the minimum value _{(VA min)} is supplied Of the plurality of cell types (CELL _i ), the wiring length calculation unit (15) that calculates the wiring information that is the combination of the optimal wiring length (l _i ) at the subsequent stage, and the arrangement information in the order of arrangement information with high driving capability A jitter value calculation unit (16) for calculating a jitter value (J) based on an average power supply voltage (VA) for a target path (23) defined by the information and the wiring information, and arrangement information having a high driving capability And a determination unit (17) for determining whether or not the jitter value (J) exceeds the allowable jitter value. When the first jitter value (J) of the target path (23) defined by the first arrangement information and the first wiring information exceeds the allowable jitter value, the determination unit (17) The second arrangement information and the second wiring information calculated before the one wiring information are determined as elements of the target path (23).

The circuit design support method of the present invention includes a step of setting a target path (23) that is a design target for signal propagation, a signal period (T), and an allowable jitter value of the signal based on user input, The average power supply voltage (VA _k ) _obtained by averaging the power supply voltage (V) supplied to the path (23) every period (T), and the maximum value (VA _max ) and the minimum value of the average power supply voltage (VA _k ) ( VA _min ) and arrangement information that is a combination of the number of logical stages (n _i ) of each of a plurality of cell types (CELL _i ) having different driving capabilities arranged as elements of the target path (23). And determining an element of the target path (23) in which the delay variation of the target path (23) is small even if the power supply voltage (V) varies.
In the step of determining the element of the target path (23), the maximum value (VA _max ) is supplied to the step of setting the first arrangement information and the target path (23) defined by the first arrangement information. Included in the first arrangement information when the difference between the first delay of the target path (23) at the time and the second delay of the target path (23) when the minimum value (VA _min ) is supplied is minimum A step of calculating first wiring information that is a combination of the optimum wiring length (l _i ) at the subsequent stage of each of the plurality of cell types (CELL _i ), and an object defined by the first arrangement information and the first wiring information A step of calculating a first jitter value (J) for the path (23) based on the average power supply voltage (VA _k ), and a step of determining that the first jitter value (J) is less than or equal to an allowable jitter value. And a second arrangement having a lower driving capability than the first arrangement information A step of setting information, a third delay of the target path (23) when the maximum value (VA _max ) is supplied to the target path (23) defined by the second arrangement information, and a minimum value ( VA _min ) when the difference from the fourth delay of the target path (23) is minimized, the optimal wiring in the subsequent stage of each of the plurality of cell types (CELL _i ) included in the second arrangement information The average power supply voltage (VA _k ) is calculated for the target path (23) defined by the step of calculating the second wiring information that is a combination of the length (l _i ) and the second arrangement information and the second wiring information. A step of calculating a second jitter value (J) based on the step, a step of determining whether or not the second jitter value (J) exceeds the allowable jitter value, and the second jitter value (J) exceeds the allowable jitter value. If the first path information and the first wiring information are the target path (2 The step of determining as an element of 3) is provided.

  The circuit design support device of the present invention can support the design of a low power consumption circuit in which the jitter value is within an allowable range even when the voltage fluctuates due to power supply noise.

FIG. 1 is a diagram showing various jitter reduction methods. FIG. 2 is a diagram regarding path delay in Non-Patent Document 1. FIG. 3A is a diagram illustrating a design flow of a semiconductor device. FIG. 3B is an outline of the circuit design support apparatus 1 of the present invention. FIG. 4 is a block diagram showing a configuration example of the circuit design support apparatus 1 of the present invention. FIG. 5 is an example of a library stored in the library unit 10. FIG. 6 illustrates the stage delay function of equation (1). FIG. 7 is a diagram illustrating the relationship between stage delay and path delay. FIG. 8 is a diagram illustrating the target path 23 for reducing the jitter value set by the condition setting unit 11. FIG. 9 is a diagram illustrating a clock signal. FIG. 10 is a diagram illustrating jitter of a clock signal. FIG. 11 is a diagram showing voltage waveform information. FIG. 12 is a diagram illustrating a process in which the cell setting unit 14 changes the combination of the number of logical stages n _i of each cell type CELL _i . FIG. 13 is a diagram showing the target path 23 corresponding to FIG. FIG. 14 is a diagram showing all combinations of the wiring length l ₁ that can be taken by CELL ₁ and the wiring length l ₂ that can be taken by CELL ₂ as executable regions, calculated by linear programming. FIG. 15 is a conceptual diagram showing that the difference between the path delay at the maximum value VA _max and the path delay at the minimum value VA _min is minimized. FIG. 16 is a diagram illustrating a target path 23 that is a calculation target of a periodic jitter value. FIG. 17 is a diagram illustrating calculation of the jitter value J based on the input clock signal and the output clock signal. FIG. 18 is a diagram illustrating the relationship between the number of determinations by the determination unit 17 and the jitter value J to be determined. FIG. 19 is a block diagram illustrating a hardware configuration example in the embodiment of the circuit design support device 1. FIG. 20 is a flowchart showing the processing operation according to the first embodiment of the circuit design support apparatus 1 of the present invention. FIG. 21 is a block diagram showing a configuration example of a circuit design support apparatus 1a according to the second embodiment of the present invention. FIG. 22A is a diagram showing that there is no executable region that satisfies all the conditions including the clock latency tolerance value. FIG. 22B is a diagram showing a case where there is an executable area. FIG. 22C is a diagram showing a case where there is an executable area. FIG. 23 is a flowchart showing the processing operation of the circuit design support apparatus 1a according to the second embodiment of the present invention.

  Hereinafter, a circuit design support apparatus according to an embodiment of the present invention will be described with reference to the accompanying drawings.

(First embodiment)
A first embodiment of the present invention will be described. First, application points of the circuit design support apparatus of the present invention will be described with reference to FIGS. 3A and 3B. For example, when designing a desired system as a semiconductor integrated circuit, as shown in FIG. 3A, the system design is generally implemented, and circuit information (functional information) described in RTL (Register Transfer Level) is generated as the output. (Step S101). Functional / logic design is performed based on the circuit information described in the RTL, and a gate-level logic circuit, that is, a net list is generated (step S102). Then, based on the net list, a layout is designed by arranging and wiring a macro and other elements (functional blocks, etc.) (steps S103, S104, and S105). Although not shown in FIG. 3A, each verification of the circuit whose layout has been completed is performed. If there is no problem, the sign-off is performed and a GDS (Graphic Design Standard) is output (step S106). Then, a mask for manufacturing the semiconductor device is created based on the GDS and used for manufacturing the semiconductor device.

In this general design flow of a semiconductor device, the circuit design support apparatus of the present invention provides a target path or circuit for providing circuit design support based on layout information at the stage of macro placement shown in FIG. 3A. The process is executed for (Step S110). Alternatively, the circuit design support apparatus according to the present invention may be configured to target paths and circuits for which circuit design support is performed based on layout information at the stage when the layout design at the end of the process is almost completed by arranging and wiring the above-described functional blocks. Then, the process is executed (step S111). In step S111, ECO (Engineering Change Orders) for correcting the circuit and the layout is executed again according to the output result of the circuit design support apparatus of the present invention (step S105).
In this specification, a system that executes this general design flow of a semiconductor device is simply referred to as a design system.

Next, FIG. 3B shows an outline of the circuit design support apparatus 1 of the present invention. The circuit design support apparatus 1 of the present invention includes at least voltage waveform information of a power source supplied to an internal circuit, a target path (or target circuit), a total wiring length of the target path (or target circuit), a cell list, , Input information including the operating frequency of the target path (or target circuit) is input. These are all input from the outside if they are already known at the design stage, and are input from the design system when they are obtained from the design system as information reflecting the information at each stage of the design flow of FIG. 3A.
In FIG. 3B, the subsystem of the circuit design support apparatus 1 obtains macro placement information from layout information (for example, DEF), performs power supply noise analysis from this information, and calculates the voltage waveform information described above ( In step S120), input to the main system of the circuit design support apparatus 1. Further, the subsystem of the circuit design support apparatus 1 calculates the total wiring length of the target path based on the target path and the layout information (step S121).

If it is better to calculate the voltage waveform information and the total wiring length of the target path (or target circuit) after a more detailed layout is performed, the circuit design support apparatus 1 is used in the phase of step S111 in FIG. 3A. Use it. Furthermore, it is possible to execute both step S110 and step S111 as needed.
Moreover, the implementation location is not limited to these. In other words, the designer may reflect the output result of the circuit design support apparatus 1 on the design system at a desired stage.
In FIG. 3B, the circuit design support apparatus 1 of the present invention is a combination of the subsystems of the circuit design support apparatus 1 and the main system described above, but the configuration of only the main system may be used.

The circuit design support apparatus 1 of the present invention performs jitter reduction design (step S130), outputs at least the designated logical stage number n _i and wiring length l _{i of the} target path (target circuit), and the above-described design system. Give feedback. When the target circuit is designated instead of the target path, the same processing is performed on one or a plurality of paths included in the target circuit. That is, the design system executes layout according to the number of logic stages _ni and the wiring length l _i output from the circuit design support apparatus 1 of the present invention. The processing interface may be appropriately performed according to the design system.

In the present embodiment, as described above, the circuit design support apparatus 1 of the present invention includes at least the voltage waveform information / target path (or target circuit) / target path (or target circuit) of the power supplied to the internal circuit. ) At least for the target path (target circuit) so that the circuit takes into account jitter based on input information including the total wiring length, cell list, and operating frequency of the target path (or target circuit). The designated logic stage number n _i and (wiring length l _i ) of (target circuit) are output to the design system. Such a circuit design support apparatus (main system) 1 of the present invention has a configuration as shown in FIG.

  FIG. 4 is a block diagram showing a configuration example of the circuit design support apparatus (main system) 1 of the present invention. Referring to FIG. 4, the circuit design support apparatus 1 includes a library unit 10, a condition setting unit 11, a voltage calculation unit 12, a cell condition setting unit 13, a cell setting unit 14, a wiring length calculation unit 15, A jitter value calculation unit 16, a determination unit 17, a power consumption calculation unit 18, and an output unit 19 are provided.

The library unit 10 stores the cell type, the range of the power supply voltage that drives the cell type, and the function of the stage delay corresponding to the range of the power supply voltage in association with each other. The library unit 10 may store a library in advance or may generate a library based on user input. FIG. 5 is an example of a library stored in the library unit 10. Referring to FIG. 5, the cell type CELL _i , the range of the power supply voltage for driving the cell type CELL _i , and the function of the stage delay corresponding to the range of the power supply voltage are associated. The function of the stage delay will be described. The stage delay is a delay based on a cell delay relating to a cell representing a circuit that realizes a predetermined function, and a wiring delay relating to a wiring connecting the cell and a subsequent cell, a cell species cELL _{i (i} = 1~m), and the power supply voltage _{v h} to drive the cell species cELL _i, a delay that is determined on the basis of the subsequent wiring length _{l i} of the cell species cELL _i. Therefore, when the cell type CELL _i and the power supply voltage v _h are determined, the stage delay can be expressed as a function having the wiring length l _i as a variable.

A case where the library unit 10 generates a library will be described. Based on a user input, the library unit 10 includes a plurality of cell types (CELL ₁ , CELL ₂ ,..., CELL _m ) and a range of power supply voltages for driving each cell type CELL _i (from the minimum voltage value v _min). The maximum voltage value v _max ) is acquired. A plurality of cell types (CELL ₁ , CELL ₂ ,..., CELL _m ) may be acquired as a cell list (details will be described later). Further, the minimum voltage value v _min and the maximum voltage value v _max may be set by the library unit 10 based on voltage waveform information (details will be described later). In calculating the stage delay function, the library unit 10 uses the voltages v ₁ , v ₂ ,... Included in the range from the minimum voltage value v _min to the maximum voltage value v _max as the power supply voltage for driving each cell type CELL _i. Use discrete values of. The library unit 10 calculates the stage delay when the power supply voltage driven by an arbitrary cell type CELL _i is the voltage v ₁ by using SPICE (Simulation Program with Integrated Circuit Emphasis) for each wiring length l _i . The library section 10 stage delay calculated for each wiring length l _i, fitting a quadratic function to the wiring length l _i and variables. The library unit 10 calculates a function of the stage delay in which the power supply voltage for driving the cell type CELL _i is the voltage v ₁ as shown in Expression (1).
D _stage = a _i (v ₁ ) × l _i ² + b _i (v ₁ ) × l _i + c _i (v ₁ ) (1)

FIG. 6 illustrates the stage delay function of equation (1). As described above, the power supply voltage for driving the cell type CELL _i is the voltage v ₁ . The library unit 10 stores the cell type CELL _i , the range of the power supply voltage V (v _min ≦ V ≦ (v ₁ + v ₂ ) / 2), and the expression (1) that is a function of the stage delay in association with each other.

Similarly, the library unit 10 calculates a function of the stage delay of the cell type CELL _i having the voltage v ₂ as shown in Expression (2).
D _stage = a _i (v ₂ ) × l _i ² + b _i (v ₂ ) × l _i + c _i (v ₂ ) (2)
The library unit 10 includes a cell type CELL _i , a range of the power supply voltage V ((v ₁ + v ₂ ) / 2 <V ≦ (v ₂ + v ₃ ) / 2), and an expression (2) that is a function of the stage delay. Associate and store. Further, the library unit 10 calculates a function of the stage delay of the cell type CELL _i having an arbitrary voltage v _h as shown in Expression (3).
D _stage = a _i (v _h ) × l _i ² + b _i (v _h ) × l _i + c _i (v _h ) (3)
The library unit 10 includes a cell type CELL _i , a range of the power supply voltage V ((v _h−1 + v _h ) / 2 <V ≦ (v _h + v _{h + 1} ) / 2), and an expression (3 ) And store it.

The library unit 10 stores the cell type CELL _i , the range of the power supply voltage V for driving the cell type CELL _i , and the calculated stage delay function in association with each other as shown in FIG. The library unit 10 similarly associates with other cell types, and generates a library including all the cell types. Although the library unit 10 stores the function of the stage delay, the library unit 10 stores coefficients such as a _i (v _h ), b _i (v _h ), and c _i (v _h ). Also good.

Here, the path delay will be described. FIG. 7 is a diagram illustrating the relationship between stage delay and path delay. As shown in FIG. 6, since the stage delay D _stage can be expressed by a function having the wiring length l _i as a variable, the desired stage delay D _stage is calculated by determining the wiring length l _i and substituting it into the stage delay function. can do. When the stage delay D _stage is multiplied by the number of logical stages n _i of the same cell type CELL _i , the path delay D _path for the cell type CELL _i can be calculated. As shown in FIG. 7, for example, target path are the same cell type CELL _i, if the number of logic stages is _{n i} stages, a path delay _{D path} is multiplying the number of logic stages _{n i} in stage delay _{D Stage} Can be calculated.

Returning to FIG. 4, the condition setting unit 11, based on the user input, the target path that is a design target for propagating the clock signal, the clock signal frequency (operating frequency), the clock signal cycle, and the clock signal tolerance. A jitter value is acquired and set as path information. In addition, the condition setting unit 11 acquires the total wiring length L _total of the target path from the subsystem of the circuit design support apparatus 1. FIG. 8 is a diagram showing the target path 23 for reducing the jitter value. The condition setting unit 11 sets a target path 23 for propagating a clock signal from a clock source 20 such as a PLL (Phase Locked Loop) to a circuit 21 such as an analog circuit. FIG. 9 is a diagram illustrating a clock signal. In FIG. 9, the period of the clock signal is indicated by T. The condition setting unit 11 sets the clock frequency (fclk = 1 / T) and the cycle T of the clock signal based on the user input. FIG. 10 is a diagram illustrating jitter of a clock signal. The condition setting unit 11 sets an allowable jitter value that is an allowable value of jitter based on a user input. The jitter value handled in the present invention may be either the maximum of the cycle-to-cycle jitter value or the periodic jitter value. The cycle-to-cycle jitter value is a jitter value represented by the difference between the period T _{1 of the} clock signal rising at a certain time t ₁ and the period T _{2 of the} clock signal rising next, and the maximum is a predetermined value. This represents the maximum value of the cycle-to-cycle jitter value within the period. The period jitter value is a jitter value represented by the difference between the maximum value and the minimum value among the periods T _k of all the clock signals within a predetermined period.

電圧算出部１２は、平均電源電圧ＶＡ_ｋを算出した後、最大値ＶＡ_ｍａｘと、最小値ＶＡ_ｍｉｎとを算出する。 The voltage calculation unit 12 acquires voltage waveform information from the subsystem of the circuit design support apparatus 1. FIG. 11 is a diagram showing voltage waveform information. Moreover, the voltage calculation part 12 acquires the period T of a clock signal based on a user input. Voltage calculation unit 12 refers to the voltage waveform information, the supply voltage V of a predetermined period including the noise to be supplied to the target path 23, the average power supply voltage VA k _(k averaged for each period of the clock signal T = 1, 2,..., Q). In addition, the voltage calculation unit 12 calculates a maximum value VA _max and a minimum value VA _min among the average power supply voltage VA _k for a predetermined period. Referring to FIG. 11, the voltage calculation unit 12, any period _{T k (k = 1,2, ···} , q) from the rising time _{t k} of the period _{T k + 1} of the power supply voltage V to the rising time _{t k + 1} An average power supply voltage VA _k is calculated by averaging.
Time _{t k} can be expressed as shown in Equation (4).
t _k = T × k (4)
Average supply voltage VA _k from time _{t k,} to time _{t k + 1} can be expressed by Equation (5).

After calculating the average power supply voltage VA _k , the voltage calculation unit 12 calculates the maximum value VA _max and the minimum value VA _min .

The cell condition setting unit 13 lists a plurality of cell types CELL _i (i = 1 to m) having different driving capabilities arranged as elements of the target path 23 based on a user input (CELL_LIST = {CELL ₁ , CELL ₂ , CELL ₃ ,..., CELL _m }). The cell condition setting unit 13, based on user input, wiring length maximum value of which connected to the subsequent stage of each cell species CELL _i included in the cell list and (maximum wire length L _i), for each cell species CELL _i The maximum number of logical stages (maximum number of logical stages N _i ) is set.

The cell setting unit 14 arranges the placement information, which is a combination of the number of logical stages n _i of the cell types CELL _{i having} different driving capabilities arranged as elements of the target path 23 so that the driving capability of the target path 23 decreases. Set in order. Specifically, the cell setting unit 14 acquires a cell list, the maximum wiring length L _i of each cell type CELL _i , and the maximum number of logical stages N _i of each cell type CELL _i from the cell condition setting unit 13. The cell setting unit 14 sets the arrangement information based on the cell list and the maximum number of logical stages N _i of each cell type CELL _i . For example, the magnitude relationship between the driving ability of each cell species CELL _i, and _{CELL 1> CELL 2> CELL 3} >···> CELL m, CELL 1 ~CELL respective maximum number of logical steps _N 1 to N _{m m} is 5 If it is assumed that there are stages, the cell setting unit 14 arranges the number of logical stages n _i of each cell type CELL _i as n ₁ = 5, n ₂ = 0, n ₃ = 0,..., N _m = 0. Set the information. In the initial setting, the cell setting unit 14 sets the number of logical stages n _i of each cell type CELL _i having the highest driving capability. Further, when the cell setting unit 14 receives a change instruction for changing the combination (arrangement information) of the number of logical stages n _i of each cell type CELL _i from the determination unit 17 described later, the driving capability is set to be lower than the previous setting. In addition, the combination of the number of logic stages n _i of each cell type CELL _i is changed. In particular, the cell setting unit 14 changes the driving capacity to be the second largest after the previously set driving capacity. For example, in the continuation described above, the cell setting unit 14 sets the number of logical stages n _i of each cell type CELL _i as n ₁ = 4, n ₂ = 1, n ₃ = 0,..., N _m = 0. . As described above, the cell setting unit 14 changes the number of logical stages of cells having high driving capability to be decreased and the number of logical stages of cells having low driving capability to be increased. FIG. 12 is a diagram illustrating a process in which the cell setting unit 14 changes the combination of the number of logical stages n _i of each cell type CELL _i . FIG. 13 is a diagram showing the target path 23 corresponding to FIG. Referring to FIG. 13, the cell setting unit 14 sets CELL ₁ to 5 levels in the first (first) process. When the cell setting unit 14 receives the change instruction from the determination unit 17, the cell setting unit 14 decreases CELL ₁ to 4 levels and increases CELL ₂ to 1 level. Furthermore, when the cell setting unit 14 receives the change instruction from the determination unit 17, the cell setting unit 14 decreases CELL ₁ to three levels and increases CELL ₂ to two levels. In this way, the cell setting unit 14 operates so as to sequentially reduce the number of high drive capacity cells.

The wiring length calculation unit 15, the jitter value calculation unit 16, and the determination unit 17 are based on arrangement information that is a combination of the number of logical stages n _i of each cell type CELL _i , even if the power supply voltage V varies. The elements of the target path 23 in which the delay variation of 23 is small are determined.

The wiring length calculation unit 15 uses the optimum wiring length l _{i at} the subsequent stage of each cell type CELL _i with small path delay variation even when the power supply voltage V supplied to each cell type CELL _i included in the target path 23 varies. Is calculated. In other words, the wiring length calculation unit 15 causes the delay of the target path 23 when the maximum value VA _max is supplied and the minimum value VA _min when the maximum value VA _max is supplied to the target path 23 specified by the placement information. Wiring information that is a combination of the optimum wiring length l _{i at} the subsequent stage of each cell type CELL _i is calculated so that the difference from the delay of the target path 23 is minimized. Note that the wiring length calculation unit 15 performs processing in the order of arrangement information having a high driving capability to arrangement information having a low driving capability in a series of processes for determining the elements of the target path 23.

ｌ_ｉ≦Ｌ_ｉ （ｉ＝１、２、・・・、ｍ）・・・（７）
式（６）は、対象パス２３の総配線長Ｌ_{ｔｏｔａｌ}が、各セル種ＣＥＬＬ_ｉの論理段数ｎ_ｉと、各セル種ＣＥＬＬ_ｉの配線長ｌ_ｉとの総和に等しいことを表している。式（７）は、対象パス２３に含まれる各セル種ＣＥＬＬ_ｉの配線長ｌ_ｉが、最大配線長Ｌ_ｉ以下であることを示している。 First, the wiring length calculation unit 15 calculates all possible combinations as the wiring length l _i subsequent to each cell type CELL _i for the target path 23 defined by the arrangement information. Specifically, the wiring length calculation unit 15 acquires the _total wiring length L _total from the condition setting unit 11. Furthermore, the wiring length calculation unit 15 acquires the arrangement information and the maximum wiring length L _i of each cell type CELL _i from the cell setting unit 14. The wiring length calculation unit 15 performs linear programming on all possible combinations as the wiring length l _i of the subsequent stage of each cell type CELL _i based on the conditional expressions represented by the expressions (6) and (7). Calculate based on

l _i ≦ L _i (i = 1, 2,..., m) (7)
Equation (6), total route length _{L total} of target path 23 represents the logic stages _{n i} of each cell species CELL _i, that is equal to the sum of the wiring length _{l i} of each cell species CELL _i. Expression (7) indicates that the wiring length l _i of each cell type CELL _i included in the target path 23 is equal to or less than the maximum wiring length L _i .

As a specific example, the wiring length calculation unit 15 receives CELL ₁ , CELL ₂ , CELL ₁ logical stage number n ₁ , CELL ₂ logical stage number n ₂ , and CELL ₁ maximum wiring as cell types from the cell setting unit 14. A case where the length L ₁ and the maximum wiring length L ₂ of CELL ₂ are acquired will be described. FIG. 14 is a diagram showing all combinations of the wiring length l ₁ that can be taken by CELL ₁ and the wiring length l ₂ that can be taken by CELL ₂ as executable regions, calculated by linear programming. Wiring length calculation unit 15 calculates all combinations of wiring length _{l 2} of the wiring length _{l 1} and CELL ₂ of CELL ₁ included in the feasible region.

同様に、配線長算出部１５は、各セル種ＣＥＬＬ_ｉと、最小値ＶＡ_ｍｉｎとに基づいて、複数のステージ遅延の関数を取得し、パス遅延を算出する。そして、配線長算出部１５は、算出された各セル種ＣＥＬＬ_ｉの後段の配線長ｌ_ｉの全ての組合せのうちで、最大値ＶＡ_ｍａｘのときのパス遅延と、最小値ＶＡ_ｍｉｎのときのパス遅延との差が最小となるような、各セル種の後段の最適配線長ｌ_ｉの組合せを算出する。各セル種ＣＥＬＬ_ｉの後段の最適配線長ｌ_ｉは、式（９）のｆ_{ｓｅｎｓｅ}の絶対値が最小となるときの配線長ｌ_ｉである。

図１５は、最大値ＶＡ_ｍａｘのときのパス遅延と、最小値ＶＡ_ｍｉｎのときのパス遅延との差を最小化することを示した概念図である。Ｄ_ｐａｔｈの傾きを小さくする事で電圧変動に関するパス遅延の感度(ｆ_{ｓｅｎｓｅ}の絶対値)を小さくさせている。このように、配線長算出部１５は、電源電圧Ｖが変動しても、パス遅延が変動しにくい各セル種ＣＥＬＬ_ｉの最適配線長ｌ_ｉの組合せである配線情報を算出する。 Next, the wiring length calculation unit 15 calculates the path delay when the maximum voltage that can be supplied as the driving voltage is supplied among all combinations of the calculated wiring length l _i of the subsequent stage of each cell type CELL _i. Then, wiring information that is a combination of the optimum wiring length l _{i in} the subsequent stage of each cell type CELL _i is calculated so that the difference from the path delay when the minimum voltage that can be supplied is supplied is minimized. Specifically, the wiring length calculation unit 15 acquires the maximum value VA _max and the minimum value VA _{min of the} average power supply voltage VA _k from the voltage calculation unit 12. The wiring length calculation unit 15 refers to the library unit 10 and acquires a plurality of corresponding stage delay functions based on each cell type CELLi and the maximum value VA _max . Wiring length calculation unit 15, based on the function of a plurality of stages delays, and possible combinations as the subsequent line length l _i of each cell species CELL _i, and logic stages n _i of each cell species CELL _i, the path delay Is calculated. The path delay at this time is expressed by equation (8).

Similarly, the wiring length calculation unit 15 acquires a plurality of stage delay functions based on each cell type CELL _i and the minimum value VA _min, and calculates a path delay. The wiring length calculation unit 15 then calculates the path delay at the maximum value VA _max and the minimum value VA _min among all combinations of the calculated wiring length l _{i at} the subsequent stage of each cell type CELL _i . The combination of the optimum wiring length l _{i at} the subsequent stage of each cell type is calculated so that the difference from the path delay is minimized. Optimal wiring length _{l i} of the subsequent respective cell species CELL _i is a wiring length _{l i} of when the absolute value of _{f sense} of formula (9) is minimized.

FIG. 15 is a conceptual diagram showing that the difference between the path delay at the maximum value VA _max and the path delay at the minimum value VA _min is minimized. By reducing the slope of D _path , the sensitivity of path delay (absolute value of f _sense ) related to voltage fluctuation is reduced. As described above, the wiring length calculation unit 15 calculates wiring information that is a combination of the optimal wiring lengths l _i of the respective cell types CELL _i in which the path delay does not easily vary even when the power supply voltage V varies.

The jitter value calculation unit 16 applies the jitter value J to the target path 23 defined by the placement information and the wiring information based on the average power supply voltage VA _k (k = 1, 2,..., Q−1). Is calculated. In other words, the jitter value calculating unit 16, and each cell type CELL _i, and logic stages _{n i} of each cell species CELL _i, and the rear stage of the optimal wiring length _{l i} of each cell species CELL _i, an average power source voltage VA _k Based on the above, the jitter value J of the target path 23 is calculated and provided to the determination unit 17. The jitter value J to be calculated is the same as the allowable jitter value set by the condition setting unit 11 and may be either the maximum of the cycle-to-cycle jitter value or the periodic jitter value. Note that the jitter value calculation unit 16 performs processing in order of arrangement information having a high driving capability in a series of processing for determining elements of the target path 23.

A case where the jitter value calculation unit 16 calculates the maximum of the cycle-to-cycle jitter value will be described. Jitter value calculating unit 16, among the jitter value J _k represented by the difference between the period T _k of the clock signal which rises at a certain time t _k, the period T _{k + 1} of the immediately following clock signal, the maximum jitter value J ( maxJ _k) is calculated. In other words, the jitter value calculation unit 16 calculates the jitter value J _k represented by the difference between the path delay of the clock signal period T _k rising at a certain time t _k and the path delay of the clock signal period T _{k + 1} immediately thereafter. Among these, the maximum jitter value J (maxJ _k ) is calculated. The jitter value calculation unit 16 calculates a cycle-to-cycle jitter value based on equation (10).

Specifically, the jitter value calculation unit 16 sends the cell type CELL _i , the logical stage number n _i of each cell type CELL _i , and the optimum wiring length l _{i after the} cell type CELL _i from the wiring length calculation unit 15. To get. In addition, the jitter value calculation unit 16 acquires the average power supply voltage VA _k from the voltage calculation unit 12. The jitter value calculation unit 16 acquires a plurality of stage delay functions based on each cell type CELL _i and the average power supply voltage VA _k . Jitter value calculation unit 16, based on the function of a plurality of stages delays, and possible combinations as the subsequent line length l _i of each cell species CELL _i, and logic stages n _i of each cell species CELL _i, the path delay Is calculated. Similarly, the jitter value calculation unit 16 acquires a plurality of stage delay functions based on each cell type CELL _i and the average power supply voltage VA _{k + 1,} and calculates a path delay. Jitter value calculating unit 16, a path delay when the average power supply voltage VA _k, based on the difference of the path delay in the average power supply voltage VA k _{+ 1,} to calculate a jitter value J _k. Then, the jitter value calculation unit 16 calculates all the cycle-to-cycle jitter values J _k based on the average power supply voltage VA _k within a predetermined period, and calculates the maximum jitter value J (maxJ _k ).

そして、ジッタ値算出部１６は、周期Ｔ_ｋの最大値ｍａｘＴ_ｋと最小値ｍｉｎＴ_ｋの差で表されるジッタ値Ｊを式（１２）に基づいて算出する。
Ｊ＝ｍａｘＴ_ｋ−ｍｉｎＴ_ｋ ・・・（１２） On the other hand, a case where the jitter value calculation unit 16 calculates a periodic jitter value will be described. The jitter value calculation unit 16 calculates all the periods T _k of the clock signal within a predetermined period, and calculates a jitter value J represented by the difference between the maximum value maxT _k and the minimum value minT _k of the period T _k. . FIG. 16 is a diagram illustrating a target path 23 that is a calculation target of a periodic jitter value. The input clock signal is output as an output clock signal with a delay of the path delay _Dpath . FIG. 17 is a diagram illustrating calculation of the jitter value J based on the input clock signal and the output clock signal. The jitter value calculation unit 16 calculates each of the periods T _{1 to} T ₄ of the output clock signal, and calculates the jitter value J from the difference between the maximum value maxT _k that is the maximum period and the minimum value minT _k that is the minimum period. calculate. Specifically, the jitter value calculation unit 16 calculates the period T _k (k = 1, 2,..., Q) based on the equation (11).

Then, the jitter value calculation unit 16 calculates a jitter value J represented by the difference between the maximum value maxT _k and the minimum value minT _k of the period T _k based on the equation (12).
J = maxT _k −minT _k (12)

The determination unit 17 determines whether or not the jitter value J exceeds the allowable jitter value in the order of arrangement information having a high driving capability. When the jitter value J of the target path 23 defined by the placement information and the wiring information exceeds the allowable jitter value, the determination unit 17 calculates the placement information calculated before the placement information and the wiring information. And the wiring information are determined as elements of the target path 23. Specifically, the determination unit 17 acquires the jitter value J of the jitter value calculation unit 16 and the allowable jitter value of the condition setting unit 11. The determination unit 17 determines whether or not the jitter value J to be determined received from the jitter value calculation unit 16 exceeds the allowable jitter value. When the jitter value J to be determined is equal to or less than the allowable jitter value, the determination unit 17 outputs a change instruction for changing the combination of the number of logical stages n _i of each cell type CELL _i to the cell setting unit 14. On the other hand, when the jitter value J to be determined exceeds the allowable jitter value, the determination unit 17 determines the jitter value J that was the previous determination target as the optimum jitter value J. In the present invention, the cell setting unit 14 changes each cell type CELL _i included in the target path 23 from one having a high driving capability to one having a low driving capability so that the jitter value J calculated by the jitter value calculating unit 16 gradually increases. And in order. As a result, when the determination unit 17 determines that the determination target jitter value J exceeds the allowable jitter value, the determination unit 17 can determine the jitter value J that was the previous determination target as the optimum jitter value J. FIG. 18 is a diagram illustrating the relationship between the number of determinations by the determination unit 17 and the jitter value J to be determined. The jitter value J to be determined is indicated by a square mark. Referring to FIG. 18, it is shown that the jitter value J to be determined increases as the number of determinations increases. In the example of FIG. 18, the determination unit 17 determines that the jitter value J to be determined is greater than or equal to the allowable jitter value at the time of the fourth determination, and determines the jitter value J that has been the third determination target as the optimum value.

  The power consumption calculation unit 18 acquires an optimum jitter value from the determination unit 17 and calculates the power consumption value P at that time. In FIG. 18, the power consumption value P is indicated by a triangle mark. Referring to FIG. 18, it is shown that the circuit design support apparatus 1 of the present invention can design a circuit that satisfies the allowable jitter value and consumes as little power as possible even when the power supply voltage fluctuates.

  The output unit 19 acquires the jitter value J (all calculated jitter values including the optimal jitter value J) and the determination result from the determination unit 17, and acquires the power consumption value P from the power consumption calculation unit 18. The output unit 19 outputs the jitter value J, the determination result, and the power consumption value P so that the user can recognize them. Further, the output unit 19 acquires the placement information and the wiring information from the wiring length calculation unit 15 and feeds back to the design system of FIG. 3A.

  The circuit design support apparatus 1 according to the embodiment of the present invention can be realized using a computer. FIG. 19 is a block diagram illustrating a hardware configuration example in the embodiment of the circuit design support device 1. Referring to FIG. 19, the circuit design support apparatus 1 of the present invention includes a CPU (Central Processing Unit) 101, a storage device 102, an input device 103, an output device 104, and a bus 105 that connects the devices. Consists of a computer system.

  The CPU 101 performs arithmetic processing and control processing related to the circuit design support device 1 of the present invention stored in the storage device 102. The storage device 102 is a device that records information, such as a hard disk or a memory. The storage device 102 is a program read from a computer-readable storage medium such as a CD-ROM or DVD, a program downloaded via a network (not shown), a signal or program input from the input device 103, and the CPU 101. Stores the processing result of. The input device 103 is a device that allows a user to input commands and signals, such as a mouse, a keyboard, and a microphone. The output device 104 is a device that causes the user to recognize the output result, such as a display or a speaker. In addition, this invention is not limited to what was shown as a hardware structural example, Each part can be implement | achieved independently or combining hardware and software.

  FIG. 20 is a flowchart showing the processing operation according to the first embodiment of the circuit design support apparatus 1 of the present invention. The processing operation according to the first embodiment of the present invention will be described with reference to FIG.

Step S01:
The library unit 10 generates a library in which a cell type, a range of a power supply voltage for driving the cell type, and a stage delay function corresponding to the range of the power supply voltage are associated with each other. Specifically, the library unit 10 calculates the stage delay when the power supply voltage driven by an arbitrary cell type CELL _i is the voltage v _h by SPICE for each wiring length l _i . The library section 10 stage delay calculated for each wiring length l _i, fitting a quadratic function to the wiring length l _i and variables. The library unit 10 calculates a function of the stage delay in which the power supply voltage for driving the cell type CELL _i is the voltage v _h as the above-described equation (3). The library unit 10 includes a cell type CELL _i , a range of the power supply voltage V ((v _h−1 + v _h ) / 2 <V ≦ (v _h + v _{h + 1} ) / 2), and an expression (3 ) In association with each other (see FIG. 5). The library unit 10 similarly associates with other cell types, and generates a library including all the cell types. The library unit 10 may store a library in advance.

Step S02:
The condition setting unit 11 sets, as path information, a target path 23 that is a design target for propagating a clock signal based on a user input. In addition, the condition setting unit 11 acquires the total wiring length L _total of the target path from the subsystem of the circuit design support apparatus 1.

Step S03:
Based on the user input, the condition setting unit 11 acquires the frequency of the clock signal of the target path 23, the period of the clock signal, and the allowable jitter value of the clock signal, and sets them as path information. As described above, the jitter value may be either the maximum of the cycle-to-cycle jitter value or the periodic jitter value.

Step S04:
The voltage calculation unit 12 acquires voltage waveform information from the subsystem of the circuit design support apparatus 1. Moreover, the voltage calculation part 12 acquires the period T of a clock signal based on a user input. Voltage calculation unit 12 refers to the voltage waveform information, the supply voltage V of a predetermined period including the noise to be supplied to the target path 23, the average power supply voltage VA k _(k averaged for each period of the clock signal T = 1, 2,..., Q). In addition, the voltage calculation unit 12 calculates a maximum value VA _max and a minimum value VA _min among the average power supply voltage VA _k for a predetermined period.

Step S05:
The cell condition setting unit 13 lists a plurality of cell types CELL _i (i = 1 to m) having different driving capabilities arranged as elements of the target path 23 based on a user input (CELL_LIST = {CELL ₁ , CELL ₂ , CELL ₃ ,..., CELL _m }). The cell condition setting unit 13, based on user input, wiring length maximum value of which connected to the subsequent stage of each cell species CELL _i included in the cell list and (maximum wire length L _i), for each cell species CELL _i The maximum number of logical stages (maximum number of logical stages N _i ) is set.

Step S06:
Cell setting unit 14 sets arrangement information is a combination of logic stages n _i of each cell species CELL _i having different driving capability which is arranged as an element of the target path 23. Specifically, the cell setting unit 14 acquires a cell list, the maximum wiring length L _i of each cell type CELL _i , and the maximum number of logical stages N _i of each cell type CELL _i from the cell condition setting unit 13. The cell setting unit 14 sets the arrangement information based on the cell list and the maximum number of logical stages N _i of each cell type CELL _i . For example, the magnitude relationship between the driving ability of each cell species CELL _i, and _{CELL 1> CELL 2> CELL 3} >···> CELL m, CELL 1 ~CELL respective maximum number of logical steps _N 1 to N _{m m} is 5 If it is assumed that there are stages, the cell setting unit 14 arranges the number of logical stages n _i of each cell type CELL _i as n ₁ = 5, n ₂ = 0, n ₃ = 0,..., N _m = 0. Set the information. In the initial setting, the cell setting unit 14 sets the number of logical stages n _i of each cell type CELL _i having the highest driving capability.

Step S07:
The wiring length calculation unit 15 uses the optimum wiring length l _{i at} the subsequent stage of each cell type CELL _i with small path delay variation even when the power supply voltage V supplied to each cell type CELL _i included in the target path 23 varies. Is calculated. First, the wiring length calculation unit 15 calculates all possible combinations as the wiring length l _i subsequent to each cell type CELL _i for the target path 23 defined by the arrangement information. Specifically, the wiring length calculation unit 15 acquires the _total wiring length L _total from the condition setting unit 11. Furthermore, the wiring length calculation unit 15 acquires the arrangement information and the maximum wiring length L _i of each cell type CELL _i from the cell setting unit 14. The wiring length calculation unit 15 linearly plans all combinations that can be taken as the wiring length l _i of the subsequent stage of each cell type CELL _i based on the conditional expressions represented by the above-described expressions (6) and (7). Calculate based on the law.

Next, the wiring length calculation unit 15 acquires the maximum value VA _max and the minimum value VA _{min of the} average power supply voltage VA _k from the voltage calculation unit 12. The wiring length calculation unit 15 refers to the library unit 10 and acquires a plurality of corresponding stage delay functions based on each cell type CELL _i and the maximum value VA _max or the minimum value VA _min . Wiring length calculation unit 15, based on the function of a plurality of stages delays, and possible combinations as the subsequent line length l _i of each cell species CELL _i, and logic stages n _i of each cell species CELL _i, the path delay Is calculated. The path delay at this time is expressed by the above equation (8). The wiring length calculation unit 15 then calculates the path delay at the maximum value VA _max and the minimum value VA _min among all combinations of the calculated wiring length l _{i at} the subsequent stage of each cell type CELL _i . The combination of the optimum wiring length l _{i at} the subsequent stage of each cell type is calculated so that the difference from the path delay is minimized. Optimal wiring length _{l i} of the subsequent respective cell species CELL _i is a wiring length _{l i} of when the absolute value of _{f sense} of formula (9) is minimized.

Step S08
The jitter value calculation unit 16 applies the jitter value J to the target path 23 defined by the placement information and the wiring information based on the average power supply voltage VA _k (k = 1, 2,..., Q−1). Is calculated. In other words, the jitter value calculating unit 16, and each cell type CELL _i, and logic stages _{n i} of each cell species CELL _i, and the rear stage of the optimal wiring length _{l i} of each cell species CELL _i, an average power source voltage VA _k Based on the above, the jitter value J of the target path 23 is calculated and provided to the determination unit 17. The calculated jitter value J is the same as the allowable jitter value set by the condition setting unit 11 in step S03, and may be either the maximum of the cycle-to-cycle jitter value or the periodic jitter value.

Step S09:
The determination unit 17 acquires the jitter value J of the jitter value calculation unit 16 and the allowable jitter value of the condition setting unit 11. The determination unit 17 determines whether or not the jitter value to be determined received from the jitter value calculation unit 16 exceeds the allowable jitter value. If the jitter value to be determined is less than or equal to the allowable jitter value, the determination unit 17 outputs a change instruction to change the combination of the number of logical stages n _i of each cell type CELL _i to the cell setting unit 14 (proceeds to step S06). . Cell setting unit 14 receives the change instruction from the determination unit 17 changes the number of logic stages n _i of each cell type, as the driving capability becomes lower than the previous set, changing the number of logic stages n _i of each cell species To do. For example, in the continuation described above, the cell setting unit 14 sets the number of logical stages n _i of each cell type CELL _i as n ₁ = 4, n ₂ = 1, n ₃ = 0,..., N _m = 0. .

  On the other hand, when the determination target jitter value J exceeds the allowable jitter value, the determination unit 17 determines the jitter value J that was the previous determination target as the optimum jitter value J (proceeds to step S10). In the present invention, the cell setting unit 14 changes the cell types included in the target path 23 from the one having the highest driving capability to the one having the lower driving capability so that the jitter value J calculated by the jitter value calculating unit 16 gradually increases. Has been changed. As a result, when the determination unit 17 determines that the determination target jitter value J exceeds the allowable jitter value, the determination unit 17 can determine the previous determination target jitter value J as the optimum jitter value. Then, the determination unit 17 determines the placement information and the wiring information at the optimal jitter value as elements of the target path 23.

Step S10:
The power consumption calculation unit 18 acquires the optimum value of the jitter value from the determination unit 17 and calculates the power consumption value P at that time. The output unit 19 acquires a jitter value and a determination result from the determination unit 17 and acquires a power consumption value P from the power consumption calculation unit 18. The output unit 19 outputs the jitter value, the determination result, and the power consumption value P so that the user can recognize them. Further, the output unit 19 acquires the placement information and the wiring information from the wiring length calculation unit 15 and feeds back to the design system of FIG. 3A.

  As described above, the circuit design support device 1 according to the first embodiment of the present invention has an effect of designing a circuit that satisfies the allowable jitter value and consumes less power even when the power supply voltage fluctuates. . In particular, the present invention has an effect of designing a circuit that consumes as little power as possible within a short period of time while satisfying the allowable jitter value, instead of designing an overspec target path for the jitter value.

Note that the cell setting unit 14 reduces the drive capability of the target path 23 for the placement information that is a combination of the number of logical stages n _i of each cell type CELL _{i having} different drive capabilities that are arranged as elements of the target path 23. However, they may be set in order so that the driving capability increases. In that case, the wiring length calculation unit 15, the jitter value calculation unit 16, and the determination unit 17 perform a series of processes in the order of arrangement information having a low driving capability to arrangement information having a high driving capability. In particular, the determination unit 17 determines the placement information and the wiring information as elements of the target path 23 when the jitter value J of the target path 23 defined by the placement information and the wiring information is equal to or less than the allowable jitter value. be able to.

(Second Embodiment)
A second embodiment of the present invention will be described. FIG. 21 is a block diagram showing a configuration example of a circuit design support apparatus 1a according to the second embodiment of the present invention. Referring to FIG. 21, the circuit design support apparatus 1a includes a library unit 10, a condition setting unit 11a, a voltage calculation unit 12, a cell condition setting unit 13, a cell setting unit 14, a wiring length calculation unit 15a, A jitter value calculation unit 16, a determination unit 17, a power consumption calculation unit 18, and an output unit 19 are provided. The second embodiment is different from the first embodiment in the configuration of the condition setting unit 11a and the wiring length calculation unit 15a. Since other configurations are the same as those of the first embodiment, the same reference numerals are given and description thereof is omitted.

Similar to the condition setting unit 11 of the first embodiment, the condition setting unit 11a is based on the user input, the target path 23 that is a design target for propagating the clock signal, the frequency of the clock signal, and the clock signal The period and the allowable jitter value of the clock signal are acquired and set as path information. Furthermore, the condition setting unit 11a, based on the user input, retrieves the clock latency tolerance of the target path 23 for propagating a clock signal from the clock source 20 to the circuit 21 _(D path _LIMIT), set as the path information.

ｌ_ｉ≦Ｌ_ｉ （ｉ＝１、２、・・・、ｍ） ・・・（１４）
Ｄ_ｐａｔｈ（ＶＡ_ｍｉｎ，ｎ_１，ｎ_２，・・・，ｎ_ｍ，ｌ_１，ｌ_２，・・・，ｌ_ｍ）≦Ｄ_ｐａｔｈ＿ＬＩＭＩＴ ・・・（１５）
式（１３）は、第１の実施の形態と式（６）と同様であり、式（１４）は式（７）と同様である。式（１５）は、パス遅延が、クロックレイテンシ許容値以下であることを表している。電源電圧Ｖが小さいときにパス遅延が大きくなるため、最小値ＶＡ_ｍｉｎを用いてクロックレイテンシ許容値を設定している。 The wiring length calculation unit 15a, even if the power supply voltage V supplied to each cell type CELL _i included in the target path 23 fluctuates, the optimal wiring length l _{i at} the subsequent stage of each cell type CELL _i with small fluctuation in path delay. Is calculated. The wiring length calculation unit 15a calculates the optimum wiring length l _i particularly including the clock latency tolerance value. First, the wiring length calculation unit 15a includes all combinations that can be taken as the wiring length l _i of the subsequent stage of each cell type CELL _i including the clock latency tolerance value as a condition for the target path 23 specified by the arrangement information. Is calculated. Specifically, the wiring length calculation unit 15a acquires the total wiring length _Ltotal and the clock latency allowable value from the condition setting unit 11a. Further, the wiring length calculation unit 15a acquires the arrangement information and the maximum wiring length L _i of each cell type CELL _i from the cell setting unit 14. The wiring length calculation unit 15a can take all possible wiring lengths l _i subsequent to each cell type CELL _i based on the conditional expressions represented by the expressions (13), (14), and (15). Is calculated based on a quadratic constraint programming problem (Quadrative Constraint Programming). That is, here, since the D _{path of the} quadratic function of the wiring length is added to the constraint condition, it becomes a quadratic constraint programming problem instead of a linear programming.

l _i ≦ L _i (i = 1, 2,..., m) (14)
D _path (VA _min , n ₁ , n ₂ ,..., N _m , l ₁ , l ₂ ,..., L _m ) ≦ D _path _LIMIT (15)
Formula (13) is the same as Formula (6) in the first embodiment, and Formula (14) is the same as Formula (7). Expression (15) represents that the path delay is equal to or less than the clock latency allowable value. Since the path delay increases when the power supply voltage V is small, the clock latency allowable value is set using the minimum value VA _min .

As a specific example, the cell length calculation unit 15a receives CELL ₁ , CELL ₂ , CELL ₁ logic stage number n ₁ , CELL ₂ logic stage number n ₂ , and CELL ₁ maximum wiring as cell types from the cell setting unit 14. A case where the length L ₁ and the maximum wiring length L ₂ of CELL ₂ are acquired will be described. The wiring length calculation unit 15a refers to the library unit 10 and obtains two stage delay functions based on CELL ₁ or CELL ₂ and the minimum value VA _min . 22A to 22C are diagrams showing all combinations of the wiring length l ₁ that can be taken by CELL ₁ calculated by the secondary constraint planning problem and the wiring length l ₂ that can be taken by CELL ₂ as executable regions. is there. FIG. 22A shows that there is no executable region that satisfies all the conditions including the clock latency tolerance. In this case, it is assumed that there is no combination that the wiring length calculation unit 15a can take as the wiring length l _i of the subsequent stage of each cell type CELL _i . Figure 22B, when there is the feasible region, that is, the case where there a single wiring length _{l 1} of CELL ₁ can take, one wiring length _{l 2} that can take and CELL ₂ is. Figure 22C also shows the case where there is a feasible region, the wiring length calculation unit 15a calculates all combinations of wiring length _{l 2} of the wiring length _{l 1} and CELL ₂ of CELL ₁ included in the feasible region.

Next, the wiring length calculation unit 15a calculates the path delay when the maximum voltage that can be supplied as the driving voltage is supplied among all combinations of the calculated wiring length l _i of the subsequent stage of each cell type CELL _i. Then, wiring information that is a combination of the optimum wiring length l _{i in} the subsequent stage of each cell type CELL _i is calculated so that the difference from the path delay when the minimum voltage that can be supplied is supplied is minimized. The process here is the same as that of the wiring length calculation part 15 of 1st Embodiment.

  FIG. 23 is a flowchart showing the processing operation of the circuit design support apparatus 1a according to the second embodiment of the present invention. Steps S11 to S15 are the same as steps S01 to S05 in the first embodiment.

Step S16:
The condition setting unit 11a acquires the clock latency allowable value (D _path LIMIT) of the target path 23 for propagating the clock signal from the clock source 20 to the circuit 21 based on the user input, and sets it as path information.

Step S17:
Cell setting unit 14 sets arrangement information is a combination of logic stages n _i of each cell species CELL _i having different driving capability which is arranged as an element of the target path 23. Specifically, the cell setting unit 14 acquires a cell list, the maximum wiring length L _i of each cell type CELL _i , and the maximum number of logical stages N _i of each cell type CELL _i from the cell condition setting unit 13. The cell setting unit 14 sets the arrangement information based on the cell list and the maximum number of logical stages N _i of each cell type CELL _i .

Step S18:
The wiring length calculation unit 15a, even if the power supply voltage V supplied to each cell type CELL _i included in the target path 23 fluctuates, the optimal wiring length l _{i at} the subsequent stage of each cell type CELL _i with small fluctuation in path delay. Is calculated. The wiring length calculation unit 15a calculates the optimum wiring length l _i particularly including the clock latency tolerance value. First, the wiring length calculation unit 15a includes all combinations that can be taken as the wiring length l _i of the subsequent stage of each cell type CELL _i including the clock latency tolerance value as a condition for the target path 23 specified by the arrangement information. Is calculated. Specifically, the wiring length calculation unit 15a acquires the total wiring length _Ltotal and the clock latency allowable value from the condition setting unit 11a. Further, the wiring length calculation unit 15a acquires the arrangement information and the maximum wiring length L _i of each cell type CELL _i from the cell setting unit 14. The wiring length calculation unit 15a can take all possible wiring lengths l _i subsequent to each cell type CELL _i based on the conditional expressions represented by the above-described Expression (13), Expression (14), and Expression (15). Is calculated based on the quadratic constraint planning problem.

Next, the wiring length calculation unit 15a calculates the path delay when the maximum voltage that can be supplied as the driving voltage is supplied among all combinations of the calculated wiring length l _i of the subsequent stage of each cell type CELL _i. Then, wiring information that is a combination of the optimum wiring length l _{i in} the subsequent stage of each cell type CELL _i is calculated so that the difference from the path delay when the minimum voltage that can be supplied is supplied is minimized. The process here is the same as that of the wiring length calculation part 15 of 1st Embodiment.

  Steps S19 to S21 are the same as steps S08 to S10 of the first embodiment.

As described above, the circuit design support apparatus 1a according to the second embodiment of the present invention satisfies the allowable jitter value even when the power supply voltage fluctuates, and has the power consumption as in the first embodiment. It has the effect of designing fewer circuits. In particular, the circuit design support device 1a adds a path delay at the minimum value VA _min that maximizes the path delay as a constraint, and thus has an effect of designing a circuit that satisfies the clock latency tolerance. Yes.

The present invention can be applied to general circuit design, but as described above, it is particularly useful for designing a semiconductor integrated circuit. For example, the circuit design support apparatus according to the present invention includes a clock circuit design distributed to an analog circuit, a clock circuit design distributed to a high-speed I / F (interface) circuit (DDR: Double Data Rate), and data between FFs (FlipFlops). It is suitable for designing a clock circuit (clock tree) distributed to lines.
Further, as described above, the present invention is not intended only for the clock signal, but can be applied to a general signal (that is, a general circuit).

DESCRIPTION OF SYMBOLS 1, 1a: Circuit design support apparatus 10: Library part 11, 11a: Condition setting part 12: Voltage calculation part 13: Cell condition setting part 14: Cell setting part 15, 15a: Wiring length calculation part 16: Jitter value calculation part 17 : Determination unit 18: Power consumption calculation unit 19: Output unit 20: Clock source 21: Circuit 23: Target path 102: Storage device 103: Input device 104: Output device 105: Bus CELLi: Cell type J: Jitter value Li: Maximum Wiring length Ltotal: Total wiring length Ni: Maximum number of logic stages T: Period

Claims (11)

A condition setting unit that sets a target path that is a design target for propagating a signal, a period of the signal, and an allowable jitter value of the signal based on a user input;
An average power supply voltage obtained by averaging the power supply voltage supplied to the target path for each period, and a voltage calculation unit that calculates a maximum value and a minimum value of the average power supply voltage;
A cell setting unit that sequentially sets arrangement information, which is a combination of the number of logical stages of each of a plurality of cell types having different driving capacities arranged as elements of the target path so that the driving capacity of the target path decreases. When,
The first delay of the target path when the maximum value is supplied and the minimum value are supplied to the target path specified by the arrangement information in the order of the arrangement information having the highest driving capability. A wiring length calculation unit that calculates wiring information that is a combination of subsequent optimal wiring lengths of each of the plurality of cell types when a difference from the second delay of the target path is minimized;
A jitter value calculating unit that calculates a jitter value based on the average power supply voltage for the target path defined by the arrangement information and the wiring information in the order of the arrangement information having a high driving capability;
A determination unit for determining whether or not the jitter value exceeds the allowable jitter value in order of the arrangement information having a high driving capability;
When the first jitter value of the target path defined by the first arrangement information and the first wiring information exceeds the allowable jitter value, the determination unit uses the first arrangement information and the first wiring information. A circuit design support device that determines the second placement information and the second wiring information, which have been calculated before, as elements of the target path. The circuit design support apparatus according to claim 1,
When the first jitter value is less than or equal to the allowable jitter value, the determination unit outputs a change instruction to change the combination of the number of logical stages of each of the plurality of cell types to the cell setting unit,
The circuit setting support device, wherein the cell setting unit sets, based on the change instruction, third arrangement information whose driving capability is lower than the first arrangement information. The circuit design support apparatus according to claim 1 or 2,
A cell list in which the plurality of cell types having different driving capabilities arranged as elements of the target path are listed, the maximum number of logical stages of each of the plurality of cell types included in the cell list, and the plurality of cell types Further comprising a cell condition setting unit for setting a maximum wiring length connected to each subsequent stage based on a user input,
The condition setting unit calculates a total wiring length of the target path,
The cell setting unit, based on the cell list and the maximum number of logical stages, sets the arrangement information in order so that the drive capability of the target path decreases,
The wiring length calculation unit includes all the combinations that can be taken as the wiring length of each subsequent stage of the plurality of cell types with respect to the target path defined by the arrangement information, and the total wiring length. And the maximum wiring length as a condition, and the wiring information when the difference between the first delay and the second delay is minimum is calculated from all the combinations. Circuit design support device. The circuit design support device according to claim 3,
The condition setting unit sets the allowable latency value of the signal based on a user input,
The wiring length calculation unit includes all the combinations that can be taken as the wiring length of each subsequent stage of the plurality of cell types with respect to the target path defined by the arrangement information, and the total wiring length. And a circuit design support apparatus that calculates a quadratic constraint planning problem on the condition of the maximum wiring length and the latency tolerance. A condition setting unit that sets a target path that is a design target for propagating a signal, a period of the signal, and an allowable jitter value of the signal based on a user input;
An average power supply voltage obtained by averaging the power supply voltage supplied to the target path for each period, and a voltage calculation unit that calculates a maximum value and a minimum value of the average power supply voltage;
A cell setting unit that sequentially sets arrangement information that is a combination of the number of logical stages of each of a plurality of cell types having different driving capabilities arranged as elements of the target path so that the driving capability of the target path increases. When,
The first delay of the target path when the maximum value is supplied and the minimum value are supplied to the target path specified by the arrangement information in the order of the arrangement information having the low driving capability. A wiring length calculation unit that calculates wiring information that is a combination of subsequent optimal wiring lengths of each of the plurality of cell types when a difference from the second delay of the target path is minimized;
A jitter value calculation unit that calculates a jitter value based on the average power supply voltage for the target path defined by the arrangement information and the wiring information in order of the arrangement information having a low driving capability;
A determination unit that determines whether or not the jitter value exceeds the allowable jitter value in the order of the arrangement information having a low driving capability;
When the first jitter value of the target path defined by the first arrangement information and the first wiring information is equal to or less than the allowable jitter value, the determination unit determines the first arrangement information and the first wiring information as the first arrangement information and the first wiring information. Circuit design support device that is determined as an element of the target path. Setting a target path that is a design target for propagating a signal, a period of the signal, and an allowable jitter value of the signal based on a user input;
Calculating an average power supply voltage obtained by averaging the power supply voltage supplied to the target path for each period, and a maximum value and a minimum value of the average power supply voltage;
Based on arrangement information that is a combination of the number of logical stages of each of a plurality of cell types having different driving capabilities arranged as elements of the target path, even if the power supply voltage fluctuates, variation in delay of the target path is small Determining an element of the target path,
Determining an element of the target path comprises:
Setting first arrangement information;
A first delay of the target path when the maximum value is supplied and a second delay of the target path when the minimum value is supplied for the target path specified by the first arrangement information. Calculating the first wiring information that is a combination of the optimal wiring lengths of the subsequent stages of each of the plurality of cell types included in the first arrangement information when the difference between
Calculating a first jitter value based on the average power supply voltage for the target path defined by the first arrangement information and the first wiring information;
Determining that the first jitter value is less than or equal to the allowable jitter value;
Setting second arrangement information having a driving capability lower than that of the first arrangement information;
A third delay of the target path when the maximum value is supplied and a fourth delay of the target path when the minimum value is supplied for the target path specified by the second arrangement information. Calculating second wiring information that is a combination of the optimal wiring lengths of the subsequent stages of each of the plurality of cell types included in the second arrangement information when the difference between
Calculating a second jitter value based on the average power supply voltage for the target path defined by the second arrangement information and the second wiring information;
Determining whether the second jitter value exceeds the allowable jitter value;
A circuit design support method, comprising: determining the first arrangement information and the first wiring information as elements of the target path when the second jitter value exceeds the allowable jitter value. The circuit design support method according to claim 6,
Determining an element of the target path comprises:
When the second jitter value is less than or equal to the allowable jitter value, outputting a change instruction to change the combination of the number of logical stages of each of the plurality of cell types;
A circuit design support method, further comprising: setting, based on the change instruction, third arrangement information whose driving capability is lower than the first arrangement information. A circuit design support method according to claim 6 or 7,
Calculating a total wiring length of the target path;
A cell list in which each of the plurality of cell types having different driving capabilities arranged as an element of the target path is listed; a maximum number of logical stages of each of the plurality of cell types included in the cell list; Further comprising a step of setting a maximum wiring length to be connected to each subsequent stage of the cell type based on a user input,
The step of setting the first arrangement information includes:
Setting the first arrangement information based on the cell list and the maximum number of logical stages,
The step of calculating the first wiring information includes:
With respect to the target path defined by the first arrangement information, all combinations that can be taken as the wiring length of each subsequent stage of the plurality of cell types included in the first arrangement information, and the first arrangement information, Calculated by a linear programming method on condition of the total wiring length and the maximum wiring length, and the first delay and the second delay when the difference between the first delay and the second delay is minimum among all the combinations. 1 calculating the wiring information,
The step of setting the second arrangement information includes:
Setting the second arrangement information based on the cell list and the maximum number of logical stages,
The step of calculating the second wiring information includes:
With respect to the target path defined by the second arrangement information, all combinations that can be taken as the wiring length of each subsequent stage of the plurality of cell types included in the second arrangement information, and the second arrangement information, Calculated by a linear programming method on the condition of the total wiring length and the maximum wiring length, and the difference between the third delay and the fourth delay is minimized among all the combinations. 2. A circuit design support method including a step of calculating wiring information. A circuit design support method according to claim 8,
Further comprising setting a latency tolerance of the signal based on user input;
The step of calculating the first wiring information includes:
For the target path defined by the first arrangement information, all combinations that can be taken as the wiring length of the subsequent stage of each of the plurality of cell types included in the first arrangement information are included in the arrangement information and the total Calculating a secondary constraint planning problem on condition that the wiring length, the maximum wiring length, and the latency tolerance value are included,
The step of calculating the second wiring information includes:
For the target path defined by the second arrangement information, all combinations that can be taken as the wiring length of each subsequent stage of the plurality of cell types included in the second arrangement information are included in the arrangement information and the total A circuit design support method including a step of calculating by a linear programming method using a wiring length, the maximum wiring length, and the latency tolerance as a condition. Setting a target path that is a design target for propagating a signal, a period of the signal, and an allowable jitter value of the signal based on a user input;
Calculating an average power supply voltage obtained by averaging the power supply voltage supplied to the target path for each period, and a maximum value and a minimum value of the average power supply voltage;
Based on arrangement information that is a combination of the number of logical stages of each of a plurality of cell types having different driving capabilities arranged as elements of the target path, even if the power supply voltage fluctuates, variation in delay of the target path is small Determining an element of the target path,
Determining an element of the target path comprises:
Setting first arrangement information;
A first delay of the target path when the maximum value is supplied and a second delay of the target path when the minimum value is supplied for the target path specified by the first arrangement information. Calculating the first wiring information that is a combination of the optimal wiring lengths of the subsequent stages of each of the plurality of cell types included in the first arrangement information when the difference between
Calculating a first jitter value based on the average power supply voltage for the target path defined by the first arrangement information and the first wiring information;
Determining that the first jitter value exceeds the allowable jitter value;
Setting second arrangement information having higher driving ability than the first arrangement information;
A third delay of the target path when the maximum value is supplied and a fourth delay of the target path when the minimum value is supplied for the target path specified by the second arrangement information. Calculating second wiring information that is a combination of the optimal wiring lengths of the subsequent stages of each of the plurality of cell types included in the second arrangement information when the difference between
Calculating a second jitter value based on the average power supply voltage for the target path defined by the second arrangement information and the second wiring information;
Determining whether the second jitter value exceeds the allowable jitter value;
A circuit design support method comprising: determining the second arrangement information and the second wiring information as elements of the target path when the second jitter value is equal to or less than the allowable jitter value. A circuit design support program for causing a computer to execute the circuit design support method according to any one of claims 6 to 10.

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