JP2015127749A - Drawing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a drawing device capable of drawing a pattern image with resolution higher than beam pitch.SOLUTION: The drawing device comprises: a strength signal generation circuit for generating a strength signal indicating strength of laser beam on the basis of pattern image data; a drive part for generating a pixel radiation drive signal on the basis of the strength signal; and a laser element for radiating laser beam on the basis of the pixel radiation drive signal. When a pixel value of pixel of a processing object is the maximum value, and a pixel value of pixel adjacent to the pixel of the processing object in a sub-scanning direction orthogonal to a main scanning direction is larger than the minimum value and smaller than the maximum value, a pixel value/strength conversion circuit included in the strength signal generation circuit converts the pixel value of pixel of the processing object into a value of the strength signal of the pixel of the processing object, so that a beam spot formed on the object by the laser beam has a spot diameter larger than predetermined beam pitch.

Description

  The present invention relates to a drawing apparatus that draws a pattern image by irradiating an object such as a substrate with laser light.

  For example, for printed circuit board (PCB, PWB) manufacturing, semiconductor package circuit board manufacturing, flexible circuit board manufacturing, etc., a pattern image such as a wiring pattern is drawn by irradiating the exposed surface of the target printed circuit board or the like with a laser beam. A drawing device is used.

  As a configuration of the conventional drawing apparatus, for example, Patent Document 1 discloses pattern exposure including beam diameter invariant beam pitch reducing means for reducing the beam pitch in the sub-scanning direction perpendicular to the scanning direction without changing the beam diameter. An apparatus is disclosed. The beam diameter invariant beam pitch reducing means is composed of two plane reflecting surfaces and two reflecting surface groups having different surface intervals.

  In Patent Document 2, the inclination angle of the pattern boundary line intersecting the main scanning direction is detected, and control is performed so as to increase the printing spot diameter by the exposure beam at least at the boundary portion according to the detected inclination angle. An exposure beam control method is disclosed.

  Further, Patent Document 3 discloses an exposure apparatus provided with a light amount control unit and a data conversion unit. The data conversion unit creates multi-value light amount data expressing the pattern by the exposure pixel based on the binary pattern data expressing the pattern by the control pixel. The light amount control unit individually controls the light amounts of the plurality of beams formed by the plurality of micromirrors while controlling the plurality of micromirrors of the spatial light modulation device based on the light amount data. Thereby, the beam diameter of the beam is controlled at a control pitch smaller than the beam pitch.

  However, although the beam pitch or the beam diameter is changed in the configurations of the above Patent Documents 1 to 3, there is a problem that it is difficult to draw a pattern image with a resolution higher than the beam pitch.

  An object of the present invention is to solve the above problems and to provide a drawing apparatus capable of drawing a pattern image with a resolution higher than the beam pitch.

A drawing apparatus according to one embodiment of the present invention includes:
A drawing apparatus that draws a pattern image on an object by scanning a laser beam in a main scanning direction,
Based on the pattern image data of the pattern image, an intensity signal generation circuit that generates an intensity signal indicating the intensity of the laser beam for each pixel of the pixel value sequence in the main scanning direction in the pattern image data;
A drive unit that generates a pixel irradiation drive signal based on the intensity signal;
A laser element that emits laser light based on a pixel irradiation drive signal from the drive unit,
The intensity signal generation circuit is
When the pixel value of the processing target pixel is the maximum value, the pixel value of the pixel adjacent to the processing target pixel in the sub-scanning direction orthogonal to the main scanning direction is larger than the minimum value and larger than the maximum value. When it is small, the pixel value of the pixel to be processed is set as the intensity signal of the pixel to be processed so that the beam spot formed on the object by the laser beam has a spot diameter larger than a predetermined beam pitch. And a pixel value / intensity conversion circuit for converting to the above value.

  ADVANTAGE OF THE INVENTION According to this invention, the drawing apparatus which can draw a pattern image with the resolution higher than a beam pitch can be provided.

It is a block diagram which shows the structure of the drawing apparatus 1 which concerns on Embodiment 1 of this invention. It is a top view which shows the structure of the laser beam introduction part 12 of FIG. It is a longitudinal cross-sectional view of the glass substrate 23 of FIG. It is a top view of the output ends 22b-1 to 22b-4 of the optical fibers 22-1 to 22-4 of FIG. 2 held by the glass substrate 23 of FIG. 3A. It is a block diagram which shows the structure of the light source circuit 11 of FIG. It is a table | surface which shows the structure of the pattern image data 31d hold | maintained at the pattern image memory 31 of FIG. It is a table | surface which shows the structure of the pixel value row | line | column I (n) of the main scanning direction X of FIG. 5A. 5 is a flowchart showing a pixel value / intensity conversion process executed by a pixel value / intensity conversion circuit 54-1 in FIG. 5 is a flowchart showing a pixel value / intensity conversion process executed by a pixel value / intensity conversion circuit 54-2 in FIG. 5 is a flowchart showing a pixel value / intensity conversion process executed by a pixel value / intensity conversion circuit 54-3 in FIG. 5 is a flowchart showing a pixel value / intensity conversion process executed by a pixel value / intensity conversion circuit 54-4 in FIG. It is a table | surface which shows an example of the pixel value P (n, k) of the pixel unit of FIG. 5B. Based on the pixel value P (n, k) of the pixel unit of FIG. 7, the intensity signal Q (N, k) of the pixel unit set by the pixel value / intensity conversion circuits 54-1 to 54-4 of FIG. It is a table | surface which shows the value of Q (N + 3, k). FIG. 9 is a top view of the substrate 2 for explaining an exposure operation of the drawing apparatus 1 in FIG. 1 according to the intensity signal Q (n, k) in pixel units in FIG. 8. It is a top view of a board | substrate for demonstrating the exposure operation | movement of the drawing apparatus of a comparative example. It is a block diagram which shows the structure of 1 A of drawing apparatuses which concern on Embodiment 2 of this invention. It is a block diagram which shows the structure of 11 A of light source circuits of FIG. It is a figure which shows the structure of arrangement | positioning of the pixel P0 of the process target which has the pixel value P (N, k) referred by the sub pixel pattern estimation part 60-1 of FIG. 12, and its surrounding pixels P1-P8. It is a figure which shows the structure of the sub pixel pattern of pixel P0 of the process target of FIG. 13a. It is a flowchart which shows the pixel value / intensity conversion process performed by the pixel value / intensity conversion circuit 54A-1 of FIG. It is a flowchart which shows the pixel value / intensity conversion process performed by the pixel value / intensity conversion circuit 54A-2 of FIG. It is a flowchart which shows the pixel value / intensity conversion process performed by the pixel value / intensity conversion circuit 54A-3 of FIG. It is a flowchart which shows the pixel value / intensity conversion process performed by the pixel value / intensity conversion circuit 54A-4 of FIG. 13A is a table 60mt1 for estimating a sub-pixel pattern of a pixel P0 to be processed when the pixel value P (N, k) of the pixel P0 to be processed in FIG. 13A is 1. (A) is a figure which shows the structure of the subpixel patterns SP11-SP14 of the area 1 corresponding to the pattern numbers 13-16 of FIG. 15, respectively, (b) is each corresponding to the pattern numbers 5-12 of FIG. It is a figure which shows the structure of subpixel pattern SP21-SP28 of the area 2 to perform, (c) is a figure which shows the structure of subpixel pattern SP31-SP34 of the area 3 respectively corresponding to the pattern numbers 1-4 of FIG. is there. 13A is a table 60mt2 for estimating a sub-pixel pattern of the processing target pixel P0 when the pixel value P (N, k) of the processing target pixel P0 of FIG. 13A is 2. (A) is a figure which shows the structure of the subpixel patterns SP41-SP44 of the area 4 corresponding to the pattern numbers 9-12 of FIG. 17, respectively, (b) respond | corresponds to the pattern numbers 5-8 of FIG. 17, respectively. It is a figure which shows the structure of subpixel pattern SP51-SP54 of the area 5 to perform, (c) is a figure which shows the structure of subpixel pattern SP61-SP64 of the area 6 respectively corresponding to the pattern numbers 1-4 of FIG. is there. 13B is a table 60mt3 for estimating a sub-pixel pattern of the processing target pixel P0 when the pixel value P (N, k) of the processing target pixel P0 of FIG. 13A is 3. (A) is a figure which shows the structure of the subpixel patterns SP71-SP78 of the area 7 corresponding to the pattern numbers 5-12 of FIG. 19, respectively, (b) respond | corresponds to the pattern numbers 1-4 of FIG. 19, respectively. FIG. 20C is a diagram illustrating a configuration of a sub-pixel pattern SP91 having an area 9 corresponding to the pattern number 13 in FIG. 19. FIG. 12 is a top view of the substrate 2 for explaining an example of the exposure operation of the drawing apparatus 1 </ b> A of FIG. 11. FIG. 12 is a top view of the substrate 2 for explaining another example of the exposure operation of the drawing apparatus 1A of FIG. (A)-(c) is a figure which shows the subpixel pattern of the areas 1-3 based on the modification of Embodiment 2 of this invention, respectively. It is a figure which shows an example of the pattern image comprised by the sub pixel pattern of FIG. FIG. 25 is a top view of the substrate 2 for explaining the exposure operation of the drawing apparatus 1A of FIG. 11 according to the subpixel pattern of FIG. 24.

  Hereinafter, embodiments according to the present invention will be described with reference to the drawings. In addition, in each following embodiment, the same code | symbol is attached | subjected about the same component.

Embodiment 1. FIG.
FIG. 1 is a block diagram showing a configuration of a drawing apparatus 1 according to Embodiment 1 of the present invention. In FIG. 1, a drawing apparatus 1 generates laser beams B1 to B4 on an exposure surface 2a of a substrate 2 such as a printed board, a glass substrate, a dielectric substrate, or a semiconductor substrate that is an object for drawing a pattern image. A pattern image is drawn by irradiation. For example, the drawing apparatus 1 is disposed on a board manufacturing apparatus such as a printed circuit board (PCB, PWB) manufacturing apparatus, a semiconductor package board manufacturing apparatus, or a flexible board manufacturing apparatus.

  In FIG. 1, a drawing apparatus 1 includes a light source circuit 11, a laser light introducing unit 12, a condensing lens 13, a cylindrical lens 14, a polygon mirror 15, an fθ lens 16, a stage 17, and a sub-scanning conveyance unit. 18. Here, the substrate 2 is disposed on the stage 17 so that the upper surface of the substrate 2 faces the upward direction Z. Further, an exposure surface 2 a coated with a photosensitive agent (photoresist) or the like is formed on the upper surface of the substrate 2.

  The light source circuit 11 generates and emits four laser beams B1 to B4. The configuration of the light source circuit 11 will be described later in detail with reference to FIG. The laser beams B1 to B4 from the light source circuit 11 travel through the laser beam introducing unit 12, the condensing lens 13, and the cylindrical lens 14 and are reflected on each mirror surface arranged on the side surface of the polygon mirror 15, and are fθ lenses. 16 reaches the exposure surface 2 a of the substrate 2.

  FIG. 2 is a plan view showing the configuration of the laser beam introducing section 12 of FIG. In FIG. 2, the laser light introducing unit 12 includes lenses 21-1 to 21-4, optical fibers 22-1 to 22-4, and a glass substrate 23. The lenses 21-1 to 21-4 converge the laser beams B1 to B4 from the light source circuit 11 and introduce them to the incident ends 22a-1 to 22a-4 of the optical fibers 22-1 to 22-4, respectively.

  3A is a longitudinal sectional view of the glass substrate 23 of FIG. In FIG. 3A, the glass substrate 23 has four grooves, which are formed by V-cut processing or the like and have a predetermined interval L of, for example, 400 μm and are parallel to each other on the upper surface. In addition, the glass substrate 23 includes the optical fibers 22-1 to 22-4 so that the emission ends 22b-1 to 22b-4 of the optical fibers 22-1 to 22-4 are arranged in a one-dimensional array in the four grooves. The portions on the emission ends 22b-1 to 22b-4 side are respectively fixed and held. 3B is a plan view of the emission ends 22b-1 to 22b-4 of the optical fibers 22-1 to 22-4 of FIG. 2 held by the glass substrate 23 of FIG. 3A. In FIG. 3B, the glass substrate 23 is arranged so that the emission ends 22b-1 to 22b-4 of the optical fibers 22-1 to 22-4 are arranged along a direction different from the main scanning direction X (hereinafter also referred to as X direction). The direction of the glass substrate 23 is adjusted to be fixed to the laser light introducing portion 12 and arranged. Specifically, the emission ends 22b-1 to 22b-4 are, for example, 5 μm beams having a size in the sub-scanning direction Y (hereinafter also referred to as Y direction) orthogonal to the main scanning direction X of one pixel. They are juxtaposed so as to be spaced apart from adjacent emission ends by a pitch D. The laser beam introducing section 12 having the glass substrate 23 configured as described above converts the laser beams B1 to B4 from the light source circuit 11 into a multi-beam array arranged at a predetermined interval L, and the subsequent condenser lens 13 and It is introduced into the cylindrical lens 14.

  In FIG. 1, the condenser lens 13 has a focal length substantially equal to the distance from the condenser lens 13 to the mirror surface of the polygon mirror 15. Each of the laser beams B <b> 1 to B <b> 4 emitted as diverging light from the laser beam introducing unit 12 becomes substantially parallel light by the condenser lens 13. The cylindrical lens 14 deflects the laser beams B1 to B4 so that the beam spots of the laser beams B1 to B4 formed on the exposure surface 2a of the substrate 2 are arranged in a line in the sub-scanning direction Y at intervals of the beam pitch D. To do. The polygon mirror 15 has a hexagonal prism shape, and its central axis 15C is arranged in a direction parallel to the sub-scanning direction Y, and is rotatably arranged with the central axis 15C as a rotation axis. When the polygon mirror 15 is driven and rotated by a motor or the like (not shown) disposed in the drawing apparatus 1, the laser beams B 1 to B 4 are reflected to the fθ lens 16 at each mirror surface disposed on the side surface of the polygon mirror 15. To do. At this time, the laser beams B1 to B4 are deflected in the main scanning direction X as the polygon mirror 15 rotates. The fθ lens 16 deflects the laser beams B1 to B4 from the polygon mirror 15 in a direction substantially perpendicular to the upper surface of the stage 17, and the laser beams B1 to B4 are exposed on the exposure surface 2a of the substrate 2 disposed on the stage 17. Is incident at a substantially right angle to. The beam spots of the laser beams B1 to B4 formed on the exposure surface 2a move in the main scanning direction X at a speed corresponding to the rotational speed of the polygon mirror 15 while being aligned in the sub scanning direction Y at intervals of the beam pitch D. To do. Thus, the laser beams B1 to B4 irradiate the exposure surface 2a and simultaneously scan four scanning rows in the main scanning direction X.

  The sub-scan transport unit 18 includes, for example, a ball screw, a motor, and the like. The stage 17 is moved together with the substrate 2 to a beam pitch D of 4 in synchronization with a clock of one main scanning cycle (hereinafter referred to as a main scanning clock). It is moved in the sub-scanning direction Y by a distance 4D that is a double distance. The laser beam B1 to B4 irradiates the exposure surface 2a and scans in the main scanning direction X, and the sub-scanning transport unit 18 moves the substrate 2 in the sub-scanning direction Y, whereby the drawing apparatus 1 is exposed to the exposure surface of the substrate 2. A pattern image such as a wiring pattern is drawn on 2a.

  FIG. 4 is a block diagram showing a configuration of the light source circuit 11 of FIG. In FIG. 4, a light source circuit 11 includes a pattern image memory 31, a readout circuit 32 having line buffers 32a-1 to 32a-6, and an intensity signal that generates and outputs an intensity signal indicating the intensity of laser light in multiple values. And generating circuits 33-1 to 33-4. The light source circuit 11 includes D / A converters 34-1 to 34-4, drive units 35-1 to 35-4, and laser elements 36a-1 to 36a-4 disposed on the semiconductor substrate 36. It is configured with. Here, the intensity signal generation circuit 33-1 includes registers 51-1 to 53-1 and a pixel value / intensity conversion circuit 54-1, and the intensity signal generation circuit 33-2 includes the register 51-. 2 to 53-2 and a pixel value / intensity conversion circuit 54-2. The intensity signal generation circuit 33-3 includes registers 51-3 to 53-3 and a pixel value / intensity conversion circuit 54-3. The intensity signal generation circuit 33-4 includes the register 51-4. To 53-4 and a pixel value / intensity conversion circuit 54-4.

  In the following description, the intensity signal generation circuits 33-1 to 33-4 are collectively referred to as an intensity signal generation circuit 33. Further, the registers 51-1 to 51-4 are collectively referred to as the register 51, the registers 52-1 to 52-4 are collectively referred to as the register 52, and the registers 53-1 to 53-4 are collectively referred to as the register 53. Also called. Further, the pixel value / intensity conversion circuits 54-1 to 54-4 are collectively referred to as a pixel value / intensity conversion circuit 54. Furthermore, the D / A converters 34-1 to 34-4, the drive units 35-1 to 35-4, the laser elements 36a-1 to 36a-4, and the laser beams B1 to B4 are collectively referred to as D / Also referred to as A converter 34, drive unit 35, laser element 36, and laser beam B.

  FIG. 5A is a table showing the configuration of pattern image data 31d held in the pattern image memory 31 of FIG. In FIG. 5A, pattern image data 31d is image data indicating a pattern image to be drawn on the exposure surface 2a of the substrate 2, and Npy pixel value sequences I (n) (0 ≦ n ≦) in the main scanning direction X. Npy-1) are juxtaposed in the sub-scanning direction Y. FIG. 5B is a table showing the configuration of the pixel value sequence I (n) in the main scanning direction X of FIG. 5A. In FIG. 5B, a pixel value column I (n) in the main scanning direction X has Npx pixel unit pixel values P (n, k) (0 ≦ k ≦ Npx−1) arranged in the main scanning direction X. Composed.

  In FIG. 5B, each pixel value P (n, k) in pixel units is from a minimum value 0 to a maximum that is proportional to the area of a part of the irradiation region of the laser beam B in the pixel region at the time k in the nth scan column. The size up to value 3 is represented by 2 bits. The value 0 of the pixel value P (n, k) is one of the laser beams B whose pixel area of the pixel value P (n, k) is not less than 0 times and less than (1/9) times the pixel area. It shows that the irradiation area | region of a part is included. The value 1 of the pixel value P (n, k) is such that the pixel area of the pixel value P (n, k) is, for example, (1/9) times or more and less than (4/9) times the pixel area. It shows that the irradiation area | region of some laser beams B is included. Further, the value 2 of the pixel value P (n, k) is such that the pixel area of the pixel value P (n, k) is, for example, (4/9) times or more and less than (7/9) times the pixel area. It shows that the irradiation area | region of some laser beams B is included. Further, the value 3 of the pixel value P (n, k) indicates that the pixel region of the pixel value P (n, k) is a laser beam having a size that is, for example, (7/9) times or more and 1 time or less of the pixel region. B indicates that a part of the irradiation region is included.

  In FIG. 4, a readout circuit 32 reads out six pixel value sequences I (N−1) to I (N + 4) in the main scanning direction X of FIG. 5A from the pattern image memory 31 in synchronization with the main scanning clock, and each line The operation of storing in the buffers 32a-1 to 32a-6 is repeated. Here, the number N is a multiple of 4 that is greater than or equal to 0 and less than or equal to Npy−1, and the readout circuit 32 starts the number N from 0 in synchronization with the main scanning clock while N ≦ Npy−1 is satisfied. Then, the above operation is repeated while increasing by 4. Note that the pixel value sequence I (−1) or I (Npy) to I (Npy + 3) in the main scanning direction X is, for example, an array of length Npx composed of only the pixel value 0. Stored.

  Further, the readout circuit 32 has pixel values P (N−1, k) to P (N + 4, k) (0 ≦ 0) included in the pixel value columns I (N−1) to I (N + 4) in the main scanning direction X, respectively. The operation of sequentially outputting k ≦ Npx−1) is repeated. In other words, the readout circuit 32 at each time k between time k = 0 and time k = Npx−1 counted in synchronization with a clock of a drawing period T of one pixel (hereinafter referred to as pixel clock). Repeat the above output operation. Specifically, at each time k, the readout circuit 32 outputs the pixel values P (N−1, k) to P (N + 1, k) to the registers 51-1 to 53-1 respectively. The readout circuit 32 outputs the pixel values P (N, k) to P (N + 2, k) to the registers 51-2 to 53-2, respectively. Further, the readout circuit 32 outputs the pixel values P (N + 1, k) to P (N + 3, k) to the registers 51-3 to 53-3, respectively. Furthermore, the readout circuit 32 outputs the pixel values P (N + 2, k) to P (N + 4, k) to the registers 51-4 to 53-4, respectively.

  Each of the intensity signal generation circuits 33-1 to 33-4 is configured by a dedicated hardware circuit for executing the pixel value / intensity conversion processing of FIGS. 6A to 6D on the fly at the time of drawing a pattern image. The pixel value / intensity conversion process in FIGS. 6A to 6D will be described later in detail.

  In the intensity signal generation circuit 33-1, the pixel value / intensity conversion circuit 54-1 includes pixel values P (N−1, k) ˜ stored in the registers 51-1 to 53-1 at each time k. P (N + 1, k) is read, and the pixel value / intensity conversion process of FIG. 6A is executed. In the pixel value / intensity conversion process of FIG. 6A, the pixel value / intensity conversion circuit 54-1 converts the pixel values P (N-1, k) to P (N + 1, k) into digital signals indicating the intensity of the laser beam B1. Is converted into an intensity signal Q (N, k) in pixel units and output to the D / A converter 34-1. The pixel value / intensity conversion process of FIG. 6A by the pixel value / intensity conversion circuit 54-1 will be described in detail later. The D / A converter 34-1 converts the intensity signal Q (N, k) into an analog intensity signal and outputs it to the drive unit 35-1. The drive unit 35-1 supplies a pixel irradiation drive signal corresponding to the analog intensity signal to the laser element 36a-1. The laser element 36a-1 emits a laser beam B1 with an intensity corresponding to the pixel irradiation drive signal.

  In the intensity signal generation circuit 33-2, the pixel value / intensity conversion circuit 54-2 includes pixel values P (N, k) to P (N + 2, k) stored in the registers 51-2 to 53-2, respectively. ) And the pixel value / intensity conversion process of FIG. 6B is executed. In the pixel value / intensity conversion process of FIG. 6B, the pixel value / intensity conversion circuit 54-2 is a digital signal indicating the intensity of the laser beam B2 with the pixel values P (N, k) to P (N + 2, k). It is converted into an intensity signal Q (N + 1, k) in pixel units and output to the D / A converter 34-2. The pixel value / intensity conversion process of FIG. 6B by the pixel value / intensity conversion circuit 54-2 will be described in detail later. The D / A converter 34-2 D / A converts the intensity signal Q (N + 1, k) into an analog intensity signal and outputs it to the drive unit 35-2. The drive unit 35-2 supplies a pixel irradiation drive signal corresponding to the analog intensity signal to the laser element 36a-2. The laser element 36a-2 emits a laser beam B2 with an intensity corresponding to the pixel irradiation drive signal.

  Further, in the intensity signal generation circuit 33-3, the pixel value / intensity conversion circuit 54-3 includes pixel values P (N + 1, k) to P (N + 3, k) stored in the registers 51-3 to 53-3, respectively. ) And the pixel value / intensity conversion process of FIG. 6C is executed. In the pixel value / intensity conversion process of FIG. 6C, the pixel value / intensity conversion circuit 54-3 is a digital signal indicating the intensity of the laser beam B3 with the pixel values P (N + 1, k) to P (N + 3, k). It is converted into an intensity signal Q (N + 2, k) in pixel units and output to the D / A converter 34-3. The pixel value / intensity conversion process of FIG. 6C by the pixel value / intensity conversion circuit 54-3 will be described in detail later. The D / A converter 34-3 D / A converts the intensity signal Q (N + 2, k) into an analog intensity signal and outputs it to the drive unit 35-3. The drive unit 35-3 supplies a pixel irradiation drive signal corresponding to the analog intensity signal to the laser element 36a-3. The laser element 36a-3 emits a laser beam B3 with an intensity corresponding to the pixel irradiation drive signal.

  Furthermore, in the intensity signal generation circuit 33-4, the pixel value / intensity conversion circuit 54-4 includes pixel values P (N + 2, k) to P (N + 4, respectively) stored in the registers 51-4 to 53-4. k) is read out and the pixel value / intensity conversion process of FIG. 6D is executed. In the pixel value / intensity conversion process of FIG. 6D, the pixel value / intensity conversion circuit 54-4 is a digital signal indicating the intensity of the laser beam B4 with the pixel values P (N + 2, k) to P (N + 4, k). It converts into the intensity signal Q (N + 3, k) of a pixel unit, and outputs it to D / A converter 34-4. The pixel value / intensity conversion process of FIG. 6D by the pixel value / intensity conversion circuit 54-4 will be described in detail later. The D / A converter 34-4 D / A converts the intensity signal Q (N + 3, k) into an analog intensity signal and outputs it to the drive unit 35-4. The drive unit 35-4 supplies a pixel irradiation drive signal corresponding to the analog intensity signal to the laser element 36a-4. The laser element 36a-4 emits a laser beam B4 with an intensity corresponding to the pixel irradiation drive signal.

  The intensity signal Q (n, k) in units of pixels output from the pixel value / intensity conversion circuit 54 in FIG. 4 will be described below. The intensity signal Q (n, k) represents the magnitude of 0 to 3 with 2 bits. The value 0 of the intensity signal Q (n, k) indicates the intensity of the laser beam B with power 0 (hereinafter referred to as intensity 0). The value 1 of the intensity signal Q (n, k) is a laser that forms a beam spot on the exposure surface 2a of the substrate 2 having a spot diameter smaller than the predetermined beam pitch D by, for example, about 30% of the beam pitch D. The intensity of light B (hereinafter referred to as intensity 1) is shown. The value 2 of the intensity signal Q (n, k) is the intensity of the laser beam B (hereinafter referred to as intensity 2) that forms a beam spot having a spot diameter substantially equal to the beam pitch D on the exposure surface 2a of the substrate 2. Show. The value 3 of the intensity signal Q (n, k) is a laser beam B that forms a beam spot on the exposure surface 2a of the substrate 2 having a spot diameter larger than the beam pitch D by, for example, about 30% of the beam pitch D. Strength (hereinafter referred to as strength 3). When the pixel value / intensity conversion circuit 54 outputs the intensity signal Q (n, k) in units of pixels, the drive unit 35 causes the laser element 36 to have an intensity 0 to 3 corresponding to the value of the intensity signal Q (n, k). The pixel irradiation drive signal is supplied to the laser element 36 so that the laser beam B is emitted.

  FIG. 6A is a flowchart showing a pixel value / intensity conversion process executed by the pixel value / intensity conversion circuit 54-1 of FIG. In step S1 of FIG. 6A, the pixel value / intensity conversion circuit 54-1 determines whether or not the pixel value P (N, k) is zero. In the case of YES in step S1, in step S2, the pixel value / intensity conversion circuit 54-1 sets the value of the intensity signal Q (N, k) to 0 and proceeds to step S11.

  When it is determined that the pixel value P (N, k) is not 0 (NO in step S1), in step S3, the pixel value / intensity conversion circuit 54-1 has a pixel value P (N, k) of 1. It is determined whether or not there is. If YES in step S3, in step S4, the pixel value / intensity conversion circuit 54-1 has a pixel value P (N-1, k) of 3 or a pixel value P (N + 1, k) of 3. Determine whether or not. If YES in step S4, the process proceeds to step S2. In the case of NO in step S4, in step S5, the pixel value / intensity conversion circuit 54-1 sets the value of the intensity signal Q (N, k) to 1, and proceeds to step S11.

  If it is determined that the pixel value P (N, k) is not 1 (NO in step S3), the pixel value / intensity conversion circuit 54-1 determines that the pixel value P (N, k) is 2 in step S6. It is determined whether or not there is. If YES in step S6, in step S7, the pixel value / intensity conversion circuit 54-1 has a pixel value P (N-1, k) of 3 or a pixel value P (N + 1, k) of 3. Determine whether or not. If YES in step S7, the process proceeds to step S5. In the case of NO in step S7, in step S8, the pixel value / intensity conversion circuit 54-1 sets the value of the intensity signal Q (N, k) to 2, and proceeds to step S11.

  When it is determined that the pixel value P (N, k) is not 2 (NO in step S6), in step S9, the pixel value / intensity conversion circuit 54-1 determines that the pixel value P (N-1, k) is It is determined whether 1 or 2 or the pixel value P (N + 1, k) is 1 or 2. In the case of YES in step S9, in step S10, the pixel value / intensity conversion circuit 54-1 sets the value of the intensity signal Q (N, k) to 3, and proceeds to step S11. If NO in step S9, the process proceeds to step S8.

  In step S11, the pixel value / intensity conversion circuit 54-1 generates an intensity signal Q (N, k) in pixel units having the value set in step S2, S5, S8, or S10, and performs D / A conversion. The pixel value / intensity conversion process in FIG. 6A is terminated.

  FIG. 6B is a flowchart showing a pixel value / intensity conversion process executed by the pixel value / intensity conversion circuit 54-2 in FIG. In step S21 of FIG. 6B, the pixel value / intensity conversion circuit 54-2 determines whether or not the pixel value P (N + 1, k) is zero. In the case of YES in step S21, in step S22, the pixel value / intensity conversion circuit 54-2 sets the value of the intensity signal Q (N + 1, k) to 0 and proceeds to step S31.

  When it is determined that the pixel value P (N + 1, k) is not 0 (NO in step S21), in step S23, the pixel value / intensity conversion circuit 54-2 indicates that the pixel value P (N + 1, k) is 1. It is determined whether or not there is. If YES in step S23, in step S24, the pixel value / intensity conversion circuit 54-2 determines whether the pixel value P (N, k) is 3 or the pixel value P (N + 2, k) is 3. Determine. If YES in step S24, the process proceeds to step S22. In the case of NO in step S24, in step S25, the pixel value / intensity conversion circuit 54-2 sets the value of the intensity signal Q (N + 1, k) to 1, and proceeds to step S31.

  When it is determined that the pixel value P (N + 1, k) is not 1 (NO in step S23), in step S26, the pixel value / intensity conversion circuit 54-2 indicates that the pixel value P (N + 1, k) is 2. It is determined whether or not there is. If YES in step S26, in step S27, the pixel value / intensity conversion circuit 54-2 determines whether the pixel value P (N, k) is 3 or the pixel value P (N + 2, k) is 3. Determine. If YES in step S27, the process proceeds to step S25. In the case of NO in step S27, in step S28, the pixel value / intensity conversion circuit 54-2 sets the value of the intensity signal Q (N + 1, k) to 2, and proceeds to step S31.

  When it is determined that the pixel value P (N + 1, k) is not 2 (NO in step S26), in step S29, the pixel value / intensity conversion circuit 54-2 determines that the pixel value P (N, k) is 1 or Whether or not the pixel value P (N + 2, k) is 1 or 2 is determined. In the case of YES in step S29, in step S30, the pixel value / intensity conversion circuit 54-2 sets the value of the intensity signal Q (N + 1, k) to 3, and proceeds to step S31. If NO in step S29, the process proceeds to step S28.

  In step S31, the pixel value / intensity conversion circuit 54-2 generates an intensity signal Q (N + 1, k) in units of pixels having the value set in step S22, S25, S28, or S30 to generate a D / A converter. 34-2, and the pixel value / intensity conversion process of FIG. 6B is terminated.

  FIG. 6C is a flowchart showing a pixel value / intensity conversion process executed by the pixel value / intensity conversion circuit 54-3 of FIG. In step S41 of FIG. 6C, the pixel value / intensity conversion circuit 54-3 determines whether or not the pixel value P (N + 2, k) is zero. In the case of YES in step S41, in step S42, the pixel value / intensity conversion circuit 54-3 sets the value of the intensity signal Q (N + 2, k) to 0 and proceeds to step S51.

  If it is determined that the pixel value P (N + 2, k) is not 0 (NO in step S41), the pixel value P (N + 2, k) is 1 in step S43. It is determined whether or not there is. If YES in step S43, in step S44, the pixel value / intensity conversion circuit 54-3 determines whether the pixel value P (N + 1, k) is 3 or the pixel value P (N + 3, k) is 3. Determine. If YES in step S44, the process proceeds to step S42. In the case of NO in step S44, in step S45, the pixel value / intensity conversion circuit 54-3 sets the value of the intensity signal Q (N + 2, k) to 1, and proceeds to step S51.

  When it is determined that the pixel value P (N + 2, k) is not 1 (NO in step S43), in step S46, the pixel value / intensity conversion circuit 54-3 determines that the pixel value P (N + 2, k) is 2. It is determined whether or not there is. If YES in step S46, in step S47, the pixel value / intensity conversion circuit 54-3 determines whether the pixel value P (N + 1, k) is 3 or the pixel value P (N + 3, k) is 3. Determine. If YES in step S47, the process proceeds to step S45. In the case of NO in step S47, in step S48, the pixel value / intensity conversion circuit 54-3 sets the value of the intensity signal Q (N + 2, k) to 2, and proceeds to step S51.

  When it is determined that the pixel value P (N + 2, k) is not 2 (NO in step S46), in step S49, the pixel value / intensity conversion circuit 54-3 determines that the pixel value P (N + 1, k) is 1 or Whether or not the pixel value P (N + 3, k) is 1 or 2 is determined. In the case of YES in step S49, in step S50, the pixel value / intensity conversion circuit 54-3 sets the value of the intensity signal Q (N + 2, k) to 3, and proceeds to step S51. If NO in step S49, the process proceeds to step S48.

  In step S51, the pixel value / intensity conversion circuit 54-3 generates the intensity signal Q (N + 2, k) in units of pixels having the value set in step S42, S45, S48, or S50 to generate a D / A converter. 34-3, and the pixel value / intensity conversion process in FIG. 6C is terminated.

  FIG. 6D is a flowchart showing a pixel value / intensity conversion process executed by the pixel value / intensity conversion circuit 54-4 of FIG. In step S61 in FIG. 6D, the pixel value / intensity conversion circuit 54-4 determines whether or not the pixel value P (N + 3, k) is zero. If YES in step S61, the pixel value / intensity conversion circuit 54-4 sets the value of the intensity signal Q (N + 3, k) to 0 in step S62, and the process proceeds to step S71.

  If it is determined that the pixel value P (N + 3, k) is not 0 (NO in step S61), in step S63, the pixel value / intensity conversion circuit 54-4 determines that the pixel value P (N + 3, k) is 1. It is determined whether or not there is. If YES in step S63, in step S64, the pixel value / intensity conversion circuit 54-4 determines whether the pixel value P (N + 2, k) is 3 or the pixel value P (N + 4, k) is 3. Determine. If YES in step S64, the process proceeds to step S62. In the case of NO in step S64, in step S65, the pixel value / intensity conversion circuit 54-4 sets the value of the intensity signal Q (N + 3, k) to 1, and proceeds to step S71.

  If it is determined that the pixel value P (N + 3, k) is not 1 (NO in step S63), the pixel value / intensity conversion circuit 54-4 determines that the pixel value P (N + 3, k) is 2 in step S66. It is determined whether or not there is. In the case of YES in step S66, in step S67, the pixel value / intensity conversion circuit 54-4 determines whether the pixel value P (N + 2, k) is 3 or the pixel value P (N + 4, k) is 3. Determine. If YES in step S67, the process proceeds to step S65. In the case of NO in step S67, in step S68, the pixel value / intensity conversion circuit 54-4 sets the value of the intensity signal Q (N + 3, k) to 2, and proceeds to step S71.

  When it is determined that the pixel value P (N + 3, k) is not 2 (NO in step S66), in step S69, the pixel value / intensity conversion circuit 54-4 determines that the pixel value P (N + 2, k) is 1 or 2 or whether or not the pixel value P (N + 4, k) is 1 or 2 is determined. If YES in step S69, in step S70, the pixel value / intensity conversion circuit 54-4 sets the value of the intensity signal Q (N + 3, k) to 3, and proceeds to step S71. If NO in step S69, the process proceeds to step S68.

  In step S71, the pixel value / intensity conversion circuit 54-4 generates an intensity signal Q (N + 3, k) in units of pixels having the value set in step S62, S65, S68, or S70 to generate a D / A converter. 34-4, and the pixel value / intensity conversion process of FIG. 6D is terminated.

  The operation of the drawing apparatus 1 configured as described above will be described below.

  FIG. 7 is a table showing an example of the pixel value P (n, k) of the pixel unit in FIG. 5B. The pattern image composed of the pixel values P (n, k) in FIG. 7 has a line and space (L / S) such as 15 μm / 15 μm, 25 μm / 25 μm, etc., which is 3 to 5 times larger than the beam pitch D, for example. A part of the pattern image which is a wiring pattern is shown. Therefore, the pattern image is composed of three or five or more connected pixels at a distance in the main scanning direction X and a distance in the sub-scanning direction Y. FIG. 8 shows pixel-by-pixel intensity signals Q (N) set by the pixel value / intensity conversion circuits 54-1 to 54-4 in FIG. 4 on the basis of the pixel value P (n, k) in FIG. , K) to Q (N + 3, k).

  7 and 8, pixel values P (N−1, k) to P (N + 4, k) are 0, 0, 1, 3, 3, and 3 at times k = 0 and 1, respectively. At this time, since the pixel value P (N + 1, k) is 1 and the pixel value P (N + 2, k) is 3, the pixel value / intensity conversion circuit 54-2 in FIG. 4 has the intensity signal Q (N + 1, k). The value of k) is set to 0 (S22). In addition, since the pixel value P (N + 2, k) is 3 and the pixel value P (N + 1, k) is 1, the pixel value / intensity conversion circuit 54-3 has the intensity signal Q (N + 2, k). Is set to 3 (S50).

  At each time k = 2, 3, the pixel values P (N-1, k) to P (N + 4, k) are 0, 0, 2, 3, 3, 3 respectively. At this time, since the pixel value P (N + 1, k) is 2 and the pixel value P (N + 2, k) is 3, the pixel value / intensity conversion circuit 54-2 in FIG. 4 has the intensity signal Q (N + 1, k). The value of k) is set to 1 (S25). In addition, since the pixel value P (N + 2, k) is 3 and the pixel value P (N + 1, k) is 2, the pixel value / intensity conversion circuit 54-3 has the intensity signal Q (N + 2, k). Is set to 3 (S50).

  Further, at each time k = 4, 5, the pixel values P (N−1, k) to P (N + 4, k) are 0, 0, 3, 3, 3, and 3, respectively. At this time, in the pixel value / intensity conversion circuit 54-2 in FIG. 4, the pixel value P (N + 1, k) is 3, and both the pixel values P (N, k) and P (N + 2, k) are Since it is neither 1 nor 2, the value of the intensity signal Q (N + 1, k) is set to 2 (S28). Further, the pixel value / intensity conversion circuit 54-3 has the pixel value P (N + 2, k) of 3 and the pixel values P (N + 1, k) and P (N + 3, k) are neither 1 nor 2. The value of the intensity signal Q (N + 2, k) is set to 2 (S48).

  At each time k = 0 to 5, the pixel value / intensity conversion circuits 54-1 to 54-4 respectively have the intensity signals Q (N, k) to Q (N + 3, k) of FIG. 8 having the values set as described above. ) To the D / A converters 34-1 to 34-4. The laser elements 36a-1 to 36a-4 emit laser beams B1 to B4 with intensities corresponding to the set intensity signals Q (N, k) to Q (N + 3, k) in FIG.

  FIG. 9 is a top view of the substrate 2 for explaining the exposure operation of the drawing apparatus 1 of FIG. 1 according to the intensity signal Q (n, k) in pixel units of FIG. 9 shows a pattern image drawn on the exposure surface 2a of the substrate 2 by the drawing apparatus 1 based on the intensity signal Q (n, k) shown in FIG. Each of the laser beams B1 to B4 scans the Nth to (N + 3) th scanning rows with the intensity corresponding to the intensity signals Q (N, k) to Q (N + 3, k) in FIG. The center lines L1 to L4 of the Nth to (N + 3) th scan rows are arranged in parallel at intervals of the beam pitch D, and the regions of the Nth to (N + 3) th scan rows scanned by the laser beams B1 to B4 are beams. It has a width of pitch D. In addition, the circle drawn in FIG. 9 shows the spot diameter of the beam spot of laser beam B1-B4 irradiated to the exposure surface 2a. In addition, for the sake of convenience, the solid grid indicates a 1-pixel area having a size of, for example, 5 μm × 5 μm, and the broken-line grid indicates a 1 sub-pixel area for convenience. One pixel area is composed of 3 × 3 subpixels.

  In FIG. 9, at each time k = 0, 1, the value of the intensity signal Q (N + 1, k) in units of pixels is set to 0 by the pixel value / intensity conversion circuit 54-2. For this reason, the laser element 36a-2 emits a laser beam B2 having an intensity of 0, which means that the laser element 36a-2 does not emit the laser beam B2. However, the spot diameter of the laser beam B3 of intensity 3 irradiated to the area of the (N + 2) th scan column that is the subsequent scan column is formed larger than the beam pitch D by, for example, 30% of the beam pitch D. As such, it is slightly adjusted to overdrive. By scanning the (N + 2) th scan row with the laser beam B3 having an intensity of 3 and overexposing the exposure surface 2a, the laser beam B3 follows the beam center line L2 in the region of the (N + 1) th scan row. The pattern image is exposed so as to be resolved in a region located on the side. As a result, as shown in FIG. 9, the boundary of the region exposed in the (N + 1) th scan row region is, for example, two thirds of pixels (2 subpixels) from the border contacting the Nth scan row region. Is shifted in the sub-scanning line direction Y by the distance of.

  At each time k = 2, 3, the value of the intensity signal Q (N + 1, k) in units of pixels is set to 1 by the pixel value / intensity conversion circuit 54-1, so that the laser element 36a-2 has an intensity of 1. The laser beam B2 is emitted. At this time, an area having a width of, for example, about 30% of the beam pitch D, which is smaller than the beam pitch D around the center line L2, is exposed by the laser light B2. Further, the spot diameter of the laser beam B3 having intensity 3 irradiated to the region of the (N + 2) th scan column that is the subsequent scan column is formed to be larger than the beam pitch D by, for example, 30% of the beam pitch D. As such, it is slightly adjusted to overdrive. Therefore, in the (N + 1) -th main scanning row, a region having a width of, for example, about 60% of the beam pitch D on the boundary side with the region of the (N + 2) -th main scanning row in the subsequent row is formed by the laser beams B2 and B3. Exposed. In other words, in the (N + 1) th main scan row, an area having a width of about 30% of the beam pitch D on the boundary side with the area of the Nth main scan row in the previous row is not exposed. As a result, as shown in FIG. 9, the boundary of the region exposed in the (N + 1) th scan column region is, for example, one third pixel (1 subpixel) from the boundary in contact with the Nth scan column region. Is shifted in the sub-scanning line direction Y by the distance of.

  Further, at each time k = 4, 5, the value of the intensity signal Q (N, k) in pixel units is set to 2 by the pixel value / intensity conversion circuit 54-1, so that the laser element 36a-2 has an intensity of 2. The laser beam B2 is emitted. Therefore, the region of the (N + 1) th scan row is irradiated with the laser beam B2 having intensity 2 having a spot diameter substantially the same as the beam pitch D. As a result, as shown in FIG. 9, the boundary of the region exposed in the (N + 1) th scan column region substantially coincides with the boundary in contact with the Nth scan column region.

  In the pixel value / intensity conversion circuit 54 configured as described above, when the pixel value P (n, k) of the pixel to be processed is the maximum value 3, the pixel value of the pixel adjacent to the pixel to be processed in the sub-scanning direction Y When P (n−1, k) or P (n + 1, k) is larger than the minimum value 0 and smaller than the maximum value 3, the following processing is performed. The pixel value / intensity conversion circuit 54 converts the pixel value P (n, k) into a pixel to be processed so that the beam spot formed on the substrate 2 by the laser light B has a spot diameter larger than the beam pitch D. To the value of the intensity signal Q (n, k). Therefore, the light source circuit 11 can emit laser beams B1 to B4 that can be resolved at a desired subpixel position. Therefore, the drawing apparatus 1 can draw a pattern image with a resolution higher than the beam pitch D.

  The pixel value / intensity conversion circuit 54 performs the following processing when the pixel value P (n, k) of the pixel to be processed is larger than the minimum value 0 and smaller than the maximum value 3. The pixel value / intensity conversion circuit 54 uses the laser beam when the pixel value P (n−1, k) or P (n + 1, k) of the pixel adjacent to the pixel to be processed in the sub-scanning direction Y is the maximum value. The spot diameter of the beam spot formed on the substrate 2 by B is converted so as to be smaller than the first spot diameter described below. The first spot diameter is a spot diameter when the pixel value P (n-1, k) or P (n + 1, k) of an adjacent pixel is larger than the minimum value 0 and smaller than the maximum value 3, and the pixel value / The intensity conversion circuit 54 converts the pixel value P (n, k) of the pixel to be processed into the value of the intensity signal Q (n, k) of the pixel to be processed. Therefore, the light source circuit 11 can draw a pattern image that can be resolved at a desired subpixel position. Therefore, the drawing apparatus 1 can draw a pattern image with a resolution higher than the beam pitch D.

  FIG. 10 is a top view of the substrate for explaining the exposure operation of the drawing apparatus of the comparative example. In FIG. 10, the drawing apparatus of the comparative example forms a pattern image on the substrate using, for example, the pixel value P (n, k) of FIG. 7 as the intensity signal value of the laser light in units of pixels. . For example, in the drawing apparatus of the comparative example, the intensity rate, which is the ratio of the intensity of the laser light emitted from the light source circuit 11 to the predetermined specified power of the laser light, is set to the values 0, 1, Set corresponding to 2 and 3. For example, in the drawing apparatus of the comparative example, the intensity rate is set to 0%, 50%, 70%, and 100% for the values 0, 1, 2, and 3 of the pixel value P (n, k), respectively. . Here, laser beams with intensity rates of 50% and 70% form spot diameters on the substrate that are 1/3 and 2/3 of the beam pitch D, respectively. Further, a laser beam having an intensity rate of 100% forms a spot diameter on the substrate that is substantially equal to the beam pitch D. Conventionally, in a light source using a semiconductor laser, in order to draw a high-resolution pattern image, it is possible to set a spot diameter developed with a laser beam having an intensity near the maximum intensity as a beam pitch in the sub-scanning direction Y. This is advantageous in terms of productivity. On the other hand, it was difficult to modulate the intensity of laser light that was weaker than the intensity near the maximum light intensity. Therefore, in the intensity modulation of laser light using an intensity lower than the intensity near the maximum intensity, as shown in FIG. 10, the region R located between the beam centers, that is, near the boundary of the main scanning line, as shown in FIG. It was difficult in principle to draw a pattern image on top.

  In FIG. 10, a region R that is not properly exposed by laser light between a region drawn with laser light having an intensity rate of 50% in the (N + 1) th scan row and a region of the (N + 2) th scan row. Exists. Therefore, the drawing apparatus of this comparative example cannot draw and draw accurate subpixels. In addition, since the said area | region R can be exposed by the temporal and spatial covering of the scanning energy density of a laser beam, the area | region R can usually be exposed exceeding a development threshold value. However, depending on conditions, there is a risk that the exposure on the region R becomes unstable, such as insufficient curing of the photosensitive agent on the region R.

  On the other hand, according to the configuration of the present embodiment, the laser beam B having an intensity of 3 is not only applied to the main scanning row area to be irradiated on the exposure surface 2a, but also to the main and rear rows adjacent to the main scanning row. The exposure surface 2a is exposed across the region on the scan row. That is, according to the configuration of the drawing apparatus 1 of the present embodiment, it is possible to prevent formation of an area that needs to be exposed on the exposure surface 2a due to temporal and spatial covering of the scanning energy density.

  In this embodiment, the pixel value / intensity conversion circuit 54 sets and outputs the value of a 2-bit digital value intensity signal Q (n, k). However, the present invention is not limited to this, and the pixel value / intensity conversion circuits 54-1 to 54-4 may set and output the value of the intensity signal Q (n, k) having a digital value of 3 bits or more. .

  In the present embodiment, the light source circuit 11 includes four laser elements 36a-1 to 36a-4. However, the present invention is not limited to this, and the light source circuit 11 may include one to three, or four or more laser elements.

  In the present embodiment, the polygon mirror 15 has a hexagonal prism shape, and a mirror is disposed on each of the six side surfaces. However, the present invention is not limited to this, and the polygon mirror 15 may have a polygonal column shape such as an octagonal column or a dodecagonal column, and a mirror may be disposed on each side surface thereof.

  In the present embodiment, the pixel value / intensity conversion circuit 54 includes a dedicated hardware circuit for executing, for example, the pixel value / intensity conversion processing of FIGS. However, the present invention is not limited to this, and the pixel value / intensity conversion circuit 54 may be configured in combination with an electronic computer such as an external personal computer instead of the dedicated hardware circuit. In this case, an electronic computer such as a personal computer executes pixel value / intensity conversion processing when off-line converting original pattern image data into raster graphic data. As a result, the pattern image of the present embodiment can be drawn by a method in which the intensity signals Q (N, k) to Q (N + 3, k) are loaded into the drawing apparatus 1.

Embodiment 2. FIG.
FIG. 11 is a block diagram showing a configuration of a drawing apparatus 1A according to the second embodiment of the present invention. In FIG. 11, the drawing apparatus 1 </ b> A is different from the drawing apparatus 1 of FIG. 1 in that a light source circuit 11 </ b> A is provided instead of the light source circuit 11.

FIG. 12 is a block diagram showing the configuration of the light source circuit 11A of FIG. In FIG. 12, the light source circuit 11A is different from the light source circuit 11 of FIG. 4 in the following points.
(1) The light source circuit 11A includes intensity signal generation circuits 33A-1 to 33A-4 instead of the intensity signal generation circuits 33-1 to 33-4, respectively, as compared with the light source circuit 11 of FIG. Specifically, it is as follows.
(1-1) The intensity signal generating circuit 33A-1 is different from the intensity signal generating circuit 33-1 in FIG. 4 in place of the registers 51-1 to 53-1, and shift registers 51A-1 to 53A-1. Having provided. Further, the intensity signal generation circuit 33A-1 includes a pixel value / intensity conversion circuit 54A-1 including a sub-pixel pattern estimation unit 60-1 instead of the pixel value / intensity conversion circuit 54-1.
(1-2) The intensity signal generation circuit 33A-2 is different from the intensity signal generation circuit 33-2 of FIG. 4 in place of the registers 51-2 to 53-2, and shift registers 51A-2 to 53A-2. Having provided. The intensity signal generation circuit 33A-2 includes a pixel value / intensity conversion circuit 54A-2 including a sub-pixel pattern estimation unit 60-2 instead of the pixel value / intensity conversion circuit 54-2.
(1-3) The intensity signal generating circuit 33A-3 is different from the intensity signal generating circuit 33-3 in FIG. 4 in place of the registers 51-3 to 53-3, and shift registers 51A-3 to 53A-3. Having provided. The intensity signal generation circuit 33A-3 includes a pixel value / intensity conversion circuit 54A-3 including a sub-pixel pattern estimation unit 60-3 instead of the pixel value / intensity conversion circuit 54-3.
(1-4) The intensity signal generating circuit 33A-4 is different from the intensity signal generating circuit 33-4 in FIG. 4 in that the shift registers 51A-4 to 53A-4 are replaced with the registers 51-4 to 53-4, respectively. Having provided. The intensity signal generation circuit 33A-4 includes a pixel value / intensity conversion circuit 54A-4 including a sub-pixel pattern estimation unit 60-4 instead of the pixel value / intensity conversion circuit 54-4.
(2) The light source circuit 11A is provided between the intensity signal generation circuits 33A-1 to 33A-4 and the D / A conversion circuits 34-1 to 34-4, respectively, as compared with the light source circuit 11 of FIG. And phase modulation circuits 37-1 to 37-4. Here, the phase modulation circuits 37-1 to 37-4 delay the output timings of the intensity signals Q (N, k) to Q (N + 3, k) to the drive units 35-1 to 35-4, respectively.

  In the following description, the intensity signal generation circuits 33A-1 to 33A-4 are collectively referred to as the intensity signal generation circuit 33A, and the subpixel pattern estimation units 60-1 to 60-4 are collectively referred to as the subpixel pattern estimation unit 60. Also called. Further, the shift registers 51A-1 to 51A-4 are collectively referred to as the shift register 51A, the shift registers 52A-1 to 52A-4 are collectively referred to as the shift register 52A, and the shift registers 53A-1 to 53A-4 are referred to as the shift register 52A-4. Also collectively referred to as a shift register 53A. Further, the pixel value / intensity conversion circuits 54A-1 to 54A-4 are collectively referred to as the pixel value / intensity conversion circuit 54A, and the phase modulation circuits 37-1 to 37-4 are collectively referred to as the phase modulation circuit 37. .

  The readout circuit 32 includes pixel values P (N−1, k + 1) ˜ in the pixel value sequences I (N−1) to I (N + 4) in the main scanning direction X stored in the line buffers 32a-1 to 32a-6, respectively. The operation of sequentially outputting P (N + 4, k + 1) (0 ≦ k ≦ Npx−1) is repeated. That is, the readout circuit 32 repeats the above-described output operation while k ≦ Npx−1 is satisfied at each time k counted in synchronization with the pixel clock. Specifically, the readout circuit 32 outputs the pixel values P (N−1, k + 1) to P (N + 1, k + 1) to the shift registers 51A-1 to 53A-1 at each time k. Further, the readout circuit 32 outputs the pixel values P (N, k + 1) to P (N + 2, k + 1) to the shift registers 51A-2 to 53A-2, respectively, at each time k. Further, the readout circuit 32 outputs the pixel values P (N + 1, k + 1) to P (N + 3, k + 1) to the shift registers 51A-3 to 53A-3 at each time k. Furthermore, the readout circuit 32 outputs the pixel values P (N + 2, k + 1) to P (N + 4, k + 1) to the shift registers 51A-4 to 53A-4 at each time k.

  In the intensity signal generation circuit 33A-1, the shift register 51A-1 includes three pixel values P (N−1, k−1) to P (N−1) sequentially input from the line buffer 32a-1 by the readout circuit 32. , K + 1). The shift register 52A-1 stores three pixel values P (N, k-1) to P (N, k + 1) sequentially input from the line buffer 32a-2 by the readout circuit 32. The shift register 53A-1 stores three pixel values P (N + 1, k−1) to P (N + 1, k + 1) sequentially input from the line buffer 32a-3 by the readout circuit 32.

  The pixel value / intensity conversion circuit 54A-1 has three pixel values P (N-1, k-1) to P (N-1, k + 1) stored in the shift register 51A-1 at each time k. Is read. The pixel value / intensity conversion circuit 54A-1 reads out the three pixel values P (N, k-1) to P (N, k + 1) stored in the shift register 52A-1 at each time k. Further, the pixel value / intensity conversion circuit 54A-1 reads out the three pixel values P (N + 1, k−1) to P (N + 1, k + 1) stored in the shift register 53A-1 at each time k. The pixel value / intensity conversion circuit 54A-1 reads the nine pixel values P (N-1, k-1) to P (N-1, k + 1), P (N, k-1) to P (N, The pixel value / intensity conversion process of FIG. 14A is executed based on (k + 1) and P (N + 1, k−1) to P (N + 1, k + 1). In the pixel value / intensity conversion process of FIG. 14A, the sub-pixel pattern estimation unit 60-1 performs the sub-pixel of FIG. 14A based on the above nine pixel values, that is, the pixel values of the pixel to be processed and its surrounding pixels. Perform pattern estimation processing. In the subpixel pattern estimation process, the subpixel pattern estimation unit 60-1 includes subpixel pattern subs each composed of pixel values (hereinafter referred to as subpixel values) of the pixel P0 to be processed in FIG. 13A in units of subpixels. Estimate the pixel pattern. The subpixel pattern will be described later in detail with reference to FIGS. 13A and 13B. In addition, the pixel value / intensity conversion circuit 54A-1 sets the value of the intensity signal Q (N, k) for each pixel based on the estimated subpixel pattern, and the intensity signal from the timing of the pixel clock. The delay time Td1 of Q (N, k) is determined. Here, the delay time Td1 is a delay time at which the value of the intensity signal Q (N, k) output from the phase modulation circuit 37-1 in FIG. 12 changes with respect to the time k of the pixel clock. The pixel value / intensity conversion circuit 54A-1 generates an intensity signal Q (N, k) having a set value and a modulation control signal PM1 indicating the delay time Td1, and outputs the modulation signal to the phase modulation circuit 37-1 in FIG. To do. The pixel value / intensity conversion processing by the pixel value / intensity conversion circuit 54A-1 will be described in detail later with reference to FIG. 14A.

  Based on the modulation control signal PM1, the phase modulation circuit 37-1 in FIG. 12 converts the intensity signal Q (N, k) from the pixel value / intensity conversion circuit 54A-1 into a delay time Td1 included in the modulation control signal PM1. Output to the D / A converter 34-1 with a delay of The D / A converter 34-1 D / A converts the intensity signal Q (N, k) delayed by the delay time Td1 from the phase modulation circuit 37-1 into an analog intensity signal, and outputs the analog intensity signal to the drive unit 35-1. . The drive unit 35-1 supplies a pixel irradiation drive signal corresponding to the analog intensity signal to the laser element 36a-1. The laser element 36a-1 emits a laser beam B1 with an intensity corresponding to the pixel irradiation drive signal.

  In the intensity signal generation circuit 33A-2, the shift register 51A-2 receives the three pixel values P (N, k−1) to P (N, k + 1) sequentially input from the line buffer 32a-2 by the readout circuit 32. Store. The shift register 52A-2 stores three pixel values P (N + 1, k−1) to P (N + 1, k + 1) sequentially input from the line buffer 32a-3 by the readout circuit 32. The shift register 53A-2 stores three pixel values P (N + 2, k−1) to P (N + 2, k + 1) sequentially input from the line buffer 32a-4 by the readout circuit 32.

  The pixel value / intensity conversion circuit 54A-2 reads the three pixel values P (N, k-1) to P (N, k + 1) stored in the shift register 51A-2 at each time k. Further, the pixel value / intensity conversion circuit 54A-2 reads the three pixel values P (N + 1, k−1) to P (N + 1, k + 1) stored in the shift register 52A-2 at each time k. Further, the pixel value / intensity conversion circuit 54A-2 reads out the three pixel values P (N + 2, k-1) to P (N + 2, k + 1) stored in the shift register 53A-2 at each time k. The pixel value / intensity conversion circuit 54A-2 includes the nine read pixel values P (N, k−1) to P (N, k + 1), P (N + 1, k−1) to P (N + 1, k + 1), and Based on P (N + 2, k−1) to P (N + 2, k + 1), the pixel value / intensity conversion process of FIG. 14B is executed. In the pixel value / intensity conversion process of FIG. 14B, the sub-pixel pattern estimation unit 60-2 executes the sub-pixel pattern estimation process of FIG. 14B based on the nine pixel values. In the subpixel pattern estimation process, the subpixel pattern estimation unit 60-2 performs a process of estimating the subpixel pattern of the processing target pixel P0 having the pixel value P (N + 1, k). Further, the pixel value / intensity conversion circuit 54A-2 sets the value of the intensity signal Q (N + 1, k) for each pixel based on the estimated subpixel pattern of the pixel P0 to be processed, and the intensity signal Q A delay time Td2 of (N + 1, k) is determined. Here, the delay time Td2 is a delay time at which the value of the intensity signal Q (N + 1, k) output from the phase modulation circuit 37-2 in FIG. 12 changes with respect to the time k of the pixel clock. The pixel value / intensity conversion circuit 54A-2 generates an intensity signal Q (N + 1, k) having a set value and a modulation control signal PM2 indicating the delay time Td2, and outputs the modulation signal to the phase modulation circuit 37-2 in FIG. To do. The pixel value / intensity conversion processing by the pixel value / intensity conversion circuit 54A-2 will be described in detail later with reference to FIG. 14B.

  Based on the modulation control signal PM2, the phase modulation circuit 37-2 delays the intensity signal Q (N + 1, k) from the pixel value / intensity conversion circuit 54A-2 by a delay time Td2 included in the modulation control signal PM2. Output to the D / A converter 34-2. The D / A converter 34-2 D / A converts the intensity signal Q (N + 1, k) delayed by the delay time Td2 from the phase modulation circuit 37-2 into an analog intensity signal, and outputs it to the drive unit 35-2. . The drive unit 35-2 supplies a pixel irradiation drive signal corresponding to the analog intensity signal to the laser element 36a-2. The laser element 36a-2 emits a laser beam B2 with an intensity corresponding to the pixel irradiation drive signal.

  In the intensity signal generation circuit 33A-3, the shift register 51A-3 receives the three pixel values P (N + 1, k−1) to P (N + 1, k + 1) sequentially input from the line buffer 32a-3 by the readout circuit 32. Store. The shift register 52A-3 stores three pixel values P (N + 2, k−1) to P (N + 2, k + 1) sequentially input from the line buffer 32a-4 by the readout circuit 32. The shift register 53A-3 stores three pixel values P (N + 3, k−1) to P (N + 3, k + 1) sequentially input from the line buffer 32a-5 by the readout circuit 32.

  The pixel value / intensity conversion circuit 54A-3 reads out the three pixel values P (N + 1, k−1) to P (N + 1, k + 1) stored in the shift register 51A-3 at each time k. The pixel value / intensity conversion circuit 54A-3 reads the three pixel values P (N + 2, k−1) to P (N + 2, k + 1) stored in the shift register 52A-3 at each time k. Further, the pixel value / intensity conversion circuit 54A-3 reads out the three pixel values P (N + 3, k−1) to P (N + 3, k + 1) stored in the shift register 53A-3 at each time k. The pixel value / intensity conversion circuit 54A-3 reads the nine pixel values P (N + 1, k−1) to P (N + 1, k + 1), P (N + 2, k−1) to P (N + 2, k + 1) and P The pixel value / intensity conversion process of FIG. 14C is executed based on (N + 3, k−1) to P (N + 3, k + 1). In the pixel value / intensity conversion process of FIG. 14C, the sub-pixel pattern estimation unit 60-3 performs the sub-pixel pattern estimation process of FIG. 14C based on the nine pixel values. In the subpixel pattern estimation process, the subpixel pattern estimation unit 60-3 performs a process of estimating the subpixel pattern of the processing target pixel P0 having the pixel value P (N + 2, k). Further, the pixel value / intensity conversion circuit 54A-3 sets the value of the intensity signal Q (N + 2, k) for each pixel based on the estimated subpixel pattern of the pixel P0 to be processed, and the intensity signal Q A delay time Td3 of (N + 2, k) is determined. Here, the delay time Td3 is a delay time at which the value of the intensity signal Q (N + 2, k) output from the phase modulation circuit 37-3 in FIG. 12 changes with respect to the time k of the pixel clock. The pixel value / intensity conversion circuit 54A-3 generates an intensity signal Q (N + 2, k) having a set value and a modulation control signal PM3 indicating the delay time Td3, and outputs them to the phase modulation circuit 37-3 in FIG. To do. The pixel value / intensity conversion processing by the pixel value / intensity conversion circuit 54A-3 will be described in detail later with reference to FIG. 14C.

  Based on the modulation control signal PM3, the phase modulation circuit 37-3 delays the intensity signal Q (N + 2, k) from the pixel value / intensity conversion circuit 54A-3 by a delay time Td3 included in the modulation control signal PM3. Output to the D / A converter 34-3. The D / A converter 34-3 D / A converts the intensity signal Q (N + 2, k) delayed by the delay time Td3 from the phase modulation circuit 37-3 into an analog intensity signal and outputs it to the drive unit 35-3. . The drive unit 35-3 supplies a pixel irradiation drive signal corresponding to the analog intensity signal to the laser element 36a-3. The laser element 36a-3 emits a laser beam B3 with an intensity corresponding to the pixel irradiation drive signal.

  In the intensity signal generation circuit 33A-4, the shift register 51A-4 receives the three pixel values P (N + 2, k−1) to P (N + 2, k + 1) sequentially input from the line buffer 32a-4 by the readout circuit 32. Store. The shift register 52A-4 stores three pixel values P (N + 3, k−1) to P (N + 3, k + 1) sequentially input from the line buffer 32a-5 by the readout circuit 32. The shift register 53A-4 stores three pixel values P (N + 4, k−1) to P (N + 4, k + 1) sequentially input from the line buffer 32a-6 by the readout circuit 32.

  The pixel value / intensity conversion circuit 54A-4 reads the three pixel values P (N + 2, k−1) to P (N + 2, k + 1) stored in the shift register 51A-4 at each time k. The pixel value / intensity conversion circuit 54A-4 reads the three pixel values P (N + 3, k−1) to P (N + 3, k + 1) stored in the shift register 52A-4 at each time k. Further, the pixel value / intensity conversion circuit 54A-4 reads the three pixel values P (N + 4, k−1) to P (N + 4, k + 1) stored in the shift register 53A-4 at each time k. The pixel value / intensity conversion circuit 54A-4 reads the nine pixel values P (N + 2, k-1) to P (N + 2, k + 1), P (N + 3, k-1) to P (N + 3, k + 1) and P The pixel value / intensity conversion process of FIG. 14D is executed based on (N + 4, k−1) to P (N + 4, k + 1). In the pixel value / intensity conversion process of FIG. 14D, the subpixel pattern estimation unit 60-4 performs the subpixel pattern estimation process of FIG. 14D based on the above nine pixel values. In the subpixel pattern estimation process, the subpixel pattern estimation unit 60-4 performs a process of estimating the subpixel pattern of the processing target pixel P0 having the pixel value P (N + 3, k). Further, the pixel value / intensity conversion circuit 54A-4 sets the value of the intensity signal Q (N + 3, k) for each pixel based on the estimated subpixel pattern of the pixel P0 to be processed, and the intensity signal Q A delay time Td4 of (N + 3, k) is determined. Here, the delay time Td4 is a delay time at which the value of the intensity signal Q (N + 3, k) output from the phase modulation circuit 37-4 in FIG. 12 changes with respect to the time k of the pixel clock. The pixel value / intensity conversion circuit 54A-4 generates an intensity signal Q (N + 3, k) having a set value and a modulation control signal PM4 indicating the delay time Td4, and outputs them to the phase modulation circuit 37-4 in FIG. To do. The pixel value / intensity conversion processing by the pixel value / intensity conversion circuit 54A-4 will be described in detail later with reference to FIG. 14D.

  The phase modulation circuit 37-4 delays the intensity signal Q (N + 3, k) from the pixel value / intensity conversion circuit 54A-4 based on the modulation control signal PM4 by the delay time Td4 included in the modulation control signal PM4. Output to the D / A converter 34-4. The D / A converter 34-4 D / A converts the intensity signal Q (N + 3, k) delayed by the delay time Td4 from the phase modulation circuit 37-4 into an analog intensity signal and outputs it to the drive unit 35-4. . The drive unit 35-4 supplies a pixel irradiation drive signal corresponding to the analog intensity signal to the laser element 36a-4. The laser element 36a-4 emits a laser beam B4 with an intensity corresponding to the pixel irradiation drive signal.

  FIG. 13A is a diagram illustrating a configuration configuration of a processing target pixel P0 having a pixel value P (N, k) referred to by the sub-pixel pattern estimation unit 60-1 in FIG. 12 and surrounding pixels P1 to P8. It is. In FIG. 13A, pixels P6, P7, and P8 are juxtaposed in the main scanning direction X in the (N−1) th scanning column, and are stored in the shift register 51A-1 in FIG. 1, k-1), P (N-1, k), and P (N-1, k + 1). Further, the pixels P5, P0, and P1 are juxtaposed in the main scanning direction X in the Nth scanning column, and are stored in the shift register 52A-1 in FIG. 12 with pixel values P (N, k-1), P (N, k), and P (N, k + 1). Further, each of the pixels P4, P3, and P2 is juxtaposed in the main scanning direction X in the (N + 1) th scanning column, and is stored in the shift register 53A-1 in FIG. P (N + 1, k) and P (N + 1, k + 1), respectively. The rows of the pixels P6, P7, and P8, the rows of the pixels P5, P0, and P1, and the rows of the pixels P4, P3, and P2 are juxtaposed in the sub-scanning direction Y.

  FIG. 13B is a diagram illustrating a configuration of a sub-pixel pattern of the pixel P0 to be processed in FIG. 13A. In FIG. 13B, the period of the clock corresponding to each column of subpixels (hereinafter referred to as subpixel clock) within the pixel P0 to be processed is (1/3) times the period T of the pixel clock ( T / 3). In the subpixel pattern of FIG. 13B, the three subpixels at time c = 1 of the subpixel clock are juxtaposed in the subscanning direction Y and have values S11, S12, and S13, respectively. In addition, the three subpixels at time c = 2 of the subpixel clock are juxtaposed in the subscanning direction Y and have values S21, S22, and S23, respectively. Further, the three subpixels at time c = 3 of the subpixel clock are juxtaposed in the subscanning direction Y and have values S31, S32, and S33, respectively. The subpixel value of each subpixel is 0 or 1. Here, the subpixel value 0 indicates that the region of the subpixel is a part of the non-irradiated region that is not irradiated with the laser beam B. Further, the subpixel value 1 indicates that the region of the subpixel is a part of the irradiation region irradiated with the laser beam B.

  FIG. 14A is a flowchart showing a pixel value / intensity conversion process executed by the pixel value / intensity conversion circuit 54A-1 in FIG. In step S81 in FIG. 14A, the sub-pixel pattern estimation unit 60-1 performs a sub-pixel pattern estimation process for estimating the sub-pixel pattern in the processing target pixel P0 in FIG. 13A. The sub-pixel pattern estimation process in step S81 will be described in detail later with reference to FIGS. Next, in step S82, the pixel value / intensity conversion circuit 54A-1 determines the pixel value P (N, k, c) (c = 1, subpixel clock unit) based on the subpixel pattern estimated in step S81. 2, 3) is set as follows. That is, the pixel value / intensity conversion circuit 54A-1 uses the subpixel values S11 to S13, S21 to S23, and S31 to S33 in FIG. 13B to generate a pixel value P (N, k, c) in units of subpixel clocks. (C = 1, 2, 3) is set as follows.

P (N, k, 1) = S11 + S12 + S13 (1)
P (N, k, 2) = S21 + S22 + S23 (2)
P (N, k, 3) = S31 + S32 + S33 (3)

  That is, in Expression (1), the pixel value / intensity conversion circuit 54A-1 calculates the sum of the subpixel values S11, S12, and S13, and uses the obtained value as the pixel value P (N at time c = 1. , K, 1). In Expression (2), the pixel value / intensity conversion circuit 54A-1 calculates the sum of the subpixel values S21, S22, and S23, and uses the obtained value as the pixel value P (N at time c = 2. , K, 2). Further, in Expression (3), the pixel value / intensity conversion circuit 54A-1 calculates the sum of the subpixel values S31, S32, and S33, and uses the obtained value as the pixel value P (N at time c = 3. , K, 3). The pixel value P (N, k, c) at each time c = 1, 2, 3 of the subpixel clock represents the area of a part of the irradiation region of the laser beam B at the time c. When the pixel value P (N, k, c) is set as described above in step S82, the pixel value / intensity conversion circuit 54A-1 proceeds to step S83.

  In step S83, the pixel value / intensity conversion circuit 54A-1 sets the count value c to an initial value 1, and in step S84, the pixel value / intensity conversion circuit 54A-1 sets the pixel value P (in sub-pixel clock units). It is determined whether N, k, c) is 0 or not. If YES in step S84, in step S85, the pixel value / intensity conversion circuit 54A-1 sets the value of the intensity signal Q (N, k, c) in units of subpixel clocks to 0, and proceeds to step S94. .

  Here, the intensity signal Q (n, k, c) (c = 1, 2, 3) in the sub pixel clock unit in the pixel region at the time k of the nth scan row will be described below. Each intensity signal Q (n, k, c) is compared with the intensity signal Q (n, k) in units of pixels in FIG. 4, and the intensity of the laser beam B1 in units of sub-pixel clocks instead of in units of pixel clocks. Is different. That is, the intensity signal Q (n, k, c) (c = 1, 2, 3) indicates the intensity of the laser beam B to be irradiated at the time c of the subpixel clock.

  When it is determined that the pixel value P (N, k) in pixel units is not 0 (NO in step S84), in step S86, the pixel value / intensity conversion circuit 54A-1 determines the pixel value P in sub pixel clock units. It is determined whether (N, k, c) is 1. If YES in step S86, in step S87, the pixel value / intensity conversion circuit 54A-1 has a pixel value P (N-1, k, c) of 3 or a pixel value P (N + 1, k, c). 3 is determined. If YES in step S87, the process proceeds to step S85. In the case of NO in step S87, in step S88, the pixel value / intensity conversion circuit 54A-1 sets the value of the intensity signal Q (N, k, c) to 1, and proceeds to step S94.

  When it is determined that the pixel value P (N, k, c) is not 1 (NO in step S86), in step S89, the pixel value / intensity conversion circuit 54A-1 determines the pixel value P (N, k, c). ) Is 2 or not. If YES in step S89, in step S90, the pixel value / intensity conversion circuit 54A-1 has a pixel value P (N-1, k, c) of 3 or a pixel value P (N + 1, k, c). 3 is determined. If YES in step S90, the process proceeds to step S88. In the case of NO in step S90, in step S91, the pixel value / intensity conversion circuit 54A-1 sets the value of the intensity signal Q (N, k, c) to 2, and proceeds to step S94.

  When it is determined that the pixel value P (N, k, c) is not 2 (NO in step S89), in step S92, the pixel value / intensity conversion circuit 54A-1 detects the pixel value P (N-1, k). , C) is 1 or 2, or whether the pixel value P (N + 1, k, c) is 1 or 2 is determined. In the case of YES in step S92, in step S93, the pixel value / intensity conversion circuit 54A-1 sets the value of the intensity signal Q (N, k, c) to 3, and proceeds to step S94. If NO in step S92, the process proceeds to step S91.

  In step S94, the pixel value / intensity conversion circuit 54A-1 increases the count value c by 1. In step S95, the pixel value / intensity conversion circuit 54A-1 determines whether the count value c is greater than 3. judge. If NO in step S95, the process returns to step S84.

  If it is determined that the count value c is greater than 3 (YES in step S95), in step S96, the pixel value / intensity conversion circuit 54A-1 converts the intensity signal Q (N, k) into an intensity signal (in subpixel clock units). N, k, 3) is set, and the process proceeds to step S97. In step S97, the pixel value / intensity conversion circuit 54A-1 determines the intensity signal Q (in units of pixels) based on the intensity signal Q (N, k, c) in units of subpixel clocks (c = 1, 2, 3). N, k) delay time Td1 is determined. Specifically, the pixel value / intensity conversion circuit 54A-1 includes an intensity signal having a value different from the intensity signal Q (N, k) in the intensity signal Q (N, k, c) (c = 1, 2). A delay time Td1 proportional to the number of Q (N, k, c) is determined. For example, when the intensity signals Q (N, k, c) (c = 1, 2, 3) are all the same value, the intensity signal Q (N, k, c) indicating a value different from the intensity signal Q (N, k). The number of c) is 0. For this reason, the pixel value / intensity conversion circuit 54A-1 determines that the delay time Td1 is zero. Further, when the intensity signal Q (N, k, 1) is different from the intensity signal Q (N, k) and the intensity signal Q (N, k, 2) is the same as the intensity signal Q (N, k), the intensity The number of intensity signals Q (N, k, c) showing values different from the signal Q (N, k) is one. For this reason, the pixel value / intensity conversion circuit 54A-1 determines that the delay time Td1 is the period (T / 3) of the subpixel clock. Further, when both the intensity signals Q (N, k, 1) and Q (N, k, 2) are different from the intensity signal Q (N, k), the intensity indicating a value different from the intensity signal Q (N, k). The number of signals Q (N, k, c) is two. For this reason, the pixel value / intensity conversion circuit 54A-1 determines that the delay time Td1 is twice the period of the subpixel clock (2T / 3). After determining the delay time Td1, the pixel value / intensity conversion circuit 54A-1 proceeds to Step S98. In step S98, the pixel value / intensity conversion circuit 54A-1 generates an intensity signal Q (N, k) and a modulation control signal PM1 indicating the delay time Td1, and outputs the modulation signal to the phase modulation circuit 37-1. The pixel value / intensity conversion process in FIG. 14A ends.

  The subpixel pattern estimation process in step S81 of FIG. 14A and the process of determining the pixel value P (N, k, c) (c = 1, 2, 3) in subpixel clock units in step S82 are shown in FIGS. Will be described below.

  FIG. 15 is a table 60mt1 for estimating the sub-pixel pattern of the processing target pixel P0 when the pixel value P (N, k) of the processing target pixel P0 of FIG. In FIG. 15, a table 60mt1 has pixel values of pixels P1 to P8 around the pixel P0 to be processed and pixels P1 to P8 around the pixel P0 having such pixel values for each of pattern numbers 1 to 16. The sub-pixel pattern of the pixel P0 to be processed is shown. Here, the pattern numbers 1 to 16 in the table 60mt1 are respectively assigned to the sub-pixel patterns SP31 to SP34, SP21 to SP28, and SP11 to SP14 of the pixel P0 to be processed when the pixel value P (N, k) is 1. Correspond. In the table 60mt1, the pixel value of each pixel P1 to P8 is indicated by any value from 0 to 3, or the symbol X or NZ. Here, the symbol X means that the pixel value is any one of 0 to 3, and the symbol NZ means that the pixel value is any one of 1 to 3. . Each subpixel pattern estimation unit 60-1 to 60-4 in FIG. 12 includes memories 60m-1 to 60m-4, and each of the memories 60m-1 to 60m-4 stores a table 60mt1.

  FIG. 16A is a diagram showing a configuration of subpixel patterns SP11 to SP14 having an area 1 corresponding to the pattern numbers 13 to 16 in FIG. FIG. 16B is a diagram illustrating a configuration of sub-pixel patterns SP21 to SP28 having an area 2 corresponding to the pattern numbers 5 to 12 in FIG. FIG. 16C is a diagram showing a configuration of sub-pixel patterns SP31 to SP34 having an area 3 corresponding to the pattern numbers 1 to 4 in FIG. In FIG. 16, the area of the subpixel pattern indicates the number of subpixels having a value of 1 in the subpixel pattern. Each of the subpixel patterns SP11 to SP14, SP21 to SP28, and SP31 to SP34 includes a part of the irradiation region of the laser beam B that is hatched with a subpixel value of 1 and an unhatched laser beam B that has a subpixel value of 0. And some non-irradiated areas. The pixel value / intensity conversion circuit 54A-1 includes a memory 54Am-1. The memory 54Am-1 stores data indicating the subpixel values S11 to S13, S21 to S23, and S31 to S33 for the subpixel patterns SP11 to SP14, SP21 to SP28, SP31 to SP34 in FIG.

  15 and 16, when the pixel value P (N, k) is 1, the subpixel pattern estimation unit 60-1 in FIG. 12 refers to the table 60mt1 and performs the subpixel pattern in step S81 in FIG. 14A. The estimation process is executed as follows. The sub-pixel pattern estimation unit 60-1 determines whether or not the pixel values of the pixels P1 to P8 around the pixel P0 to be processed match the pixel values of the pixels P1 to P8 having any pattern number, respectively. Determination is made in the order of 1-16. When the pixel values of the pixels P1 to P8 around the pixel P0 to be processed match the pixel values of the pixels P1 to P8 indicated by a certain pattern number, the subpixel pattern estimation unit 60-1 identifies the pattern number. . Then, the subpixel pattern estimation unit 60-1 estimates the subpixel pattern indicated by the pattern number in the table 60mt1 as the subpixel pattern of the processing target pixel P0.

  For example, when the pixel value P (N, k) of the pixel P0 to be processed is 1, when the pixels P1, P3, and P7 around the pixel P0 have pixel values 0, NZ, and NZ, The pixels P1 to P8 have the pixel values of the pixels P1 to P8 of the pattern number 1, respectively. For this reason, the subpixel pattern estimation unit 60-1 estimates the subpixel pattern SP31 with the pattern number 1 as the subpixel pattern of the pixel P0 to be processed. As shown in FIG. 16, in the subpixel pattern SP31, the subpixel values S11 to S13 are 1, and the subpixel values S21 to S23 and S31 to S33 are 0. Further, the subpixel pattern SP31 includes a part of the irradiation region R31 of the laser beam B having an edge E31 parallel to the Y direction. Therefore, in this case, in step S82 of FIG. 14A, the pixel value / intensity conversion circuit 54A-1 sets the pixel value P (N, k, 1) to 3 (= S11 + S12 + S13) based on the equation (1). Further, the pixel value / intensity conversion circuit 54A-1 sets the pixel value P (N, k, 2) to 0 (= S21 + S22 + S23) based on Expression (2). Further, the pixel value / intensity conversion circuit 54A-1 sets the pixel value P (N, k, 3) to 0 (= S31 + S32 + S33) based on Expression (3).

  For example, when the pixel value P (N, k) of the pixel P0 to be processed is 1, the pixels P1, P3, P5, and P7 around the pixel P0 have pixel values 2, 0, 0, and 1 respectively. The pixels P1 to P8 have the pixel values of the pixels P1 to P8 of the pattern number 6, respectively. For this reason, the subpixel pattern estimation unit 60-1 estimates the subpixel pattern SP22 having the pattern number 6 as the subpixel pattern of the pixel P0 to be processed. As shown in FIG. 16, in the subpixel pattern SP22, the subpixel values S31 and S32 are 1, and the subpixel values S11 to S13, S21 to S23, and S33 are 0. The sub-pixel pattern SP22 includes a part of the laser light B irradiated region R22 having a convex corner C22 where an edge E22a parallel to the X direction and an edge E22b parallel to the Y direction intersect each other. Therefore, in this case, in step S82 of FIG. 14A, the pixel value / intensity conversion circuit 54A-1 sets the pixel value P (N, k, 1) to 0 (= S11 + S12 + S13) based on the equation (1). Further, the pixel value / intensity conversion circuit 54A-1 sets the pixel value P (N, k, 2) to 0 (= S21 + S22 + S23) based on Expression (2). Further, the pixel value / intensity conversion circuit 54A-1 sets the pixel value P (N, k, 3) to 2 (= S31 + S32 + S33) based on Expression (3).

  FIG. 17 is a table 60mt2 for estimating the sub-pixel pattern of the processing target pixel P0 when the pixel value P (N, k) of the processing target pixel P0 of FIG. In FIG. 17, for each pattern number 1 to 12, the table 60 mt 2 shows such pixel values for the pixel values of the pixels P 1 to P 8 around the pixel P 0 to be processed and the pixel values P 1 to P 8 around the pixel P 0. The sub-pixel pattern of the pixel P0 to be processed when it is included. Here, the pattern numbers 1 to 12 in the table 60mt2 are sub-pixel patterns SP61 to SP64, SP51 to SP54, and SP41 to SP44 of the pixel P0 to be processed when the pixel value P (N, k) is 2, respectively. Correspond. In the table 60mt2, the pixel value of each pixel P1 to P8 is indicated by any value from 0 to 3, or the symbol X or NZ. In addition, each memory 60m-1 to 60m-4 of the subpixel pattern estimation units 60-1 to 60-4 in FIG. 12 stores a table 60mt2.

  FIG. 18A is a diagram showing a configuration of sub-pixel patterns SP41 to SP44 having an area 4 corresponding to the pattern numbers 9 to 12 in FIG. FIG. 18B is a diagram illustrating a configuration of sub-pixel patterns SP51 to SP54 having an area 5 corresponding to the pattern numbers 5 to 8 in FIG. FIG. 18C is a diagram showing a configuration of sub-pixel patterns SP61 to SP64 having an area 6 corresponding to the pattern numbers 1 to 4 in FIG. In FIG. 18, the area of the subpixel pattern indicates the number of subpixels having a value of 1 in the subpixel pattern. Each of the subpixel patterns SP41 to SP44, SP51 to SP54, and SP61 to SP64 includes an irradiation region of a part of the laser beam B that is hatched with a subpixel value of 1 and an unhatched laser beam B that has a subpixel value of 0. And some non-irradiated areas. The memory 54Am-1 of the pixel value / intensity conversion circuit 54A-1 stores subpixel values S11 to S13, S21 to S23, and S31 to S33 for the subpixel patterns SP41 to SP44, SP51 to SP54, SP61 to SP64 in FIG. The data indicating is stored.

  17 and 18, when the pixel value P (N, k) is 2, the sub-pixel pattern estimation unit 60-1 in FIG. 12 refers to the table 60mt2 and performs the sub-pixel pattern in step S81 in FIG. 14A. The estimation process is executed as follows. The sub-pixel pattern estimation unit 60-1 determines whether or not the pixel values of the pixels P1 to P8 around the pixel P0 to be processed match the pixel values of the pixels P1 to P8 having any pattern number, respectively. Determination is made in the order of pattern numbers 1-12. When the pixel values of the pixels P1 to P8 around the pixel P0 to be processed match the pixel values of the pixels P1 to P8 indicated by a certain pattern number, the subpixel pattern estimation unit 60-1 identifies the pattern number. . Then, the subpixel pattern estimation unit 60-1 estimates the subpixel pattern indicated by the pattern number in the table 60mt2 as the subpixel pattern of the processing target pixel P0.

  For example, when the pixel value P (N, k) of the pixel P0 to be processed is 2, when the pixels P1, P3, and P5 around the pixel P0 have the pixel values NZ, 0, and NZ, respectively, The peripheral pixels P1 to P8 have pixel values of the pixels P1 to P8 of pattern number 2, respectively. For this reason, the subpixel pattern estimation unit 60-1 estimates the subpixel pattern SP62 with the pattern number 2 as the subpixel pattern of the pixel P0 to be processed. As shown in FIG. 18, in the subpixel pattern SP62, the subpixel values S11, S12, S21, S22, S31, and S31 are 1, and the subpixel values S13, S23, and S33 are 0. is there. Further, the sub-pixel pattern SP62 includes a partial irradiation region R62 of the laser beam B having an edge E62 parallel to the X direction. Therefore, in this case, in step S82 of FIG. 14A, the pixel value / intensity conversion circuit 54A-1 sets the pixel value P (N, k, 1) to 2 (= S11 + S12 + S13) based on the equation (1). Further, the pixel value / intensity conversion circuit 54A-1 sets the pixel value P (N, k, 2) to 2 (= S21 + S22 + S23) based on Expression (2). Further, the pixel value / intensity conversion circuit 54A-1 sets the pixel value P (N, k, 3) to 2 (= S31 + S32 + S33) based on Expression (3).

  Further, for example, when the pixel value P (N, k) of the pixel P0 to be processed is 2, and the peripheral pixels P1, P7, and P8 all have the pixel value 0, the peripheral pixel P1 of the pixel P0 To P8 have pixel values of the pixels P1 to P8 of the pattern number 12, respectively. Therefore, the subpixel pattern estimation unit 60-1 estimates the subpixel pattern SP44 with the pattern number 12 as the subpixel pattern of the pixel P0 to be processed. As shown in FIG. 18, in the subpixel pattern SP44, the subpixel values S12, S13, S22, and S23 are 1, and the subpixel values S11, S21, and S31 to S33 are 0. The sub-pixel pattern SP44 includes a part of the irradiation region R44 of the laser beam B having a convex corner C22 where an edge E44a parallel to the X direction and an edge E44b parallel to the Y direction intersect each other. Therefore, in this case, in step S82 of FIG. 14A, the pixel value / intensity conversion circuit 54A-1 sets the pixel value P (N, k, 1) to 2 (= S11 + S12 + S13) based on the equation (1). Further, the pixel value / intensity conversion circuit 54A-1 sets the pixel value P (N, k, 2) to 2 (= S21 + S22 + S23) based on Expression (2). Further, the pixel value / intensity conversion circuit 54A-1 sets the pixel value P (N, k, 3) to 0 (= S31 + S32 + S33) based on Expression (3).

  FIG. 19 is a table 60mt3 for estimating the sub-pixel pattern of the processing target pixel P0 when the pixel value P (N, k) of the processing target pixel P0 of FIG. In FIG. 19, the table 60 mt3 is a process in which the pixel values of the peripheral pixels P1 to P8 of the pixel P0 to be processed and the peripheral pixels P1 to P8 have such pixel values for each of the pattern numbers 1 to 13. The sub-pixel pattern of the target pixel P0 is shown. Here, the pattern numbers 1 to 13 in the table 60mt3 correspond to the sub-pixel patterns SP81 to SP84, SP71 to SP78, and SP91 of the pixel P0 to be processed when the pixel value P (N, k) is 3, respectively. . In the table 60mt3, the pixel value of each pixel P1 to P8 is indicated by any value from 0 to 3, or the symbol X or NZ. Note that the memories 60m-1 to 60m-4 of the sub-pixel pattern estimation units 60-1 to 60-4 in FIG. 12 store a table 60mt3.

  FIG. 20A is a diagram showing a configuration of sub-pixel patterns SP71 to SP78 having an area of 7 corresponding to the pattern numbers 5 to 12 in FIG. FIG. 20B is a diagram showing a configuration of sub-pixel patterns SP81 to SP84 having an area of 8 corresponding to the pattern numbers 1 to 4 in FIG. FIG. 20C is a diagram showing a configuration of a sub-pixel pattern SP91 having an area 9 corresponding to the pattern number 13 in FIG. In FIG. 20, each of the subpixel patterns SP71 to SP78, SP81 to SP84, and SP91 includes a part of the irradiation region of the laser beam B that is hatched with a subpixel value of 1, and a laser beam that is not hatched with a subpixel value of 0. And a part of non-irradiated region of B. The memory 54Am-1 of the pixel value / intensity conversion circuit 54A-1 stores the subpixel values S11 to S13, S21 to S23, and S31 to S33 for the subpixel patterns SP71 to SP78, SP81 to SP84, and SP91 in FIG. Stores the indicated data.

  19 and 20, when the pixel value P (N, k) is 3, the subpixel pattern estimation unit 60-1 in FIG. 12 refers to the table 60mt3 and performs the subpixel pattern in step S81 in FIG. 14A. The estimation process is executed as follows. The sub-pixel pattern estimation unit 60-1 determines whether or not the pixel values of the pixels P1 to P8 around the pixel P0 to be processed match the pixel values of the pixels P1 to P8 having any pattern number, respectively. The determination is made in the order of 1-13. When the pixel values of the pixels P1 to P8 around the pixel P0 to be processed match the pixel values of the pixels P1 to P8 indicated by a certain pattern number, the subpixel pattern estimation unit 60-1 identifies the pattern number To do. Then, the subpixel pattern estimation unit 60-1 estimates the subpixel pattern indicated by the pattern number in the table 60mt3 as the subpixel pattern of the processing target pixel P0.

  For example, when the pixel value P (N, k) of the pixel P0 to be processed is 3, and the pixels P3, P4, and P5 around the pixel P0 have pixel values 2, 0, and 1, respectively, the pixel P0 The pixels P1 to P8 in the vicinity of each have pixel values of the pixels P1 to P8 of the pattern number 7 respectively. Therefore, the subpixel pattern estimation unit 60-1 estimates the subpixel pattern SP73 with the pattern number 7 as the subpixel pattern of the pixel P0 to be processed. As shown in FIG. 20, in the subpixel pattern SP73, the subpixel values S11, S21 to S23, and S31 to S33 are 1, and the subpixel values S12 and S13 are 0. Further, the sub-pixel pattern SP73 includes a partial irradiation region R73 of the laser beam B having a concave corner C73 where an edge E73a parallel to the X direction and an edge E73b parallel to the Y direction intersect each other. Therefore, in this case, in step S82 of FIG. 14A, the pixel value / intensity conversion circuit 54A-1 sets the pixel value P (N, k, 1) to 0 (= S11 + S12 + S13). Further, the pixel value / intensity conversion circuit 54A-1 sets the pixel value P (N, k, 2) to 0 (= S11 + S12 + S13). Further, the pixel value / intensity conversion circuit 54A-1 sets the pixel value P (N, k, 3) to 2 (= S11 + S12 + S13).

  As described above, the subpixel pattern estimation unit 60-1 in FIG. 12 performs the subpixel pattern estimation processing in step S81 in FIG. 14A and the pixel value P (N, k, c) in step S82 (c = 1, 2). , 3) is executed. When the pixel value P (N, k) of the pixel P0 is 0, the subpixel pattern estimation unit 60-1 determines that each subpixel in the subpixel pattern of the processing target pixel P0 has a subpixel value of 0. judge.

  The pixel value / intensity conversion circuit 54A-1 in FIG. 12 performs the pixel value / intensity conversion processing in FIG. 14A as described above. Next, pixel value / intensity conversion processing executed by the pixel value / intensity conversion circuits 54A-2 to 54A-4 in FIG. 12 will be described below with reference to FIGS. 14B to 14D.

  FIG. 14B is a flowchart showing a pixel value / intensity conversion process executed by the pixel value / intensity conversion circuit 54A-2 in FIG. In step S101 of FIG. 14B, the sub-pixel pattern estimation unit 60-2 executes a sub-pixel pattern estimation process for estimating a sub-pixel pattern in the pixel P0 to be processed in FIG. 13A.

The subpixel pattern estimation process in step S101 by the subpixel pattern estimation unit 60-2 is the same as the subpixel pattern estimation process in step S81 of FIG. 14A except for the following differences.
(1) The pixel value of the pixel P0 to be processed in FIG. 13A is a pixel value P (N + 1, k) instead of the pixel value P (N, k).
(2) The pixel values of the pixels P1 to P3 around the pixel P0 to be processed in FIG. 13A are replaced with the pixel values P (N, k + 1), P (N + 1, k + 1), and P (N + 1, k), respectively. , Pixel values P (N + 1, k + 1), P (N + 2, k + 1), and P (N + 2, k). The pixel values of the pixels P4 to P6 around the pixel P0 to be processed are the pixel values P (N + 1, k−1), P (N, k−1), and P (N−1, k−1), respectively. ) Instead of pixel values P (N + 2, k−1), P (N + 1, k−1), and P (N, k−1). Furthermore, the pixel values of the pixels P7 and P8 around the pixel P0 to be processed are replaced with the pixel values P (N-1, k + 1) and the pixel values P (N, k + 1), respectively. ) And P (N, k + 1).
(3) The sub-pixel pattern estimation unit 60-2 refers to the tables 60mt1 to 60mt3 in FIGS. 15, 17 and 19 stored in the memory 60m-2 instead of the memory 60m-1 in FIG. Performing the sub-pixel pattern estimation process of S101.

  Next, in step S102, the pixel value / intensity conversion circuit 54A-2, based on the subpixel pattern estimated in step S101, the pixel value P (N + 1, k, c) (c = 1, 2, 3) is set as follows. That is, the pixel value / intensity conversion circuit 54A-2 uses the subpixel values S11 to S13, S21 to S23, and S31 to S33 in FIG. 13B to generate pixel values P (N + 1, k, c) (c = 1, 2, 3) is set as follows:

P (N + 1, k, 1) = S11 + S12 + S13 (4)
P (N + 1, k, 2) = S21 + S22 + S23 (5)
P (N + 1, k, 3) = S31 + S32 + S33 (6)

  That is, in Expression (4), the pixel value / intensity conversion circuit 54A-2 calculates the sum of the subpixel values S11, S12, and S13, and uses the obtained value as the pixel value P (N + 1) at time c = 1. , K, 1). In Expression (5), the pixel value / intensity conversion circuit 54A-2 calculates the sum of the subpixel values S21, S22, and S23, and uses the obtained value as the pixel value P (N + 1) at time c = 2. , K, 2). Further, in Expression (6), the pixel value / intensity conversion circuit 54A-2 calculates the sum of the subpixel values S31, S32, and S33, and uses the obtained value as the pixel value P (N + 1) at time c = 3. , K, 3). The pixel value P (N + 1, k, c) at each time c = 1, 2, 3 of the sub-pixel clock represents the area of a part of the irradiation region of the laser beam B at the time c. The pixel value / intensity conversion circuit 54A-2 stores data indicating the subpixel values S11 to S13, S21 to S23, and S31 to S33 for the subpixel patterns shown in FIGS. A memory 54Am-2 is provided. The pixel value / intensity conversion circuit 54A-2 refers to the subpixel value of each of the subpixel patterns stored in the memory 54Am-2, so that the pixel value P (N + 1, k, c) (c = The process of setting 1, 2, 3) is executed. When the pixel value P (N + 1, k, c) is set as described above in step S102, the pixel value / intensity conversion circuit 54A-2 proceeds to step S103.

  In step S103, the pixel value / intensity conversion circuit 54A-2 sets the count value c to an initial value 1, and in step S104, the pixel value / intensity conversion circuit 54-2 sets the pixel value P (N + 1, k, c). ) Is 0 or not. If YES in step S104, the pixel value / intensity conversion circuit 54-2 sets the value of the intensity signal Q (N + 1, k, c) to 0 in step S105, and the process proceeds to step S114.

  When it is determined that the pixel value P (N + 1, k) is not 0 (NO in step S104), in step S106, the pixel value / intensity conversion circuit 54-2 determines that the pixel value P (N + 1, k, c) is It is determined whether or not 1. If YES in step S106, in step S107, the pixel value / intensity conversion circuit 54-2 has a pixel value P (N, k, c) of 3 or a pixel value P (N + 2, k, c) of 3. Determine whether or not. If YES in step S107, the process proceeds to step S105. In the case of NO in step S107, in step S108, the pixel value / intensity conversion circuit 54-2 sets the value of the intensity signal Q (N + 1, k, c) to 1, and proceeds to step S114.

  When it is determined that the pixel value P (N + 1, k, c) is not 1 (NO in step S106), in step S109, the pixel value / intensity conversion circuit 54-2 determines the pixel value P (N + 1, k, c). ) Is 2 or not. If YES in step S109, in step S110, the pixel value / intensity conversion circuit 54-2 has a pixel value P (N, k, c) of 3 or a pixel value P (N + 2, k, c) of 3. Determine whether or not. If YES in step S110, the process proceeds to step S108. In the case of NO in step S110, in step S111, the pixel value / intensity conversion circuit 54-2 sets the value of the intensity signal Q (N + 1, k, c) to 2, and proceeds to step S114.

  When it is determined that the pixel value P (N + 1, k, c) is not 2 (NO in step S109), in step S112, the pixel value / intensity conversion circuit 54-2 has the pixel value P (N, k, c). It is determined whether 1 or 2 or the pixel value P (N + 2, k, c) is 1 or 2. If YES in step S112, in step S113, the pixel value / intensity conversion circuit 54-2 sets the value of the intensity signal Q (N + 1, k, c) to 3, and proceeds to step S114. If NO in step S112, the process proceeds to step S111.

  In step S114, the pixel value / intensity conversion circuit 54-2 increases the count value c by 1. In step S115, the pixel value / intensity conversion circuit 54-2 determines whether the count value c is greater than 3. judge. If NO in step S115, the process returns to step S104.

  If it is determined that the count value c is greater than 3 (YES in step S115), in step S116, the pixel value / intensity conversion circuit 54-2 converts the value of the intensity signal Q (N + 1, k) into the intensity signal (N + 1, k). k, 3) is set, and the process proceeds to step S117. In step S117, the pixel value / intensity conversion circuit 54A-2 uses the intensity signal Q ((pixel unit) based on the intensity signal Q (N + 1, k, c) (c = 1, 2, 3) in units of subpixel clocks. N + 1, k) delay time Td2 is determined. Specifically, the pixel value / intensity conversion circuit 54A-2 has an intensity of a value different from the intensity signal Q (N + 1, k) in the intensity signal Q (N + 1, k, c) (c = 1, 2). The number of signals Q (N + 1, k, c) is determined. Then, the pixel value / intensity conversion circuit 54A-2 determines a delay time Td2 proportional to the number of intensity signals Q (N + 1, k, c) having a value different from the intensity signal Q (N + 1, k). For example, when the intensity signals Q (N + 1, k, c) (c = 1, 2, 3) are all the same value, the intensity signal Q (N + 1, k, showing a value different from the intensity signal Q (N + 1, k). The number of c) is 0. Therefore, the pixel value / intensity conversion circuit 54A-2 determines that the delay time Td2 is zero. Further, when the intensity signal Q (N + 1, k, 1) is different from the intensity signal Q (N + 1, k) and the intensity signal Q (N + 1, k, 2) is the same as the intensity signal Q (N + 1, k), the intensity The number of intensity signals Q (N + 1, k, c) showing values different from the signal Q (N + 1, k) is one. For this reason, the pixel value / intensity conversion circuit 54A-2 determines that the delay time Td2 is the period (T / 3) of the subpixel clock. Further, when both the intensity signals Q (N + 1, k, 1) and Q (N + 1, k, 2) are different from the intensity signal Q (N + 1, k), the intensity indicating a value different from the intensity signal Q (N + 1, k). The number of signals Q (N + 1, k, c) is two. Therefore, the pixel value / intensity conversion circuit 54A-2 determines that the delay time Td2 is (2T / 3) which is twice the period of the subpixel clock. After determining the delay time Td2, the pixel value / intensity conversion circuit 54A-2 proceeds to Step S118. In step S118, the pixel value / intensity conversion circuit 54A-2 generates an intensity signal Q (N + 1, k) and a modulation control signal PM2 indicating the delay time Td2, and outputs the modulation signal to the phase modulation circuit 37-2. The pixel value / intensity conversion process in FIG. 14B ends.

  FIG. 14C is a flowchart showing a pixel value / intensity conversion process executed by the pixel value / intensity conversion circuit 54A-3 in FIG. In step S121 of FIG. 14C, the sub-pixel pattern estimation unit 60-3 performs a sub-pixel pattern estimation process for estimating the sub-pixel pattern in the processing target pixel p0 of FIG. 13A.

The subpixel pattern estimation process in step S121 by the subpixel pattern estimation unit 60-3 is the same as the subpixel pattern estimation process in step S81 of FIG. 14A except for the following differences.
(1) The pixel value of the pixel P0 to be processed in FIG. 13A is a pixel value P (N + 2, k) instead of the pixel value P (N, k).
(2) The pixel values of the pixels P1 to P3 around the pixel P0 to be processed in FIG. 13A are replaced with the pixel values P (N, k + 1), P (N + 1, k + 1), and P (N + 1, k), respectively. Pixel values P (N + 2, k + 1), P (N + 3, k + 1), and P (N + 3, k). The pixel values of the surrounding pixels P4 to P6 are pixels instead of the pixel values P (N + 1, k−1), P (N, k−1), and P (N−1, k−1), respectively. The values P (N + 3, k-1), P (N + 2, k-1), and P (N + 1, k-1). Further, the pixel values of the peripheral pixels P7 and P8 are P (N + 1, k) and P (N + 1, k + 1) instead of P (N-1, k) and P (N-1, k + 1), respectively. about.
(3) The sub-pixel pattern estimation unit 60-3 refers to the tables 60mt1 to 60mt3 in FIGS. 15, 17 and 19 stored in the memory 60m-3 instead of the memory 60m-1 in FIG. Performing the sub-pixel pattern estimation process of S121.

  Next, in step S122, the pixel value / intensity conversion circuit 54A-3, based on the subpixel pattern estimated in step S121, the pixel value P (N + 2, k, c) (c = 1, 2, 3) is set as follows. That is, the pixel value / intensity conversion circuit 54A-3 uses the subpixel values S11 to S13, S21 to S23, and S31 to S33 in FIG. 13B to obtain the pixel value P (N + 2, k, c) (c = 1, 2, 3) is set as follows:

P (N + 2, k, 1) = S11 + S12 + S13 (7)
P (N + 2, k, 2) = S21 + S22 + S23 (8)
P (N + 2, k, 3) = S31 + S32 + S33 (9)

  That is, in Expression (7), the pixel value / intensity conversion circuit 54A-3 calculates the sum of the subpixel values S11, S12, and S13, and uses the obtained value as the pixel value P (N + 2 at time c = 1. , K, 1). In Expression (8), the pixel value / intensity conversion circuit 54A-3 calculates the sum of the subpixel values S21, S22, and S23, and uses the obtained value as the pixel value P (N + 2) at time c = 2. , K, 2). Further, in Expression (9), the pixel value / intensity conversion circuit 54A-3 calculates the sum of the sub-pixel values S31, S32, and S33, and uses the obtained value as the pixel value P (N + 2) at time c = 3. , K, 3). The pixel value / intensity conversion circuit 54A-3 outputs the subpixel values S11 to S13, S21 to S23, and S31 to S33 for the subpixel patterns (SP11 to SP91) shown in FIGS. A memory 54Am-3 for storing the data shown. The pixel value / intensity conversion circuit 54A-3 sets the pixel value P (N + 2, k, c) in step S122 by referring to the subpixel value of each subpixel pattern stored in the memory 54Am-3. Execute the process. When the pixel value P (N + 2, k, c) is set as described above in step S122, the pixel value / intensity conversion circuit 54A-3 proceeds to step S123.

  In step S123, the pixel value / intensity conversion circuit 54A-3 sets the count value c to the initial value 1, and in step S124, the pixel value / intensity conversion circuit 54-3 sets the pixel value P (N + 2, k, c). ) Is 0 or not. If YES in step S124, the pixel value / intensity conversion circuit 54-3 sets the value of the intensity signal Q (N + 2, k, c) to 0 in step S125, and the process proceeds to step S134.

  When it is determined that the pixel value P (N + 2, k, c) is not 0 (NO in step S124), in step S126, the pixel value / intensity conversion circuit 54-3 determines that the pixel value P (N + 2, k, c). ) Is 1 or not. If YES in step S126, in step S127, the pixel value / intensity conversion circuit 54-3 has a pixel value P (N + 1, k, c) of 3 or a pixel value P (N + 3, k, c) of 3. Determine whether or not. If YES in step S127, the process proceeds to step S125. In the case of NO in step S127, in step S128, the pixel value / intensity conversion circuit 54-3 sets the value of the intensity signal Q (N + 2, k, c) to 1, and proceeds to step S134.

  When it is determined that the pixel value P (N + 2, k, c) is not 1 (NO in step S126), in step S129, the pixel value / intensity conversion circuit 54-3 determines that the pixel value P (N + 2, k, c). ) Is 2 or not. If YES in step S129, in step S130, the pixel value / intensity conversion circuit 54-3 has a pixel value P (N + 1, k, c) of 3 or a pixel value P (N + 3, k, c) of 3. Determine whether or not. If YES in step S130, the process proceeds to step S128. In the case of NO in step S130, in step S131, the pixel value / intensity conversion circuit 54-3 sets the value of the intensity signal Q (N + 2, k, c) to 2, and proceeds to step S134.

  If it is determined that the pixel value P (N + 2, k, c) is not 2 (NO in step S129), the pixel value / intensity conversion circuit 54-3 proceeds to step S132. In step S132, the pixel value / intensity conversion circuit 54-3 determines whether the pixel value P (N + 1, k, c) is 1 or 2, or the pixel value P (N + 3, k, c) is 1 or 2. Determine whether. If YES in step S132, in step S133, the pixel value / intensity conversion circuit 54-3 sets the value of the intensity signal Q (N + 2, k, c) to 3, and proceeds to step S134. If NO in step S132, the process proceeds to step S131.

  In step S134, the pixel value / intensity conversion circuit 54-3 increases the count value c by 1. In step S135, the pixel value / intensity conversion circuit 54-3 determines whether the count value c is greater than 3. judge. If NO in step S135, the process returns to step S124.

  If it is determined that the count value c is greater than 3 (YES in step S135), in step S136, the pixel value / intensity conversion circuit 54-3 converts the value of the intensity signal Q (N + 2, k) into the intensity signal Q (N + 2). , K, 3) and proceeds to step S137. In step S137, the pixel value / intensity conversion circuit 54A-3 determines the intensity signal Q (in pixel units) based on the intensity signal Q (N + 2, k, c) (c = 1, 2, 3) in subpixel clock units. N + 2, k) delay time Td3 is determined. Specifically, the pixel value / intensity conversion circuit 54A-3 has an intensity indicating a value different from the intensity signal Q (N + 2, k) in the intensity signal Q (N + 2, k, c) (c = 1, 2). The number of signals Q (N + 2, k, c) is determined. Then, the pixel value / intensity conversion circuit 54A-3 determines a delay time Td3 proportional to the number of intensity signals Q (N + 2, k, c) indicating values different from the intensity signal Q (N + 2, k). For example, when the intensity signals Q (N + 2, k, c) (c = 1, 2, 3) are all the same value, the intensity signal Q (N + 2, k, showing a value different from the intensity signal Q (N + 2, k). The number of c) is 0. For this reason, the pixel value / intensity conversion circuit 54A-3 determines that the delay time Td3 is zero. When the intensity signal Q (N + 2, k, 1) is different from the intensity signal Q (N + 2, k) and the intensity signal Q (N + 2, k, 2) is the same as the intensity signal Q (N + 2, k), the intensity The number of intensity signals Q (N + 2, k, c) showing a value different from the signal Q (N + 2, k) is one. For this reason, the pixel value / intensity conversion circuit 54A-3 determines that the delay time Td3 is the period (T / 3) of the subpixel clock. Further, when both of the intensity signals Q (N + 2, k, 1) and Q (N + 2, k, 2) are different from the intensity signal Q (N + 2, k), the sub signal indicating a value different from the intensity signal Q (N + 2, k). The number of intensity signals Q (N + 2, k, c) in pixel clock units is 2. Therefore, the pixel value / intensity conversion circuit 54A-3 determines that the delay time Td3 is (2T / 3) which is twice the period of the subpixel clock. After determining the delay time Td3, the pixel value / intensity conversion circuit 54A-3 proceeds to Step S138. In step S138, the pixel value / intensity conversion circuit 54A-3 generates an intensity signal Q (N + 2, k) and a modulation control signal PM3 indicating the delay time Td3, and outputs them to the phase modulation circuit 37-3. The pixel value / intensity conversion process in FIG. 14C ends.

  FIG. 14D is a flowchart showing a pixel value / intensity conversion process executed by the pixel value / intensity conversion circuit 54A-4 of FIG. In step S141 in FIG. 14D, the sub-pixel pattern estimation unit 60-4 performs a sub-pixel pattern estimation process for estimating a sub-pixel pattern in the processing target pixel P0 in FIG. 13A.

The subpixel pattern estimation process in step S141 by the subpixel pattern estimation unit 60-4 is the same as the subpixel pattern estimation process in step S81 of FIG. 14A except for the following differences.
(1) The pixel value of the pixel P0 to be processed in FIG. 13A is a pixel value P (N + 2, k) instead of the pixel value P (N + 1, k).
(2) The pixel values of the pixels P1 to P3 around the pixel P0 to be processed in FIG. 13A are replaced with the pixel values P (N, k + 1), P (N + 1, k + 1), and P (N + 1, k), respectively. , Pixel values P (N + 3, k + 1), P (N + 4, k + 1), and P (N + 4, k). Further, the pixel values of the peripheral pixels P4 to P6 are P (N + 4) instead of P (N + 1, k-1), P (N, k-1), and P (N-1, k-1), respectively. , K-1), P (N + 3, k-1), and P (N + 2, k-1). Further, the pixel values of the surrounding pixels P7 and P8 are replaced with pixel values P (N + 2, k) and P (N + 2, k + 1) instead of P (N-1, k) and P (N-1, k + 1), respectively. Be.
(3) The sub-pixel pattern estimation unit 60-4 refers to the tables 60mt1 to 60mt3 in FIGS. 15, 17 and 19 stored in the memory 60m-4 instead of the memory 60m-1 in FIG. The subpixel pattern estimation process of S141 is executed.

  Next, in step S142, the pixel value / intensity conversion circuit 54A-4, based on the subpixel pattern estimated in step S141, the pixel value P (N + 3, k, c) (c = 1, unit of subpixel clock). 2, 3) is set as follows. That is, the pixel value / intensity conversion circuit 54A-4 uses the subpixel values S11 to S13, S21 to S23, and S31 to S33 in FIG. 13B to generate pixel values P (N + 3, k, c) (c = 1, 2, 3) is set as follows:

P (N + 3, k, 1) = S11 + S12 + S13 (10)
P (N + 3, k, 2) = S21 + S22 + S23 (11)
P (N + 3, k, 3) = S31 + S32 + S33 (12)

  That is, in Expression (10), the pixel value / intensity conversion circuit 54A-4 calculates the sum of the subpixel values S11, S12, and S13, and uses the obtained value as the pixel value P (N + 3 at time c = 1. , K, 1). In Expression (11), the pixel value / intensity conversion circuit 54A-4 calculates the sum of the subpixel values S21, S22, and S23, and uses the obtained value as the pixel value P (N + 3 at time c = 2. , K, 2). Further, in Expression (12), the pixel value / intensity conversion circuit 54A-4 calculates the sum of the sub-pixel values S31, S32, and S33, and uses the obtained value as the pixel value P (N + 3 at time c = 3. , K, 3). That is, the pixel value P (N + 3, k, c) at each time c = 1, 2, 3 of the subpixel clock represents the area of a part of the irradiation region of the laser beam B at the time c. The pixel value / intensity conversion circuit 54A-4 stores data indicating the subpixel values S11 to S13, S21 to S23, and S31 to S33 for the subpixel patterns shown in FIGS. A memory 54Am-4 is provided. The pixel value / intensity conversion circuit 54A-4 refers to the subpixel values S11 to S33 of each of the subpixel patterns stored in the memory 54Am-4, so that the pixel value P (N + 3, k, c) in step S142 is obtained. A process of setting (c = 1, 2, 3) is executed. When the pixel value P (N + 3, k, c) is set as described above in step S142, the pixel value / intensity conversion circuit 54A-4 proceeds to step S143.

  In step S143, the pixel value / intensity conversion circuit 54A-4 sets the count value c to the initial value 1, and in step S144, the pixel value / intensity conversion circuit 54-4 sets the pixel value P (N + 2, k, c). ) Is 0 or not. In the case of YES in step S144, in step S145, the pixel value / intensity conversion circuit 54-4 sets the value of the intensity signal Q (N + 3, k, c) to 0, and proceeds to step S154.

  When it is determined that the pixel value P (N + 2, k, c) is not 0 (NO in step S144), in step S146, the pixel value / intensity conversion circuit 54-4 determines the pixel value P (N + 2, k, c). ) Is 1 or not. If YES in step S146, in step S147, whether the pixel value P (N + 1, k, c) is 3 or the pixel value P (N + 3, k, c) is 3 in the pixel value / intensity conversion circuit 54-4. Determine whether or not. If YES in step S147, the process proceeds to step S145. In the case of NO in step S147, in step S148, the pixel value / intensity conversion circuit 54-4 sets the value of the intensity signal Q (N + 3, k, c) to 1, and proceeds to step S154.

  When it is determined that the pixel value P (N + 2, k, c) is not 1 (NO in step S146), in step S149, the pixel value / intensity conversion circuit 54-4 determines the pixel value P (N + 2, k, c). ) Is 2 or not. If YES in step S149, in step S150, whether the pixel value P (N + 1, k, c) is 3 or the pixel value P (N + 3, k, c) is 3 in the pixel value / intensity conversion circuit 54-4. Determine whether or not. If YES in step S150, the process proceeds to step S148. In the case of NO in step S150, in step S151, the pixel value / intensity conversion circuit 54-4 sets the value of the intensity signal Q (N + 3, k, c) to 2, and proceeds to step S154.

  If it is determined that the pixel value P (N + 2, k, c) is not 2 (NO in step S149), the pixel value / intensity conversion circuit 54-4 proceeds to step S152. In step S152, the pixel value / intensity conversion circuit 54-4 determines whether the pixel value P (N + 1, k, c) is 1 or 2, or the pixel value P (N + 3, k, c) is 1 or 2. Determine whether. If YES in step S152, in step S153, the pixel value / intensity conversion circuit 54-4 sets the value of the intensity signal Q (N + 3, k, c) to 3, and the process proceeds to step S154. If NO in step S152, the process proceeds to step S151.

  In step S154, the pixel value / intensity conversion circuit 54-4 increases the count value c by 1. In step S155, the pixel value / intensity conversion circuit 54-4 determines whether the count value c is greater than 3. judge. If NO in step S155, the process returns to step S144.

  When it is determined that the count value c is greater than 3 (YES in step S155), in step S156, the pixel value / intensity conversion circuit 54-4 converts the value of the intensity signal Q (N + 3, k) into the intensity signal Q ( N + 3, k, 3) is set, and the process proceeds to step S157. In step S157, the pixel value / intensity conversion circuit 54A-4 determines the intensity signal Q (in pixel units) based on the intensity signal Q (N + 3, k, c) (c = 1, 2, 3) in subpixel clock units. N + 3, k) delay time Td4 is determined. Specifically, the pixel value / intensity conversion circuit 54A-4 has an intensity indicating a value different from the intensity signal Q (N + 3, k) in the intensity signal Q (N + 3, k, c) (c = 1, 2). The number of signals Q (N + 3, k, c) is determined. Then, the pixel value / intensity conversion circuit 54A-4 determines a delay time Td4 that is proportional to the number of intensity signals Q (N + 3, k, c) indicating values different from the intensity signal Q (N + 3, k). For example, when the intensity signals Q (N + 3, k, c) (c = 1, 2, 3) are all the same value, the intensity signal Q (N + 3, k, showing a value different from the intensity signal Q (N + 3, k). Since the number of c) is 0, the pixel value / intensity conversion circuit 54A-4 determines that the delay time Td4 is 0. Further, when the intensity signal Q (N + 3, k, 1) is different from the intensity signal Q (N + 3, k) and the intensity signal Q (N + 3, k, 2) is the same as the intensity signal Q (N + 3, k), the intensity The number of intensity signals Q (N + 3, k, c) showing a value different from the signal Q (N + 3, k) is one. For this reason, the pixel value / intensity conversion circuit 54A-4 determines that the delay time Td4 is the period (T / 3) of the subpixel clock. Further, when both the intensity signals Q (N + 3, k, 1) and Q (N + 3, k, 2) are different from the intensity signal Q (N + 3, k), the intensity indicating a value different from the intensity signal Q (N + 3, k). The number of signals Q (N + 3, k, c) is two. Therefore, the pixel value / intensity conversion circuit 54A-4 determines that the delay time Td4 is (2T / 3) which is twice the period of the subpixel clock. After determining the delay time Td4, the pixel value / intensity conversion circuit 54A-4 proceeds to Step S158. In step S158, the pixel value / intensity conversion circuit 54A-4 generates an intensity signal Q (N + 3, k) and a modulation control signal PM4 indicating the delay time Td4, and outputs them to the phase modulation circuit 37-4. The pixel value / intensity conversion process in FIG. 14D ends.

  The operation of the drawing apparatus 1A according to the second embodiment configured as described above will be described below with reference to FIGS.

  FIG. 21 is a top view of the substrate 2 for explaining an example of the exposure operation of the drawing apparatus 1A of FIG. In FIG. 21, the numbers exemplified in each pixel region represent the pixel value P (n, k) in pixel units in the pattern image data 31d of FIG. 5A. For example, the pixel values P (N, 1), P (N, 2), P (N + 1,1), and P (N + 1,2) of the pixels G1 to G4 shown in FIG. , 3. Note that the example of the pattern image data shown in FIG. 21 does not have an edge parallel to an oblique direction different from the main scanning direction X and the sub-scanning direction Y. Therefore, the sub-pixel pattern of each pixel in the pattern image matches any of the sub-pixel patterns shown in FIG. 16, FIG. 18, and FIG.

  In FIG. 21, each subpixel pattern estimation part 60-1 to 60-4 of FIG. 12 performs a subpixel pattern estimation process, and estimates a subpixel pattern (step S81, S101, S121, S141). For example, the subpixel pattern estimation unit 60-1 estimates that the subpixel patterns of the pixels G1 and G2 are the subpixel patterns SP24 and SP34 in FIG. 16, respectively. Further, the subpixel pattern estimation unit 60-2 estimates that the subpixel patterns of the pixels G3 and G4 are the subpixel pattern SP63 in FIG. 17 and the subpixel pattern SP91 in FIG. A part of the irradiation area of the laser beam B surrounded by the two-dot chain line in FIG. 21 configured by the subpixel pattern estimated in this way is parallel to the edge E1 parallel to the X direction and the Y direction in the pixel G1. It has a convex corner C1 where the edge E2 intersects each other. The corner C1 is shifted by a distance of 1/3 pixel, that is, 1 subpixel in the main scanning direction X from the upper left corner of the pixel G1 in the drawing, and 2/3 pixel, that is, 2 subpixels in the subscanning direction Y. At a position shifted by the distance.

  Based on the subpixel pattern estimated as described above, the pixel value / intensity conversion circuits 54A-1 to 54A-4 respectively calculate the values of the intensity signals Q (N, k) to Q (N + 3, k) in pixel units. Set. Specifically, in the pixel value / intensity conversion process of FIG. 14A, the pixel value / intensity conversion circuit 54A-1 sets the value of the intensity signal Q (N, k) to 0 at each time k = 1 and 2. At the same time, the delay time Td1 is set to zero. Therefore, at each time k = 1, 2, the pixel value / intensity conversion circuit 54A-1 does not emit the laser beam B1 at each time k = 1, 2. In the pixel value / intensity conversion process of FIG. 14B, the pixel value / intensity conversion circuit 54A-2 sets the value of the intensity signal Q (N, 1) to 3 at time k = 1 and sets the delay time Td2. It is set to (1/3) of the period T of one pixel clock, that is, (T / 3). Also, the pixel value / intensity conversion circuit 54A-2 sets the value of the intensity signal Q (N, 2) to 3 and sets the delay time Td2 to 0 at time k = 2. Therefore, the laser beam B2 having the intensity 3 is delayed by the delay time Td2 = T / 3 at the time k = 1, and starts to irradiate the area of the (N + 1) th scan row, and at the time k = 2 (N + 1). ) Continue to irradiate the area of the scan line. At this time, the laser beam B2 having intensity 3 exposes the exposure surface 2a across the areas on the Nth and (N + 2) th scan rows adjacent to the (N + 1) th scan row.

  FIG. 22 is a top view of the substrate 2 for explaining another example of the exposure operation of the drawing apparatus 1A of FIG. In FIG. 22, the numbers exemplified in each pixel region represent the pixel value P (N + 1, k) in the pattern image data 31d of FIG. 5A. For example, the pixel values P (N + 1, 2), P (N + 1, 3), P (N + 2, 2), and P (N + 2, 3) of the pixels G5 to G8 shown in FIG. , 3.

  In FIG. 22, each subpixel pattern estimation part 60-1 to 60-4 of FIG. 12 performs a subpixel pattern estimation process, and estimates a subpixel pattern (step S81, S101, S121, S141). For example, the subpixel pattern estimation unit 60-2 estimates that the subpixel patterns of the pixels G5 and G6 are the subpixel pattern SP33 of FIG. 16 and the subpixel pattern SP91 of FIG. Further, the subpixel pattern estimation unit 60-3 estimates that the subpixel patterns of the pixels G7 and G8 are the subpixel patterns SP75 and SP91 of FIG. 18, respectively. A part of the irradiation area of the laser beam B surrounded by the two-dot chain line in FIG. 22 configured by the subpixel pattern estimated in this way is parallel to the edge E3 parallel to the X direction and the Y direction in the pixel G7. A convex corner C2 intersecting with the edge E4 is provided. The corner C2 is shifted by a distance of 2/3 pixels, that is, 2 sub-pixels in the main scanning direction X from the upper left corner of the pixel G7 in the figure, and 1/3 pixels, that is, 1 sub-pixel in the sub scanning direction Y At a position shifted by the distance.

  Based on the subpixel pattern estimated as described above, the pixel value / intensity conversion circuits 54A-1 to 54A-4 respectively calculate the values of the intensity signals Q (N, k) to Q (N + 3, k) in pixel units. Set. Specifically, in the pixel value / intensity conversion process of FIG. 14B, the pixel value / intensity conversion circuit 54A-2 sets the value of the intensity signal Q (N + 1, 2) to 2 at each time k = 2. The delay time Td2 is set to (2T / 3). The pixel value / intensity conversion circuit 54A-2 sets the value of the intensity signal Q (N + 1, 3) to 2 and sets the delay time Td2 to 0 at each time k = 3. Therefore, the laser beam B2 having the intensity 2 is delayed by the delay time Td2 = 2T / 3 at the time k = 2, and starts to irradiate the area of the (N + 2) th scan row, and at the time k = 3, (N + 2). ) Continue to irradiate the area of the scan line. In the pixel value / intensity conversion process of FIG. 14C, the pixel value / intensity conversion circuit 54A-3 sets the value of the intensity signal Q (N + 2, 2) to 3 at time k = 2 and sets the delay time Td3. Set to (2T / 3). The pixel value / intensity conversion circuit 54A-3 sets the value of the intensity signal Q (N + 2, 3) to 2 and sets the delay time Td3 to 0 at time k = 3. For this reason, at time k = 2, the laser beam B3 continues to irradiate the area of the (N + 2) th scan row at intensity 1 following time k = 1, and further from time k = 2 to delay time Td3 = 2T. The intensity of the laser beam B3 is changed from intensity 2 to intensity 3 with a delay of / 3.

  According to the rendering apparatus 1A according to the second embodiment configured as described above, the pixel value / intensity conversion circuit 54A generates a sub-pixel pattern from the pixel values of the pixel P0 to be processed and the surrounding pixels P1 to P8. A subpixel pattern estimation processing unit for estimation is provided. Further, the pixel value / intensity conversion circuit 54A determines delay times Td1 to Td4 of the output timing of the intensity signal Q (n, k) from each pixel value in units of subpixel clocks based on the estimated subpixel pattern. Then, modulation control signals PM1 to PM4 indicating the delay times Td1 to Td4 are generated. Furthermore, the drawing apparatus 1A further includes a phase modulation circuit 37 provided between the intensity signal generation circuit 54A and the drive unit 35. The phase modulation circuit 37 shifts the output timing of the intensity signal Q (n, k) to the drive unit 35 by the delay times Td1 to Td4 indicated by the modulation control signals PM1 to PM4. Therefore, the light source circuit 11 can emit laser beams B1 to B4 that can be resolved at a desired subpixel position. Therefore, the drawing apparatus 1A can perform exposure drawing with higher accuracy than the beam pitch D, more accurately and more efficiently than the prior art.

  In the present embodiment, the pixel value / intensity conversion circuits 54A-1 to 54A-4 set the delay times Td1 to Td4 to 0 or a positive value, respectively. However, the present invention is not limited to this, and some of the pixel value / intensity conversion circuits 54A-1 to 54A-4 may set the delay times Td1 to Td4 to negative values. When the delay times Td1 to Td4 are negative, the phase modulation circuits 37-1 to 37-4 respectively transfer the intensity signals Q (N, k) to Q (N + 3, k) to the drive units 35-1 to 35-4. The output timing is shifted so as to be advanced by delay times Td1 to Td4.

  In the present embodiment, the sub-pixel pattern estimation units 60-1 to 60-4 execute the sub-pixel pattern estimation process on the fly at the time of drawing the pattern image. However, the present invention is not limited to this, and the subpixel patterns 60-1 to 60-4 execute the subpixel pattern estimation process before drawing the pattern image, and store the estimated subpixel pattern in, for example, the pattern image memory 31. You may do it. The pixel value / intensity conversion circuits 54A-1 to 54A-4 refer to, for example, the subpixel patterns stored in the pattern image memory 31 at the time of drawing the pattern image, and the intensity signal generation circuits Q (N, k) to Q (N + 3, k) and delay times Td1 to Td4 are set.

  In the present embodiment, the light source circuit 11 includes a phase modulation circuit 37. However, the present invention is not limited to this, and the light source circuit 11 modulates the pulse width so as to delay the output timing of the signal Q (n, k) to the D / A converter 34 instead of the phase modulation circuit 37. A PWM (Pulse Width Modulation) circuit may be provided. In general, the PWM circuit is used, for example, in a copying machine to modulate the phase of a pixel clock.

Modified example.
FIGS. 23A to 23C are diagrams showing examples of sub-pixel patterns with areas 1 to 3 according to the modification of the second embodiment of the present invention. 23A to 23C, the subpixel patterns are estimated by the subpixel pattern estimation unit 60 in each case where the pixel value P (n, k) is 1 to 3. Here, the subpixel pattern estimation unit 60 may create a mirror image or a rotated image of each subpixel pattern shown in FIG. 23 and use it as a subpixel pattern. Since the object of exposure is a wiring pattern such as a printed circuit board, a subpixel pattern that is a part of a pattern image that is a wiring pattern is a connected image, and is one of the subpixel patterns shown in FIG.

  FIG. 24 is a diagram illustrating an example of a pattern image configured by the sub-pixel pattern of FIG. The illustrated pattern image has corners that are chamfered with sub-pixel accuracy. In FIG. 24, the numbers exemplified in each pixel region represent the pixel value P (n, k) in the pattern image data 31d. 24, the sub-pixel pattern estimation units 60-1 to 60-4 according to the present modification are hatched based on the pixel values of the pixel P0 to be processed and the surrounding pixels P1 to P8 in FIG. 13A. A sub-pixel pattern including a part irradiation region is estimated. That is, the sub-pixel pattern estimation units 60-1 to 60-4 estimate the sub-pixel pattern candidates to be drawn so that the accuracy error with respect to the sub-pixel pattern of the original pattern image is smaller than the other sub-pixel patterns. In addition, when there are a plurality of subpixel pattern candidates, the subpixel pattern estimation units 60-1 to 60-4 select a subpixel pattern candidate with a smaller accuracy error and a lower accuracy, thereby improving accuracy. Draw a pattern image with few errors.

  In FIG. 24, pixel value / intensity conversion circuits 54A-1 to 54A-4 set values of intensity signals Q (N, k) to Q (N + 3, k) based on the estimated subpixel patterns, respectively. At the same time, delay times Td1 to Td4 for designating the irradiation start position are determined. Pixel value / intensity conversion circuits 54A-1 to 54A-4 generate modulation control signals PM1 to PM4 including intensity signals Q (N, k) to Q (N + 3, k) and delay times Td1 to Td4, respectively. It outputs to the modulation circuits 37-1 to 37-4. For example, in the (N + 1) th scan row, the pixel value P (N + 1, 3) of the target pixel G9 at time k = 3 is 2. The pixel value above the target pixel G9 is 0, the left pixel value is 0, and the lower left pixel value is 2. For example, when the line and space rule is 25 μm / 25 μm, the sub-pixel pattern of the pattern image does not have local unevenness of 5 μm or less. Therefore, the sub-pixel pattern estimation units 60-1 to 60-4 estimate the sub-pixel pattern shown in FIG. 24, assuming that the sub-pixel pattern including a part of the diagonal line has the least accuracy error with respect to the original pattern image. .

  FIG. 25 is a top view of the substrate 2 for explaining the exposure operation of the drawing apparatus 1A of FIG. 11 according to the sub-pixel pattern of FIG. In FIG. 25, the pixel value / intensity conversion circuits 54A-1 to 54A-4 each determine the irradiation start position of the laser beams B1 to B4 based on the estimated subpixel pattern of FIG. In other words, each of the pixel value / intensity conversion circuits 54A-1 to 54A-4 is based on the sub-pixel pattern of FIG. 24, and the irradiation delay time of the laser beams B1 to B4 (hereinafter, the delay time is the pixel clock at each time). ) Td1 to Td4 are determined by the time accuracy of the subpixel clock. The phase modulation circuits 37-1 to 37-4 control the irradiation position based on the delay times Td1 to Td4 set according to the estimated / selected subpixel pattern. Such control of the shooting start position is generally used in, for example, a copying machine. The pixel value / intensity conversion circuits 54A-1 to 54A-4 respectively control the phase modulation circuits 37-1 to 37-4 according to the estimated and selected subpixel patterns.

  The pixel value / intensity conversion circuit 54A-1 sets the value of the intensity signal Q (N, k) to 0 and the intensity signal Q (N, k) at each time k = 1, 2, 3 of the pixel clock. The delay time Td1 of the output timing is set to 0. The pixel value / intensity conversion circuit 54A-2 sets the value of the intensity signal Q (N + 1, 2) to 1 at time k = 2 and delays the output timing of the intensity signal Q (N + 1, 2). Td2 is set to (T / 3). As a result, in the pixel region at time k = 2 in the (N + 1) th scanning column, the laser beam B2 is not irradiated to the first subpixel row, and the laser beam B2 having intensity 1 is the pixel clock at time k = 2. The second subpixel row is irradiated with a delay of Td2 = T / 3 from the timing. Further, the pixel value / intensity conversion circuit 54A-3 sets the value of the intensity signal Q (N + 2, 1) and the delay time Td3 of the output timing of the intensity signal Q (N + 2, 1) at time k = 1 as follows. Set. That is, the pixel value / intensity conversion circuit 54A-3 sets the value of the intensity signal Q (N + 2, 1) to 1, and sets the delay time Td3 of the output timing of the intensity signal Q (N + 2, 1) of the value 1 to T / Set to 3. The pixel value / intensity conversion circuit 54A-3 sets the value of the intensity signal Q (N + 2, 1) to 2, and sets the delay time Td3 of the output timing of the intensity signal Q (N + 2, 1) of the value 2 to (2 / 3) Set to T. As a result, in the pixel region at time k = 1 in the (N + 2) th scanning column, the first subpixel row has a delay time Td3 = (2/3) T from the timing of the pixel clock at time k = 1. The laser beam B3 having intensity 2 is irradiated with a delay. The second sub-pixel row in the pixel region is irradiated with the laser beam B3 having an intensity of 1 with a delay time Td3 = T / 3 from the timing of the pixel clock. Furthermore, the pixel value / intensity conversion circuit 54A-3 sets the value of the intensity signal Q (N + 2, 2) to 3 and sets the delay time Td3 to 0 at time k = 2. As a result, the laser beam B3 having intensity 2 is applied to the third sub-pixel row in the pixel region at time k = 2 in the (N + 2) th scan column at the timing of the pixel clock at time k = 2. Furthermore, the pixel value / intensity conversion circuit 54A-4 sets the value of the intensity signal Q (N + 3, 1) to 3 and delays the output timing of the intensity signal Q (N + 3, 1) at time k = 1. Time Td4 is set to (T / 3). As a result, the laser beam B2 having the intensity 3 is delayed by the delay time Td4 = T / 3 from the timing of the pixel clock at time k = 1, and the pixel region at time k = 1 in the (N + 3) th scanning column ( Irradiation is performed on the third sub-pixel row in the pixel region at time k = 1 in the (N + 2) th scan column.

  With the configuration of the drawing apparatus 1A according to the present modification of the second embodiment configured as described above, it is possible to draw a pattern image including a subpixel pattern including a boundary of diagonal lines with high resolution. Therefore, the drawing apparatus 1A according to the present modified example performs exposure drawing more accurately and more efficiently than the pattern image drawing operation performed by the drawing apparatus 1A according to the second embodiment described with reference to FIGS. It can be performed.

  In the first and second embodiments, the pixel is composed of nine subpixels obtained by dividing the pixel into three rows and three columns. However, the present invention is not limited to this, and the pixel may be composed of a plurality of subpixels obtained by dividing the pixel into a predetermined number of rows and a predetermined number of columns.

Summary of Embodiment A drawing apparatus according to a first aspect is a drawing apparatus that draws a pattern image on an object by scanning laser light in a main scanning direction,
Based on the pattern image data of the pattern image, an intensity signal generation circuit that generates an intensity signal indicating the intensity of the laser beam for each pixel of the pixel value sequence in the main scanning direction in the pattern image data;
A drive unit that generates a pixel irradiation drive signal based on the intensity signal;
A laser element that emits laser light based on a pixel irradiation drive signal from the drive unit,
The intensity signal generation circuit is
When the pixel value of the processing target pixel is the maximum value, the pixel value of the pixel adjacent to the processing target pixel in the sub-scanning direction orthogonal to the main scanning direction is larger than the minimum value and larger than the maximum value. When it is small, the pixel value of the pixel to be processed is set as the intensity signal of the pixel to be processed so that the beam spot formed on the object by the laser beam has a spot diameter larger than a predetermined beam pitch. And a pixel value / intensity conversion circuit for converting to the above value.

  The drawing device according to a second aspect is the drawing device according to the first aspect, wherein the pixel value / intensity conversion circuit has a pixel value of the pixel to be processed larger than the minimum value and larger than the maximum value. If small, the spot diameter of the beam spot formed on the object by the laser beam when the pixel value of the pixel adjacent to the processing target pixel in the sub-scanning direction is the maximum value is set to the adjacent The pixel value of the pixel to be processed is set to the value of the intensity signal of the pixel to be processed so that the pixel value of the pixel to be processed is smaller than the spot diameter when the pixel value is larger than the minimum value and smaller than the maximum value. It is characterized by converting into.

The drawing device according to a third aspect is the drawing device according to the first or second aspect, wherein the pixel value / intensity conversion circuit is based on the pixel values of the pixel to be processed and surrounding pixels. A sub-pixel pattern estimation processing unit that estimates a sub-pixel pattern composed of pixel values in units of sub-pixels obtained by dividing a pixel to be processed into a predetermined number of rows and a predetermined number of columns from pixel values of surrounding pixels. With
Based on the estimated subpixel pattern, the pixel value / intensity conversion circuit includes each pixel of a plurality of subpixels in a subpixel clock unit corresponding to each column of the subpixels within the pixel to be processed. Determining a delay time of the output timing of the intensity signal from the value, and generating a modulation control signal indicating the delay time;
The drawing apparatus is provided between the intensity signal generation circuit and the drive unit, and includes phase modulation means for shifting the output timing of the intensity signal to the drive unit by a delay time indicated by the modulation control signal. It is further provided with the feature.

  A drawing apparatus according to a fourth aspect is the drawing apparatus according to any one of the first to third aspects, wherein the beam pitch is a size of one pixel in the sub-scanning direction. Features.

  A drawing apparatus according to a fifth aspect is the drawing apparatus according to any one of the first to fourth aspects, wherein the object is a substrate.

1, 1A ... drawing device,
2 ... substrate,
2a ... exposed surface,
11, 11A ... Light source circuit,
12 ... Laser beam introduction part,
13 ... Condensing lens,
14 ... Cylindrical lens,
15 ... Polygon mirror,
16 ... fθ lens,
17 ... stage,
18 ... Sub-scanning conveyance unit,
21-1 to 21-4 ... lens,
22-1 to 22-4: optical fiber,
23 ... Glass substrate,
31 ... Pattern image memory,
32. Read circuit,
32a-1 to 32a-4 ... line buffer,
33-1 to 33-4, 33A-1 to 33A-4, an intensity signal generating circuit,
34-1 to 34-4 ... D / A converter,
35-1 to 35-4 drive unit,
36 ... Semiconductor substrate,
36a-1 to 36a-4 ... laser element,
37-1 to 37-4: phase modulation circuit,
51-1 to 51-4, 52-1 to 52-4, 53-1 to 53-4, registers,
51A-1 to 51A-4, 52A-1 to 52A-4, 53A-1 to 53A-4... Shift register,
54-1 to 54-4, 54A-1 to 54A-4, pixel value / intensity conversion circuit,
54Am-1 to 54Am-4 ... memory,
60-1 to 60-4... Subpixel pattern estimation unit,
60m-1 to 60m-4 ... Memory.

Japanese Patent No. 4938069 Japanese Patent Publication No. 2-54937 JP 2010-156901 A

Claims (5)

A drawing apparatus that draws a pattern image on an object by scanning a laser beam in a main scanning direction,
Based on the pattern image data of the pattern image, an intensity signal generation circuit that generates an intensity signal indicating the intensity of the laser beam for each pixel of the pixel value sequence in the main scanning direction in the pattern image data;
A drive unit that generates a pixel irradiation drive signal based on the intensity signal;
A laser element that emits laser light based on a pixel irradiation drive signal from the drive unit,
The intensity signal generation circuit is
When the pixel value of the processing target pixel is the maximum value, the pixel value of the pixel adjacent to the processing target pixel in the sub-scanning direction orthogonal to the main scanning direction is larger than the minimum value and larger than the maximum value. When it is small, the pixel value of the pixel to be processed is set as the intensity signal of the pixel to be processed so that the beam spot formed on the object by the laser beam has a spot diameter larger than a predetermined beam pitch. A drawing apparatus comprising a pixel value / intensity conversion circuit for converting to a value of.   The pixel value / intensity conversion circuit, when a pixel value of the pixel to be processed is larger than the minimum value and smaller than the maximum value, a pixel value of a pixel adjacent to the pixel to be processed in the sub-scanning direction When the spot diameter of the beam spot formed on the object by laser light when is the maximum value, the pixel value of the adjacent pixel is larger than the minimum value and smaller than the maximum value 2. The drawing apparatus according to claim 1, wherein the pixel value of the pixel to be processed is converted into a value of an intensity signal of the pixel to be processed so as to be smaller than a spot diameter of the pixel. The pixel value / intensity conversion circuit, based on the pixel values of the pixel to be processed and its surrounding pixels, calculates the pixel to be processed from the pixel values of the peripheral pixels and a predetermined number of rows. A sub-pixel pattern estimation processing unit that estimates a sub-pixel pattern composed of pixel values in units of sub-pixels divided into columns of
Based on the estimated subpixel pattern, the pixel value / intensity conversion circuit includes each pixel of a plurality of subpixels in a subpixel clock unit corresponding to each column of the subpixels within the pixel to be processed. Determining a delay time of the output timing of the intensity signal from the value, and generating a modulation control signal indicating the delay time;
The drawing apparatus is provided between the intensity signal generation circuit and the drive unit, and includes phase modulation means for shifting the output timing of the intensity signal to the drive unit by a delay time indicated by the modulation control signal. The drawing apparatus according to claim 1, further comprising:   The drawing apparatus according to claim 1, wherein the beam pitch is a size of one pixel in a sub-scanning direction.   The drawing apparatus according to claim 1, wherein the object is a substrate.

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