JP2015126378A - Signal modulation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow for real time correction of the output state while reducing the effects of distortion and noise component due to a delay device, and to output an input signal while performing PDM modulation with high voltage utilization efficiency.SOLUTION: A signal modulation circuit includes a subtractor 20 for calculating the difference of an input signal and feedback signal, an integrator 22, and a DFF 24 for inserting a zero level at a timing synchronous with the clock signal, and performing quantization with a delay. A switching section 30 changes the pulse width by comparing the signal level of the integrator 22 with a predetermined value, fixing the pulse width by allowing insertion of zero level in the DFF 24 when the signal level is within a predetermined value, and prohibiting insertion of zero level when the predetermined value is exceeded.

Description

  The present invention relates to a signal modulation circuit, and more particularly to a circuit that performs delta-sigma modulation.

  Conventionally, delta-sigma modulation (ΔΣ modulation) is used in switching amplifiers and the like. The delta-sigma modulator includes a subtracter, an integrator, a quantizer, and a quantization error feedback circuit.

  FIG. 10 shows a basic configuration of the delta-sigma modulation circuit. The subtracter 16 calculates the difference between the input signal and the feedback signal, and the integrator 10 integrates the difference signal. The integrated signal is quantized by the quantizer 14 and output as, for example, a signal of 1 bit = 2 values. The quantization error is fed back via the delay unit 12.

  The following Patent Document 1 discloses a delta-sigma modulation circuit composed of an integrator group, an adder group, a quantizer, and a pulse width round-up circuit, which is converted into a 1-bit signal synchronized with a sampling clock and output. Is disclosed. Further, it is disclosed that a D-type flip-flop is used as a quantizer. Patent Document 2 also discloses a digital sigma modulation circuit.

  Patent Document 3 discloses a configuration in which the minimum pulse width is controlled in a delta sigma modulator depending on the value of an input signal of the delta sigma modulator or a value including a component of the input signal. When the amplitude of the input signal is particularly large, the minimum pulse width is reduced to ensure the oscillation limit value, while when the amplitude of the input signal is not so large, the minimum pulse width is increased.

JP 2007-31258 A Special table 2012-527187 gazette Japanese Patent No. 4111605

  In the configuration shown in FIG. 10, noise shaping is performed by providing a delay unit 12 in the feedback path, but at the same time, there is a problem that the output state cannot be corrected in real time by the delay unit 12 in the feedback path, or a delay There is a problem that distortion / noise components generated in the chamber are output as they are without noise shaping.

  When the delta-sigma modulation circuit is used for a 1-bit audio amplifier or the like, there are pulse width modulation (PWM) and pulse density modulation (PDM) as methods for converting an input signal into a 1-bit digital signal. When using a PDM suitable for expressing an input signal by frequency, it is necessary to insert a zero level at a predetermined timing to maintain the pulse width and to reliably modulate the level of the input signal to the frequency of the pulse.

  In Patent Document 3, in the delta-sigma modulator, the minimum pulse width is controlled according to the value of the input signal. As a premise, this is a modulation method in which the pulse width is variable, and a zero level is inserted at a predetermined timing. Thus, the pulse width is not maintained.

  An object of the present invention is to correct an output state in real time and reduce the influence of distortion and noise components caused by a delay device, and to maintain a pulse width by inserting a zero level at a predetermined timing. An object of the present invention is to provide a circuit that can modulate and output an input signal with high voltage utilization efficiency.

  The present invention relates to a signal modulation circuit that outputs a delta-sigma modulation of an input signal in synchronization with a clock signal, and calculates a difference between the input signal and a feedback signal, and integrates an output from the subtractor. A quantizer that delays and quantizes the signal integrated by the integrator while inserting a zero level at a timing synchronized with the clock signal, and is quantized by the quantizer A feedback circuit that feeds back a signal to the input signal, and a level of the signal integrated by the integrator is compared with a predetermined value, and if it is within the predetermined value, the insertion of the zero level in the quantizer is permitted. And a control section for changing the pulse width by prohibiting insertion of the zero level in the quantizer when the pulse width is fixed and exceeds the predetermined value.

  In one embodiment of the present invention, the quantizer is a flip-flop having a reset terminal, and a zero level is inserted at a timing synchronized with the clock signal by supplying the clock signal to the reset terminal. The control unit supplies the clock signal to the reset terminal when the level of the signal integrated by the integrator is within the predetermined value, and supplies the clock signal to the reset terminal when the level exceeds the predetermined value. It is characterized by not.

In addition, the present invention is a signal modulation circuit that outputs a delta-sigma modulation of an input signal in synchronization with a clock signal, and calculates a difference between the input signal and a feedback signal, and an output from the subtractor An integrator that integrates the signal, a phase inversion circuit that inverts the phase of the signal integrated by the integrator, and a zero level inserted into the signal integrated by the integrator at a timing synchronized with the clock signal. A first quantizer for quantizing with delay, and a second quantizer for delaying and quantizing the signal inverted in phase by the phase inverting circuit while inserting a zero level at a timing synchronized with the clock signal , A pulse synthesis circuit that synthesizes the signal quantized by the first quantizer and the signal quantized by the second quantizer, and the signal synthesized by the pulse synthesis circuit is fed back to the input signal Return And the level of the signal integrated by the integrator and the level of the phase-inverted signal are compared with a predetermined value, and if the level is within the predetermined value, the first quantizer and the second quantizer The pulse width is fixed by permitting the insertion of the zero level, and the pulse width is suppressed by prohibiting the insertion of the zero level in the first quantizer and the second quantizer when the predetermined value is exceeded. It is characterized by having a control part to change.
In one embodiment of the present invention, each of the first quantizer and the second quantizer is a flip-flop having a reset terminal, and is synchronized with the clock signal by supplying the clock signal to the reset terminal. The control unit supplies the clock signal to the reset terminal when the level of the signal integrated by the integrator and the level of the phase-inverted signal are within the predetermined value. The clock signal is not supplied to the reset terminal when the predetermined value is exceeded.

  According to the present invention, the output state can be corrected in real time, the influence of distortion and noise components caused by the delay device can be reduced, and the input signal can be modulated and output with high voltage utilization efficiency.

It is a circuit block diagram used as the premise of embodiment. It is a circuit block diagram of an embodiment. It is signal waveform explanatory drawing of embodiment. It is a circuit block diagram of other embodiment. It is signal waveform explanatory drawing of other embodiment. It is a circuit block diagram of other embodiment. It is a circuit block diagram of other embodiment. It is a circuit block diagram of other embodiment. It is a circuit block diagram of a monovalent ternary waveform generation circuit and a driver circuit. It is a conventional circuit block diagram.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<Assumed circuit configuration>
First, a circuit configuration that is a premise in the present embodiment will be described. FIG. 1 shows a prerequisite circuit configuration. The signal modulation circuit shown in FIG. 1 performs delta-sigma modulation on an input signal, and includes a subtracter 20, an integrator 22, and a zero reset type DFF (delay type flip-flop) 24 as a quantizer. The clock signal from the clock signal source 26 is delayed by the delay circuit 28 and supplied to the clock terminal of the zero reset type DFF 24, and the clock signal is also supplied to the reset terminal of the zero reset type DFF 24.

  The subtracter 20 calculates a difference between the input signal and the feedback signal and outputs the difference to the integrator 22. The integrator 22 integrates the difference signal and outputs it to the zero reset type DFF 24. The zero reset type DFF 24 converts the output of the integrator 22 into a 1-bit digital signal in synchronization with the clock signal and outputs it, and the output signal is fed back to the subtracter 20 by a feedback circuit.

  Comparing the circuit shown in FIG. 1 with the circuit shown in FIG. 10, in the circuit of FIG. 1, the delay circuit 12 does not exist in the feedback circuit, and the zero reset type DFF 24 is provided in the subsequent stage of the integrator 22. Therefore, the circuit of FIG. 1 can correct the output state in real time. The delay function and the quantization function are realized by the DFF 24. In the zero reset type DFF 24, the output can be made zero by supplying a signal to the reset terminal, and the clock signal is supplied to the reset terminal. Thus, a zero level is inserted at a timing synchronized with the clock signal.

  In the circuit configuration of FIG. 1, since a zero level is always inserted at a timing synchronized with the clock signal, the output of the zero reset type DFF 24 is a 1-bit digital signal, and the pulse width is always a fixed digital signal. That is, since the DFF outputs a signal at the rising edge of the input clock signal, for example, when the clock signal is supplied after being delayed and inverted by the delay circuit 28, the signal is output at the falling edge of the clock signal. The output is reset to zero level at the rising edge of, and the process is repeated thereafter, whereby the pulse width of the 1-bit digital signal becomes equal to the pulse width of the clock signal. In the circuit configuration of FIG. 1, although the magnitude of the input signal can be expressed by the number of pulses having a fixed pulse width, the modulation by the number of pulses is saturated when the amplitude of the input signal is particularly large. There is a limit to the amplitude of the input signal that can be used, and the voltage utilization efficiency is reduced.

  Therefore, in the present embodiment, the delay circuit 12 is not included in the feedback circuit as in the circuit configuration of FIG. 1, and a zero level is inserted and quantized at a predetermined timing in synchronization with the clock signal to quantize the 1-bit digital signal. The input signal is reliably modulated even when the amplitude of the input signal is large. Specifically, when the amplitude of the input signal is small and the level of the integral output is small, the pulse width is fixed and modulated. When the amplitude of the input signal is large and the level of the integral output is large, the level is zero. By prohibiting insertion, the pulse width is consequently expanded and modulated. Specifically, the pulse width is fixed and modulated as 1, 0, 1, 0, 1, 0,..., But by prohibiting zero level insertion, 1, 1, 1, 1, 1 , 1... To increase the pulse width. In the circuit configuration of FIG. 1, the zero level insertion timing is controlled by supplying a clock signal. Therefore, in order to prohibit the insertion of the zero level, the supply of the clock signal to the reset terminal may be prohibited.

  In the circuit configuration of FIG. 1, modulation is performed while fixing the pulse width by always inserting a zero level at a timing synchronized with the clock signal. In this embodiment, the modulation is performed with the pulse width fixed as described above. It is defined as PDM (pulse density modulation). According to such a definition, the signal modulation according to the present embodiment is a PDM with an expanded pulse width when the amplitude of the input signal is large, and each pulse corresponds to a bit. Can also be expressed. Note that in the conventional patent document 3, the minimum pulse width is controlled according to the amplitude of the input signal, and the pulse width always fluctuates, so that it is essentially different from the PDM in this embodiment.

  Further, PWM for changing the pulse width according to the amplitude of the input signal is also known, and the pulse width is expanded also in this embodiment when the amplitude of the input signal is large and the level of the integral output of the integrator 22 is large. If attention is paid only to this part, it can be said that the modulation is similar to PWM, but in this embodiment, the zero level is inserted when exceeding a certain level, assuming a PDM in which the pulse width is fixed by inserting the zero level. Since the pulse width is expanded by prohibiting the above, it is different from the known PWM.

<Circuit Configuration of Embodiment>
FIG. 2 shows a signal modulation circuit of this embodiment. In addition to the circuit configuration of FIG. 1, a switching unit 30 and a zero reset signal generation unit 32 are further provided as a control unit that controls insertion of a zero level in the zero reset type DFF 24.

  The switching unit 30 compares the output level of the integrator 22 with a predetermined value, and outputs a switching signal to the zero reset signal generating unit 32 when the output level of the integrator 22 exceeds the predetermined value. In other words, the switching unit 30 sets the switching signal to a low level when the output level of the integrator 22 is equal to or lower than a predetermined value, and outputs the switching signal as a high level when the output level of the integrator 22 exceeds a predetermined value. This switching signal functions as a signal for switching from modulation with a fixed pulse width to modulation with an increased pulse width.

  The zero reset signal generation unit 32 is supplied with the clock signal 26 and the switching signal from the switching unit 30. The zero reset signal generator 32 outputs the clock signal 26 as it is to the reset terminal of the zero reset type DFF 24 when the switching signal is at the Low level, and does not output the clock signal 26 to the reset terminal when the switching signal is at the Hi level.

  As in the case of FIG. 1, the zero-reset type DFF 24 converts the output of the integrator 22 into a 1-bit digital signal and outputs it while inserting a zero level at the timing when the signal is supplied to the reset terminal. In the present embodiment, when the output of the integrator 22 is equal to or less than a predetermined value, the clock signal is supplied to the reset terminal as in FIG. 1, so that a zero level is inserted as in FIG. A digital signal is output, but when the output of the integrator 22 exceeds a predetermined value, the clock signal is not supplied to the reset terminal, so that no zero level is inserted, and as a result, the pulse width is fixed compared to the case where the pulse width is fixed. Expand. As the amplitude of the input signal increases, the output of the integrator 22 expands accordingly. Therefore, the period during which no cell level is inserted is expanded, and as a result, the pulse width is also expanded. Accordingly, a pulse width corresponding to the amplitude of the input signal is obtained, and a digital signal having a pulse width corresponding to the amplitude of the input signal is generated.

  FIG. 3 shows the relationship between the input signal and the output of the zero reset type DFF 24. FIG. 3A shows an output waveform of the zero reset type DFF 24, and FIG. 3B shows a waveform obtained by removing the high frequency component by passing the input signal through a low-pass filter. When the amplitude of the input signal is small, PDM with a fixed pulse width in which a zero level is inserted is performed. When the amplitude of the input signal is large, PDM with an expanded pulse width is performed without inserting a zero level.

  In the present embodiment, the switching unit 30 compares the output of the integrator 22 with a predetermined value and outputs a switching signal. The predetermined value is no longer modulated in a pulse width fixed PDM in which a zero level is inserted. It is preferable that the saturation level is not possible, and an integration level corresponding to a modulation degree of 100% by PDM can be set to a predetermined value. Of course, a predetermined margin may be provided for an integration level corresponding to a modulation degree of 100% by PDM.

  FIG. 4 shows a signal modulation circuit according to another embodiment. The circuit configuration of FIG. 2 is different from the circuit configuration of FIG. 2 in that a binary signal of +1,0 is output from the zero reset type DFF 24, but this is expanded to a ternary signal of + 1,0, -1. Is a point. Due to the spread of portable devices in recent years and the demand for energy saving, further efficiency improvement of class D amplifiers is demanded. In general class D amplifiers, the level is expressed by the average value of two signals, positive voltage and negative voltage, zero voltage. In the no-signal state, a positive voltage and a negative voltage are expressed with a duty of 50%, a switching loss occurs, and this improvement is demanded. Therefore, in this embodiment, a state in which switching is not performed when there is no signal is generated by generating +1, 0, −1 ternary signals while utilizing the circuit configuration of FIG. 2.

  In addition to the circuit configuration of FIG. 2, the signal modulation circuit of this embodiment further includes a phase inversion circuit 23, bias generation circuits 50 and 51, a zero reset type DFF 25, and a pulse synthesis circuit 34.

  The phase inversion circuit 23 inverts the phase of the output of the integrator 22 and outputs the inverted phase to the switching unit 30 and the bias generation circuit 51.

  The bias generation circuits 50 and 51 apply predetermined biases to the output of the integrator 22 and the output of the phase inversion circuit 23, respectively, and output them to the zero reset type DFFs 24 and 25. The bias generation circuits 50 and 51 increase and adjust the outputs of the integrators 22 and 23. This is achieved by adjusting the level of the no-signal state to the zero level, so that the zero-level (zero voltage) is ensured in the no-signal state. This is to realize a state where no switching is performed.

  The switching unit 30 compares the output from the integrator 22 and the output from the phase inverting circuit 23 with a predetermined value, and outputs a switching signal to the zero reset signal generating unit 32 when the predetermined value is exceeded.

  The zero reset signal generation unit 32 outputs a clock signal to the reset terminals of the zero reset type DFFs 24 and 25 when the switching signal from the switching unit 30 is at a low level, and cuts off the clock signal when the switching signal is at a high level. The zero reset type DFFs 24 and 25 do not output the reset terminal.

  The zero reset type DFF 24 converts the output of the bias generation circuit 50 into a 1-bit digital signal and outputs it. At this time, if the output of the bias generation circuit 50 is equal to or less than a predetermined value, a zero level is inserted at a timing synchronized with the clock signal and output as a signal having a fixed pulse width, and the output of the bias generation circuit 50 exceeds the predetermined value Is output as a signal with an expanded pulse width without inserting a zero level.

  Similarly, the zero reset type DFF 25 converts the output of the bias generation circuit 51 into a 1-bit digital signal and outputs it. At this time, if the output of the bias generation circuit 51 is equal to or less than a predetermined value, a zero level is inserted at a timing synchronized with the clock signal and output as a signal having a fixed pulse width, and the output of the bias generation circuit 51 exceeds the predetermined value Is output as a signal with an expanded pulse width without inserting a zero level.

  The pulse synthesis circuit 34 synthesizes and outputs the outputs of the zero reset type DFFs 24 and 25. The output of the zero reset type DFF 24 is a binary signal of +1, 0. On the other hand, the output of the zero reset type DFF 25 modulates the signal whose phase is inverted by the phase inversion circuit 23. It is a value signal. The pulse synthesis circuit 34 synthesizes these two binary signals to generate +1, 0, −1 ternary signals and outputs them. As the pulse synthesis circuit 34, any circuit capable of synthesizing two 1-bit digital signals can be used. As an example, a first potential and a second potential, and a third potential that is a midpoint between the first potential and the second potential and serves as a reference potential, the output is the first potential, A switch group for fixing the second potential and the third potential is provided, and these switch groups are controlled to be turned on and off by the output signals of the zero reset type DFFs 24 and 25, and the first potential, the second potential, and the third potential are controlled. A circuit configuration that selectively outputs one of them may be used.

  FIG. 5 shows the relationship between the input signal waveform and the output waveform of the pulse synthesis circuit 34. The output waveform of the pulse synthesizing circuit 34 is a ternary waveform of +1, 0, −1. When the amplitude of the input signal is small, it is a PDM signal with a fixed pulse width, and the amplitude of the input signal exceeds a predetermined value. And a combined signal of a PDM with an expanded pulse width and a PDM with a fixed pulse width. When the amplitude of the input signal is particularly large, all the pulse widths are expanded.

  In the circuit configuration of FIG. 4, the outputs of the integrators 22 and 23 are supplied to the switching unit 30 to generate a switching signal. Instead, the outputs of the bias generation circuits 50 and 51 are supplied to the switching unit 30. Then, the switching signal may be generated. FIG. 6 shows a circuit configuration in this case.

  Further, in the circuit configuration of FIG. 4, the outputs of the zero reset type DFFs 24 and 25 are synthesized by the pulse synthesis circuit 34 to generate +1, 0 and −1 ternary signals. In order to obtain an output, it is necessary to drive the speaker with a voltage VB higher than the modulator power supply Vdd. However, if the speaker is driven with the ternary signal, it is necessary to provide not only the high voltage VB but also a midpoint voltage source (VB / 2) and a midpoint voltage holding circuit separately, which increases the circuit scale.

  Therefore, as shown in FIG. 7, the single-value ternary waveform generation circuit 36 generates a single power source three-state speaker drive signal and outputs it to the driver circuit 38, and the driver circuit 38 drives the speaker as the load 44. Good.

  The monovalent ternary waveform generation circuit 36 converts the +1,0 binary signal from the zero reset type DFF 24 and the -1,0 binary signal from the zero reset type DFF 25 into a monovalent ternary waveform signal. Here, “single-value ternary” refers to a state in which a speaker driven by a single power source is driven by a positive current (positive on), a state driven by a negative current (negative on), and an off state by a short circuit. It means to realize two driving states. A positive current and a negative current mean that directions of currents flowing through the speaker are opposite to each other.

  FIG. 9 shows circuit configurations of the monovalent ternary waveform generation circuit 40 and the driver circuit 42. The monovalent ternary waveform generation circuit 40 includes NOR gates 33a and 33b and four NOT gates 40a to 40d. These NOT gates 40a to 40d are referred to as G11, G12, G13, and G14 in order from the top in the figure, that is, the NOT gate 40a is referred to as G11, the NOT gate 40b is referred to as G12, the NOT gate 40c is referred to as G13, and the NOT gate 40d is referred to as G14. , G11 and G12 are supplied with the output signal of the NOR gate 33a, and G13 and G14 are supplied with the output signal of the NOR gate 33b. G11 to G14 invert respective input signals and supply output signals to the driver circuit 42, respectively.

  The NOR gate 33a performs a logical operation on the signal from the inverting output terminal (Q bar) of the zero reset type DFF 32 and the signal from the output terminal (Q) of the zero reset type DFF 33, and the NOR gate 33b outputs the output of the zero reset type DFF 32. The signal from the terminal (Q) and the signal from the inverting output terminal (Q bar) of the zero reset type DFF 33 are logically operated and output.

  The driver circuit 42 includes level shift circuits 42a1 and 42a2, gate drive circuits 42b1 to 42b4, and switching FETs 42c1 to 42c4. The switching FETs 42c1 and 42c3 are P-channel FETs, and the switching FETs 42c2 and 42c4 are N-channel FETs.

  The speaker as the load 44 has one end connected to the connection node of the switching FET 42c1 and the switching FET 42c2 connected in series with each other, and the other end connected to the connection node of the switching FET 42c3 and the switching FET 42c4 connected in series. The switching FET 42c1 and the switching FET 42c3 are connected to the positive side of the single power source, and the switching FET 42c2 and the switching FET 42c4 are connected to the negative side of the single power source. Therefore, when the switching FET 42c1 is turned on, the switching FET 42c2 is turned off, and the switching FET 42c3 is turned off and the switching FET 42c4 is turned on, a current flows in the switching FET 42c1 → speaker 44 → switching 42c4, and the positive current is turned on. Further, when the switching FET 42c1 is turned off and the switching FET 42c2 is turned on, and when the switching FET 42c3 is turned on and the switching FET 42c4 is turned off, a current flows through the switching FET 42c3 → speaker → switching FET 42c2, and the negative current is turned on. Further, when the switching FETs 42c1 and 42c3 are turned off and the switching FETs 42c2 and 42c4 are turned on, no current flows through the speaker 44, and the speaker 44 is turned off (off state due to a short circuit).

  The output signals of the four logic gates G11 to G14 of the monovalent ternary waveform generation circuit 40 are supplied to the respective gate drive circuits 42b1 to 42b4 for driving the four switching FETs 42c1 to 42c4. That is, the output signal of G11 is supplied to the gate drive circuit 42b1 via the level shift circuit 42a1, and drives the switching FET 42c1. The output signal of G12 is supplied to the gate drive circuit 42b2, and drives the switching FET 42c2. The output signal of G14 is supplied to the gate drive circuit 42b3 via the level shift circuit 42a2, and drives the switching FET 42c3. The output signal of G13 is supplied to the gate drive circuit 42b4 and drives the switching FET 42c4.

When the outputs of the NOR gates 33b and 33a are “1” and “0”, respectively, the outputs of G11 and G12 are “0” obtained by inverting “1”, and the outputs of G13 and G14 are “0” obtained by inverting “0”. 1 ". Then, the switching FET 42c1 is turned on, the switching FET 42c2 is turned off, the switching FET 42c3 is turned off, and the switching FET 42c4 is turned on.
Switching FET 42c1 → speaker 44 → switching FET 42c4
(+ ON state).
When the outputs of the NOR gates 33b and 33a are “0” and “1”, respectively, the outputs of G11 and G12 are “1” obtained by inverting “0”, and the outputs of G13 and G14 are “1” obtained by inverting “1”. 0 ". Then, the switching FET 42c1 is turned off, the switching FET 42c2 is turned on, the switching FET 42c3 is turned on, the switching FET 42c4 is turned off, and the current is switched from the switching FET 42c3 to the speaker 44 to the switching FET 42c2.
(-ON state).

  When the outputs of the NOR gates 33b and 33a are “1”, the outputs of G11 to G14 are “0” obtained by inverting “1”. Then, the switching FET 42c1 is turned on, the switching FET 42c2 is turned off, the switching FET 42c3 is turned on, and the switching FET 42c4 is turned off, so that no current flows through the speaker 44 (off state due to a short circuit).

  Further, when the outputs of the NOR gates 33b and 33a are “0”, the outputs of G11 to G14 are “1” obtained by inverting “0”. Then, the switching FET 42c1 is turned off, the switching FET 42c2 is turned on, the switching FET 42c3 is turned off, and the switching FET 42c4 is turned on, so that no current flows through the speaker 44 (off state due to short circuit).

  As described above, the load 44 can be driven without increasing the circuit scale by generating the signal for driving the single power source tri-state speaker from the ternary pulse density modulation signal by the monovalent ternary waveform generating circuit 40. can do.

  In the circuit configuration of FIG. 7, the signal supplied from the driver circuit 42 to the load 44 is synthesized by the pulse synthesis circuit 34 and fed back to the subtracter 20, but as with the circuit configuration of FIG. 25 signals are synthesized by the pulse synthesizing circuit 34 and fed back to the subtracter 20, and separately from this feedback circuit, the signals of the zero reset type DFFs 24 and 25 are driven by the monovalent ternary waveform generating circuit 40 and the driver circuit 42. A signal may be generated to drive the load 44. FIG. 8 shows a circuit configuration in this case.

  As described above, according to the present embodiment, the output state can be corrected in real time, and the influence of distortion and noise components caused by the delay device can be reduced, and a zero level is inserted at a predetermined timing to obtain a pulse width. However, if the amplitude of the input signal is large and the integration output level of the integrator 22 is large, the input signal can be modulated and output with high voltage utilization efficiency by extending the pulse width. .

  In the present embodiment, as shown in the circuit configuration of FIGS. 2 and 4, the output of the integrator 22, which is the output in the feedback circuit, is compared with a predetermined value and switched by the switching unit 30 to expand the pulse width. Since it is determined whether to perform pulse width expansion or not, it is determined that noise during switching, that is, pulse width expansion from a PDM with a fixed pulse width is compared to when switching according to the amplitude of the input / output signal outside the feedback circuit. Noise generated at the timing of switching to the PDM and the timing of switching from the PDM with pulse width expansion to the PDM with a fixed pulse width can be effectively suppressed.

  Furthermore, in this embodiment, the zero level is inserted by supplying a clock signal to the reset terminals of the zero reset type DFFs 24 and 25, and the insertion of the zero level is prohibited by prohibiting the supply of the clock signal to the reset terminal. However, instead of prohibiting the supply of the clock signal, the insertion of the zero level may be prohibited by temporarily increasing the period of the clock signal and supplying it to the reset terminal. This is substantially equivalent to prohibiting the supply of a clock signal having an original period.

20 subtractor, 22 integrator, 24, 25 zero reset type DFF, 26 clock signal source, 28 delay circuit, 30 switcher, 32 zero reset signal generation unit, 34 pulse synthesis circuit, 50, 51 bias generation circuit.

Claims (4)

A signal modulation circuit that outputs a delta-sigma modulation of an input signal in synchronization with a clock signal,
A subtractor that calculates the difference between the input signal and the feedback signal;
An integrator for integrating the output from the subtractor;
A quantizer that delays and quantizes the signal integrated by the integrator while inserting a zero level at a timing synchronized with the clock signal;
A feedback circuit that feeds back the signal quantized by the quantizer to the input signal;
The level of the signal integrated by the integrator is compared with a predetermined value, and if it is within the predetermined value, the pulse width is fixed by allowing the insertion of the zero level in the quantizer and exceeds the predetermined value A controller that changes the pulse width by prohibiting the insertion of the zero level in the quantizer,
A signal modulation circuit comprising: The signal modulation circuit according to claim 1,
The quantizer is a flip-flop having a reset terminal,
By supplying the clock signal to the reset terminal, a zero level is inserted at a timing synchronized with the clock signal,
The control unit supplies the clock signal to the reset terminal when the level of the signal integrated by the integrator is within the predetermined value, and supplies the clock signal to the reset terminal when the level exceeds the predetermined value. A signal modulation circuit characterized by not. A signal modulation circuit that outputs a delta-sigma modulation of an input signal in synchronization with a clock signal,
A subtractor that calculates the difference between the input signal and the feedback signal;
An integrator for integrating the output from the subtractor;
A phase inversion circuit for inverting the phase of the signal integrated by the integrator;
A first quantizer for delaying and quantizing the signal integrated by the integrator while inserting a zero level at a timing synchronized with the clock signal;
A second quantizer that delays and quantizes the signal whose phase is inverted by the phase inverting circuit while inserting a zero level at a timing synchronized with the clock signal;
A pulse synthesis circuit for synthesizing the signal quantized by the first quantizer and the signal quantized by the second quantizer;
A feedback circuit that feeds back a signal synthesized by the pulse synthesis circuit to an input signal;
The level of the signal integrated by the integrator and the level of the phase-inverted signal are compared with a predetermined value, and if the level is within a predetermined value, the zero level in the first quantizer and the second quantizer Control to change the pulse width by prohibiting the insertion of the zero level in the first quantizer and the second quantizer when the pulse width exceeds the predetermined value by allowing the insertion of And
A signal modulation circuit comprising: The signal modulation circuit according to claim 3.
The first quantizer and the second quantizer are flip-flops having a reset terminal,
By supplying the clock signal to the reset terminal, a zero level is inserted at a timing synchronized with the clock signal,
The control unit supplies the clock signal to the reset terminal when the level of the signal integrated by the integrator and the level of the phase-inverted signal are within the predetermined value, and when the level exceeds the predetermined value, A signal modulation circuit, wherein a clock signal is not supplied to the reset terminal.