JP2011097322A - CONTINUOUS-TIME TYPE MULTI-BIT DeltaSigmaADC CIRCUIT - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve an S/N characteristic by preventing the occurrence of a glitch. <P>SOLUTION: The continuous-time type multi-bit ΔΣADC circuit includes: an adder 1; an integrator 2 for integrating signals outputted from the adder 1; a quantizer 3 for quantizing the output of the integrator 2 to a 3-bit output digital signal; a delay circuit 4 for delaying the 3-bit output digital signal outputted from the quantizer 3 by one sampling clock; a PWM circuit 5 for subjecting the 3-bit delayed digital signal outputted from the delay circuit 4 to parallel/serial conversion and PWM modulation to generate two feedback PWM signals; and resistors R2, R3 for converting the two feedback PWM signals outputted from the PWM circuit 5 to feedback analog signals by performing resistance addition to be input to the adder 1. A glitch canceling circuit 6 is inserted between the resistors R2, R3 and the adder 1, and a re-timing process is executed to the feedback analog signals outputted from the resistors R2, R3. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a continuous-time multi-bit ΔΣ ADC circuit in which glitches are canceled to improve S / N characteristics.

  FIG. 8 shows a conventional continuous-time multi-bit ΔΣ ADC circuit (reference example: Patent Document 1). The input analog signal Vin is input to the adder 1 via the resistor R1, and the adder 1 is compared with the feedback analog signal Vfb obtained by analog conversion of the signal one sampling clock before the output digital signal Dout, and the difference ( Vin−Vfb) is input to the integrator 2 and integrated over time. Then, the output voltage of the integrator 2 is quantized by the multi-bit quantizer 3 into 3-bit data (any one of four patterns “LLL”, “LLH”, “LHH”, “HHH” data). And output as an output digital signal Dout. The 3-bit output digital signal Dout is delayed by one sampling time by the sampling clock SCK in the delay circuit 4 and input to the PWM circuit 5 as 3-bit delayed digital signals Di1, Di2, Di3. In the PWM circuit 5, parallel / serial conversion and PWM modulation are performed by the clocks CK and CP to form two feedback PWM signals Do 1 and Do 2, which are added by a resistance adding circuit including resistors R 2 and R 3. The analog signal Vfb is input to the adder 1.

  FIG. 9 is a waveform diagram of signals on the feedback path of the continuous-time multi-bit ΔΣ ADC circuit of FIG. The delayed digital signals Di1, Di2 and Di3 output from the delay circuit 4 correspond to a clock CK having a frequency four times that of the sampling clock SCK after the clock PS in the PWM circuit 5 during one period of the sampling clock SCK. Thus, the feedback PWM signal Do1 in the order of Di3 → Di2 → Di1 is divided into the feedback PWM signal Do2 in the order of Di1 → Di2 → Di3. Then, the addition of (Di3 + Di1) → (Di2 + Di2) → (Di1 + Di3) is sequentially performed by the resistors R2 and R3, so that the feedback analog signal Vfb is obtained.

  In this continuous time type, resistance addition is used in the feedback path. Therefore, compared to the case of using the discrete type, the advantage that the characteristic deterioration due to the leakage current is small and the complexity required for controlling the switched capacitor are required. There is an advantage that a clock is unnecessary. Further, the increase in the number of bits also has an advantage that the system can be easily stabilized as compared with the case of 1 bit.

Japanese Patent No. 3336576

  However, in the above-described continuous-time multi-bit ΔΣ ADC circuit, when the feedback PWM signals Do1 and Do2 from the PWM circuit 5 are added, the feedback PWM signal Do1 and the feedback PWM signal Do2 in the PWM circuit 5 are mutually connected. 9 causes two types of glitches as shown in FIG. 9 due to the difference in on-resistance between the NMOS transistor and the PMOS transistor and the difference between the rise time and fall time of the transistor, thereby degrading the S / N characteristics. there were.

  An object of the present invention is to provide a continuous-time multi-bit ΔΣ ADC circuit that includes a glitch cancel circuit to prevent the occurrence of glitches and improve the S / N characteristics.

  In order to achieve the above object, an invention according to claim 1 includes an adder for generating a difference between an input analog signal and a feedback analog signal obtained by converting a signal one sampling clock before the output digital signal into an analog signal; An integrator for time-integrating the difference signal obtained by the adder; a quantizer for quantizing the integrated signal output from the integrator into an output digital signal of N (N: a positive integer of 2 or more); A delay circuit that delays the N-bit output digital signal obtained by the quantizer by one sampling clock, and the N-bit delayed digital signal output from the delay circuit is subjected to parallel / serial conversion and PWM modulation to obtain M (M .Ltoreq.N) PWM circuit that generates feedback PWM signals and a resistance adder that converts M feedback PWM signals output from the PWM circuit into the feedback analog signal. In a continuous-time multi-bit ΔΣ ADC circuit comprising: a glitch cancel circuit inserted between the resistor adder and the adder, and the feedback analog signal output from the resistor adder by the glitch cancel circuit A retiming process is performed on this.

  According to a second aspect of the present invention, there is provided an adder for generating a difference between an input analog signal and a feedback analog signal obtained by converting a signal one sampling clock before the output digital signal into an analog signal, and a difference signal obtained by the adder Obtained by the quantizer, a quantizer that quantizes the integral signal output from the integrator into an output digital signal of N (N: a positive integer greater than or equal to 2) bits, and the quantizer A delay circuit that delays an N-bit output digital signal by one sampling clock, and M (M ≦ N) feedback PWM signals by parallel / serial conversion and PWM modulation of the N-bit delayed digital signal output from the delay circuit. A continuous-time multi-channel circuit, and a resistance adding means for converting M feedback PWM signals output from the PWM circuit into the feedback analog signal. In the ΔΔ ADC circuit, a glitch cancel circuit is inserted between the PWM circuit and the resistance adding means, and the G feedback cancel signal output from the PWM circuit is identical to each of the M feedback PWM signals. A retiming process is performed.

  According to a third aspect of the present invention, in the continuous-time multi-bit ΔΣ ADC circuit according to the first aspect, the glitch cancel circuit inputs a clock having the same phase or a reverse phase as a clock for parallel / serial conversion in the PWM circuit. And a switch circuit for generating a delay clock delayed by a predetermined time and a switch means for performing a retiming process on the feedback analog signal by the delay clock output from the control circuit.

  According to a fourth aspect of the present invention, in the continuous-time multi-bit ΔΣ ADC circuit according to the second aspect, the glitch cancel circuit inputs a clock having the same phase or a reverse phase as a clock for parallel / serial conversion in the PWM circuit. And a control circuit that generates a delay clock delayed by a predetermined time, and M switch means for performing retiming processing on the M feedback PWM signals by the delay clock output from the control circuit. Features.

  According to a fifth aspect of the present invention, in the continuous-time multi-bit ΔΣ ADC circuit according to the first, second, third, or fourth aspect, a point in time when the retiming process is performed by the glitch cancel circuit is parallel / serial in the PWM circuit. It is characterized in that it is a point in time that deviates from the effective edge of the clock for conversion.

  According to the present invention, the retiming process is performed on the feedback analog signal output from the resistance adding means or on the M feedback PWM signals output from the PWM circuit. Generation of glitches can be prevented, and the S / N characteristics can be improved.

1 is a functional block diagram of a continuous-time multibit ΔΣ ADC circuit according to a first embodiment of the present invention. FIG. 3 is a detailed functional block diagram of a PWM circuit of a continuous-time multi-bit ΔΣ ADC circuit according to the first embodiment. FIG. 3 is an operation waveform diagram of the PWM circuit of FIG. 2. FIG. 3 is an operation waveform diagram of the continuous-time multi-bit ΔΣ ADC circuit according to the first embodiment. FIG. 3 is a circuit diagram of a control circuit of the continuous-time multi-bit ΔΣ ADC circuit according to the first embodiment. FIG. 6 is a functional block diagram of a continuous-time multibit ΔΣ ADC circuit according to a second embodiment of the present invention. It is an operation waveform diagram of the continuous time type multi-bit ΔΣ ADC circuit of the second embodiment. It is a functional block diagram of a conventional continuous time type multi-bit ΔΣ ADC circuit. It is an operation waveform diagram of a conventional continuous time type multi-bit ΔΣ ADC circuit.

<First embodiment>
FIG. 1 shows a continuous-time multibit ΔΣ ADC circuit according to a first embodiment of the present invention. 1 is an adder that adds (subtracts) the input analog signal Vin and the feedback analog signal Vfb, 2 is an integrator that integrates the output voltage of the adder 2 over time, and 3 is an output voltage of the integrator that is 3-bit data (4 types). A multi-bit quantizer that quantizes the data to any one of the patterns “LLL”, “LLH”, “LHH”, and “HHH”), 4 is one sampling of the 3-bit output digital signal Dout of the quantizer 3 A delay circuit 5 for delaying time receives PWM digital signals Di1, Di2 and Di3 output from the delay circuit 4 and performs parallel / serial conversion and PWM modulation to generate two feedback PWM signals Do1 and Do2. The circuit 6 performs a retiming of the feedback analog signal Vfb ′ generated from the feedback PWM signals Do1 and Do2 to generate a feedback analog signal Vfb. This is a di-cancellation circuit. R1, R2, and R3 are resistors, and among them, R2 and R3 constitute a resistance adding circuit that adds the feedback PWM signals Do1 and Do2 to generate a feedback analog signal Vfb ′.

  As shown in FIG. 2, the PWM circuit 5 includes four logic circuits 51 to 54 that receive clocks CK and PS, one of the delayed digital signals Di1, Di2, and Di3 and one of the voltages VDD and VSS. A circuit that performs serial conversion and PWM modulation to generate the feedback PWM signal Do1 is included. Further, feedback is performed by performing parallel / serial conversion and PWM modulation with four logic circuits 55 to 58 that receive clocks CK and PS, one of the delayed digital signals Di1, Di2 and Di3 and one of the voltages VDD and VSS. A circuit for generating the PWM signal Do2 is included.

  Each of the logic circuits 51 to 58 outputs data input to the terminal P to the terminal Q while the clock PS is “H”. Further, the data input to the terminal D during the period when the clock PS is “H” is output to the terminal Q at the rising edge of the clock CK after the clock PS becomes “L”, and the next rising edge of the clock CK. Hold to the edge.

  Therefore, as shown in FIG. 3A, the feedback PWM signal Do1 is output from the Q terminal of the logic circuit 54 in the order of VDD → Di3 → Di2 → Di1 → VSS. Further, as shown in FIG. 3B, the feedback PWM signal Do2 is output from the terminal Q of the logic circuit 58 in the order of VSS → Di1 → Di2 → Di3 → VDD.

  The two feedback PWM signals Do1 and Do2 output from the PWM circuit 5 are subjected to analog addition in the order of (Di3 + Di1) → (Di2 + Di2) → (Di1 + Di3) in a resistance adding circuit including resistors R2 and R3, and feedback analog signals. Vfb ′. For example, when Di1, Di2, Di3 = L, H, H, if H = VDD = 1V and L = VSS = 0V, the addition result is 0.5V → 1V → 0.5V. Since 0.5 V is applied before and after this, the data component of the feedback analog signal Vfb ′ is collected at the center.

  The glitch cancel circuit 6 includes a control circuit 61 and switch means SW1 controlled by the control circuit 61. For example, as shown in FIG. 5, the control circuit 61 includes an inverter INV1 in which the operating current is set by the current sources I1 and I2, a capacitor C1 that time-integrates the output voltage of the inverter INV1, and an integrated voltage of the capacitor C1. The inverter INV2 to be inverted is generated, and a delayed clock SK is generated by delaying the input master clock MCK by a predetermined time. The master clock MCK is a clock having a polarity opposite to that of the clock CK. As shown in FIG. 4, the rising timing of the delay clock SK is slightly delayed from the rising timing of the clock CK (a time shorter than a half cycle of the clock CK).

  The switch means SW1 holds and outputs the value of the feedback analog signal Vfb ′ at the time when the delay clock SK output from the control circuit 61 rises to “H” for one cycle of the delay clock SK. This is repeated every time SK rises to “H”. As a result, as shown in FIG. 4, the feedback analog signal Vfb ′ is retimed at a timing deviating from the rising edge of the clock CK to generate the feedback analog signal Vfb, which is input to the adder 1. .

  From the above, the feedback analog signal Vfb rises from a point after the feedback analog signal Vfb ′ completely rises and stabilizes. Therefore, the on-resistance of the NMOS transistor and the PMOS transistor in the PWM circuit 5, the rise time of the transistor, and the fall The glitch can be canceled completely without being affected by the time lag.

<Second embodiment>
FIG. 6 shows a continuous-time multi-bit ΔΣ ADC circuit according to the second embodiment of the present invention. In the present embodiment, the switching means SW2 and SW3 are inserted between the output side of the PWM circuit 5 and the resistors R2 and R3, and the glitch for controlling the switching means SW2 and SW3 with the delay clock SK output from the control circuit 61. The difference from the first embodiment is that a cancel circuit 6A is provided.

  As shown in FIG. 7, the switch means SW2 and SW3 set the values (binary values) of the feedback PWM signals Do1 and Do2 when the delay clock SK of the control circuit 61 rises to “H” for one cycle of the delay clock SK. This level is held and output as feedback PWM signals Do1 ′ and Do2 ′, and this is repeated each time the delay clock SK rises to “H”. As a result, the feedback PWM signals Do1, Do2 are retimed at a timing deviating from the rising edge of the clock CK to generate feedback PWM signals Do1 ', Do2'. The feedback analog signal Vfb is generated by adding the feedback PWM signals Do1 'and Do2' by a resistance adding circuit of resistors R2 and R3.

  Since the feedback PWM signals Do1 and Do2 are binary digital signals, a DFF circuit that latches the feedback PWM signals Do1 and Do2 every time the delay clock SK rises can be used as the switch means SW2 and SW3. .

  In the first embodiment shown in FIG. 1, the feedback analog signal Vfb ′ has the glitch described in FIG. 9 near the rising edge of the clock CK due to the addition by the resistors R2 and R3. By avoiding this glitch occurrence timing by retiming processing for the analog signal Vfb ′, no glitch is generated in the feedback analog signal Vfb input to the adder 1.

On the other hand, in the second embodiment, the feedback PWM signals Do1 and Do2 output individually from the PWM circuit 5 before the resistance addition by the resistors R2 and R3 are individually performed for the feedback PWM signals Do1 and Do2. When the logic is stable, the same retiming processing is performed by the switch means SW2 and SW3 to generate feedback PWM signals Do1 ′ and Do2 ′, and then the feedback analog signals Vfb are generated by adding them by the resistors R2 and R3. As a result, no glitch is originally generated. As described above, in the second embodiment, since the feedback PWM signals Do1 and Do2 are added after being stabilized, no glitch is theoretically generated in the feedback path.
<Other examples>

  In the first and second embodiments described above, a 3-bit output digital signal is output from the multi-bit quantizer 3, but this is N (N: a positive integer of 2 or more) bits or more. If it is. The PWM circuit 5 outputs two feedback PWM signals that have been subjected to parallel / serial conversion and PWM modulation. However, M (M ≦ N) feedback PWM signals may be output.

  Further, the delay clock SK for controlling the switch means SW1, SW2 and SW3 is not limited to the delayed clock CK, and a clock having the same phase or opposite phase as the parallel / serial conversion clock of the PWM circuit 5 is input. Thus, the delay clock may be a delay clock that is delayed by a predetermined time so that the valid edge comes off the rising edge of the clock CK.

  1: adder, 2: integrator, 3: multi-bit quantizer, 4: delay circuit, 5: PWM circuit, 6, 6A: glitch cancel circuit

Claims (5)

An adder that generates a difference between an input analog signal and a feedback analog signal obtained by converting a signal one sampling clock before the output digital signal into an analog signal, an integrator that time-integrates the difference signal obtained by the adder, A quantizer that quantizes the integral signal output from the integrator into an N (N: positive integer greater than or equal to 2) -bit output digital signal, and an N-bit output digital signal obtained by the quantizer is 1 A delay circuit that delays by a sampling clock; a PWM circuit that generates M (M ≦ N) feedback PWM signals by performing parallel / serial conversion and PWM modulation on an N-bit delayed digital signal output from the delay circuit; A continuous-time multi-bit ΔΣ ADC circuit comprising: resistance addition means for converting M feedback PWM signals output from the PWM circuit into the feedback analog signal And
A continuous glitch cancel circuit is inserted between the resistor adder and the adder, and the feedback analog signal output from the resistor adder is retimed by the glitch cancel circuit. Time-type multi-bit ΔΣ ADC circuit. An adder that generates a difference between an input analog signal and a feedback analog signal obtained by converting a signal one sampling clock before the output digital signal into an analog signal, an integrator that time-integrates the difference signal obtained by the adder, A quantizer that quantizes the integral signal output from the integrator into an N (N: positive integer greater than or equal to 2) -bit output digital signal, and an N-bit output digital signal obtained by the quantizer is 1 A delay circuit that delays by a sampling clock; a PWM circuit that generates M (M ≦ N) feedback PWM signals by performing parallel / serial conversion and PWM modulation on an N-bit delayed digital signal output from the delay circuit; A continuous-time multi-bit ΔΣ ADC circuit comprising: resistance addition means for converting M feedback PWM signals output from the PWM circuit into the feedback analog signal And
A glitch cancel circuit is inserted between the PWM circuit and the resistance adding means, and the same retiming processing is performed on the M feedback PWM signals output from the PWM circuit by the glitch cancel circuit. A continuous-time multi-bit ΔΣ ADC circuit characterized by The continuous time multi-bit ΔΣ ADC circuit according to claim 1,
The glitch cancel circuit includes a control circuit that generates a delay clock that is delayed by a predetermined time by inputting a clock that is in phase or opposite phase to the parallel / serial conversion clock in the PWM circuit, and a delay clock that is output from the control circuit And a switch means for performing retiming processing on the feedback analog signal. The continuous time multi-bit ΔΣ ADC circuit according to claim 2,
The glitch cancel circuit includes a control circuit that generates a delay clock that is delayed by a predetermined time by inputting a clock that is in phase or opposite phase to the parallel / serial conversion clock in the PWM circuit, and a delay clock that is output from the control circuit A continuous-time multi-bit ΔΣ ADC circuit comprising M switch means for performing retiming processing on each of the M feedback PWM signals. The continuous time multi-bit ΔΣ ADC circuit according to claim 1, 2, 3 or 4,
The continuous-time multi-bit ΔΣ ADC circuit characterized in that the retiming processing by the glitch cancel circuit is performed at a time deviating from the effective edge of the parallel / serial conversion clock in the PWM circuit.

Images