JP5788292B2 - Delta-sigma modulator and semiconductor device - Google Patents

Description

  The present invention relates to a delta-sigma (ΔΣ) modulator and a semiconductor device.

  One type of AD (Analog to Digital) converter is a delta-sigma modulator. The delta-sigma modulator has high AD conversion accuracy (S / N ratio). In addition, since most of the delta-sigma modulator can be realized by a complementary metal oxide semiconductor (CMOS) circuit, it has an advantage that it can be easily incorporated into a semiconductor device such as a microcomputer.

FIG. 1 is a block diagram illustrating a configuration example of a general delta-sigma modulator 100. The delta sigma modulator 100 is a multi-bit delta sigma modulator, and converts the analog signal A into a digital signal D having n (≧ 2) bits. Here, an n = 2-bit delta-sigma modulator 100 is taken as an example. In this case, the delta-sigma modulator 100 includes a subtractor 110, an integrator 120, an n = 2-bit quantizer 130, k = 3 DA (Digital to Analog) converters 140, a decoder 150, Is provided. Hereinafter, the kth DA converter 140 is referred to as a “kth DA converter 140 _k ”.

The subtractor 110 outputs a difference S between the analog signal A and a total DAC current I _DAC described later to the integrator 12. The integrator 120 integrates the difference S over time. The quantizer 130 quantizes the output of the integrator 120 to n = 2 bits. After that, the quantizer 130 outputs a 3-bit thermometer code C corresponding to the quantization level (quantization value). Therefore, the number of DA converters 140 is k = 3. The decoder 150 converts the k = 3-bit thermometer code C into an n = 2-bit binary code. This is a digital signal D of n = 2 bits from which this binary code is finally obtained.

In order to increase the accuracy of AD conversion, it is desirable to increase the slew rate of the integrator 120 as much as possible. In order to increase the slew rate, it is necessary to supply as much steady current as possible to the integrator 120 while ensuring the settling time of the integrator 120. Therefore, the integrator 120 is designed so that a steady current larger than the peak value of the sum of the outputs of the first to third DA converters 140 _{1 to} 140 ₃ is supplied.

Hereinafter, this point will be described. First, attention is focused on the first to third DA converters 140 _{1 to} 140 ₃ . The first to _third DA converters 140 _{1 to} 140 ₃ are each a 1-bit DA converter and have the same structure. First to 3DA converter ₁₄₀ 1 -140 _3, with the inflow node ND _I and converging node ND _O, are connected in parallel, respectively. The 3DA converter ₁₄₀ 1 -140 ₃ from the first, from the first type the third bit _C 1 -C _3, converting the first and third bit _C 1 -C _3, each analog signal. Here, the first to third bits C _{1 to} C ₃ correspond to, for example, LSB (least significant bit) to MSB (most significant bit) of the thermometer code C, respectively. For example, when the thermometer code C = “111”, the first to third bits C ₁ -C ₃ are each “1”.

One type of DA converter is a DA converter called an SCR (Switched Capacitor Resistor) type. In the case of the SCR type, each output of the first to third DA converters 140 _{1 to} 140 ₃ is a current. Hereinafter, the SCR type is taken as an example. The output of the _k- th DA converter 140 _k is referred to as “ _k- th DAC current I _DACk ”.

Figure 2 is a diagram illustrating the time change of the kDAC current _{I DACK} at a sampling period _{T S.} Here, a case where the thermometer code C = "111" is simply taken as an example. In this case, the first to third _DAC currents I _DAC have substantially the same waveform.

In the case of the SCR type, the k-th DAC current I _DACk instantaneously reaches a peak at time T ₁ which is the output start time. The current I _P at this time is referred to as a "peak current". Thereafter, the k-th DAC current I _DACk decays nonlinearly. However, the k-th DAC current I _DACk becomes 0 at a stage earlier than the sampling time T _S. This is because the output of the _k- th DA converter 140 _k is stopped at that stage.

FIG. 3 is a diagram illustrating the time change of the total DAC current I _{DAC at} a certain sampling time T _S. “Total DAC current I _DAC ” is a sum of first to third DAC currents I _DAC1 -I _DAC3 . The first to third DA converters 140 _{1 to} 140 ₃ output the first to third DAC currents I _{DAC1 to} I _DAC3 at the same time at time T ₁ , respectively. Therefore, the total peak current _{I TP} reaches approximately three times the peak current _{I P} of the first kDAC current _{I DACK} take. The “total peak current I _TP ” refers to a current when the total DAC current I _DAC reaches a peak.

FIG. 4 is a diagram illustrating the time change of the k-th DAC current I _DACk by another type of DA converter. In addition to the SCR type, the type of DA converter includes a type called a constant current feedback type. In the case of the constant current feedback type, the DA converter includes a plurality of current sources and a plurality of switches. The DA converter outputs a constant current as shown in FIG. Even in the case of the constant current feedback type, the same can be said as in the case of the SCR type.

  Next, focus on the integrator 120. The integrator 120 includes an operational amplifier and a feedback capacitor. Basically, an operational amplifier includes a differential stage composed of a differential pair and the like, and an output stage that amplifies and outputs the output of the differential stage. The output stage is composed of a plurality of transistors. One end of the feedback capacitor is connected to the inverting input terminal of the operational amplifier. The other end of the feedback capacitor is connected to the output terminal of the operational amplifier.

In order to increase the operation speed of the operational amplifier, it is necessary that a current approximately equal to the total peak current I _TP constantly flows through the transistor at the output stage of the operational amplifier. Therefore, the integrator 120 is normally designed so that a steady current larger than the total peak current _ITP is supplied. This current flows from the output side of the first to third DA converters 140 ₁ -140 ₃ to the output stage of the operational amplifier via the feedback capacitor.

Therefore, the higher the total peak current I _TP , the higher the power consumption of the integrator 120. In particular, in the case of the SCR type, the time during which the total peak current _ITP exists is much shorter than that in the case of the current feedback type. Although temporarily, a current higher than the total peak current I _TP flows through the operational amplifier of the integrator 120. This leads to wasteful power consumption. Methods for solving this problem are disclosed in patent documents and non-patent documents, respectively.

US Patent Application No. 7768433B2

Aldo Pena Perez, Edoardo Bonizzoni, and FrancoMaloberti, “A 84dB SNDR 100kHz Bandwidth Low-PowerSingle Op-Amp Third-Order ΔΣ Modulator Consuming 140uW”, ISSCC, 2011

The technique of the patent document and the non-patent document is basically to temporarily supply the integrator 120 with a current larger than the total peak current _ITP when necessary. For this purpose, an analog control circuit for controlling the slew rate of the integrator 120 and an analog control circuit for controlling the variable current source are separately required. Therefore, the layout area of the delta-sigma modulator 100 is increased as compared with a digital circuit that can be configured by a CMOS circuit. This hinders downsizing of the delta-sigma modulator.

  Therefore, it is desired to reduce the power consumption and the size of the delta sigma modulator.

  Hereinafter, reference numerals used in [DETAILED DESCRIPTION] will be added in parentheses, and [Means for Solving the Problems] will be described. This reference numeral is added to clarify the correspondence between the description of [Claims] and the description of [Mode for Carrying Out the Invention]. This symbol should not be used for the interpretation of the technical scope of the invention described in [Claims].

A delta-sigma modulator (1) according to the present invention receives a first analog signal (A) and a second analog signal (I _DAC ), and subtracts the second analog signal from the first analog signal. 11), an integrator (12) for integrating the subtraction result (S) of the subtractor, and a plurality of DA converters (14 _{1 to} 14 _k ), each connected in parallel, each having an output from the integrator The digital signal (C) quantized based on the signal is converted into an analog signal (I _DAC1 −I _DACk ), and the converted analog signal is converted into the second analog signal (I _DAC = I _DAC1 + I _DAC2 +. The plurality of DA converters that output to the subtractor at different timings as + I _DACk ).

  Preferably, the delta-sigma modulator (1) of the present invention quantizes the output of the integrator into n (≧ 2) bits, and k (> n) bits of the thermometer code (C) corresponding to the quantization level. , A processing circuit (17) for processing the thermometer code as the digital signal, and k DA converters as the plurality of DA converters. The thermometer code is the thermometer code in which k bits are arranged from the first bit to the k-th bit. The processing circuit changes the order of the arrangement of the k bits constituting the thermometer code. The k DA converters convert the currents respectively corresponding to the k bits of the thermometer code whose order of the arrangement has been changed by the processing circuit.

Preferably, the delta-sigma modulator (1) of the present invention further includes a control unit (15) for controlling the timing of the output of each of the k DA converters. The k DA converters include a first DA converter (for example, 14 ₁ ) that outputs a first current (for example, I _DAC1 ) and a second DA converter (for example, I _DAC2 ) that outputs a second current (for example, I _DAC2 ). For example, 14 ₂ ). The control unit causes the first DA converter to output the first current, delays a predetermined time (for example, Td1) from the start of output of the first current by the first DA converter, and causes the second DA converter to output the first current. The second current is output.

Preferably, the control unit delays the output of the second current by the second DA converter for a predetermined time from the start of the output of the first current by the first DA converter (for example, 152 ₁ -152 ₃ ).

  The power consumption and size of the delta sigma modulator can be reduced.

FIG. 1 is a block diagram illustrating a configuration example of a general delta-sigma modulator 100. Figure 2 is a diagram illustrating the time change of the kDAC current _{I DACK} at a sampling period _{T S.} FIG. 3 is a diagram illustrating the time change of the total DAC current I _{DAC at} a certain sampling time T _S. FIG. 4 is a diagram illustrating the time change of the k-th DAC current I _DACk by another type of DA converter. FIG. 5 is a block diagram showing an outline of the delta-sigma modulator 1 according to the first embodiment. Figure 6 is a view from the first illustrates a first 3DAC current _I DAC1 _{-I DAC 3,} respectively. FIG. 7 is a diagram illustrating the total DAC current I _DAC . FIG. 8 is a circuit diagram showing a detailed configuration example of the delta-sigma modulator 1 according to the first embodiment. FIG. 9 is a partially enlarged view of the _first DA converter 141. FIG. 10 is a timing chart showing an operation example of the delta-sigma modulator 1. FIG. 11 is a diagram illustrating an example of an arrangement layout of the delta-sigma modulator 1. FIG. 12 is a block diagram illustrating a configuration example of the microcomputer 2 including the delta-sigma modulator 1. FIG. 13 is a circuit diagram illustrating a configuration example of the delta-sigma modulator 1A according to the second embodiment. FIG. 14 is a circuit diagram showing a configuration example of a delta-sigma modulator 1B according to the third embodiment. FIG. 15 is a circuit diagram showing a configuration example of a delta-sigma modulator 1C according to the fourth embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the embodiments, the same components are denoted by the same reference numerals in principle.

[First Embodiment]
1. Outline of Delta Sigma Modulator FIG. 5 is a block diagram showing an outline of the delta sigma modulator 1 according to the first embodiment. The delta-sigma modulator 1 includes a subtractor 11, an integrator 12, an n-bit quantizer 13, k (≧ 1) DA converters 14, a control unit 15, and a decoder 16. The kth DA converter 14 is referred to as a “kth DA converter 14 _k ”.

The delta sigma modulator 1 has a (negative) feedback loop in which the output of the quantizer 13 is fed back to the subtractor 11 via the first to kDA converters 14 _{1 to} 14 _k . The delta-sigma modulator 1 converts the analog signal A into an n-bit digital signal D using this feedback loop.

Here, the specification of the delta-sigma modulator 1 will be described.
1) The first to kth DA converters 14 ₁ -14 _k are each SCR type. This is an example of the DA converter 14. The k DA converters 14 may be a constant current feedback type or other types. Hereinafter, the output current of the _k- th DA converter 14 _k is referred to as “ _k- th DAC current I _DACk ”.

2) The number of DA converters 14 is determined by the resolution of the quantizer 13, that is, the number of bits n. When the resolution is n bits, the quantizer 13 outputs a 2 ⁿ −1 bit thermometer code C. Therefore, the number of DA converters 14 is k = 2 ⁿ −1 (> n).

  Hereinafter, each component of the delta-sigma modulator 1 will be described.

The subtractor 11 includes a first input terminal (+) and a second input terminal (−). The subtractor 11 inputs the analog signal A to the first input terminal. At the same time, the subtractor 11 inputs the total DAC current I _DAC to the second input terminal. The “total DAC current I _DAC ” is a sum of the first to k-th DAC currents I _DAC1 −I _DACk and is an analog signal. The subtractor 11 subtracts the total DAC current I _DAC from the analog signal A, and outputs a difference S (= A−I _DAC ) as a result of the subtraction to the integrator 12.

The integrator 12 integrates the difference S input from the subtractor 11 in units of sampling time T _S and outputs the integration value to the quantizer 13. Since the integrator 12 integrates the difference S, it has a noise shaping action of driving the quantization noise in the quantizer 13 to a high frequency band. Two or more integrators 12 can be provided. By increasing the order of integration, higher noise shaping characteristics can be obtained.

The quantizer 13 quantizes the integral value input from the integrator 12 into n bits. After that, the quantizer 13 creates a 2 ⁿ −1 bit thermometer code C corresponding to the quantization level. After the creation, the quantizer 13 outputs the thermometer code C to the decoder 16. At the same time, the quantizer 13 outputs the first to k-th bits C ₁ -C _k of the thermometer code C to the first to k-th DA converters 14 ₁ -14 _k , respectively.

Here, the first bit C ₁ indicates LSB which is the first bit of the thermometer code C. The second bit C _2, refers to the second bit of the thermometer code C. Hereinafter, in order, the k-th bit C _k indicates the MSB that is the k-th bit of the thermometer code C. Needless to say, the first to kth bits C ₁ -C _k are each a digital signal and take “0” or “1”. Note that the first to kth bits C ₁ -C _k may correspond to MSB to LSB in order, respectively.

The kDA converter ₁₄ 1 -14 _k from the first is connected in parallel with the inflow node ND _I and converging node ND _O. The first to _kth DA converters 14 _{1 to} 14 _k are 1-bit DA converters, respectively. The first to kth DA converters 14 _{1 to} 14 _k convert the first to kth DAC currents I _{DAC1 to} I _DACk corresponding to the first to kth bit thermometer codes C _{1 to} C _k , respectively. After DA conversion, the kDA converter ₁₄ 1 -14 _k from the first outputs from the first to the second input terminal of the subtracter 11 via the converging node ND _O the first kDAC current _I DAC1 _{-I DACk.} The kDAC current _I DAC1 _{-I DACK} from the first merges at the converging node ND _O, the total DAC current _{I DAC} corresponding to the thermometer code C.

Conventionally, a plurality of DA converters output DAC currents simultaneously (see FIG. 1). Here, “simultaneous” means substantially simultaneous. On the other hand, in the present embodiment, the first to kth DA converters 14 _{1 to} 14 _k output the first to kth DAC currents I _{DAC1 to} I _DACk at different timings.

The controller 15 controls the first to kDA converters 14 _{1 to} 14 _k so that the first to _k- th DAC currents I _{DAC1 to} I _DACk are output at different timings.

The decoder 16 converts the 2 ⁿ −1 bit thermometer code C into an n bit binary code.

As described above, the first to _k- th DA converters 14 _{1 to} 14 _k output the first to _k- th DAC currents I _{DAC1 to} I _DACk at different timings, respectively. Hereinafter, this point will be described. Here, in order to simplify the description, an example is given in which the resolution of the quantizer 13 is n = 2 bits and the number of DA converters 14 is k = 3.

Figure 6 is a view from the first illustrates a first 3DAC current _I DAC1 _{-I DAC 3,} respectively. FIG. 6 illustrates a case where the thermometer code C = “111”. The first to third DA converters 14 _{1 to} 14 ₃ sequentially output the first to third DAC currents I _{DAC1 to} I _DAC3 while shifting the delay times Td respectively. The delay time Td is determined in advance at the design stage.

Specifically, at time _{T 1,} the control unit 15 to start the output of the 1DAC current _{I DAC1} to the 1DA converter 14 _1. At time _{T 1} time delay time Td has elapsed from _{T 2,} the control unit 15 to start the output of the 2DAC current _{I DAC2} to the 2DA converter 14 _2. Finally, at the time _{T 3} has elapsed delay time Td from the time _{T 2,} the control unit 15 to start the output of the 3DAC current _{I DAC 3} to the 3DA transducer 14 _3. Accordingly, the output of the 3DAC current _{I DAC 3} is delayed by Td × 2 from the output of the 1DAC current _{I DAC1.} The delay time Td may be different from the first for each output of the 3DAC current _I DAC1 _{-I DAC 3.}

For the thermometer code C = "111", each peak current _{I P} of the first to 3DAC current _I DAC1 _{-I DAC 3} are substantially identical. Note that the 3DAC current _I DAC1 _{-I DAC 3} from the first _is represented by the I DAC αexp (-T / τ) . “T” is a variable representing time. “Τ (tau)” is a time constant and is expressed by τ = R × C. “R” represents the resistance value of the resistor constituting the kDA converter 14 _k (for example, the resistance value of the first resistor Ra, see FIG. 9). “C” represents the capacitance of the capacitor constituting the kDA converter 14 _k (for example, the capacitance of the first capacitor Ca, see FIG. 9). Time to take the peak current I _P, when determined by the constant tau.

FIG. 7 is a diagram illustrating the total DAC current I _DAC . Only the _first DA converter 14 ₁ outputs a DAC current during the period from time T ₁ to T ₂ . Therefore, the total DAC current I _DAC is I _DAC = I _DAC1 . Total DAC current _{I DAC} is also instantaneously peaks at time _{T 1.} The total peak current I _{TP at} this time is I _TP = I _TP1 .

Next, in the period from time T ₂ to T ₃ , the first and second DA converters 14 ₁ and 14 ₂ output DAC currents, respectively. Therefore, the total DAC current I _DAC is I _DAC = I _DAC1 + I _DAC2 . Total DAC current _{I DAC} is instantaneously peaks at time _{T 2.} At this time, the total peak current I _TP = I _TP2 is larger than I _TP1 . However, the total peak current I _TP2 is smaller than I _TP1 + I _TP2 .

Then, during the period from time _{T 3 T S,} the 3DA converter ₁₄ 1 -14 ₃ is outputting DAC current from each of the first. Total DAC current _{I DAC} is instantaneously peaks at time _{T 3.} At this time, the total peak current I _TP = I _TP3 is larger than I _TP2 . However, the total peak current I _TP3 is smaller than I _TP1 + I _TP2 + I _TP3 .

As described above, the timings at which the first to k-th DAC currents I _DAC1 -I _DACk are output are different. Therefore, as shown in FIG. 7, the timing at which each total peak current I _TP is generated is dispersed. As shown in FIG. 6, even if the peak currents of the first to k-th DAC currents I _DAC1 -I _DACk have the same value, the total peak current I _TP itself is lower than the conventional one. Therefore, the current supplied to the integrator 12 can be reduced. This leads to lower power consumption.

2. Detailed Configuration Example of Delta Sigma Modulator FIG. 8 is a circuit diagram illustrating a detailed configuration example of the delta sigma modulator 1 according to the first embodiment. The delta sigma modulator 1 further includes a DEM (Dynamic Element Matching) circuit 17. The DEM circuit 17 is an example of a processing circuit that performs a predetermined process on the thermometer code C. The control unit 15 includes a signal generation circuit 151 and a plurality of delay circuits 152.

In addition, the delta-sigma modulator 1 has a differential interface in order to reduce noise. Therefore, as shown in FIG. 8, two signal lines are used for transmission of one type of signal. Of the two signal lines, the positive signal line is referred to as a “first signal line L _P ”. The negative signal line is referred to as “second signal line L _N ”. For example, the analog signal A to be input to the delta-sigma modulator 1 voltage, and the analog signal A _P supplied to the first signal line L _P, the analog signal A _P supplied to the second signal line L _N Determined by potential difference.

Hereinafter, in order to simplify the description, an n = 2-bit delta-sigma modulator 1 is taken as an example. In this case, the following is assumed.
1) The quantizer 13 has a resolution of n = 2 bits. Therefore, the thermometer code C is 3 bits.
2) The number of DA converters 14 is k = 2 ² −1 = 3. Therefore, the total DAC current I _DAC is the sum of the first to third DAC currents I _DAC1 -I _DAC3 .
3) The control unit 15 includes m = 6 delay circuits 152.

2.1. Subtractor 11
The subtractor 11 will be described. The subtractor 11 has a first subtractor node 111P and a second subtractor node 111N. First subtractor node 111P is be on the first signal line _{L P,} lies between the non-inverting input terminal of the operational amplifier 123 and the first input resistor 121P (+). On the other hand, the second subtractor node 111N is be on the second signal line _{L N,} the inverting input terminal of the second input resistor 121N and operational amplifier 123 - is between ().

2.2. Integrator 12
The integrator 12 will be described. The integrator 12 includes a first input resistor 121P, a second input resistor 121N, a first feedback capacitor 122P, a second feedback capacitor 122N, and an operational amplifier 123.

The first input resistor 121P is an analog signal A _P supplied to the first signal line L _P, into a current corresponding to the voltage. This current merges with the total DAC current I _DAC at the first subtractor node 111P. The combined current is referred to as “differential current S _P ”. Differential current _{S P} is supplied to the first feedback capacitor 122P.

Similar to the first input resistor 121P, the second input resistor 121N converts the analog signal A _N supplied to the second signal line _LN into a current corresponding to the voltage. This current merges with the total DAC current I _DAC at the second subtractor node 111N. The combined current is called “differential current S _N ”. The differential current _SN is supplied to the second feedback capacitor 122N.

The first feedback capacitor 122P includes two electrode plates. One electrode plate is connected to the non-inverting input terminal (+) of the operational amplifier 123. The other electrode plate is connected to the inverting output terminal (−) of the operational amplifier 123. First feedback capacitor 122P accumulates charge corresponding to the differential current _{S P.}

The second feedback capacitor 122N also includes two electrode plates. One electrode plate is connected to the inverting input terminal (−) of the operational amplifier 123. The other electrode plate is connected to the non-inverting output terminal (+) of the operational amplifier 123. The second feedback capacitor 122N accumulates electric charge according to the differential current _SN .

Specifically, the operational amplifier 123 is a differential amplifier. The operational amplifier 123 integrates the difference S by the subtractor 11, that is, the potential difference between the two input voltages, by sampling time Ts. One of the two input voltages is the input voltage _VINP to the non-inverting input terminal (+). The other is the input voltage _VINN to the inverting input terminal (−). The operational amplifier 123 outputs a voltage V _OUTP corresponding to the amount of charge stored in the first feedback capacitor 122P to the inverting output terminal (−). At the same time, the operational amplifier 123 outputs a voltage V _OUTN corresponding to the amount of charge accumulated in the second feedback capacitor 122N to the non-inverting output terminal (+). The voltage V _{OUTP with} respect to the voltage V _OUTN is an integral value of the integrator 12.

2.3. Quantizer 13
The quantizer 13 will be described. The quantizer 13 performs the following processing during the period of the quantizer control signal CLKCMP = “H (high level)”. First, the quantizer 13 compares the integrated value that is the output of the integrator 12 with 2 ² (= 4) reference voltages using a voltage comparison circuit (not shown). The quantizer 13 quantizes the integral value based on the comparison result. The integral value is quantized to one of four quantization levels (four values). Next, the quantizer 13 creates a 3-bit thermometer code C corresponding to the four-level quantization level. The quaternary quantization levels are respectively associated with the quaternary thermometer codes C as shown in Table 1. The quantizer 13 outputs the created thermometer code C to the decoder 16 and the DEM circuit 17.

2.4. DEM circuit 17
The DEM circuit 17 will be described. DEM circuit 17 every sampling time _{T S,} and inputs the thermometer code C from the quantizer 13. As shown in Table 1, the thermometer code C has k = 3 first to third bits C ₁ -C ₃ arranged from the _first bit to the third bit. Each time the DEM circuit 17 inputs the thermometer code C, the DEM circuit 17 changes the order of the arrangement of the first to third bits C ₁ -C ₃ constituting the input thermometer code C. The order change may be regular or random. Further, it is sufficient if the order is changed when each of the first to third bits C ₁ -C ₃ is not the same value. The DEM circuit 17 outputs the first to third output bits OUT ₁ -OUT ₃ reflecting the change of the order to the first to third DA converters 14 ₁ -14 ₃ , respectively.

Here, the first output bit OUT ₁ indicates the LSB that is the first bit of the output OUT. The second output bit OUT ₂ indicates the second bit of the output OUT. The third bit OUT ₃ indicates the MSB that is the k-th bit of the output OUT.

An example of the operation (DEM processing) of the DEM circuit 17 is given. For example, when the thermometer code C = “001”, the first to third bits C ₁ -C ₃ are “1”, “0”, and “0”, respectively. The DEM circuit 17 operates as follows when the thermometer code C = “001” is continuously input a plurality of times.

First input:
The output OUT at this time is “001”. Accordingly, the first to third DA converters 14 _{1 to} 14 ₃ receive “1”, “0”, and “0”, respectively.

Second input:
With this input, the DEM circuit 17 replaces the position of the first bit C ₁ having “1” with the position of the second bit C ₂ . Therefore, the output OUT is “010”. The first to third DA converters 14 _{1 to} 14 ₃ receive “0”, “1”, and “0”, respectively.

Third input:
With this input, the DEM circuit 17 replaces the position of the second bit C ₂ having “1” with the position of the third bit C ₃ . Therefore, the output OUT is “100”. Accordingly, the first to third DA converters 14 _{1 to} 14 ₃ respectively input “0”, “0”, and “1”.

4th input:
With this input, the DEM circuit 17 replaces the position of the third bit C ₃ having “1” with the position of the first bit C ₁ . The output OUT at this time is “001”. The DEM 17 performs the same processing as the first input.

  When the thermometer code C having the same value continues as in the above example, the DEM circuit 17 prevents “1” from being continuously input to the same DA converter 14. Therefore, the following two remarkable effects can be obtained.

The first is to reduce harmonic noise. There are three peak currents I _TP1 -I _{TP3 in the} total DAC current I _DAC (see FIG. 7). The total DAC current I _DAC is input to the integrator 12 via the subtractor 11. Therefore, the integrator 12 can easily catch the three peak currents I _TP1 -I _TP3 as harmonic noise. The DEM circuit 17 reduces the harmonic noise generated because the first to third DAC currents I _{DAC1 to} I _DAC3 are output at different timings.

The second is to reduce noise caused by individual differences in each of the first to third DA converters 14 _{1 to} 14 ₃ . This individual difference occurs in the manufacturing process of the delta-sigma modulator 1. The above two effects become more significant as the resolution of the quantizer 13 increases.

2.5. 1st DA converter 14 ₁
About 1DA converter 14 ₁ will be described. The main points of the _first DA converter 141 are as follows.

1) When the first output bit OUT ₁ = “1”:
In this case, the 1DA converter 14 ₁ outputs the first 1DAC current _{I DAC1} with a positive sign to the first converging node _{ND OP.} The first junction node ND _OP is connected to the second subtractor node 111N of the subtractor 11.

2) When the first output bit OUT ₁ = “0”:
In this case, the 1DA converter 14 ₁ is first 1DAC current _{I DAC1} obtained by inverting the sign, that is, to output a first 1DAC current _{I DAC1} with a negative sign to the second converging node _{ND ON.} The second junction node ND _ON is connected to the first subtractor node 111P of the subtractor 11.

Subtractor 11 shown in FIG. 8, instead of subtracting the total DAC current _{I DAC} from the analog signal A, taking the structure to be added to the analog signal A total DAC current _{I DAC} the sign is inverted. Therefore, the output destination of the 1DAC current _{I DAC1} is different depending on the first value of the output bit OUT _1.

It will be described in detail first 1DA converter 14 _1. FIG. 9 is a partially enlarged view of the _first DA converter 141. The _first DA converter 141 is a differential DA converter. The 1DA converter 14 ₁ is provided with six switches, and two capacitors, two resistors.

  The six switches refer to the first switch SW1a, the second switch SW1b, the third switch SW1c, the fourth switch SW1d, the fifth switch SW1e, and the sixth switch SW1f. Each of the six switches is, for example, an n-channel MOS (Metal Oxide Semiconductor) transistor.

  The two capacitors refer to the first capacitor Ca and the second capacitor Cb. The two capacitors have substantially the same capacitance. The two resistors refer to the first resistor Ra and the second resistor Rb. The two resistors have substantially the same resistance value.

The connection relationship of the _first DA converter 141 will be described. A first switch SW1a, a third switch SW1c, and a first resistor Ra are connected in series between the first inflow node ND _IP and the first junction node ND _OP . Between the second inflow node _{ND IN} and second junction node _{ND ON,} a second switch SW1b, and a fourth switch SW1d, and a second resistor Rb is connected in series.

Additionally, the fifth switch SW1e is connected between two connection nodes ND _a and ND _b. Sixth switch SW1f is connected between two connection nodes ND _c and ND _d.

The first and second capacitors Ca and Cb are connected in series between the first and second nodes ND _e and ND _f . The third node ND _g, the common voltage _{V COM} is supplied.

  The operation of each of the six switches is as follows. Each of the six switches is on while a high level (“H”) control signal is applied. On the other hand, each of the six switches is off while a low level (“L”) control signal is applied. Specifically, it is as follows.

SW1a, SW1b:
The first and second switches SW1a and SW1b are controlled to be turned on / off by the first DAC control signal CLKS1. Both on / off operations are linked to each other. Both are on when charging the first and second capacitors Ca and Cb, respectively.

SW1c, SW1d:
The third and fourth switches SW1c and SW1d are each turned on / off by the first DAC control signal CLKHP1. Both on / off operations are linked to each other. When the output OUT ₁ = “1”, both are on. On the other hand, when the output OUT ₁ = “0”, both are off.

SW1e, SW1f:
The fifth and sixth switches SW1e and SW1f are controlled to be turned on / off by the first DAC control signal CLKHM1, respectively. Both on / off operations are linked to each other. When the output OUT ₁ = “1”, both are off. On the other hand, when the output OUT ₁ = “0”, both are on.

Next, the operation of the _first DA converter 141 at the sampling time Ts will be described with reference to FIGS. The operation is roughly divided into two steps.

1) When the output OUT ₁ = “1” Step 1: Charge state When the operation of the quantizer 13 starts, the first and second switches SW1a and SW1b receive the first DAC control signal CLKS1 = “H”, respectively. Held on. On the other hand, the third and fourth switches SW1c and SW1d receive the first DAC control signal CLKHP1 = "L" and are held off. Similarly, the fifth and sixth switches SW1e, SW1f receive the first DAC control signal CLKHM1 = "L" and are held off. The state of the _first DA converter 14 ₁ (the same applies to other DA converters) at this time is referred to as a “charged state”.

Eventually, the operation of the quantizer 13 stops. Then, the DEM circuit 17 outputs the first output bit OUT ₁ = “1”. At this time, each of the two capacitors is charged. Therefore, the voltage V _DACP of the first node ND _e gradually increases. When the output OUT ₁ = “1”, the voltage V _DACP is larger than the common voltage V _COM . On the other hand, the voltage V _DACN of the second node ND _f gradually decreases. Here, the voltage V _DACN is _equal to the voltage V _DACP inverted.

Step 2: Output State After the charging of the two capacitors is completed, the first and second switches SW1a and SW1b are switched from on to off in response to the first DAC control signal CLKS1 = “L”. On the other hand, the third and fourth switches SW1c and SW1d are switched from off to on in response to the first DAC control signal CLKHP1 = "H". However, the fifth and sixth switches SW1e and SW1f are held off. The state of the _first DA converter 14 ₁ (the same applies to other DA converters) at this time is referred to as an “output state”.

The first capacitor Ca is accumulating charges corresponding to the difference between the common voltage _{V COM} and the voltage _{V DACP.} Since the third switch SW1c is on, the first capacitor Ca is discharged by the first resistor Ra. Due to this discharge, a current corresponding to the amount of charge of the first capacitor Ca flows through the first resistor Ra. This current is the second 1DAC current _{I DAC1.} Then, the 1DAC current _{I DAC1} flows into the first converging node _{ND OP.}

The second capacitor Cb is in charges according to a difference between the common voltage _{V COM} and the voltage _{V DACn.} Since the fourth switch SW1d is on, the second capacitor Cb is discharged by the second resistor Rb. Due to this discharge, a current corresponding to the amount of charge of the second capacitor Cb flows through the second resistor Rb. This current is equal to one obtained by inverting the sign of the 1DAC current _{I DAC1.} Then, this current flows to the second junction node ND _ON .

2) When First Output Bit OUT ₁ = "0" Step 1: Charge State Step 1 is the same as when the first output bit OUT ₁ = "1". However, the sign of the voltage V _DACP is opposite to the case where the first output bit OUT ₁ = “1”. The same _{applies to} the sign of the voltage V _DACN .

Step 2: Output State As in the case of the first output bit OUT ₁ = “0”, the first and second switches SW1a and SW1b are switched from on to off in response to the first DAC control signal CLKS1 = “L”. . However, the third and fourth switches SW1c and SW1d are held off. On the other hand, the fifth and sixth switches SW1e and SW1f are switched from off to on in response to the first DAC control signal CLKHM1 = “H”.

Since the fifth switch SW1e is on, the first capacitor Ca is discharged by the second resistor Rb. Due to this discharge, a current corresponding to the amount of charge of the first capacitor Ca flows through the second resistor Rb. When the first output bit OUT ₁ = “0”, this current is the first DAC current I _DAC1 . However, the sign of the 1DAC current _{I DAC1} is the case opposite to the first output bit _OUT 1 = "0". Then, the first DAC current I _DAC1 flows to the second junction node ND _ON .

Further, since the sixth switch SW1f is on, the second capacitor Cb is discharged by the first resistor Ra. Due to this discharge, a current corresponding to the amount of charge of the second capacitor Cb flows through the first resistor Ra. This current is equal to one obtained by inverting the sign of the 1DAC current _{I DAC1.} Then, the current flows into the first converging node _{ND OP.}

2.6. Second DA converter 14 ₂
The 2DA converter 14 ₂ receives the control signal is different from the first 1DA converter 14 _1. The differences are listed below.

SW2a, SW2b:
The first and second switches SW2a and SW2b are controlled to be turned on / off by the second DAC control signal CLKS2.
SW2c, SW2d:
The third and fourth switches SW2c and SW2d are controlled to be turned on / off by the second DAC control signal CLKHP2.
SW2e, SW2f:
The fifth and sixth switches SW1e and SW1f are controlled to be turned on / off by the second DAC control signal CLKHM2.

2.7. 3rd DA converter 14 ₃
The _third DA converter 143 also receives a different control signal from the first and second DA converters 14 ₁ and 14 ₂ . The differences are listed below.

SW3a, SW3b:
The first and second switches SW3a and SW3b are controlled to be turned on / off by the third DAC control signal CLKS3.
SW3c, SW3d:
The third and fourth switches SW3c, SW3d are controlled to be turned on / off by the third DAC control signal CLKHP3.
SW3e, SW3f:
The fifth and sixth switches SW3e and SW3f are controlled to be turned on / off by the third DAC control signal CLKHM3.

2.8. Control unit 15
The control unit 15 will be described. The control unit 15 includes a signal generation circuit 151 and m = 6 delay circuits 152. The mth delay circuit 152 is referred to as an “mth delay circuit 152”. The control unit 15 roughly generates two types of control signals. One is a quantizer control signal CLKCMP for controlling the quantizer 13. The control unit 15 generates a quantizer control signal CLKCMP using a circuit (not shown) and outputs it to the quantizer 13. The other is the first DAC control signals CLKS1, CLKHP1, and CLKHM1.

2.8.1. Signal generation circuit 151
The signal generation circuit 151 is composed of a clock oscillator, various logic circuits, and the like. Signal generating circuit 151 generates a first 1DAC control signal CLKS1, CLKHP1, CLKHM1, and outputs the each caused to the 1DA converter 14 _1. At the same time, the signal generation circuit 151 outputs the first DAC control signals CLKS1, CLKHP1, and CLKHM1 to the corresponding delay circuits 152 of the _six delay circuits 152 _{1 to} 1526, respectively. Details are as follows.

First DAC control signal CLKS1:
The signal generation circuit 151 outputs the first DAC control signal CLKS1 to the first and second switches SW1a and SW1b, respectively. Furthermore, the signal generating circuit 151 outputs the first 1DAC control signal CLKS1 the first delay circuit 152 _1.

First DAC control signal CLKHP1:
The signal generation circuit 151 outputs the first DAC control signal CLKHP1 to the third and fourth switches SW1c and SW1d, respectively. Furthermore, the signal generating circuit 151 outputs the first 1DAC control signal CLKHP1 the second and fifth delay circuits ₁₅₂ 2, 152 _5.

First DAC control signal CLKHM1:
The signal generation circuit 151 outputs the first DAC control signal CLKHM1 to the fifth and sixth switches SW1e and SW1f, respectively. Furthermore, the signal generating circuit 151 outputs the first 1DAC control signal CLKHM1 to the third and sixth delay circuit ₁₅₂ 3, 152 _6.

2.8.2. First to sixth delay circuits 152 _{1 to} 152 ₆
The first to sixth delay circuits 152 _{1 to} 15 ₂₆ have, for example, the same configuration as that of the RC low-pass filter. The RC low-pass filter includes one resistor (R) and one capacitor (C), and outputs an input signal with a delay corresponding to a time constant RC. Each of the six delay circuits 152 may be configured with a shift register or the like. In any case, each of the six delay circuits 152 is a digital circuit.

Delay circuits 152 ₁ -152 ₃ :
First to third delay circuits ₁₅₂ 1 -152 _3, a 1DAC control signal CLKS1, CLKHP1, CLKHM1 the delaying time Td1 delays respectively. The third delay circuit ₁₅₂ 1 -152 ₃ from the first, second 1DAC control signal CLKS1 delayed, CLKHP1, CLKHM1 respective first 2DAC control signal CLKS2, CLKHP2, and outputs it as CLKHM2 to the 2DA converter 14 _2.

Specifically, the first delay circuit 152 _1, the first 2DAC control signal CLKS2 first and second switches SW2a, and outputs respectively SW2b. The second delay circuit 152 _2, respectively, and output the first 2DAC control signal CLKHP2 third and fourth switch SW2c, the SW2d. The third delay circuit 152 _3, respectively, and output the first 2DAC control signal CLKHM2 fifth and sixth switch SW2e, the SW2f.

Delay circuit 152 ₄ -152 ₆ :
4 from the sixth delay circuit ₁₅₂ 4 -152 _6, first 1DAC control signal CLKS1, CLKHP1, CLKHM1 the delaying time Td2 respectively delayed. The delay time Td2 is larger than the delay time Td1 (Td2> Td1). The sixth delay circuit ₁₅₂ 4 -152 ₆ from the 4 outputs the 1DAC control signal CLKS1 delayed, CLKHP1, CLKHM1 to the first 3DAC control signal CLKS3, CLKHP3, as CLKHM3 the 3DA converter 14 _3, respectively.

Specifically, the fourth delay circuit 152 _4, and outputs the first 3DAC control signal CLKS3 first and second switches SW3a, the SW3b. The fifth delay circuit 152 _5, and outputs the first 3DAC control signal CLKHP3 third and fourth switches SW3c, the SW3d. The sixth delay circuit 152 _6, a first 3DAC control signal CLKHM3 fifth and sixth switch SW3e, outputs respectively SW3f.

2.9. Decoder 16
The decoder 16 will be described. The quaternary thermometer code C is associated with a quaternary binary code as shown in Table 2. The decoder 16 converts the 3-bit output thermometer code C of the quantizer 13 into an n = 2-bit binary code.

3. Operation Example of Delta Sigma Modulator FIG. 10 is a timing chart showing an operation example of the delta sigma modulator 1.

3.1. Description of Entire Timing Chart First, the entire timing chart illustrated in FIG. 10 will be described. Delta-sigma modulator 1 converts the analog signal A into a digital signal D for each sampling period T _S. As shown in FIG. 1A, the sampling time Ts is the time from the rise of a certain clock CLK to the rise of the next clock CLK. The clock CLK is supplied from the outside of the delta sigma modulator 1. Here, among the many sampling times Ts, the first to third sampling times T _{S1 to} T _S3 are taken as an example.

As shown in FIG. 10B, the quantizer 13 starts to quantize the analog signal A in synchronization with the rise of the quantizer control signal CLKCMP. Before the start, the subtractor 11 has already output the difference S between the analog signal A and the total DAC current _IDAC to the integrator 12. Then, the integrator 12, and integrates the difference S by the sampling time T _S units. The quantization needs to be completed during the period of the quantizer control signal CLKCMP = “H”.

As shown in FIG. 10C, it is assumed that the thermometer code C that is the output of the quantizer 13 is C = “001” in all of the first to third sampling times T _{S1 to} T _S3. . As shown in FIG. 10D, every time the thermometer code C is input from the quantizer 13, the DEM circuit 17 performs first to third bits C ₁ -C on the input thermometer code C. The order of the array of ₃ is changed. The results are as follows.

First sampling time T _S1 : Output OUT = “001”
Second sampling time T _S2 : Output OUT = “010”
Third sampling time T _S3 : Output OUT = “100”

Part 3DA converter ₁₄ 1 -14 ₃ from the first, for each sampling period _{T S,} the 3DAC current from a first forming the output OUT of the third output bit _OUT 1 -OUT ₃ from the first _I DAC1 _{-I DAC 3} Respectively. At that time, the first to third DA converters 14 _{1 to} 14 ₃ operate as follows.

First sampling time T _S1 :
At time _{T 11,} the 1DA converter 14 ₁ starts output of the 1DAC current _{I DAC1.} Since the first output bit OUT ₁ = “1”, the first DA converter 14 ₁ outputs the first DAC current I _DAC1 shown in FIG. 10 (N) to the first junction node ND _OP .

In the delay time Td1 elapsed time _{T 12} from the time _{T 11,} the 2DA converter 14 ₂ starts output of the 2DAC current _{I DAC2.} Since the second output bit _OUT 2 = "0", the 2DA converter 14 ₂ outputs a first 2DAC current _{I DAC2} shown in FIG. 10 (O) to the second confluence node _{ND ON.}

In the delay time Td2 elapsed time _{T 13} from the time _{T 11,} the 3DA transducer 14 ₃ starts output of the 3DAC current _{I DAC 3.} Since the third is the output bit _OUT 3 = "0", the 3DA transducer 14 ₃ outputs a first 3DAC current _{I DAC 3} shown in FIG. 10 (P) to the second confluence node _{ND ON.}

Second sampling time T _S2 :
The first to third DA converters 14 _{1 to} 14 ₃ operate in the same manner as in the case of the first sampling time T _S1 . However, the following points are different from the case of the first sampling time T _S1 .

First, the 1DA converter 14 _1, at time _{T 21,} and outputs a first 1DAC current _{I DAC1} shown in FIG. 10 (N) to the second confluence node _{ND ON.} This is because the first output bit OUT ₁ is “0”. Second, the 2DA converter 14 _2, at time _{T 22,} and outputs a first 2DAC current _{I DAC2} shown in FIG. 10 (O) to the first converging node _{ND OP.} This is because the second output bit OUT ₂ is “1”.

Third sampling time T _S3 :
The first to third DA converters 14 _{1 to} 14 ₃ operate in the same manner as in the case of the first sampling time T _S1 . However, the following points are different from the case of the first sampling time T _S1 .

First, the 1DA converter 14 _1, at time _{T 31,} and outputs a first 1DAC current _{I DAC1} shown in FIG. 10 (N) to the second confluence node _{ND ON.} This is due to the same reason as in the case of the second sampling time _TS2 . Second, the 3DA transducer 14 _3, at time _{T 33,} and outputs a first 3DAC current _{I DAC 3} shown in FIG. 10 (P) to the first converging node _{ND OP.} This is because the third output bit OUT ₃ is “1”.

3.2. Operation Example of First to Third DA Converters 14 _{1 to} 14 ₃ Next, an operation example of the first to third DA converters 14 _{1 to} 14 ₃ will be described in association with the control unit 15.

3.2.1. First sampling time T _S1
At the rise of the quantizer control signal CLKCMP:
At this time, the first to third DA converters 14 _{1 to} 14 ₃ are in a charged state. At this time, the control unit 15 operates as follows.

Control unit 15, FIG. 10 (E), and outputs, respectively (H), the first 1DAC control signal CLKS1, CLKHP1, CLKHM1 shown respectively in first 1DA converter 14 ₁ (K). The level of the first DAC control signal is shown below.

First DAC control signal CLKS1 = "H"
First DAC control signal CLKHP1 = "L"
First DAC control signal CLKHM1 = "L"

Similarly, the control unit 15, FIG. 10 (F), and outputs, respectively (I), the first 2DAC control signal CLKS2, CLKHP2, CLKHM2 shown respectively in the 2DA converter 14 ₂ (L). The respective levels of the second DAC control signal are shown below.

Second DAC control signal CLKS2 = "H"
Second DAC control signal CLKHP2 = "L"
Second DAC control signal CLKHM2 = "L"

Similarly, the control unit 15 outputs third DAC control signals CLKS3, CLKHP3, and CLKHM3 shown in FIGS. 10G, 10J, and 10M to the _third DA converter 143, respectively. The level of the third DAC control signal is shown below.

Third DAC control signal CLKS3 = "H"
Third DAC control signal CLKHP3 = "L"
Third DAC control signal CLKHM3 = "L"

Accordingly, the six switches of the _first DA converter 141 take the following states.
First and second switches SW1a, SW1b = “ON”
Third and fourth switches SW1c, SW1d = “off”
Fifth and sixth switches SW1e, SW1f = “off”

The six switches of the _second DA converter 142 take the following states.
First and second switches SW2a, SW2b = “ON”
Third and fourth switches SW2c, SW2d = "OFF"
Fifth and sixth switches SW2e, SW2f = "OFF"

The six switches of the _third DA converter 143 take the following states.
First and second switches SW3a, SW3b = “ON”
Third and fourth switches SW3c, SW3d = "OFF"
Fifth and sixth switches SW3e, SW3f = "OFF"

At the rising edge of the quantizer control signal CLKCMP, the first to third DA converters 14 _{1 to} 14 ₃ stop outputting the first to third DAC currents I _{DAC1 to} I _DAC3 .

Time T ₁₁ :
At time _{T 11,} the 1DA converter 14 ₁ is switched to the output state from the charged state. On the other hand, the second and third DA converters 14 ₂ and 14 ₃ are each kept in a charged state.

At this time, the control unit 15 operates as follows. Incidentally, each level of the 1DAC control signal, between time _{T 11} time [Delta] T, is maintained.

The control unit 15 switches the first DAC control signal CLKS1 from “H” to “L”.
The control unit 15 switches the first DAC control signal CLKHP1 from “L” to “H”.
The control unit 15 holds the first DAC control signal CLKHM1 at “L”.

Thus, six switches of the 1DA converter 14 _1, between time _{T 11} time [Delta] T, taking each of the following conditions.

First and second switches SW1a, SW1b = “off”
Third and fourth switches SW1c, SW1d = “ON”
Fifth and sixth switches SW1e, SW1f = “off”

As a result, as shown in FIG. 10N, the first DA converter 14 ₁ starts outputting the _first DAC current IDAC ₁ at time T ₁₁ .

Time T ₁₂ :
At time _{T 12,} the 2DA converter 14 ₂ is switched to the output state from the charged state. The 3DA transducer 14 ₃ is charged.

At this time, the control unit 15 operates as follows. Incidentally, each level of the 2DAC control signal, between time _{T 12} time [Delta] T, is maintained. Each of the second DAC control signals is delayed by a delay time Td1 from each of the first DAC control signals by the first to third delay circuits 152 ₁ -152 ₂ .

The control unit 15 switches the second DAC control signal CLKS2 from “H” to “L”.
The control unit 15 holds the second DAC control signal CLKHP2 at “L”.
The control unit 15 switches the second DAC control signal CLKHM2 from “L” to “H”.

Thus, six switches of the 2DA converter 14 _2, between the time _{T 12} time [Delta] T, taking each of the following conditions.

First and second switches SW2a, SW2b = “off”
Third and fourth switches SW2c, SW2d = "OFF"
Fifth and sixth switches SW2e, SW2f = “ON”

As a result, as shown in FIG. 10 (O), at time _{T 12,} the 2DA converter 14 _2, it starts outputting the first 2DAC current IDAC _2.

Time T ₁₃ :
At time _{T 13,} the 3DA transducer 14 ₃ is switched to the output state from the charged state.

At this time, the control unit 15 operates as follows. Incidentally, each level of the 3DAC control signal, between time _{T 13} time [Delta] T, is maintained. Each of the third DAC control signals is delayed by a delay time Td2 with respect to each of the first DAC control signals by the fourth to sixth delay circuits 152 _{4 to} 15 ₂₆ .

The control unit 15 switches the third DAC control signal CLKS3 from “H” to “L”.
The control unit 15 holds the third DAC control signal CLKHP3 at “L”.
The control unit 15 switches the third DAC control signal CLKHM3 from “L” to “H”.

Thus, six switches of the 3DA transducer 14 _3, between time _{T 13} time [Delta] T, taking each of the following conditions.

First and second switches SW3a, SW3b = “off”
Third and fourth switches SW3c, SW3d = "OFF"
Fifth and sixth switches SW3e, SW3f = "ON"

As a result, as shown in FIG. 10 (P), at time _{T 13,} the 3DA transducer 14 ₃ starts output of the 3DAC current IDAC _3.

Time T ₁₄ :
At time ΔT elapsed time _{T 14} from the time _{T 11,} the 1DA converter 14 ₁ is switched from the output state to the charging state. On the other hand, the second and third DA converters 14 ₂ and 14 ₃ are each held in an output state. At this time, the control unit 15 outputs the first 1DAC control signal CLKS1, CLKHP1, CLKHM1 similar to the rise of quantizer control signal CLKCMP to the 1DA converter 14 _1. Accordingly, the 1DA converter 14 ₁ stops the output of the 1DAC current _{I DAC1.}

Time T ₁₅ :
At time ΔT elapsed time _{T 15} from the time _{T 12,} the 2DA converter 14 ₂ is switched from the output state to the charging state. The 3DA transducer 14 ₃ is held in the output state. At this time, the control unit 15, when the same first 2DAC control signal and the rising edge of the quantizer control signal CLKCMP CLKS2, CLKHP2, and outputs the CLKHM2 to the 2DA converter 14 _2. Accordingly, the 2DA converter 14 ₂ stops the output of the 2DAC current _{I DAC2.}

Time T ₁₆ :
At the time ΔT elapsed time _{T 16} time _{T 13,} the 3DA transducer 14 ₃ is switched from the output state to the charging state. At this time, the control unit 15 outputs each similar first 3DAC control signal and the rising edge of the quantizer control signal CLKCMP CLKS3, CLKHP3, the CLKHM3 to the 3DA transducer 14 _3. Accordingly, the 3DA transducer 14 ₃ stops outputting of the 3DAC current _{I DAC 3.}

3.2.3. Second sampling time T _S2
Operation of the first to 3DA converter ₁₄ 1 -14 ₃ and the control unit 15 at this time is the same as the first sampling time _{T S1.} However, when each of these operations is compared with the case of the first sampling time _TS1 , there are differences in two points. The first is the level of the 1DAC control signal CLKHP1, CLKHM1 at time _{T 21.} The second is the level of the 2DAC control signal CLKHP2, CLKHM2 at time _{T 22.} Specifically, it is as follows.

First DAC control signal CLKHP1 = "L" (time T ₂₁ )
First DAC control signal CLKHM1 = “L” to “H” (time T ₂₁ )
Second DAC control signal CLKHP2 = “L” to “H” (time T ₂₂ )
Second DAC control signal CLKHM2 = “L” (time T ₂₂ )

3.2.4. Third sampling time T _S3
Operation of the first to 3DA converter ₁₄ 1 -14 ₃ and the control unit 15 at this time is the same as the case of the first sampling time _{T S1.} However, when each of these operations is compared with each operation in the first sampling time _TS1 , there are two differences. The first is the level of the 1DAC control signal CLKHP1, CLKHM1 at time _{T 31.} The second is the level of the 3DAC control signal CLKHP3, CLKHM3 at time _{T 33.} Specifically, it is as follows.

First DAC control signal CLKHP1 = "L" (time T ₃₁ )
First DAC control signal CLKHM1 = “L” to “H” (time T ₃₁ )
Third DAC control signal CLKHP3 = “L” to “H” (time T ₃₂ )
Third DAC control signal CLKHM3 = “L” (time T ₃₂ )

As described above, the output timings of the first to third DA converters 14 _{1 to} 14 ₃ are different. Therefore, each of the peak current _{I P} of the 3DAC current _I DAC1 _{-I DAC 3} is dispersed from the first. The degree of dispersion depends on the two delay times Td1 and Td2. As the two delay times Td1 and Td2 is larger respectively, the peak current _{I P} is increased dispersion. When the SCR type DA converter is used, the two delay times Td1 and Td2 are in a range in which the time interval from the rise of the quantizer control signal CLKCMP to the fall of the third DAC control signal CLKHM3 is zero or more. It is desirable to be within.

Due to the dispersion of the three peak currents I _P , the total peak current is lower than the conventional one, so that the current supplied to the integrator 12 can be reduced. This leads to lower power consumption.

4). Arrangement Layout of Delta Sigma Modulator FIG. 11 is a diagram illustrating an example of an arrangement layout of the delta sigma modulator 1. The controller 15 and the decoder 16 are not shown. The first to sixth delay circuits 152 _{1 to} 15 ₂₆ are arranged adjacent to the corresponding second and third DA converters 14 ₂ and 14 ₃ , respectively. This is to minimize the propagation delay of each of the second and third DAC control signals.

As shown in FIG. 11, in addition to the first to sixth delay circuits ₁₅₂ 1 -152 _6, ninth delay circuit ₁₅₂ 7 -152 ₉ from the seventh is arranged adjacent to the 1DA converter 14 ₁ . This assumes the following case.

In this embodiment, based on the first 1DA converter 14 ₁ of the output start, the 2DA converter 14 ₂ of the output start is delayed. Then, the 3DA converter 14 _third output start is delayed with respect to the output start of the 2DA converter 14 _2. Therefore, a delay circuit corresponding to the _first DA converter 141 is not provided.

In order to disperse the respective peak current _{I P} may be different timing of the output of each of the 3DA converter ₁₄ 1 -14 ₃ of the first is. For example, after the first 2DA converter 14 ₂ starts output of the 2DAC current _{I DAC 3,} the 3DA transducer 14 ₃ starts output of the 3DAC current _{I DAC2,} then the 1DA converter 14 ₁ is first 1DAC The output of the current _IDAC1 may be started. In that case, the seventh with the ninth delay circuit ₁₅₂ 7 -152 _9, the delay of the 1DAC control signal CLKS1, CLKHP1, CLKHM1 is achieved.

Each of the first to 9 delay circuit 152 ₁ is constituted by a digital circuit does not require the layout area than the analog circuit. Therefore, in addition to reducing the power consumption of the delta-sigma modulator 1, it is possible to reduce the size.

5. FIG. 12 is a block diagram showing a configuration example of a microcomputer 2 provided with a delta sigma modulator 1. The delta sigma modulator 1 having the above-described features is suitable for a semiconductor device. In the present embodiment, the microcomputer 2 is taken as an example of a semiconductor device.

  The microcomputer 2 is configured as follows. In addition to the delta-sigma modulator 1, the microcomputer 2 includes a CPU (Central Processing Unit) 21, a RAM (Random Access Memory) 22, a ROM (Read Only Memory) 23, a multiplier 24, and a DA converter 25. With.

  CPU21 performs various calculations according to a program. The RAM 22 temporarily stores data necessary for the processing of the CPU 21. The ROM 23 stores, for example, firmware that controls the hardware of the microcomputer 2. The multiplier 24 generates a clock used inside the microcomputer 2. The DA converter 25 converts the digital data processed by the CPU 24 into analog data.

[Second Embodiment]
A second embodiment will be described. In the delta-sigma modulator 1 shown in FIG. 8, six delay circuits 152 are used. The six delay circuits 152 have individual differences due to manufacturing variations. Therefore, there may be variations in the output timing of each of the six delay circuits 152. In that case, each of the first to third DA converters 14 _{1 to} 14 ₃ may not be able to transition from the charge state to the output state during the sampling time Ts. In order to avoid this situation, in this embodiment, the time constants of the six delay circuits 152 are individually corrected.

  FIG. 13 is a circuit diagram illustrating a configuration example of the delta-sigma modulator 1A according to the second embodiment. In FIG. 13, the signal generation circuit 151 is not shown.

  There are two main differences between the present embodiment and the first embodiment. The first is that the delta-sigma modulator 1 </ b> A further includes a time constant correction circuit 17. The second is to individually correct the time constants of the six delay circuits 152 using the time constant correction circuit 17.

The first to sixth delay circuits 152 _{1 to} 15 ₂₆ have the same connection configuration as the RC low-pass filter. The time constant of each of the third delay circuit ₁₅₂ 1 -152 ₃ from the first is the same. The time constants of the fourth to sixth delay circuits 152 _{4 to} 15 ₂₆ are also the same. However, the former time constant is different from the latter time constant. The details are as follows.

Each of the first to third delay circuits 152 ₁ -152 ₃ includes a resistor R1 having a resistance value | R1 | and a capacitor C1 having a capacitance | C1 |. These time constants τ ₁ are τ ₁ = R1 × C1. On the other hand, each of the fourth to sixth delay circuits 152 _{4 to} 15 ₂₆ includes a resistor R2 having a resistance value | R2 | and a capacitor C2 having a capacitance | C2 |. This time constant τ ₂ is τ ₂ = R2 × C2. In the present embodiment, the capacitance | C1 | of the three capacitors C1 and the capacitance | C2 | of the three capacitors C2 can be varied independently. In order to make these capacitances variable by electronic control, for example, a varicap diode is used for each capacitor.

When the first to third delay circuits ₁₅₂ 1 -152 ₃ receives the control signal CNT1-CNT3, respectively, the capacitance of the capacitors C1 | C1 | is variably to the ideal value. Similarly, when the fourth to sixth delay circuit ₁₅₂ 4 -152 ₆ receives a control signal CNT4-CNT6, the capacitance of the capacitors C2 | C2 | is varied to the ideal value. The “ideal” here is a theoretical value that should be taken.

The time constant correction circuit 17 stores a first reference time constant τ ₁ and a second reference time constant τ ₂ . The first reference time constant τ ₁ is a theoretical value that satisfies the delay time Td1. The second reference time constant τ ₂ is a theoretical value that satisfies the delay time Td2. The time constant correction circuit 17 measures the actual time constant τ ₁ for each of the first to third delay circuits 152 ₁ -152 ₃ . In addition to this, the time constant correction circuit 17 measures an actual time constant τ ₂ for each of the fourth to sixth delay circuits 152 _{4 to} 15 ₂₆ . After the measurement, the time constant correction circuit 17 performs the following processing.

First, the time constant compensation circuit 17 compares the first and third delay circuits ₁₅₂ 1 -152 ₃ each actual time constant tau ₁ of the first reference time constant tau ₁ of. This comparison is referred to as a “first comparison”. By the first comparison, the time constant correction circuit 17 obtains the difference Δτ ₁ between them. This represents a deviation from the first reference time constant τ ₁ . The time constant correction circuit 17 outputs the control signal CNT1-CNT3 from the first to the third delay circuit ₁₅₂ 1 -152 _3. Control signal CNT1-CNT3, as the difference .DELTA..tau ₁ to zero, i.e., so that the actual time constant tau ₁ is equal to the first reference time constant tau _1, the electrostatic capacity | C1 | for varying the Signal. Each of the control signals CNT1-CNT3 has a value of a plurality of levels according to the degree of difference .DELTA..tau _1.

Second, the time constant correction circuit 17 compares the actual time constant τ ₂ with the second reference time constant τ ₂ for each of the fourth to sixth delay circuits 152 _{4 to} 15 ₂₆ . This comparison is referred to as a “second comparison”. The subsequent operation is the same as in the first comparison. The time constant correction circuit 17 obtains the difference Δτ ₂ between them. The time constant correction circuit 17 outputs the control signal CNT4-CNT6 fourth to sixth delay circuit ₁₅₂ 4 -152 _6. Control signal CNT4-CNT6, as the difference .DELTA..tau ₂ to zero, i.e., as ₂ actual time constant tau is equal to the first reference time constant tau _2, the electrostatic capacity | C2 | for varying the Signal. Each of the control signal CNT4-CNT6 also has a value of a plurality of levels according to the degree of difference .DELTA..tau _2.

An operation of the delta sigma modulator 1A including the time constant correction circuit 17 will be described. For example, the time constant correction circuit 17 performs the first and second comparisons for each sampling time Ts. The first and second comparisons can be performed not at the sampling time Ts but at a fixed time (for example, in minutes). The time constant correction circuit 17 outputs the control signal CNT1-CNT3 from the first to the third delay circuit ₁₅₂ 1 -152 _3. Additionally, the time constant correction circuit 17 outputs the control signal CNT4-CNT6 fourth to sixth delay circuit ₁₅₂ 4 -152 _6.

When the first to third delay circuits ₁₅₂ 1 -152 ₃ receives the control signal CNT1-CNT3, respectively, the capacitance of each of capacitors C1 | C1 | is corrected to ideal values. Similarly, when the fourth to sixth delay circuits 152 _{4 to} 15 ₂₆ receive the control signals CNT _{4 to} CNT _{6, the} capacitance | C 2 | of each capacitor C 2 is also corrected to an ideal value.

In the present embodiment, the time constants of the six delay circuits 152 are corrected. As a result, variations in the output timing of each of the six delay circuits 152 are suppressed. Therefore, it is possible to avoid a situation in which each of the first to third DA converters 14 _{1 to} 14 ₃ cannot transition from the charge state to the output state during the sampling time Ts. In addition to this, the effect of the first embodiment can be obtained.

  This embodiment can be suitably modified. For example, the time constant can be corrected by changing the resistance value instead of the capacitance. In this case, the time constant correction circuit 17 measures the resistance value. The time constant can be corrected by changing both the capacitance and the resistance value.

  In the case of the integrator 12 shown in FIG. 13, two time constants can be corrected by using the time constant correction circuit 17. Here, the two time constants refer to the following two. One is the product of the resistance value of the first input resistor 121P and the capacitance of the first feedback capacitor 122P. The other is the product of the resistance value of the second input resistor 121N and the capacitance of the second feedback capacitor 122N.

[Third Embodiment]
A third embodiment will be described. As shown in FIG. 12, the delta sigma modulator 1 can be mounted on the microcomputer 2. The microcomputer 2 usually includes a multiplier 24. The present embodiment discloses a delta-sigma modulator that does not require six delay circuits 152 by using the multiplier 24.

  FIG. 14 is a circuit diagram showing a configuration example of a delta-sigma modulator 1B according to the third embodiment. FIG. 14 also shows a multiplier 24 in addition to the delta sigma modulator 1B.

  There are two main differences between the present embodiment and the first and second embodiments. The first is that a multiplier 24 is used. The multiplier 24 functions as a part of the control unit 15 and plays the role of the signal generation circuit 151. In the present embodiment, since the multiplier 24 included in the microcomputer 2 is used, it is not necessary to newly provide a multiplier. However, even if the delta-sigma modulator 1B itself includes the multiplier 24, there is no problem. Second, the control unit 15 includes an output circuit 153.

  The multiplier 24 will be described. The multiplier 24 is, for example, a PLL (Phase Locked Loop). The multiplier 24 generates a new signal synchronized with the phase of the clock signal CLK. The configuration of the multiplier 24 is as follows.

  The multiplier 24 includes a phase comparator 241, a low-pass filter 242, a VCO (Voltage Controlled Oscillator) 243, and a dividing period 244. The phase comparator 241 detects the phase difference between the clock signal CLK and the output of the division cycle 244 and outputs this to the low-pass filter 242. The low-pass filter 242 smoothes the DC signal that is the output of the phase comparator 241. The VCO 243 includes a ring oscillator. The ring oscillator is composed of p inverters. Here, “p” is an odd number greater than 3 (in the present embodiment, p is an odd number of 7 or more). Each of the p inverters is connected in multiple stages in a ring shape so that the output is input to the next-stage inverter. The VCO 243 oscillates according to the voltage of the DC signal input from the low pass filter 242. The dividing period 244 divides the oscillation frequency of the VCO 243.

  In the present embodiment, among the odd number of inverters, the outputs of the following three inverters are used.

  The first inverter is, for example, the first stage inverter 2431. The control unit 15 uses the output as the first DAC control signal CLKS1.

  The second is an inverter 2432 in the subsequent stage that separates a plurality of inverters from the inverter 2431. The control unit 15 uses the output as the second DAC control signal CLKS2. The second DAC control signal CLKS2 is delayed by a delay time Td1 by a plurality of inverters between the inverter 2431 and the inverter 2432.

  The third is an inverter 2433 in the subsequent stage in which a plurality of inverters are separated from the inverter 2432. The control unit 15 uses the output as the third DAC control signal CLKS3. The third DAC control signal CLKS3 is delayed by a delay time Td2 by a plurality of inverters between the inverter 2431 and the inverter 2433.

  The output circuit 153 will be described. The output circuit 153 includes first to sixth AND gates 1531 to 1536. Each of the first to sixth AND gates 1531 to 1536 includes a first input terminal and a second input terminal. Hereinafter, the first to sixth AND gates 1531 to 1536 will be described.

First AND gate 1531:
The first AND gate 1531 generates the first DAC control signal CLKHP1. Specifically, the 1AND gate 1531, the first input terminal and enter the first 1DAC control signal / CLKS1, inputting the first output bit OUT ₁ to the second input terminal. The first DAC control signal / CLKS1 is the first DAC control signal CLKS1 whose level is inverted. For this level inversion, for example, an inverter (not shown) is used. This is the same as the second DAC control signal / CLKS2 and the third DAC control signal / CLKS3.

When the first DAC control signal / CLKS1 = “H” (that is, CLKS1 = “L”) and the first output bit OUT ₁ = “1”, the first AND gate 1531 outputs the first DAC control signal CLKHP1 = “H”. . In other cases, the first AND gate 1531 outputs the first DAC control signal CLKHP1 = "L".

Second AND gate 1532:
The second AND gate 1532 generates the first DAC control signal CLKHM1. Specifically, the 2AND gate 1532, the first input terminal and enter the first 1DAC control signal / CLKS1, inputting the first output bit OUTB ₁ to the second input terminal. The first output bit OUTB ₁ is an output of the DEM circuit 17 output to the negative second signal line L _N and has a complementary relationship with the first output bit OUT ₁ . For example, when the first output bit OUT ₁ = “1”, the first output bit OUTB ₁ is “0”.

The 1DAC control signal / CLKS1 = "H" and the case of the first output bit OUTB ₁ = "1", the 2AND gate 1532 outputs the first 1DAC control signal CLKHM1 = "H". In other cases, the second AND gate 1532 outputs the first DAC control signal CLKHM1 = “L”.

Third AND gate 1533:
The third AND gate 1533 generates the second DAC control signal CLKHP2. Specifically, the 3AND gate 1533, the first input terminal and enter the first 2DAC control signal / CLKS2, inputs the second output bit OUT ₂ to the second input terminal.

In the case of the 2DAC control signal / CLKS2 = "H" (i.e. CLKS2 = "L") and the second output bit _OUT 2 = "1", the 3AND gate 1533 outputs the first 2DAC control signal CLKHP2 = "H" . In other cases, the third AND gate 1533 outputs the second DAC control signal CLKHP2 = "L".

Fourth AND gate 1534:
The fourth AND gate 1534 generates the second DAC control signal CLKHM2. Specifically, the 4AND gate 1534, the first input terminal and enter the first 2DAC control signal / CLKS2, you input the second output bit OUTB ₂ to the second input terminal.

The 2DAC control signal / CLKS2 = "H" and the second output bit OUTB case ₂ = "1", the 4AND gate 1534 outputs the first 2DAC control signal CLKHM2 = "H". In other cases, the fourth AND gate 1534 outputs the second DAC control signal CLKHM2 = “L”.

5th AND gate 1535:
The fifth AND gate 1535 generates the third DAC control signal CLKHP3. Specifically, the 5AND gate 1535, the first input terminal and enter the first 3DAC control signal / CLKS3, inputs the third output bit OUT ₃ to the second input terminal.

In the case of the 3DAC control signal / CLKS3 = "H" (i.e. CLKS3 = "L") and the third output bit _OUT 3 = "1", the 5AND gate 1535 outputs the first 3DAC control signal CLKHP3 = "H" . In other cases, the fifth AND gate 1535 outputs the third DAC control signal CLKHP3 = "L".

Sixth AND gate 1536:
The sixth AND gate 1536 generates the third DAC control signal CLKHM3. Specifically, the 6AND gate 1536, the first input terminal and enter the first 3DAC control signal / CLKS3, inputs the second output bit OUTB ₃ to the second input terminal.

The 3DAC control signal / CLKS3 = "H" and the third case of output bits OUTB ₃ = "1", the 6AND gate 1536 outputs the first 3DAC control signal CLKHM3 = "H". In other cases, the sixth AND gate 1536 outputs the third DAC control signal CLKHM3 = “L”.

  In the first and second embodiments, the signal generation circuit 151 only generates the first DAC control signal CLKS1. Therefore, a delay circuit is necessary to generate the second DAC control signal CLKS2 delayed by the delay time Td1. On the other hand, in the present embodiment, a ring oscillator with high accuracy and an output circuit 153 composed of a plurality of logic circuits are used. Therefore, a delay circuit is not required, and each of the first to third DAC control signals with high accuracy can be generated.

[Fourth Embodiment]
A fourth embodiment will be described. In the present embodiment, as the multiplier 24, a DLL (Delay
Locked Loop) is used.

  FIG. 15 is a circuit diagram showing a configuration example of a delta-sigma modulator 1C according to the fourth embodiment. The multiplier 24 further includes an edge combiner 245. The multiplier 24 generates the first to third DAC control signals CLKS1, CLKS2, and CLKS3 by delaying the phase of the clock signal CLK. Specifically, the phase comparator 241 detects the phase difference between the clock signal CLK and the output of the VCO 243 and outputs this to the low-pass filter 242. The low-pass filter 242 smoothes the DC signal that is the output of the phase comparator 241. The VCO 243 oscillates with the clock signal CLK as an input. Based on the DC signal of the low-pass filter 242, the number of inverter stages of the VCO 243 is increased or decreased.

  Also in this embodiment, the same effect as that of the third embodiment can be obtained.

1: Delta sigma modulator 11: Subtractor 12: Integrator 13: Quantizer 14: DA converter 15: Control unit 151: Signal generator 152: Delay circuit 16: Decoder 17: DEM

Claims (5)

A subtractor that inputs a first analog signal and a second analog signal and subtracts the second analog signal from the first analog signal;
An integrator for integrating the subtraction result of the subtractor;
One quantizer for quantizing the output of the integrator;
Each a plurality of DA converters which are connected in parallel to receive the common output of the single quantizer above quantized by said one quantizer based on the output of the integrator A plurality of DA converters for converting a digital signal into an analog signal and outputting the converted analog signal as the second analog signal to the subtractor at different timings, respectively. Said one quantizer, the output of the integrator is quantized into n (≧ 2) bit, a quantizer which outputs thermometer code k (> n) bits corresponding to the quantization level ,
In addition to the one quantizer,
A processing circuit for processing the thermometer code as the digital signal;
K DA converters as the plurality of DA converters,
The thermometer code is
The thermometer code in which k bits are arranged from the 1st bit to the kth bit,
The processing circuit is
Changing the order of the arrangement of the k bits constituting the thermometer code;
The k DA converters are
The delta-sigma modulator according to claim 1, wherein the delta-sigma modulator converts the current into one corresponding to each of the k bits of the thermometer code in which the order of the arrangement is changed by the processing circuit. A control unit for controlling the output timing of each of the k DA converters;
The k DA converters are
A first DA converter that outputs a first current;
A second DA converter that outputs a second current,
The controller is
The first DA converter outputs the first current, the output of the first current by the first DA converter is delayed for a predetermined time, and the second DA converter outputs the second current. A delta-sigma modulator as described in 1. The controller is
4. The delta-sigma modulator according to claim 3, further comprising a delay circuit that delays the output of the second current by the second DA converter for the predetermined time from the start of the output of the first current by the first DA converter.   A semiconductor device comprising the delta-sigma modulator according to claim 1.

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