JP2015126111A - Semiconductor element manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor element manufacturing method which prevents residue of wax between a semiconductor layer and an electrode when performing a polishing process of a sapphire wafer before an electrode formation process.SOLUTION: A semiconductor element manufacturing method comprises: a group III nitride semiconductor layer formation process of growing a group III nitride semiconductor layer Ep1 on a first surface Y1 of a sapphire wafer Sa; a protection film formation process of forming a protection film F1 on a surface X1 on the group III nitride semiconductor layer Ep1; a polishing process of polishing a second surface Y2 of the sapphire wafer Sa in a state of holding the protection film F1; and a protection film removal process of removing the protection film F1 to expose a surface X1 of the group III nitride semiconductor layer Ep1.

Description

  The present invention relates to a method for manufacturing a semiconductor device having a wafer polishing step.

  A semiconductor element manufacturing process generally includes a semiconductor layer forming process for growing a semiconductor layer on a wafer, an electrode forming process for forming an electrode on the semiconductor layer, and a polishing process for polishing the wafer. . In particular, when manufacturing a thin semiconductor element, the polishing step is important.

  In the manufacturing process described in Patent Document 1, the sapphire wafer is polished after the semiconductor layer forming process and the electrode forming process of forming an electrode on the semiconductor layer (paragraph [0042] of Patent Document 1). -See [0048]).

JP 2007-109822 A

  In order to improve the flexibility of the manufacturing process, the inventors studied polishing the wafer before the electrode forming process. For example, when semiconductor layers are formed on wafers having different thicknesses, the thicknesses of these wafers can be made uniform by a polishing process. Therefore, the manufacturing process after the polishing process can be shared. Thereby, the production line can be simplified.

  In this case, the semiconductor layer is coated with wax, and the semiconductor layer side is fixed to the holding unit of the polishing apparatus. Then, the back surface of the wafer is polished. After the polishing is completed, the wax is removed by washing with, for example, acetone. Thereafter, an electrode is formed on the semiconductor layer. In this case, the present inventors have found that the electrical characteristics and light emitting characteristics of the light emitting element are not so good.

  The present inventors have found that this is because the wax component remains on the surface of the semiconductor layer. When the manufacturing steps are performed in this order, the adhesion between the semiconductor layer and the electrode is not sufficient. As a result, sufficient electrical characteristics and light emission characteristics could not be obtained. If the wax cleaning process is lengthened, the cycle time becomes longer. In addition, it is not always possible to remove the residual components of the wax.

  The present invention has been made to solve the above-described problems of the prior art. That is, the subject is providing the manufacturing method of the semiconductor element which prevents that a wax remains between a semiconductor layer and an electrode, when performing the grinding | polishing process of a wafer before an electrode formation process.

  According to a first aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: a semiconductor layer forming step of growing a semiconductor layer on a first surface of a wafer; a protective film forming step of forming a protective film on a surface of the semiconductor layer; A polishing step of polishing the second surface of the wafer in a state, and a protective film removing step of removing the protective film to expose the surface of the semiconductor layer.

  In this method of manufacturing a semiconductor element, a protective film is provided on a semiconductor layer, and a wax for polishing process is applied on the protective film. Therefore, there is no possibility that the wax remains on the unevenness of the semiconductor layer. For this reason, the adhesion between the semiconductor layer and the electrode is high. That is, the electrical characteristics of the light emitting device of this embodiment are good. In the present embodiment, the polishing process is performed after the semiconductor layer forming process. For example, when semiconductor layers are formed on wafers having different thicknesses, these thicknesses can be made uniform by a polishing process. Therefore, the manufacturing process after the polishing process can be shared. Thereby, the production line can be simplified.

  The semiconductor element manufacturing method according to the second aspect uses a polishing apparatus having a holding portion in the polishing step. The holding unit holds the protective film in a state in which wax is interposed between the holding surface and the protective film within a period of polishing the second surface of the wafer.

  According to a third aspect of the present invention, there is provided a method for manufacturing a semiconductor element, comprising: a first electrode forming step of forming a first electrode on a semiconductor layer exposed in a protective film removing step; and etching a portion of the semiconductor layer to form a groove. And a groove forming step to be formed.

  The method for manufacturing a semiconductor element in the fourth aspect includes an element dividing step of dividing the wafer into a plurality of semiconductor elements.

  In the semiconductor element manufacturing method according to the fifth aspect, a buffered hydrofluoric acid solution is used in the protective film removing step.

In the semiconductor element manufacturing method according to the sixth aspect, in the protective film forming step, the protective film is formed of any one of SiO ₂ , ITO, IZO, and SiN. This is because the surface of the semiconductor layer can be protected and the protective film can be easily removed.

  In the semiconductor element manufacturing method according to the seventh aspect, any of a sapphire wafer, a silicon wafer, a SiC wafer, a GaN wafer, a GaP wafer, a GaAs wafer, and an InP wafer is used as the wafer.

  In the semiconductor element manufacturing method according to the eighth aspect, in the semiconductor layer forming step, a group III nitride semiconductor layer is grown on the first surface of the wafer.

  The present invention provides a method for manufacturing a semiconductor element that prevents wax from remaining between a semiconductor layer and an electrode when a wafer polishing step is performed before the electrode formation step.

1 is a schematic configuration diagram illustrating a light emitting element according to a first embodiment. It is a top view showing a semiconductor wafer concerning an embodiment. It is FIG. (The 1) which shows the manufacturing process of the light emitting element which concerns on embodiment. It is FIG. (2) which shows the manufacturing process of the light emitting element which concerns on embodiment. It is FIG. (The 3) which shows the manufacturing process of the light emitting element which concerns on embodiment. It is FIG. (The 4) which shows the manufacturing process of the light emitting element which concerns on embodiment. It is FIG. (5) which shows the manufacturing process of the light emitting element which concerns on embodiment. It is a figure which shows the case where it etches with the manufacturing method of the light emitting element which concerns on embodiment. It is a figure which shows the case where it etched to the wafer which performed the grinding | polishing process, without forming a protective film. It is a figure which shows the position which investigated the etching amount of the overetching in the semiconductor wafer. It is a graph which shows the relationship between the etching amount of ITO overetching, and a drive voltage. It is a schematic block diagram which illustrates the HEMT element which concerns on 2nd Embodiment. It is a schematic block diagram which illustrates the power element which concerns on 3rd Embodiment.

  Hereinafter, specific embodiments will be described with reference to the drawings, taking a semiconductor light emitting element as an example. However, the present invention is not limited to the following embodiment. In addition, a laminated structure and an electrode structure of each layer of the light emitting element described later are examples. Therefore, it is of course possible to have a laminated structure different from that of the embodiment. And the thickness of each layer in each figure is only what was shown notionally.

(First embodiment)
1. Semiconductor Light-Emitting Element FIG. 1 is a schematic configuration diagram showing a light-emitting element 100 manufactured by the method for manufacturing a semiconductor light-emitting element of this embodiment. The light emitting device 100 is a face-up type light emitting device in which a group III nitride semiconductor is formed on a sapphire substrate.

  As shown in FIG. 1, the light emitting device 100 includes a sapphire substrate 110, a low temperature buffer layer 120, an n-type contact layer 130, an n-type ESD layer 140, an n-type superlattice layer 150, a light-emitting layer 160, A p-type superlattice layer 170, a p-type contact layer 180, a transparent electrode 190, a p-electrode P1, and an n-electrode N1 are included.

  The transparent electrode 190 is a first electrode. The transparent electrode 190 is formed on the p-type contact layer 180. The material of the transparent electrode 190 is ITO. Alternatively, it may be IZO. The p electrode P1 is formed on the transparent electrode 190. The n electrode N <b> 1 is formed on the n-type contact layer 130.

2. Semiconductor Wafer FIG. 2 shows the semiconductor wafer W1 after the semiconductor layer is formed on the sapphire wafer. FIG. 3 is a side view of the semiconductor wafer W1 as seen from the side. The semiconductor wafer W1 is a first semiconductor wafer in which a group III nitride semiconductor layer is formed on a sapphire wafer Sa. The sapphire wafer Sa is c-plane sapphire on which an orientation flat OF is formed. As described above, the semiconductor layer Ep1 is formed on the semiconductor wafer W1, but the electrode is not yet formed.

  As shown in FIG. 3, a semiconductor layer Ep1 is formed on the first surface Y1 of the sapphire wafer Sa. The surface X1 of the semiconductor layer Ep1 is exposed. The second surface Y2 of the sapphire wafer Sa is a surface that is polished in a polishing process described later. The thickness of the semiconductor wafer W1 before the polishing is L0.

3. Manufacturing Method of Semiconductor Light-Emitting Element The manufacturing method of the semiconductor light-emitting element of this embodiment is characterized in that the sapphire wafer Sa is polished before forming the electrodes and a protective film is formed at that time.

3-1. Semiconductor Layer Forming Step As shown in FIG. 3, the semiconductor layer Ep1 is formed on the first surface Y1 of the sapphire wafer Sa. The semiconductor layer Ep1 includes the low-temperature buffer layer 120, the n-type contact layer 130, the n-type ESD layer 140, the n-type superlattice layer 150, the light emitting layer 160, and the p-type superlattice layer from the sapphire wafer Sa side. 170 and p-type contact layer 180 are formed in this order. Thereby, the semiconductor wafer W1 is manufactured. In forming the semiconductor layer Ep1, a metal organic chemical vapor deposition method (MOCVD method) may be used.

3-2. First Cleaning Step Next, the semiconductor wafer W1 is cleaned with an acetone solution. Alternatively, the semiconductor wafer W1 may be cleaned with isopropyl alcohol (IPA) or the like.

3-3. Protection Film Formation Step As shown in FIG. 4, a protection film F1 is formed on the surface X1 of the semiconductor layer Ep1 using the CVD method. The protective film F1 is temporarily formed in order to protect the surface of the semiconductor layer Ep1 from wax during the polishing process to be performed later.

The thickness of the protective film F1 should just be a grade which fills the unevenness | corrugation of the surface X1 of the semiconductor layer Ep1. Therefore, the thickness of the protective film F1 should just be 2 nm or more. Since the protective film F1 is removed after the polishing process, as will be described later, it does not need to be so thick. Therefore, the thickness of the protective film F1 is preferably, for example, 300 nm or less. Of course, it may be thicker than this. The material of the protective film F1 is, for example, SiO ₂ . Thereby, as shown in FIG. 4, the semiconductor wafer W2 having the protective film F1 is manufactured. The semiconductor wafer W2 is a second semiconductor wafer.

3-4. Polishing Step Next, the sapphire wafer Sa is polished using a polishing apparatus. For this purpose, wax is applied to the surface Z1 of the protective film F1. Then, the surface Z1 of the protective film F1 coated with wax is mounted on the chuck jig of the polishing apparatus. This chuck jig is a holding unit for holding the semiconductor wafer W2 during the period of polishing the second surface Y2 of the sapphire wafer Sa. Actually, the chuck jig holds the protective film F1 of the semiconductor wafer W2 with a wax interposed between the chuck jig and the protective film F1 of the semiconductor wafer W2.

  Then, the second surface Y2 of the sapphire wafer Sa is polished while holding the protective film F1. The second surface Y2 is a surface on the back side of the first surface Y1. In the initial stage of polishing, rough polishing may be performed, and in the latter stage of polishing, fine polishing may be performed. Thereby, as shown in FIG. 5, the polished semiconductor wafer W3 is manufactured. FIG. 5 shows the second surface Y3 of the polished sapphire wafer Sa.

  At this time, as shown in FIG. 5, the semiconductor wafer W3 has a polished sapphire wafer Sa1. The thickness of the polished sapphire wafer Sa1 is L1. The thickness L1 is, for example, 500 μm. Of course, other thicknesses may be used. Then, after the polishing is completed, the semiconductor wafer W3 is removed from the chuck jig of the polishing apparatus.

3-5. Second Cleaning Step Thereafter, the semiconductor wafer W3 may be cleaned with acetone, isopropyl alcohol (IPA), or the like. Thereby, most of the wax can be removed from the protective film F1 of the semiconductor wafer W3.

3-6. Next, the protective film F1 is removed from the semiconductor wafer W3. For this purpose, the semiconductor wafer W3 is immersed in a buffered hydrofluoric acid solution (BHF solution). Thus, by reacting HF and the SiO ₂ contained in the buffered hydrofluoric acid, SiO ₂ is subjected to etching. The reaction formula at that time is represented by the following formula.
SiO ₂ + 6HF → H ₂ SiF ₆ + 2H ₂ O
Here, H ₂ SiF ₆ is a liquid. The etching rate is about 3 nm / sec. The processing time is, for example, not less than 2 seconds and not more than 10 minutes. The processing time depends on the thickness of the protective film F1. By this immersion, as shown in FIG. 6, the protective film F1 is peeled off from the surface X1 of the semiconductor layer Ep1. At this time, the wax slightly remaining on the surface of the protective film F1 is removed together with the protective film F1. Thus, the protective film F1 is removed from the surface X1 of the semiconductor layer Ep1, and the surface X1 of the semiconductor layer Ep1 is exposed. Thereby, the semiconductor wafer W4 is obtained.

3-7. First electrode forming step (transparent electrode forming step)
Next, a transparent electrode 190 is formed on the exposed p-type contact layer 180. At this time, no wax remains on the surface X 1 of the p-type contact layer 180.

3-8. Groove forming step Then, a groove for partitioning the element is formed. Further, a groove for exposing the n-electrode N1 is formed. In this manner, a part of the semiconductor layer Ep1 is etched to form a groove. Therefore, dry etching using ICP may be performed using a mask. In the present embodiment, overetching of the transparent electrode 190 can be suppressed during this dry etching. This is because no wax remains between the p-type contact layer 180 and the transparent electrode 190. Here, as shown in FIG. 7, the partitioned semiconductor layer Ep2 is formed by the formed groove. The semiconductor layer Ep2 is a semiconductor functional unit that functions as a single semiconductor element after being divided by an element dividing step described later. In this way, the semiconductor wafer W5 shown in FIG. 7 is obtained.

3-9. Second Electrode Formation Step Then, an n-electrode N1 is formed on the exposed portion of the n-type contact layer 130. Further, the p-electrode P <b> 1 is formed on the transparent electrode 190.

3-10. Element Dividing Step Thereafter, the semiconductor wafer W5 is divided using a laser device, a braking device, or the like. Thereby, a large number of chips are manufactured.

3-11. Other Steps In addition, a step of forming an insulating film that protects the entire element, a step of applying a phosphor, and a step of performing heat treatment may be appropriately performed. Moreover, you may implement processes other than the above. Thus, the light emitting device 100 is manufactured.

4). As described above, in this embodiment, the protective film F1 is provided on the semiconductor layer Ep1, and the wax is applied on the protective film F1. Therefore, there is no possibility that the wax remains on the unevenness of the surface X1 of the semiconductor layer Ep1. Therefore, the adhesion between the semiconductor layer Ep1 and the transparent electrode 190 is high. That is, the electrical characteristics of the light emitting device 100 of this embodiment are good.

  In the present embodiment, the polishing process is performed after the semiconductor layer forming process. For example, when semiconductor layers are formed on sapphire wafers Sa having different thicknesses, the thicknesses of these sapphire wafers Sa can be made uniform by a polishing process. Therefore, the manufacturing process after the polishing process can be shared. Thereby, the production line can be simplified.

5. Comparison between this embodiment and the case where no protective film is formed 5-1. Over-Etching in Groove Formation Step First, the case where the light emitting device 100 is manufactured by the manufacturing process of this embodiment will be described. FIG. 8 is a diagram showing a state after a resist R1 is formed on the transparent electrode 190 (ITO) and dry etching by ICP is performed. As shown in FIG. 8, the transparent electrode 190 has a sufficiently small amount of overetching compared to the resist R1.

  Here, the case where the protective film formation process and the protective film removal process are not performed from the manufacturing process of the present embodiment will be described. In this case, as shown in FIG. 9, the etching amount of the overetching in the transparent electrode 190 is larger than the etching amount in the case shown in FIG. This is presumably because wax remains on the surface X1 of the p-type contact layer 180 and the adhesion between the p-type contact layer 180 and the transparent electrode 190 is not sufficient.

  Actually, when the amount of overetching between the semiconductor layer Ep2 and the transparent electrode 190 was measured at a position K3 in FIG. 10, the following results were obtained. When the protective film F1 was formed as in the present embodiment, the etching amount was 5.7 μm. On the other hand, when the protective film F1 was not formed, the etching amount was 25 μm as described later.

5-2. Driving Voltage Next, an experiment for examining the relationship between the degree of overetching and the driving voltage will be described. In this experiment, the degree of overetching between the semiconductor layer Ep2 located at the positions K1, K2, and K3 shown in FIG. 10 and the transparent electrode 190 was examined. In this experiment, the experiment was performed without providing the protective film F1. The position K3 is near the center of the sapphire wafer Sa. The position K1 is a position on the opposite side of the orientation flat OF as viewed from the position K3. The position K2 is a position closer to the orientation flat OF than the position K3.

  Table 1 shows the results. At the position K1, the overetch amount is 8 μm and the drive voltage Vf is 2.93V. At the position K2, the overetch amount is 15 μm and the drive voltage Vf is 3.04V. At the position K3, the overetch amount is 25 μm and the drive voltage Vf is 3.20V. The results are shown in FIG.

  As described above, when the polishing step was performed with the protective film F1 formed, the overetch amount was 5.7 μm. Therefore, it can be estimated from the graph of FIG. 11 that the driving voltage Vf of the light emitting element in which the protective film F1 is formed and the polishing process is performed is about 2.89V. That is, the driving voltage Vf of the light emitting element 100 manufactured by the manufacturing method of the present embodiment is lower than the driving voltage Vf of the light emitting element in which the protective film F1 is not formed.

[Table 1]
Position Overetch amount Drive voltage Vf
This embodiment 5.7 μm 2.89V
K1 8μm 2.93V
K2 15μm 3.04V
K3 25μm 3.20V

5-3. Etching Rate when Removing Protective Film Table 2 shows the etching rate when forming the protective film F1 with SiO ₂ and removing the protective film F1 with buffered hydrofluoric acid. As shown in Table 2, the etching rate slightly changes depending on the output of the CVD apparatus in the protective film forming process. However, it is about 3 nm / sec. As described above, the protective film F1 can be suitably removed. The concentration of the buffered hydrofluoric acid used here was as follows. The HF concentration was 4.8 mass percent and the NH ₄ F concentration was 36.3 mass percent.

[Table 2]
RF Power (during film formation) Etching rate 55W 3.09nm / sec
75W 2.91nm / sec
95W 2.70nm / sec

6). Modification 6-1. Types of Light-Emitting Elements In this embodiment, the face-up type light-emitting element has been described as an example. However, it can also be applied to flip chips.

6-2. Kind of Wafer In this embodiment, a sapphire wafer is used as a wafer that is a growth substrate. However, a wafer other than sapphire may be used. Examples include GaN wafers, SiC wafers, silicon wafers, GaP wafers, InP wafers, and GaAs wafers. Of course, other wafers may be used.

6-3. Kind of Semiconductor In this embodiment, a group III nitride semiconductor such as GaN is grown on a sapphire wafer. However, the present invention can be applied not only to group III nitride semiconductors but also to other semiconductors. Examples include III-V group semiconductors such as GaAs, IV-IV group semiconductors such as SiC, and Group II chalcogenides such as ZnSe. Also, other semiconductors may be used.

6-4. Material of Protective Film The material of the protective film F1 is SiO ₂ . Other materials include ITO, IZO, and SiN. Other materials may be used as long as they can be suitably removed from the semiconductor layer Ep1 using a solution that does not damage the semiconductor layer Ep1.

6-5. Etching in groove forming step In this embodiment, dry etching by ICP is performed. However, other dry etching may be performed. Alternatively, other wet etching may be performed.

6-6. Groove Forming Process In this embodiment, the groove for forming the n electrode and the groove for partitioning the element are formed at a time by etching in the groove forming process. However, these grooves may be formed separately. In that case, the second groove forming step may be performed before the second electrode forming step.

6-7. Second cleaning step The second cleaning step may not necessarily be performed. If the protective film F1 can be removed, wax may adhere to the surface.

7). Summary of this Embodiment As described above in detail, in the method for manufacturing the light emitting device 100 according to this embodiment, the sapphire wafer Sa is polished before the transparent electrode 190 is formed on the semiconductor layer Ep1. And after forming the protective film F1 on the semiconductor layer Ep1, the wax for grinding | polishing processes is apply | coated on the protective film F1. Then, after the polishing process is completed, the protective film F1 is removed from the semiconductor layer Ep1. Therefore, there is no possibility that wax remains on the surface of the semiconductor layer Ep1. Therefore, the adhesion between the semiconductor layer Ep1 and the transparent electrode 190 is high.

  In addition, this Embodiment is only a mere illustration and does not limit this invention at all. Therefore, the present invention can be variously improved and modified without departing from the scope of the invention. The stacked structure of the semiconductor layers is not necessarily limited to that shown in the drawing. The laminated structure may be arbitrarily selected. Moreover, it is not restricted to a metal organic chemical vapor deposition method (MOCVD method). Other crystal growth methods may be used.

(Second Embodiment)
A second embodiment will be described. The semiconductor element of the present embodiment is a horizontal HEMT element 200 as shown in FIG. The HEMT device 200 includes a substrate 210, a buffer layer 220, a first carrier traveling layer 230, a second carrier traveling layer 240, a carrier supply layer 250, an insulating film 260, a source electrode S2, and a gate electrode G2. And a drain electrode D2.

  Also for such a HEMT device 200, as described in the first embodiment, the protective film forming step, the polishing step, and the protective film removing step can be performed to polish the wafer. . As a result, it is still possible to prevent the wax from remaining on the surface of the semiconductor layer. Even in this case, it is possible to share a production line when wafers having different thicknesses are used.

(Third embodiment)
A third embodiment will be described. The semiconductor device of this embodiment is a vertical power device 300 as shown in FIG. The power element 300 includes a substrate 310, an n-type layer 320, a p-type layer 330, an n-type layer 340, an insulating film 350, a source electrode S1, a gate electrode G1, and a drain electrode D1. ing.

  Also for such a power element 300, as described in the first embodiment, the wafer can be polished by performing the protective film forming step, the polishing step, and the protective film removing step. . As a result, it is still possible to prevent the wax from remaining on the surface of the semiconductor layer. Even in this case, the production line can be shared when wafers having different thicknesses are used.

DESCRIPTION OF SYMBOLS 100 ... Light emitting element 110 ... Sapphire substrate 120 ... Low temperature buffer layer 130 ... n-type contact layer 140 ... n-type ESD layer 150 ... n-type superlattice layer 160 ... Light-emitting layer 170 ... p-type superlattice layer 180 ... p-type contact layer 190 ... transparent electrode P1 ... p electrode N1 ... n electrode Sa, Sa1 ... sapphire wafer Y1 ... first surface Y2 ... second surface Ep1, Ep2 ... semiconductor layer X1 ... surface W1, W2, W3, W4, W5 ... semiconductor wafer

Claims (8)

A semiconductor layer forming step of growing a semiconductor layer on the first surface of the wafer;
A protective film forming step of forming a protective film on the surface of the semiconductor layer;
A polishing step of polishing the second surface of the wafer while holding the protective film;
Removing the protective film to expose the surface of the semiconductor layer; and
A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device according to claim 1,
In the polishing step,
Using a polishing apparatus having a holding part,
The holding part is
A method of manufacturing a semiconductor device, wherein the protective film is held in a state in which wax is interposed between the protective film and the second surface of the wafer while the second surface is polished. In the manufacturing method of the semiconductor device according to claim 1 or 2,
A first electrode forming step of forming a first electrode on the semiconductor layer exposed in the protective film removing step;
A groove forming step of forming a groove by etching a part of the semiconductor layer;
A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor element of any one of Claim 1- Claim 3,
A method of manufacturing a semiconductor element, comprising: an element dividing step of dividing the wafer into a plurality of semiconductor elements. In the manufacturing method of the semiconductor element of any one of Claim 1- Claim 4,
In the protective film removal step,
A method for producing a semiconductor element, comprising using a buffered hydrofluoric acid solution. In the manufacturing method of the semiconductor element of any one of Claim 1- Claim 5,
In the protective film forming step,
And SiO _2, ITO and, IZO and method of manufacturing a semiconductor device characterized by forming the protective film in any of the material of the SiN. In the manufacturing method of the semiconductor element of any one of Claim 1- Claim 6,
As the wafer,
A method of manufacturing a semiconductor device, wherein any one of a sapphire wafer, a silicon wafer, a SiC wafer, a GaN wafer, a GaP wafer, a GaAs wafer, and an InP wafer is used. In the manufacturing method of the semiconductor element of any one of Claim 1- Claim 7,
In the semiconductor layer forming step,
A method of manufacturing a semiconductor device, comprising growing a group III nitride semiconductor layer on the first surface of the wafer.

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