JP2015125351A - Display device drive circuit and display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a display device drive circuit, designed to shorten a drive time and reduce power consumption, that realizes partial drive.SOLUTION: The display device drive circuit comprises: a shift register circuit (20); a memory unit (10) for outputting a complementary output signal that drives a T signal high when activating a gate line and drives a B signal high when not activating the gate line; and a switch unit (30) for executing control of gate line drive and control of carry signal output, the switch unit of an n'th stage (n is an integer greater than or equal to 2) reading an n'th stage complementary output signal from the memory unit of the n'th stage and an n+1'th stage complementary output signal from the memory unit of an n+1'th stage and executing the control of gate line drive and control of carry signal output.

Description

  The present invention relates to a drive circuit for a liquid crystal display device or an organic EL display device, and more particularly to a partial drive circuit technology capable of continuously driving only desired gate lines.

  In recent years, TVs and mobile / smartphones using oxide semiconductors for backplane TFTs have been commercialized. An oxide semiconductor has favorable off-leakage characteristics, and can reduce power consumption by reducing the refresh rate. There are two low refresh rate (LRR) technologies as follows.

(1) Full screen LRR
In this method, the video data writing rate (refresh rate) is reduced by detecting the case where the video data of the previous screen and the screen to be displayed next are the same. This technique is effective in the case of still image display, and normally reduces from 60 Hz operation to a rate of 10 Hz or less. In this case, it is necessary to change the panel driving algorithm, but it is not necessary to change the circuit inside the panel.

(2) Partial LRR
In this method, the difference from the previous screen data is detected for each gate line, and video data is written only when the difference is detected. This is effective for images that are almost still images but need to be partially refreshed. In this case, it is necessary to change the panel driving algorithm and the circuit inside the panel (gate line driving circuit). Products equipped with partial LRR circuits are not yet on the market, and it is considered that reliable circuit technologies are being developed by each company.

  In addition, by using the LRR drive, touch detection can be performed during a time when video data is not written. As a result, it is possible to detect a smaller point (Pen destination recognition, etc.) or to detect a point where the S / N ratio has not been obtained so far, and to provide a more comfortable user interface function.

  As a conventional technique for the purpose of displaying an image only in a desired area, there is a liquid crystal display device that displays black in areas other than the display area. FIG. 8 is a block diagram showing an example of a drive circuit used in a conventional liquid crystal display device (see, for example, Patent Document 1).

  As shown in FIG. 8, the gate driver 104 is connected to each of the shift register stages S / R1 to S / R5 and the shift register stages S / R1 to S / R5 that are cascade-connected to the input line of the gate start pulse GSP. It includes a plurality of output switching units 104A to 104E connected. The plurality of shift register stages S / R1 to S / R5 receive one of the first clock CLK1 and the second clock CLK2.

  The first clock CLK1 and the second clock CLK2 are alternately input to the shift register stages S / R1 to S / R5. That is, the first clock CLK1 is input to the odd-numbered shift register stages S / R1, S / R3, and S / R5, but the second shift register stages S / R2 and S / R4 receive the second clock register CLK. The clock CLK2 is input.

  The first clock CLK1 and the second clock CLK2 have opposite phases and a frequency corresponding to ½ of the horizontal synchronization signal (that is, a period corresponding to twice). The plurality of shift register stages S / R1 to S / R5 are responsive to the first clock CLK1 or the second clock CLK2, and the gate start pulse GSP or the gate signal (Vg1) from the previous shift register stage S / R1 to S / R4. Any one of -Vg4) is latched, and gate signals Vg1-Vg5 supplied to the corresponding gate lines GL1-GL5 are generated.

  In response to the first clock CLK1, the first shift register stage S / R1 latches the gate start pulse GSP to generate the first gate signal Vg1. The first gate signal Vg1 is supplied to the first output switching unit 104A and the second shift register stage S / R2. The second shift register stage S / R2 latches the first gate signal Vg1 from the first shift register stage S / R1, which is the previous stage, by the second clock CLK2, and generates the second gate signal Vg2. The second gate signal Vg2 is supplied to the second output switching unit 104B and the third shift register stage S / R3, which is the next stage.

  The third shift register stage S / R3 responding to the first clock CLK1 also shifts the second gate signal Vg2 from the second shift register stage S / R2, which is the previous stage, to generate the third gate signal Vg3. . The third gate signal Vg3 is supplied to the third output switching unit 104C and the fourth shift register stage S / R4, which is the next stage.

  Accordingly, the remaining shift register stages S / R4 and S / R5 also respond to the first clock CLK1 or the second clock CLK2 and the third gate signal Vg3 from the previous shift register stages S / R3 and S / R4. Alternatively, the fourth gate signal Vg4 is latched and the corresponding gate signal Vg4 (or Vg5) is generated. The plurality of gate signals Vg1 to Vg5 generated from the plurality of shift register stages S / R1 to S / R5 are sequentially enabled in a specific logic (for example, high logic) state for each period of one horizontal synchronization signal.

  The plurality of output switching units 104A to 104E are electrically connected to the plurality of gate lines GL1 to GL5 on the display area of the liquid crystal panel, respectively. Further, the plurality of output switching units 104A to 104E commonly input the vertical window control signal VWS or the delayed vertical window control signal DVWS. The plurality of output switching units 104A to 104E responding in common to the vertical window control signal VWS or the delayed window control signal DVWS from the corresponding shift register stages S / R1 to S / R5 to the corresponding gate lines GL1 to GL5. The supplied gate signals Vg1 to Vg5 are switched.

  In the vertical window pulse period (base logic period) of the vertical window control signal VWS or the delayed vertical window control signal DVWS, the output switching units 104A to 104E correspond to the corresponding shift register stages S / R1 to S / R5. The corresponding gate signals Vg1 to Vg5 supplied to the gate lines GL1 to GL5 are cut off. On the other hand, in the specific logic enable period of the vertical window control signal VWS or the delayed vertical window control signal DVWS, each output switching unit 104A to 104A receives the gate from the corresponding shift register stage S / R1 to S / R5. Signals Vg1 to Vg5 are supplied to corresponding gate lines GL1 to GL5. The CLK signal is introduced only into the shift registers S / R1 to S / R5 and is not introduced into the output switching units Vg1 to Vg5.

  FIG. 9 is a circuit diagram of an output switching unit of the conventional liquid crystal display device shown in FIG. 8 and a diagram showing an example of a drive waveform. The n-th output switching unit Vgn controls whether the output Vgn of the n-th shift register S / Rn is passed or not by the vertical window control signal VWS. Here, when the vertical window control signal VWS is “H”, GLn (Vgn) is output, and when it is “L”, GLn (Vgn) is cut off.

  The transistor Tdrv in the nth shift register S / Rn drives the gate line through the transistor TGn in the nth output switching unit Vgn, and requires a large driving capability. The transistor TGn itself is also set to a large gate width in order to reduce the output resistance of the transistor Tdrv.

  The drive waveform of the vertical window control signal VWS is as follows. As shown in FIG. 9B, a case where the output to the first gate line GL1 and the second gate line GL2 and the output of the third gate line GL3 are cut off will be described. In this case, the vertical window control signal VWS maintains “H” until the second gate line GL2 becomes sufficiently “L”, and then is set to “L” before the third gate line GL3 rises.

JP 2008-003548 A

However, the prior art has the following problems.
In the conventional shift register circuit, it is necessary to sequentially operate the shift register circuit up to the Gate line address to be activated next. Therefore, partial driving cannot be performed by continuously driving only desired gate lines, and wasteful time and power consumption are required. In other words, since there is no control circuit for transferring the Carry to the next circuit to be activated, wasteful time and power consumption are required.

  The present invention has been made to solve the above-described problems, and provides a drive circuit for a display device and a display device that realize partial drive with reduced drive time and reduced power consumption. With the goal.

  A driving circuit for a display device according to the present invention is provided corresponding to a gate line of each stage, and is provided corresponding to a shift register circuit including a shift register that operates in synchronization with a clock and corresponding to the gate line of each stage. A control signal for switching whether or not to activate the gate line is stored for each gate line, and when activated, the T signal is set to “High”, and when not activated, the B signal is set to “High”. A memory unit that outputs a type output signal, and a switch unit that is provided corresponding to the gate line of each stage and that controls the drive of the gate line and the output control of the Carry signal. The switch unit of the above integer) reads the n-stage complementary output signal from the n-th memory section and the n + 1-stage complementary output signal from the (n + 1) -th memory section, and outputs the T of the n-stage complementary output signal. The signal is “High In this case, the n-th stage gate line is activated, and when the T signal of the n-stage complementary output signal is “High” and the T signal of the n + 1-stage complementary output signal is “High”, The Carry signal read from the shift register is output to the shift register at the (n + 1) th stage, and the T signal of the n-stage complementary output signal is “High” and the B signal of the n + 1-stage complementary output signal is “High”. Outputs the Carry signal read from the n-th stage shift register to the n + 1-th stage switch unit as a Skip Carry signal, the B signal of the n-stage complementary output signal is “High”, and the n + 1-stage complementary output signal When the T signal of “High” is “High”, the Skip Carry signal read from the switch unit of the (n−1) th stage is output as the Carry signal to the shift register of the (n + 1) th stage. When the B signal of the complementary output signal is “High” and the B signal of the n + 1 stage complementary output signal is “High”, the Skip Carry signal read from the switch unit of the (n−1) th stage is changed to the switch of the (n + 1) th stage. Output as a Skip Carry signal.

  According to the present invention, a drive circuit for a display device that realizes partial drive with reduced drive time and lower power consumption by providing a switch circuit configuration capable of continuously driving only desired gate lines. And a display device can be obtained.

It is explanatory drawing of the skip function in the partial GIP circuit in Embodiment 1 of this invention. It is a block diagram of the partial drive circuit with a skip function in Embodiment 1 of this invention. It is explanatory drawing which showed the switching control operation | movement by a switch part of the partial drive circuit with a skip function in Embodiment 1 of this invention (case 1). It is explanatory drawing which showed the switching control operation | movement by a switch part of the partial drive circuit with a skip function in Embodiment 1 of this invention (case 2). It is explanatory drawing which showed the switching control operation | movement by a switch part of the partial drive circuit with a skip function in Embodiment 1 of this invention (case 3). It is explanatory drawing which showed the switching control operation | movement by a switch part of the partial drive circuit with a skip function in Embodiment 1 of this invention (case 4). It is a block diagram of the memory part used with the partial drive circuit with a skip function in Embodiment 1 of this invention. It is explanatory drawing which shows the relationship between acquisition of the partial drive information in the partial drive circuit with a skip function in Embodiment 1 of this invention, and a partial drive timing. It is explanatory drawing of the partial drive by the partial drive circuit with a skip function in Embodiment 1 of this invention (when there is no skip operation | movement). It is explanatory drawing of the partial drive by the partial drive circuit with a skip function in Embodiment 1 of this invention (when there exists a skip operation | movement). It is the block diagram which showed an example of the drive circuit used for the conventional liquid crystal display device. FIG. 9 is a circuit diagram of an output switching unit of the conventional liquid crystal display device shown in FIG. 8 and a diagram illustrating an example of a drive waveform.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of a display device driving circuit and a display device according to the present invention will be described below with reference to the drawings.

  Embodiment 1 FIG.

  FIG. 1 is an explanatory diagram of a skip function in a partial GIP (Gate In Panel) circuit according to the first embodiment of the present invention. In the partial GIP circuit, the gate line is activated and video data is written only when different from the data of the previous screen. At this time, if the next gate line needs to be activated, the Carry signal is transferred to the next shift register.

  However, when the next image information is the same as the data of the previous screen (that is, in the case of a still image), it is not necessary to activate the gate line. Therefore, the partial GIP circuit according to the first embodiment shown in FIG. 1 stops sending the Carry signal to the shift register corresponding to the gate line that does not need to be activated, and shifts to the shift register that needs the Carry data. It has a function to skip and transfer.

  FIG. 2 is a block diagram of a partial drive circuit with a skip function according to the first embodiment of the present invention. The partial drive circuit with a skip function shown in FIG. 2 includes a memory unit 10, a shift register (SR) unit 20, a switch unit 30, and a driver unit 40. In FIG. 2, the portion from the (n−1) th gate line to the (n + 1) th gate line is partially described. And n-1, n, n + 1 described as subscripts in parentheses means line numbers.

  A memory unit 10, a shift register unit 20, a switch unit 30, and a driver unit 40 are provided for each gate line. Furthermore, the switch unit 30 (n) includes switch units (n−1) and (n + 1), memory units 10 (n) and (n + 1), shift register units 20 (n) and 20 (n + 1), and a driver. Connected to (n).

  The switch unit 30 (n) is controlled to be switched by a complementary output signal (High, Low) from the memory unit 10 (n). When the T signal is “High”, the gate line (n) is raised. When the B signal is “High”, the gate line (n) is not raised and the signal passes.

  Note that the switch unit 30 (n) outputs the output (Carry (n)) from the shift register unit 20 (n) when the gate line (n) is activated based on the output from the memory unit (n). Read and output to the driver unit 40 (n). On the other hand, when the switch unit 30 (n) does not start the gate line (n) based on the output from the memory unit (n), the output from the shift register unit 20 (n) (Carry (n)) Is read from the preceding switch unit 30 (n-1) (Skip Carry (x)).

Further, the switch unit 30 (n) outputs to the next stage as follows in accordance with the complementary output signals from the memory unit 10 (n) at the current stage and the memory unit 10 (n + 1) at the next stage. .
(Case 1) When the T signal of the memory unit 10 (n) is “High” and the T signal of the memory unit 10 (n + 1) is “High” (corresponding to the case where both the gate lines n and n + 1 are activated)
In this case, Carry (n) read from the shift register unit 20 (n) is output as Carry (n + 1) to the shift register unit 20 (n + 1) at the next stage.
(Case 2) When the T signal of the memory unit 10 (n) is “High” and the B signal of the memory unit 10 (n + 1) is “High” (when the gate line n is activated and the gate line n + 1 is not activated) Equivalent)
In this case, Carry (n) read from the shift register unit 20 (n) is output as Skip Carry (x + 1) to the switch unit 30 (n + 1) at the next stage.

(Case 3) When the B signal of the memory unit 10 (n) is “High” and the T signal of the memory unit 10 (n + 1) is “High” (the gate line n is not activated and the gate line n + 1 is activated) Equivalent to the case)
In this case, Skip Carry (x) read from the switch unit 30 (n−1) is output as Carry (n + 1) to the next stage shift register unit 20 (n + 1).
(Case 4) When the B signal of the memory unit 10 (n) is “High” and the B signal of the memory unit 10 (n + 1) is “High” (corresponding to the case where both the gate lines n and n + 1 are not activated)
In this case, Skip Carry (x) read from the switch unit 30 (n−1) is output as Skip Carry (x + 1) to the next stage switch unit 30 (n + 1).

  3A to 3D are explanatory diagrams showing the switching control operation by the switch unit 30 of the partial drive circuit with a skip function according to the first embodiment of the present invention. More specifically, FIGS. 4 states individually.

  3A to 3D, the shift register unit 20 is roughly divided into two. One is a shift register (corresponding to symbols SR21 (1), SR21 (2),...) That creates timing for taking in gate line activation information, and the other generates gate line drive timing. It is a shift register (corresponding to symbols SR22 (1), SR22 (2),...). The latter shift register SR22 corresponds to the shift register unit 20 shown in FIG. 2, and the former shift register SR21 is omitted in FIG.

  3A to 3D correspond to cases 1 to 4 described above, respectively. In this way, the switch unit 30 (n) can control whether to activate the gate line (n) by the driver unit 40 (n) according to the state of the memory unit 10 (n). Further, the switch unit 30 (n) outputs Carry (n + 1) to the shift register unit 20 (n + 1) as an output to the next stage according to the state of the memory units 10 (n) and 10 (n + 1). , Skip Carry (x + 1) can be switched to be output to the switch unit 30 (n + 1). As a result, it is possible to realize the switch unit 30 that can continuously drive only a desired gate line.

  Next, the internal configuration of the memory unit 10 will be described. FIG. 4 is a block diagram of the memory unit 10 used in the partial drive circuit with a skip function according to the first embodiment of the present invention. The memory unit 10 illustrated in FIG. 4 includes a data capturing unit 11, a transfer transistor 12, and a data holding / driving unit 13.

  The data capturing unit 11 captures the gate line activation signal OE, which is information as to whether or not to start up the gate line, at the timing of the vertical scanning start signal (VST) or the output signal (VSR) from the shift register SR21.

  The data fetched by the data fetching unit 11 is transferred to the data holding / driving unit 13 when the transfer transistor 12 is turned on by the transfer signal (DT). As a result, the data holding / driving unit 13 outputs the complementary output. A signal is output and the switch unit 30 is driven.

  Next, the relationship between the capture of partial drive information (OE information) and the partial drive timing will be described with reference to FIG. In the partial drive circuit with a skip function of the present invention, two vertical scanning periods are used, the gate line activation information is fetched in the first frame, the necessary gate line is started in the next frame, and video data is written. Yes.

  The transfer timing of the gate line activation information (when the DT signal is turned on) is performed during the period from the end of the first frame to the start of the second frame. In the partial drive, touch detection can be performed when the gate line is not actually activated.

  Next, a specific example of partial driving will be described. 6 and 7 are explanatory diagrams of partial drive by the partial drive circuit with skip function in Embodiment 1 of the present invention. Specifically, FIG. 6 is an operation explanatory diagram when all the gate lines 1, 2, and 3 are activated, and FIG. 7 is an example of partial driving, in which the gate lines 1 and 2 are skipped and the gate lines are skipped. FIG. 10 is an operation explanatory diagram when line 3 is activated. According to the output from the memory unit 10, the path direction by the switch unit 30 is switched, and only a desired gate line can be continuously driven.

As described above, by using the partial drive circuit with a skip function of the present invention, a desired gate line drive (partial drive) within the frame can be achieved, and has the following technical significance.
(1) Since there is no unnecessary CLK toggle, low power consumption can be expected.
(2) By skipping, unnecessary time is eliminated, time allocated for touch detection and the like can be secured, and a comfortable user interface becomes possible.

  10 memory section, 11 data reading section, 12 transfer transistor, 13 data holding / driving section, 20 shift register section, 30 switch section, 40 driver section.

Claims (4)

A shift register circuit comprising shift registers provided corresponding to the gate lines of each stage and operating in synchronization with the clock;
A control signal provided corresponding to the gate line of each stage for switching whether the gate line is activated or not is stored for each gate line, and when activated, the T signal is set to “High” and not activated A memory unit for outputting a complementary output signal in which the B signal is set to “High”;
Provided corresponding to the gate line of each stage, and provided with a switch unit that performs drive control of the gate line and output control of the Carry signal,
The switch part of the nth stage (n is an integer of 2 or more)
Read the n-stage complementary output signal from the n-th memory section and the n + 1-stage complementary output signal from the n + 1-th memory section,
When the T signal of the n-stage complementary output signal is “High”, the n-th stage gate line is activated,
When the T signal of the n-stage complementary output signal is “High” and the T signal of the n + 1-stage complementary output signal is “High”, the Carry signal read from the n-th shift register is converted into the n + 1-stage complementary output signal. Output to the shift register
When the T signal of the n-stage complementary output signal is “High” and the B signal of the n + 1-stage complementary output signal is “High”, the Carry signal read from the n-th stage shift register is changed to the n + 1-th stage output signal. Is output as a Skip Carry signal to the switch section of
When the B signal of the n-stage complementary output signal is “High” and the T signal of the n + 1-stage complementary output signal is “High”, the Skip Carry signal read from the switch unit of the (n−1) th stage is Output as a Carry signal to the n + 1 stage shift register,
When the B signal of the n-stage complementary output signal is “High” and the B signal of the n + 1-stage complementary output signal is “High”, the Skip Carry signal read from the switch unit of the (n−1) -th stage is n + 1. A driving circuit for a display device that outputs a Skip Carry signal to a switch unit at a stage. The drive circuit for a display device according to claim 1,
A drive circuit for a display device, wherein the timing at which the control signal is taken into the memory unit is one frame before the timing at which the switch unit drives the gate line corresponding to the control signal. The drive circuit for a display device according to claim 1 or 2,
The memory unit is
A data capturing unit that captures the control signal at the timing of a vertical scanning start signal (VST) or an output signal from the shift register;
A data holding / driving unit that extracts the control signal fetched by the data fetching unit according to a transfer signal and outputs the complementary output signal for driving the switch unit. .   A display device comprising the drive circuit for the display device according to claim 1.

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