JP6599100B2 - DRIVE CIRCUIT FOR DISPLAY DEVICE AND DISPLAY DEVICE - Google Patents

Description

  The present invention relates to a drive circuit for a liquid crystal display device or an organic EL display device, and more particularly to a partial drive circuit technology for a gate line.

  In recent years, TVs and mobile / smartphones using oxide semiconductors for backplane TFTs have been commercialized. An oxide semiconductor has favorable off-leakage characteristics, and can reduce power consumption by reducing the refresh rate. There are two low refresh rate (LRR) technologies as follows.

(1) Full screen LRR
In this method, the video data writing rate (refresh rate) is reduced by detecting the case where the video data of the previous screen and the screen to be displayed next are the same. This technique is effective in the case of still image display, and normally reduces from 60 Hz operation to a rate of 10 Hz or less. In this case, it is necessary to change the panel driving algorithm, but it is not necessary to change the circuit inside the panel.

(2) Partial LRR
In this method, the difference from the previous screen data is detected for each gate line, and video data is written only when the difference is detected. This is effective for images that are almost still images but need to be partially refreshed. In this case, it is necessary to change the panel driving algorithm and the circuit inside the panel (gate line driving circuit). Products equipped with partial LRR circuits are not yet on the market, and it is considered that reliable circuit technologies are being developed by each company.

  In addition, by using the LRR drive, touch detection can be performed during a time when video data is not written. As a result, it is possible to detect a smaller point (Pen destination recognition, etc.) or to detect a point where the S / N ratio has not been obtained so far, and to provide a more comfortable user interface function.

  As a conventional technique for the purpose of displaying an image only in a desired area, there is a liquid crystal display device that displays black in areas other than the display area. FIG. 23 is a block diagram showing an example of a drive circuit used in a conventional liquid crystal display device (see, for example, Patent Document 1).

  As shown in FIG. 23, the gate driver 104 is connected to each of the shift register stages S / R1 to S / R5 and the shift register stages S / R1 to S / R5 that are cascade-connected to the input line of the gate start pulse GSP. It includes a plurality of output switching units 104A to 104E connected. The plurality of shift register stages S / R1 to S / R5 receive one of the first clock CLK1 and the second clock CLK2.

  The first clock CLK1 and the second clock CLK2 are alternately input to the shift register stages S / R1 to S / R5. That is, the first clock CLK1 is input to the odd-numbered shift register stages S / R1, S / R3, and S / R5, but the second shift register stages S / R2 and S / R4 receive the second clock register CLK. The clock CLK2 is input.

  The first clock CLK1 and the second clock CLK2 have opposite phases and a frequency corresponding to ½ of the horizontal synchronization signal (that is, a period corresponding to twice). The plurality of shift register stages S / R1 to S / R5 are responsive to the first clock CLK1 or the second clock CLK2, and the gate start pulse GSP or the gate signal (Vg1) from the previous shift register stage S / R1 to S / R4. Any one of -Vg4) is latched, and gate signals Vg1-Vg5 supplied to the corresponding gate lines GL1-GL5 are generated.

  In response to the first clock CLK1, the first shift register stage S / R1 latches the gate start pulse GSP to generate the first gate signal Vg1. The first gate signal Vg1 is supplied to the first output switching unit 104A and the second shift register stage S / R2. The second shift register stage S / R2 latches the first gate signal Vg1 from the first shift register stage S / R1, which is the previous stage, by the second clock CLK2, and generates the second gate signal Vg2. The second gate signal Vg2 is supplied to the second output switching unit 104B and the third shift register stage S / R3, which is the next stage.

  The third shift register stage S / R3 responding to the first clock CLK1 also shifts the second gate signal Vg2 from the second shift register stage S / R2, which is the previous stage, to generate the third gate signal Vg3. . The third gate signal Vg3 is supplied to the third output switching unit 104C and the fourth shift register stage S / R4, which is the next stage.

  Accordingly, the remaining shift register stages S / R4 and S / R5 also respond to the first clock CLK1 or the second clock CLK2 and the third gate signal Vg3 from the previous shift register stages S / R3 and S / R4. Alternatively, the fourth gate signal Vg4 is latched and the corresponding gate signal Vg4 (or Vg5) is generated. The plurality of gate signals Vg1 to Vg5 generated from the plurality of shift register stages S / R1 to S / R5 are sequentially enabled in a specific logic (for example, high logic) state for each period of one horizontal synchronization signal.

  The plurality of output switching units 104A to 104E are electrically connected to the plurality of gate lines GL1 to GL5 on the display area of the liquid crystal panel, respectively. Further, the plurality of output switching units 104A to 104E commonly input the vertical window control signal VWS or the delayed vertical window control signal DVWS. The plurality of output switching units 104A to 104E responding in common to the vertical window control signal VWS or the delayed window control signal DVWS are transferred from the corresponding shift register stages S / R1 to S / R5 to the corresponding gate lines GL1 to GL5. The supplied gate signals Vg1 to Vg5 are switched.

  In the vertical window pulse period (base logic period) of the vertical window control signal VWS or the delayed vertical window control signal DVWS, the output switching units 104A to 104E correspond to the corresponding shift register stages S / R1 to S / R5. The corresponding gate signals Vg1 to Vg5 supplied to the gate lines GL1 to GL5 are cut off. On the other hand, in the specific logic enable period of the vertical window control signal VWS or the delayed vertical window control signal DVWS, each output switching unit 104A to 104A receives the gate from the corresponding shift register stage S / R1 to S / R5. Signals Vg1 to Vg5 are supplied to corresponding gate lines GL1 to GL5. The CLK signal is introduced only into the shift registers S / R1 to S / R5 and is not introduced into the output switching units Vg1 to Vg5.

  FIG. 24 is a circuit diagram of an output switching unit of the conventional liquid crystal display device shown in FIG. 23 and a diagram showing an example of a drive waveform. The n-th output switching unit Vgn controls whether the output Vgn of the n-th shift register S / Rn is passed or not by the vertical window control signal VWS. Here, when the vertical window control signal VWS is “H”, GLn (Vgn) is output, and when it is “L”, GLn (Vgn) is cut off.

  The transistor Tdrv in the nth shift register S / Rn drives the gate line through the transistor TGn in the nth output switching unit Vgn, and requires a large driving capability. The transistor TGn itself is also set to a large gate width in order to reduce the output resistance of the transistor Tdrv.

  The drive waveform of the vertical window control signal VWS is as follows. As shown in FIG. 24B, a case where the output to the first gate line GL1 and the second gate line GL2 and the output of the third gate line GL3 are cut off will be described. In this case, the vertical window control signal VWS maintains “H” until the second gate line GL2 becomes sufficiently “L”, and then is set to “L” before the third gate line GL3 rises.

JP 2008-003548 A

However, the prior art has the following problems.
In order to cut off the output on the desired gate line, it is necessary to switch the vertical window control signal VWS accurately at the timing as shown in FIG. 24B, and the margin of the switching timing is small. .

  Further, the vertical window control signal VWS is connected to the gates of the transistors TG of all the output switching units Vg1 to Vgn, and the load is large, and there is a critical aspect in timing control. Furthermore, such a configuration results in corresponding power consumption.

  In addition, the conventional liquid crystal display device as shown in Patent Document 1 is intended for area display, and “black display” is provided except for the display portion. However, in applications where moving images and still images are displayed within one screen, video data is written only to pixels whose display data is different from the previous screen.

  However, in the conventional driving circuit, the output Vgn of the shift register S / Rn is synchronized with the waveforms of CLK1 and CLK2, and in order to cut off one gate line, it is vertical before Vgn becomes “H”. The window control signal VWS is set to “L”, and VWS needs to be set to “H” before the next Vgn becomes “H”. Therefore, in applications where the moving image portion is partially rewritten, in the conventional drive circuit, the drive timing of the vertical window control signal VWS is severe, and there is a possibility of pixel data destruction due to malfunction of the gate line.

  Furthermore, when the number of gate lines is increased to increase the definition, an increase in load and a decrease in the H period may occur, and the operation margin may be reduced. Further, in the conventional driving circuit as shown in FIG. 24, the load of the output TFT (Tdrv) is heavy, and it is difficult to increase the speed. Therefore, it is unsuitable for dealing with high-speed partial driving that partially rewrites the moving image portion.

  Also, in order to maintain the same driving capability as before, the gate width of the driving TFT is four times that of the conventional one (ie, the size of the shift register TFT is doubled and the size of the output switching TFT is doubled). There is a need to. As a result, the frame portion of the liquid crystal display device may become large.

Regarding the conventional drive circuit, the problems when performing partial drive are summarized as follows.
(Problem 1) There is no timing margin between drive signals (Problem 2) The load of the output of the shift register circuit is large and high-speed operation is impossible (Problem 3) Two gate lines for the shift register and the output switching unit Since there are driving transistors, and they are connected in series, the gate width (GW) of the transistors needs to be doubled.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a display circuit driving circuit and a display device for realizing a partial drive capable of stable operation without causing a malfunction.

  A driving circuit for a display device according to the present invention includes a shift register circuit including a plurality of stages of shift registers that operate in synchronization with a clock, and a driver unit that drives a plurality of gate lines in synchronization with the clock. The driver circuit further includes an AND circuit that outputs a logical product of the output signal of the previous shift register and a control signal for switching whether or not to raise the gate line as a logical output, and the driver unit uses the output from the AND circuit. The gate line is driven.

  According to the present invention, the shift register unit and the driver unit of the gate line are separated, and the driver unit is activated when both the output of the shift register unit and the output control signal of the gate line are “H”. Is provided to both the shift register unit and the driver unit, it is possible to obtain a display device driving circuit and a display device that realize partial driving capable of stable operation without causing malfunction.

It is explanatory drawing for solving the problem with few timing margins in the prior art. It is a block diagram of the partial GIP circuit in Embodiment 1 of this invention. It is the figure which showed the drive waveform by the partial GIP circuit shown in FIG. 2 in Embodiment 1 of this invention. 1 is an overall configuration diagram of a partial GIP circuit according to a first embodiment of the present invention. 3 is a block diagram of a driver unit in Embodiment 1. FIG. FIG. 6 is a diagram illustrating an example of a Logic circuit in FIG. 5. FIG. 10 is a block diagram of a driver unit in Embodiment 2. FIG. 8 is a diagram illustrating an example of a Logic circuit in FIG. 7. FIG. 10 is a block diagram of a driver unit in Embodiment 3. FIG. 10 is a block diagram of a driver unit according to a fourth embodiment. FIG. 10 is a block diagram of a driver unit according to a fifth embodiment. FIG. 10 is a block diagram of a driver unit according to a sixth embodiment. It is a whole block diagram of the partial GIP circuit in Embodiment 2 of this invention. It is the figure which showed the drive waveform by the partial GIP circuit shown in FIG. 13 in Embodiment 2 of this invention. FIG. 10 is a block diagram of a driver unit according to a seventh embodiment. FIG. 16 is a diagram illustrating an example of a Logic circuit in FIG. 15. FIG. 10 is a block diagram of a driver unit in an eighth embodiment. It is the figure which showed an example of the Logic circuit in FIG. FIG. 20 is a block diagram of a driver unit according to a ninth embodiment. FIG. 20 is a block diagram of a driver unit in Example 10. FIG. 20 is a block diagram of a driver unit in Example 11. FIG. 20 is a block diagram of a driver unit in Example 12. It is the block diagram which showed an example of the drive circuit used for the conventional liquid crystal display device. FIG. 24 is a circuit diagram of an output switching unit of the conventional liquid crystal display device shown in FIG. 23 and a diagram showing an example of a drive waveform.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of a display device driving circuit and a display device according to the present invention will be described below with reference to the drawings.

Embodiment 1 FIG.
FIG. 1 is an explanatory diagram for solving the problem that the timing margin is small in the prior art. FIG. 1A shows timings of two CLKs, a vertical window control signal VWS, and GL1 to GL3, and FIG. 1B is an enlarged view for explaining the operation allowable timing. It is shown.

  By changing the vertical window control signal VWS starting from the toggle of CLK, the gate line GL2 is pulled down and the rise of the gate line GL3 is blocked. Here, the permissible timing for normal operation is the period A shown in FIG. In order to increase the allowable timing A, it is effective to change the drive starting point from time t1 to time t2 shown in FIG. If the timing start point can be advanced from the time t1 to the time t2, the permissible timing can be obtained by the amount B shown in FIG. Therefore, a specific circuit for realizing such an increase in allowable timing will be described next.

  FIG. 2 is a block diagram of a partial GIP (Gate In Panel) circuit according to the first embodiment of the present invention. The partial GIP circuit shown in FIG. 2 includes a shift register unit 10, an AND circuit 20, and a driver unit 30, and shows a circuit portion related to two gate lines GL1 and GL2.

  The output VSR 1 and 2 (or VST) of the shift register unit 10 and the logical output DE (Driver Enable) by the AND circuit 20 of the output control signal OE are applied to the driver unit 30.

  FIG. 3 is a diagram showing a driving waveform by the partial GIP circuit shown in FIG. 2 in the first embodiment of the present invention. By setting the output control signal OE to “H” during the period when VSR1 is “H”, DE2 becomes “H”, the driver unit 30 (2) is activated, and the gate line GL2 is activated.

The “H” period of the output control signal OE is the shortest period (Tss) during which the DE node is charged to “H”, and the longest period is the “H” period (T) of the VSR. At this time, the timing margin Tm can be expressed by the following equation.
Tm = T-Tss
As a result, a longer (larger) period than the allowable timing A shown in FIG. 1B can be prepared as a timing margin.

  FIG. 4 is an overall configuration diagram of the partial GIP circuit according to the first embodiment of the present invention, and shows an overall diagram in which the previous FIG. 2 showing only two lines is expanded to n lines. The characteristics of the partial GIP circuit according to the first embodiment are summarized as follows.

(Feature 1) The shift register section and the gate line driver section are separated.
As a result, the shift register unit always operates according to CLK1 and CLK2, and the gate line to be activated can be specified by always operating. On the other hand, by separating, the load of VSR and OE can be reduced, and the overall layout size can be reduced.

(Characteristic 2) When both the output (VSR) of the preceding shift register unit and the output control signal OE of the gate line are “H”, DE becomes “H” and activates the driver unit.
As a result, for example, when the gate line GL3 is activated, OE can be set to “H” in advance at the timing when VSR2 is output (the gate line GL2 rises).

(Characteristic 3) CLK1 and CLK2 are clocks having the same period and opposite phases, and are input to both the shift register unit and the driver unit.
As a result, the clock plays the role of the operation reference CLK in the shift register section, and plays the role of the gate line drive according to the DE signal in the driver section.

  Note that CLK may be any one that can drive the shift register unit, and may be three-phase or four-phase. Further, in this embodiment, the partial GIP circuit is set only on one side of the display unit, but driving from both sides is also possible. Furthermore, the circuit configuration of the shift register unit / driver unit is an example, and any circuit configuration may be used.

  As described above, according to the first embodiment, by using the partial GIP circuit having the above-described features 1 to 3, the margin for the switching operation of the gate line can be made larger than the conventional one. As a result, it is possible to realize a driving circuit for a display device that realizes partial driving capable of stable operation without causing malfunction.

More specifically, the following effects are provided for enabling desired gate line driving (partial driving).
(Effect 1) The output of the logical product of the output (VSR) of the shift register unit and the output control signal (OE) is applied to one gate by a circuit configuration that directly or indirectly activates the gate of the gate line driving transistor. Line drive is now possible.

(Effect 2) By setting the output control signal (OE) to “H” during the output (VSR) period of the shift register section, one gate line can be driven, the control timing margin can be increased, and malfunction can be prevented. It became possible.
(Effect 3) Since only pixels that have changed from the previous screen are refreshed, low power consumption can be expected.
(Effect 4) Since the partial drive of the gate line is possible, the time for touch detection is increased, the touch sensitivity is improved, and a comfortable user interface can be provided.

  Next, the specific configuration of the driver unit in the partial GIP circuit of the invention according to the first embodiment will be specifically described as Example 1 to Example 6 with reference to the drawings.

[Example 1]
FIG. 5 is a block diagram of the driver unit in the first embodiment, and FIG. 6 is a diagram illustrating an example of the Logic circuit in FIG.
The gate line driving circuit shown in FIG. 5 has the following configuration.
An AND logic circuit of the output signal (VSR) and output control signal (OE) of the shift register unit. A logic circuit that receives the output of the AND logic circuit and outputs a control signal to the gates of the transistors Tdh and Tdl that drive the gate lines. A drive transistor (Tdh) in which the CLK signal is input to the drain, the gate line is connected to the source output, and the output from the logic circuit is connected to the gate electrode
A drive transistor (Tdl) in which the gate line is connected to the drain, the Vss potential is connected to the source, and the output from the logic circuit is connected to the gate electrode

[Example 2]
FIG. 7 is a block diagram of the driver unit in the second embodiment, and FIG. 8 is a diagram illustrating an example of the Logic circuit in FIG.
The gate line driving circuit shown in FIG. 7 has the following configuration.
-AND logic circuit of output signal (VSR) and output control signal (OE) of shift register unit-AND logic output (DE) is input to gate, CLK signal is input to drain, and gate line is connected to source output Drive transistor (Tdh)
A drive transistor (Tdl) in which the gate line is connected to the drain, the Vss potential is connected to the source, and the output from the logic circuit is connected to the gate electrode
-Logic circuit connected to the gates of two drive transistors

[Example 3]
FIG. 9 is a block diagram of the driver unit in the third embodiment.
The gate line driving circuit shown in FIG. 9 has the following configuration.
A transistor (Tvsr) in which the output signal (VSR) of the shift register unit is input to the gate
-Transistor (Toe) whose output control signal (OE) is input to the gate
An AND logic circuit composed of a circuit in which the drain of Toe is connected to VDD, the source of Tvsr is connected to DE, and the other terminals of Toe and Tvsr are connected to each other. Logic output (DE) of the AND logic circuit. Is input to the gate, the CLK signal is input to the drain, and the gate transistor is connected to the source output (Tdh)
A drive transistor (Tdl) in which the gate line is connected to the drain, the source is connected to the Vss potential, and the output from the logic circuit is connected to the gate electrode
-Logic circuit connected to the gates of two drive transistors

[Example 4]
FIG. 10 is a block diagram of a driver unit according to the fourth embodiment.
The gate line driving circuit shown in FIG. 10 has the following configuration.
-The output logic signal (OE) is input to the gate, the output signal (VSR) of the shift register unit is input to the drain, and the AND logic is configured by one transistor whose source is connected to the gate of the drive transistor (Tdh). The drive transistor (Tdh) whose logic output (DE) is input to the gate, the CLK signal is input to the drain, and the gate line is connected to the source output
A drive transistor (Tdl) in which the gate line is connected to the drain, the source is connected to the Vss potential, and the output from the logic circuit is connected to the gate electrode
-Logic circuit connected to the gates of two drive transistors

[Example 5]
FIG. 11 is a block diagram of a driver unit according to the fifth embodiment.
The gate line driving circuit shown in FIG. 11 has the following configuration.
The output signal (VSR) of the shift register is input to the gate, the output control signal (OE) is input to the drain, and one transistor gate with the source connected to the transistor (Ts) is either the drain or the source Connected transistor (Ts)
Either the drain or source of Ts is input to the gate of the gate line drive transistor (Tdh), the CLK signal is input to the drain, and the drive transistor (Tdh) is connected to the gate line of the source output.
A drive transistor (Tdl) in which the gate line is connected to the drain, the source is connected to the Vss potential, and the output from the logic circuit is connected to the gate electrode
-Logic circuit connected to the gates of two drive transistors

[Example 6]
FIG. 12 is a block diagram of a driver unit according to the sixth embodiment.
The gate line driving circuit shown in FIG. 12 has the following configuration.
A transistor (Ts) that is connected to the gate and one of its drain and source and to which the output control signal (OE) is input to the drain, and the output signal (VSR) of the shift register unit is input to the gate, and the drain is Ts The AND logic circuit / DE signal consisting of one transistor whose source is the DE signal is input to the gate of the gate line drive transistor (Tdh), the CLK signal is input to the drain, and the gate is connected to the source output. Drive transistor (Tdh) connected to a line
A drive transistor (Tdl) in which the gate line is connected to the drain, the source is connected to the Vss potential, and the output from the logic circuit is connected to the gate electrode
-Logic circuit connected to the gates of two drive transistors

Embodiment 2. FIG.
In the second embodiment, a circuit configuration that realizes partial driving with higher speed using the 8-phase clocks CLK1 to CLK8 will be described.

  FIG. 13 is an overall configuration diagram of a partial GIP circuit according to the second embodiment of the present invention. The partial GIP circuit shown in FIG. 13 includes a shift register unit 10, an AND circuit 20, and a driver unit 30, and particularly shows circuit portions related to the gate lines GL1, GL3, GL5, GL7, and GL9. Yes.

  Note that FIG. 13 shows a circuit for driving the GIP disposed on one side of the display panel, which is driven using four clocks CLK1, CLK3, CLK5, and CLK7. Although not shown, the circuit for driving the GIP disposed on the other side of the display panel is driven using the remaining four clocks CLK2, CLK4, CLK6, and CLK8.

  The characteristics of the partial GIP circuit according to the second embodiment having the configuration shown in FIG. 13 are summarized as follows.

(Feature 1) The shift register section and the gate line driver section are separated.
As a result, the shift register unit always operates according to CLK1, 3, 5, and 7, and the gate line to be activated can be specified by always operating. On the other hand, by separating, the load of VSR and OE can be reduced, and the overall layout size can be reduced.

(Feature 2) When both the output (VSR) of the previous shift register unit and the output control signal OE of the gate line are “H”, DE becomes “H” and the driver unit is activated. Yes.
As a result, for example, when the gate line GL5 is activated, OE can be set to “H” in advance at the timing when VSR1 is output (the gate line GL1 rises).

(Characteristic 3) CLK1, 3, 5, and 7 are clocks having the same period and shifted phases, and are input to both the shift register unit and the driver unit.
As a result, the clock plays the role of the operation reference CLK in the shift register section, and plays the role of the gate line drive according to the DE signal in the driver section.

  FIG. 14 is a diagram showing a drive waveform by the partial GIP circuit shown in FIG. 13 in the second embodiment of the present invention, and shows waveforms of respective parts when OE is always set to “H”. Qi indicates a node of the shift register unit 10.

  The operation of the gate line GL5 will be described below using the circuit configuration of FIG. 13 and the drive waveform of FIG. 14 as an example. At the timing when CLK1 switches to “H”, the Q5 node of the shift register unit 10 (5) becomes “H”. Here, since OE is always “H”, the Q5 node becomes “H”, and at the same time, the Q node of the driver unit 30 (5) also becomes “H”, and at the same time as the activation of CLK5, the gate line GL5 becomes “H”. H "is output. The Q5 node drops to VSS at the timing when VSR9 becomes “H”.

  The timing at which the gate line output control signal OE is input is a period in which VSR1 is “H”. The pulse width of the OE may be a period in which the Q node of the driver unit 30 can be “H” and the QB node can be “L”.

Further, when the AND logic of the OE signal and the VSR signal is performed in the driver unit 30, a comparison between the first embodiment and the second embodiment is as follows.
In the case of the first embodiment using a four-phase clock In the case of four phases (one-sided two-phase or one-sided positive / negative phase), it is set with the VSR signal at the previous stage and reset with the VSR signal at the subsequent stage To do.
In the case of the second embodiment using an 8-phase clock In the case of 8 phases (4 phases on one side), it is set by the VSR signal before the second stage and reset by the VSR signal after the second stage.

  Note that CLK may be anything that can drive the shift register unit, and may be multiphase driving. Therefore, the AND logic of the OE signal and the VSR signal may set the VSR output that matches the timing. Furthermore, the circuit configuration of the shift register unit / driver unit is an example, and any circuit configuration may be used.

  As described above, according to the second embodiment, by using the partial GIP circuit having the above-described features 1 to 3, the margin for performing the switching operation of the gate line can be made larger than the conventional one. As a result, it is possible to realize a driving circuit for a display device that realizes partial driving capable of stable operation without causing malfunction.

More specifically, as in the first embodiment, there are the following effects for enabling desired gate line driving (partial driving).
(Effect 1) The output of the logical product of the output (VSR) of the shift register unit and the output control signal (OE) is applied to one gate by a circuit configuration that directly or indirectly activates the gate of the gate line driving transistor. Line drive is now possible.

(Effect 2) By setting the output control signal (OE) to “H” during the output (VSR) period of the shift register section, one gate line can be driven, the control timing margin can be increased, and malfunction can be prevented. It became possible.
(Effect 3) Since only pixels that have changed from the previous screen are refreshed, low power consumption can be expected.
(Effect 4) Since the partial drive of the gate line is possible, the time for touch detection is increased, the touch sensitivity is improved, and a comfortable user interface can be provided.

  Next, a specific configuration of the driver unit in the partial GIP circuit according to the second embodiment will be specifically described as Example 7 to Example 12 with reference to the drawings.

[Example 7]
FIG. 15 is a block diagram of the driver unit in the seventh embodiment, and FIG. 16 is a diagram illustrating an example of the Logic circuit in FIG.
The gate line driving circuit shown in FIG. 15 has the following configuration.
An AND logic circuit of the output signal (VSR_i-1 or VSR_i-2) of the shift register unit and the output control signal (OE), an output of the AND logic circuit and an output signal (VSR_i + 1 or VSR_i + 2) of the shift register unit, and a gate A logic circuit that outputs a control signal to the gates of the transistors Tdh and Tdl that drive the line. A CLK signal is input to the drain, a gate line is connected to the source output, and a drive transistor (Tdh that is connected to the output from the logic circuit is connected to the gate electrode). )
A drive transistor (Tdl) in which the gate line is connected to the drain, the Vss potential is connected to the source, and the output from the logic circuit is connected to the gate electrode

[Example 8]
FIG. 17 is a block diagram of the driver unit in the eighth embodiment, and FIG. 18 is a diagram illustrating an example of the Logic circuit in FIG.
The gate line driving circuit shown in FIG. 17 has the following configuration.
An AND logic circuit of the output signal (VSR_i-1 or VSR_i-2) of the shift register unit and the output control signal (OE). An AND logic output (DE) is input to the gate, and a CLK signal is input to the drain. Driving transistor (Tdh) with gate line connected to output
A drive transistor (Tdl) in which the gate line is connected to the drain, the Vss potential is connected to the source, and the output from the logic circuit is connected to the gate electrode
A logic circuit that receives the output signal (VSR_i + 1 or VSR_i + 2) of the shift register unit and is connected to the gates of two drive transistors

[Example 9]
FIG. 19 is a block diagram of a driver unit according to the ninth embodiment.
The gate line driving circuit shown in FIG. 19 has the following configuration.
A transistor (Tvsr) in which the output signal (VSR) of the shift register unit is input to the gate
-Transistor (Toe) whose output control signal (OE) is input to the gate
An AND logic circuit composed of a circuit in which the drain of Toe is connected to VDD, the source of Tvsr is connected to DE, and the other terminals of Toe and Tvsr are connected to each other. Logic output (DE) of the AND logic circuit. Is input to the gate, the CLK signal is input to the drain, and the gate transistor is connected to the source output (Tdh)
A drive transistor (Tdl) in which the gate line is connected to the drain, the source is connected to the Vss potential, and the output from the logic circuit is connected to the gate electrode
A logic circuit that receives the output signal (VSR) of the shift register and is connected to the gates of the two drive transistors

[Example 10]
FIG. 20 is a block diagram of a driver unit according to the tenth embodiment.
The gate line driving circuit shown in FIG. 20 has the following configuration.
-The output logic signal (OE) is input to the gate, the output signal (VSR) of the shift register unit is input to the drain, and the AND logic is configured by one transistor whose source is connected to the gate of the drive transistor (Tdh). The drive transistor (Tdh) whose logic output (DE) is input to the gate, the CLK signal is input to the drain, and the gate line is connected to the source output
A drive transistor (Tdl) in which the gate line is connected to the drain, the source is connected to the Vss potential, and the output from the logic circuit is connected to the gate electrode
A logic circuit that receives the output signal (VSR) of the shift register and is connected to the gates of the two drive transistors

[Example 11]
FIG. 21 is a block diagram of the driver unit in the eleventh embodiment.
The gate line driving circuit shown in FIG. 21 has the following configuration.
The output signal (VSR) of the shift register is input to the gate, the output control signal (OE) is input to the drain, and one transistor gate with the source connected to the transistor (Ts) is either the drain or the source Connected transistor (Ts)
Either the drain or source of Ts is input to the gate of the gate line drive transistor (Tdh), the CLK signal is input to the drain, and the drive transistor (Tdh) is connected to the gate line of the source output.
A drive transistor (Tdl) in which the gate line is connected to the drain, the source is connected to the Vss potential, and the output from the logic circuit is connected to the gate electrode
A logic circuit that receives the output signal (VSR) of the shift register and is connected to the gates of the two drive transistors

[Example 12]
FIG. 22 is a block diagram of a driver unit according to the twelfth embodiment.
The gate line driving circuit shown in FIG. 22 has the following configuration.
A transistor (Ts) that is connected to the gate and one of its drain and source and to which the output control signal (OE) is input to the drain, and the output signal (VSR) of the shift register unit is input to the gate, and the drain is Ts The AND logic circuit / DE signal consisting of one transistor whose source is the DE signal is input to the gate of the gate line drive transistor (Tdh), the CLK signal is input to the drain, and the gate is connected to the source output. Drive transistor (Tdh) connected to a line
A drive transistor (Tdl) in which the gate line is connected to the drain, the source is connected to the Vss potential, and the output from the logic circuit is connected to the gate electrode
A logic circuit that receives the output signal (VSR) of the shift register and is connected to the gates of the two drive transistors

  10 shift register section, 20 AND circuit, 30 driver section.

Claims (12)

A shift register circuit composed of a plurality of shift registers operating in synchronization with the input clock;
A plurality of stages of driver units separated from the shift register circuit , each corresponding to the plurality of stages of shift registers and driving a plurality of gate lines in synchronization with the input clock; With
A AND circuit of the connected plurality of stages between the driver portion of the shift register and the plurality of stages of said plurality of stages, as the AND circuits in each stage receives the output signal from the preceding stage of the shift register Connected to the previous stage shift register and connected to the same stage driver so as to send the output signal from the AND circuit of each stage, the output signal of the previous stage shift register and the gate line in response to input of a control signal for switching whether launching, and outputs the logical product as a logic output, further comprising an aND circuit in a plurality of stages,
The driver unit receives an output signal from the AND circuit, and generates and outputs a signal for driving the gate line using the output signal . A drive circuit for a display device according to claim 1,
In the AND circuit, the timing for inputting the control signal is one stage before a desired gate line driving time. A shift register circuit comprising a plurality of shift registers operating in synchronization with any of the four input clocks having the same period and different phases;
A plurality of stages of driver units separated from the shift register circuit , each of which corresponds to the plurality of stages of shift registers, and which has a plurality of stages for driving a plurality of gate lines in synchronization with any of the inputted clocks. With a driver and
A AND circuit of the connected plurality of stages between the driver portion of the shift register and the plurality of stages of said plurality of stages, as the AND circuits in each stage receives the output signals from the 2-stage preceding the shift register Connected to the two-stage previous shift register and connected to the same stage driver so as to send the output signal from the AND circuit of each stage, the output signal of the two-stage previous shift register and the gate line in response to input of a control signal for switching whether launching, and outputs the logical product as a logic output, further comprising an aND circuit in a plurality of stages,
The driver unit receives an output signal from the AND circuit and generates and outputs a signal for driving the gate line using the output signal . A drive circuit for a display device according to claim 3,
In the AND circuit, the timing for inputting the control signal is two stages before a desired gate line driving time. A drive circuit for a display device according to any one of claims 1 to 4,
The AND circuit includes at least one transistor that outputs a logical product of the output signal of the shift register circuit and the control signal as the logical output.
The driver part is
A first driving transistor for driving the gate line to “H”;
A second drive transistor for driving the gate line to “L”;
A control circuit that receives the logic output from the AND circuit and outputs a signal for controlling gate potentials of the first drive transistor and the second drive transistor;
A driving circuit for a display device comprising: A drive circuit for a display device according to any one of claims 1 to 4,
The AND circuit includes at least one transistor that outputs a logical product of the output signal of the shift register circuit and the control signal as the logical output.
The driver part is
A first drive transistor that inputs the logic output from the AND circuit as a gate potential and drives the gate line to “H”;
A second drive transistor for driving the gate line to “L”;
A drive circuit for a display device, comprising: a control circuit that receives the logic output from the AND circuit and outputs a signal for controlling a gate potential of the second drive transistor. A drive circuit for a display device according to any one of claims 1 to 4,
The AND circuit is
A first transistor having the control signal input to a gate;
A second transistor in which an output signal of the shift register is input to a gate;
And a logic circuit in which the drain of the first transistor is connected to VDD, the source of the second transistor is the logic output, and the source of the first transistor and the drain of the second transistor are connected to each other. Configured as a circuit,
The driver part is
A first driving transistor in which the logic output is input to a gate, a clock signal is input to a drain, and a gate line is connected to a source output;
A second drive transistor having a gate line connected to the drain, a Vss potential connected to the source, and an output from the control circuit connected to the gate electrode;
A drive circuit for a display device, comprising: a control circuit that receives the logic output from the AND circuit and outputs a signal for controlling a gate potential of the second drive transistor. A drive circuit for a display device according to any one of claims 1 to 4,
In the AND circuit, the control signal is input to the gate, the output signal of the shift register circuit is input to the drain, and the AND logic is configured by one transistor whose source is the logic output.
The driver part is
A first driving transistor in which the logic output from the AND circuit is input to a gate, a clock signal is input to a drain, and a gate line is connected to a source output;
A second drive transistor having a gate line connected to the drain, a Vss potential connected to the source, and an output from the control circuit connected to the gate electrode;
A drive circuit for a display device, comprising: a control circuit that receives the logic output from the AND circuit and outputs a signal for controlling a gate potential of the second drive transistor. A drive circuit for a display device according to any one of claims 1 to 4,
The AND circuit is
An output signal of the shift register is input to a gate and the control signal is input to a drain;
The source of the one transistor is connected to the drain, the source becomes the logic output,
It consists of a transistor whose gate is connected to either the drain or the source,
The driver part is
A first driving transistor in which the logic output from the AND circuit is connected to a gate, a clock signal is input to a drain, and a gate line is connected to a source output;
A second drive transistor having a gate line connected to the drain, a Vss potential connected to the source, and an output from the control circuit connected to the gate electrode;
A drive circuit for a display device, comprising: a control circuit that receives the logic output from the AND circuit and outputs a signal for controlling a gate potential of the second drive transistor. A drive circuit for a display device according to any one of claims 1 to 4,
The AND circuit is
A transistor whose gate is connected to either the drain or the source, and the control signal is input to the drain;
The output signal of the shift register is input to the gate, the drain is connected to the source of the transistor, and the source is composed of an AND logic circuit including one transistor that is the logic output,
The driver part is
A first driving transistor in which the logic output from the AND circuit is input to a gate, a clock signal is input to a drain, and a gate line is connected to a source output;
A second drive transistor in which a gate line is connected to the drain, a source is connected to the Vss potential, and an output from the control circuit is connected to the gate electrode;
A drive circuit for a display device, comprising: a control circuit that receives the logic output from the AND circuit and outputs a signal for controlling a gate potential of the second drive transistor. A drive circuit for a display device according to any one of claims 5 to 10,
The first drive transistor is a drive circuit for a display device in which a clock signal is input to a drain.   A display device comprising the drive circuit for the display device according to claim 1.

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