JP2015111646A - Multilayer wiring board connection structure - Google Patents

Multilayer wiring board connection structure Download PDF

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JP2015111646A
JP2015111646A JP2014041808A JP2014041808A JP2015111646A JP 2015111646 A JP2015111646 A JP 2015111646A JP 2014041808 A JP2014041808 A JP 2014041808A JP 2014041808 A JP2014041808 A JP 2014041808A JP 2015111646 A JP2015111646 A JP 2015111646A
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signal conductor
bvh
connection structure
conductor pattern
multilayer wiring
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JP6422222B2 (en
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素実 渡辺
Motomi Watanabe
素実 渡辺
大和田 哲
Satoru Owada
哲 大和田
一彦 菊井
Kazuhiko Kikui
一彦 菊井
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Mitsubishi Electric Corp
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Abstract

PROBLEM TO BE SOLVED: To shorten the current path length by enabling visual confirmation of a connection state of a master substrate and a slave substrate.SOLUTION: A multilayer wiring board connection structure includes: a master slave 1 which is made of a dielectric substrate and in which a signal conductor pattern 11 is wired on the upper surface; a slave substrate 2 which is made of a multilayer dielectric substrate and in which a signal conductor pattern 21 is wired in the inner layer; and a half-cut BVH24 which is provided from the outer layer on the surface side opposite to the master substrate 1 of the slave substrate 2 and electrically connects the signal conductor patterns 11, 21; and a connection structure 4 which connects the slave substrate 2 with the master slave 1 at the surface opposite thereto.

Description

この発明は、マイクロ波回路などに用いられる多層配線基板の接続構造に関するものである。   The present invention relates to a connection structure for multilayer wiring boards used in microwave circuits and the like.

従来、親基板上面に配線された信号導体パターンと、子基板上面に配線された信号導体パターンとを電気的に接続する多層配線基板の接続構造において、半割りスルーホールを用いた構成が知られている(例えば特許文献1参照)。ここで、半割りスルーホールとは、子基板端面に設けられ、上下の外層を貫通する穴の壁を導体で覆い当該子基板の信号導体パターンと電気的に接続されたスルーホールを半割りにしたものである。そして、この半割りスルーホールを用いて半田により親基板の信号導体パターンと電気的に接続することで、多層配線基板の接続を行っている。   Conventionally, in a multi-layer wiring board connection structure that electrically connects a signal conductor pattern wired on the upper surface of the parent board and a signal conductor pattern wired on the upper surface of the child board, a configuration using a half through hole is known. (For example, refer to Patent Document 1). Here, the half through hole is provided on the end face of the sub board, covers the wall of the hole passing through the upper and lower outer layers with a conductor, and divides the through hole electrically connected to the signal conductor pattern of the sub board. It is a thing. Then, the multi-layered wiring board is connected by electrically connecting to the signal conductor pattern of the parent board by solder using the half through hole.

特開平9−8167号公報Japanese Patent Laid-Open No. 9-8167

しかしながら、特許文献1に開示されるような従来の多層配線基板接続構造では、子基板に配線された信号導体パターンが多層基板の内層に構成されている場合に、問題が生じる。すなわち、この場合、子基板の内層に配線された信号導体パターンと、子基板の上面に配線され半割りスルーホールが電気的に接続された信号導体パターンとを電気的に接続するために、内層間で貫通した穴の壁を導体で覆ったBVH(Blind via hole)により電気的に接続する必要があり、電流経路長が長くなる。その結果、損失が大きくなるという課題がある。   However, the conventional multilayer wiring board connection structure as disclosed in Patent Document 1 has a problem when the signal conductor pattern wired to the sub board is configured in the inner layer of the multilayer board. That is, in this case, in order to electrically connect the signal conductor pattern wired on the inner layer of the daughter board and the signal conductor pattern wired on the upper surface of the daughter board and electrically connected to the half through-holes, It is necessary to make an electrical connection by BVH (Blind Via Hole) in which the wall of the hole penetrating between layers is covered with a conductor, and the current path length becomes long. As a result, there is a problem that loss increases.

また、上記電流経路長が長くなることで、半割スルーホールによる寄生インダクタンスが大きくなり、親基板及び子基板の信号導体パターンの不整合が発生し、反射損失が劣化するという課題がある。さらに、半割スルーホールからの放射損失が大きくなるという課題もある。   Further, since the current path length is increased, the parasitic inductance due to the half through hole is increased, the signal conductor patterns of the parent substrate and the child substrate are mismatched, and the reflection loss is deteriorated. Further, there is a problem that radiation loss from the half through hole becomes large.

この発明は、上記のような課題を解決するためになされたもので、親基板及び子基板の接続状態の目視確認を可能とし、かつ、電流経路長を短縮することができる多層配線基板構造を提供することを目的としている。   The present invention has been made in order to solve the above-described problems, and provides a multilayer wiring board structure that enables visual confirmation of the connection state of the parent board and the child board and that can shorten the current path length. It is intended to provide.

この発明に係る多層配線基板接続構造は、誘電体基板からなり、上面に第1の信号導体パターンが配線された親基板と、多層誘電体基板からなり、内層に第2の信号導体パターンが配線された子基板と、子基板の親基板との対向面側の外層から内層にかけて設けられ、第1,2の信号導体パターンを電気的に接続する半割りされたBVHと、親基板及び子基板を対向面で接続する接続構造とを備えたものである。   The multi-layer wiring board connection structure according to the present invention is composed of a dielectric substrate, a parent substrate having a first signal conductor pattern wired on the upper surface, and a multilayer dielectric substrate, and a second signal conductor pattern is wired on the inner layer. A half-divided BVH that is provided from the outer layer to the inner layer on the opposite surface side of the sub-board and the sub-board of the sub-board and electrically connects the first and second signal conductor patterns, and the main board and the sub-board Are connected to each other on the opposite surface.

この発明によれば、上記のように構成したので、親基板及び子基板の接続状態の目視確認を可能とし、かつ、電流経路長を短縮することができる。   According to this invention, since it comprised as mentioned above, the visual confirmation of the connection state of a parent board | substrate and a child board | substrate is attained, and a current path length can be shortened.

この発明の実施の形態1に係る多層配線基板接続構造の構成を示す図であり、(a)側面透視図であり、(b)斜視透視図である。BRIEF DESCRIPTION OF THE DRAWINGS It is a figure which shows the structure of the multilayer wiring board connection structure concerning Embodiment 1 of this invention, (a) Side perspective drawing, (b) Perspective perspective drawing. この発明の実施の形態2に係る多層配線基板接続構造の構成を示す図であり、(a)側面透視図であり、(b)斜視透視図である。It is a figure which shows the structure of the multilayer wiring board connection structure concerning Embodiment 2 of this invention, (a) It is a side perspective view, (b) It is a perspective perspective view. この発明の実施の形態3に係る多層配線基板接続構造の構成を示す図であり、(a)側面透視図であり、(b)斜視透視図である。It is a figure which shows the structure of the multilayer wiring board connection structure concerning Embodiment 3 of this invention, (a) Side perspective drawing, (b) Perspective perspective drawing. この発明の実施の形態3に係る多層配線基板接続構造の信号導体パターンを示す上面図である。It is a top view which shows the signal conductor pattern of the multilayer wiring board connection structure concerning Embodiment 3 of this invention. この発明の実施の形態4に係る多層配線基板接続構造の構成を示す図であり、(a)側面透視図であり、(b)斜視透視図である。It is a figure which shows the structure of the multilayer wiring board connection structure concerning Embodiment 4 of this invention, (a) Side perspective drawing, (b) Perspective perspective drawing. この発明の実施の形態5に係る多層配線基板接続構造の構成を示す側面透視図である。It is a side perspective view which shows the structure of the multilayer wiring board connection structure based on Embodiment 5 of this invention. この発明の実施の形態5に係る多層配線基板接続構造の別の構成を示す斜視透視図である。It is a perspective perspective view which shows another structure of the multilayer wiring board connection structure concerning Embodiment 5 of this invention. この発明の実施の形態5に係る多層配線基板接続構造の従来例の構成を示す側面透視図である。It is a side perspective view which shows the structure of the prior art example of the multilayer wiring board connection structure concerning Embodiment 5 of this invention. この発明の実施の形態6に係る多層配線基板接続構造の構成を示す側面透視図である。It is a side see-through | perspective view which shows the structure of the multilayer wiring board connection structure concerning Embodiment 6 of this invention. この発明の実施の形態7に係る多層配線基板接続構造の構成を示す側面透視図である。It is a side perspective view which shows the structure of the multilayer wiring board connection structure based on Embodiment 7 of this invention. この発明の実施の形態8に係る多層配線基板接続構造の構成を示す側面透視図である。It is a side perspective view which shows the structure of the multilayer wiring board connection structure based on Embodiment 8 of this invention.

以下、この発明の実施の形態について図面を参照しながら詳細に説明する。
実施の形態1.
図1はこの発明の実施の形態1に係る多層配線基板接続構造の構成を示す図であり、(a)側面透視図であり、(b)斜視透視図である。
多層配線基板接続構造は、図1に示すように、親基板1及び子基板2から構成されている。
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
Embodiment 1 FIG.
1A and 1B are diagrams showing a configuration of a multilayer wiring board connection structure according to Embodiment 1 of the present invention, wherein FIG. 1A is a side perspective view, and FIG. 1B is a perspective perspective view.
As shown in FIG. 1, the multilayer wiring board connection structure includes a parent substrate 1 and a child substrate 2.

親基板1は、誘電体基板からなり、上面に信号導体パターン(第1の信号導体パターン)11が配線されたものである。また、親基板1の上面には、子基板2との対向部分に地導体12及びレジスト層13が設けられている。また、親基板1の下面には、地導体14が設けられている。そして、地導体12と地導体14とは、スルーホール15により電気的に接続されている。   The parent substrate 1 is made of a dielectric substrate, and has a signal conductor pattern (first signal conductor pattern) 11 wired on the upper surface. Further, a ground conductor 12 and a resist layer 13 are provided on the upper surface of the parent substrate 1 at a portion facing the child substrate 2. A ground conductor 14 is provided on the lower surface of the parent substrate 1. The ground conductor 12 and the ground conductor 14 are electrically connected by a through hole 15.

子基板2は、多層誘電体基板からなり、内層に信号導体パターン(第2の信号導体パターン)21が配線されたものである。また、子基板2の下面には、地導体(第1の地導体)22及びレジスト層23が設けられている。また、子基板2の端面には、親基板1の対向面である外層から信号導体パターン21が配線された内層にかけて貫通した穴の壁を導体で覆ったBVHを半割りにした半割りBVH24が設けられている。この半割りBVH24は、信号導体パターン21に電気的に接続されている。そして、親基板1の信号導体パターン11と半割りBVH24とは、例えば半田3により電気的に接続される。   The sub board 2 is composed of a multilayer dielectric board, and a signal conductor pattern (second signal conductor pattern) 21 is wired in the inner layer. A ground conductor (first ground conductor) 22 and a resist layer 23 are provided on the lower surface of the sub-board 2. In addition, a half-divided BVH 24 obtained by halving the BVH in which the wall of the hole penetrating from the outer layer, which is the opposite surface of the parent substrate 1 to the inner layer where the signal conductor pattern 21 is wired, is covered with a conductor is formed on the end surface of the child substrate 2. Is provided. The half BVH 24 is electrically connected to the signal conductor pattern 21. Then, the signal conductor pattern 11 and the half BVH 24 of the parent substrate 1 are electrically connected by, for example, solder 3.

また、親基板1及び子基板2の対向面には、親基板1と子基板2とを接続する接続構造4が設けられている。この接続構造4としては、例えば、親基板1及び子基板2のレジスト層13,23内にクリーム半田41を配置し、リフロー接続により接続する構造が挙げられる。   Further, a connection structure 4 for connecting the parent substrate 1 and the child substrate 2 is provided on the opposing surfaces of the parent substrate 1 and the child substrate 2. Examples of the connection structure 4 include a structure in which cream solder 41 is disposed in the resist layers 13 and 23 of the parent substrate 1 and the child substrate 2 and connected by reflow connection.

次に、上記のように構成された多層配線基板接続構造による効果について説明する。
本発明では、図1に示すように、子基板2の端面に半割りBVH24を設け、この半割りBVH24を介して親基板1及び子基板2の信号導体パターン11,21を電気的に接続する構造とした。これにより、信号導体パターン11が子基板2の内層に配線されている場合であっても、電流経路長を、従来の半割りスルーホールを用いた構成に対して短縮することができ、損失を小さくすることができる。また、半割りされたBVH24を用いたので、従来と同様に、親基板1及び子基板2の接続状態の目視確認が可能である。
また、従来の半割りスルーホールを用いずに電流経路長を短縮できるため、半割りスルーホールによる寄生インダクタンスが大きくならず、親基板1と子基板2の信号導体パターン11,21の不整合の発生を抑制でき、反射損失の劣化を回避できる。さらに、半割りスルーホールからの放射損失の増大も抑制できる。
Next, the effect of the multilayer wiring board connection structure configured as described above will be described.
In the present invention, as shown in FIG. 1, a half BVH 24 is provided on the end face of the sub board 2, and the parent board 1 and the signal conductor patterns 11 and 21 of the sub board 2 are electrically connected through the half BVH 24. The structure. As a result, even when the signal conductor pattern 11 is wired in the inner layer of the daughter board 2, the current path length can be shortened compared to the configuration using the conventional half through hole, and the loss can be reduced. Can be small. Further, since the half-divided BVH 24 is used, it is possible to visually check the connection state of the parent board 1 and the child board 2 as in the conventional case.
Further, since the current path length can be shortened without using the conventional half through hole, the parasitic inductance due to the half through hole does not increase, and the signal conductor patterns 11 and 21 of the parent board 1 and the child board 2 are not matched. Occurrence can be suppressed and deterioration of reflection loss can be avoided. Further, an increase in radiation loss from the half through hole can be suppressed.

また、例えば、親基板1及び子基板2の熱膨張率を同等にすることで、外乱に対する感度を同等にすることができ、親基板1と子基板2との接続の機械的強度を向上させることができる。   Further, for example, by making the thermal expansion coefficients of the parent board 1 and the child board 2 equal, the sensitivity to disturbance can be made equal, and the mechanical strength of the connection between the parent board 1 and the child board 2 is improved. be able to.

以上のように、この実施の形態1によれば、半割りBVH24により親基板1及び子基板2の信号導体パターン11,21を電気的に接続するように構成したので、親基板1及び子基板2の接続状態の目視確認を可能とし、かつ、電流経路長を短縮することができる。   As described above, according to the first embodiment, since the signal conductor patterns 11 and 21 of the parent board 1 and the child board 2 are electrically connected by the half BVH 24, the parent board 1 and the child board are provided. 2 can be visually confirmed, and the current path length can be shortened.

実施の形態2.
図2はこの発明の実施の形態2に係る多層配線基板接続構造の構成を示す図であり、(a)側面透視図であり、(b)斜視透視図である。図2に示す実施の形態2に係る多層配線基板接続構造は、図1に示す実施の形態1に係る多層配線基板接続構造の子基板2に、地導体(第2の地導体)25及び半割りスルーホール26を追加したものである。その他の構成は同様であり、同一の符号を付してその説明を省略する。
Embodiment 2. FIG.
2A and 2B are diagrams showing a configuration of a multilayer wiring board connection structure according to Embodiment 2 of the present invention, wherein FIG. 2A is a side perspective view, and FIG. 2B is a perspective perspective view. The multilayer wiring board connection structure according to the second embodiment shown in FIG. 2 includes a ground conductor (second ground conductor) 25 and a half conductor on the sub-board 2 of the multilayer wiring board connection structure according to the first embodiment shown in FIG. A split through hole 26 is added. Other configurations are the same, and the same reference numerals are given and description thereof is omitted.

地導体25は、子基板2の上面に設けられたものである。
半割りスルーホール26は、子基板2の端面に設けられ、上下面にかけて貫通した穴の壁を導体で覆ったスルーホールを半割りにしたものである。この半割りスルーホール26は、子基板2の上下面の地導体22,25と電気的に接続されている。なお図2では、半割りスルーホール26を介した地導体22,25の接続は、親基板1及び子基板2の接続を行う接続構造4としての機能も有している。この場合、接続構造4では、半田41bを用いて接続を行う。
The ground conductor 25 is provided on the upper surface of the daughter board 2.
The half through hole 26 is provided in the end surface of the sub-board 2 and halves the through hole in which the wall of the hole penetrating the upper and lower surfaces is covered with a conductor. The half through-holes 26 are electrically connected to the ground conductors 22 and 25 on the upper and lower surfaces of the daughter board 2. In FIG. 2, the connection of the ground conductors 22 and 25 through the half through hole 26 also has a function as the connection structure 4 for connecting the parent substrate 1 and the child substrate 2. In this case, in the connection structure 4, the connection is performed using the solder 41b.

このように、子基板2の上下面に地導体22,25を備え、半割りスルーホール26により電気的に接続することで、子基板2の内層の信号導体パターン21からの放射ノイズを低減することができる。また、半割りスルーホール26により地導体22,25を電気的に接続することで、グラウンドの強化が図れる。
さらに、半割りのスルーホール26を用いて接続構造4としても機能させることで、半割りスルーホール26と地導体22,25との接続状態を目視確認でき、親基板1と子基板2の固定を強固にすることができるため、機械的信頼性を向上させることができる。
As described above, the ground conductors 22 and 25 are provided on the upper and lower surfaces of the child board 2 and are electrically connected by the half through-holes 26, thereby reducing radiation noise from the signal conductor pattern 21 on the inner layer of the child board 2. be able to. In addition, the ground can be strengthened by electrically connecting the ground conductors 22 and 25 through the half through hole 26.
Furthermore, by making it function as the connection structure 4 using the halved through hole 26, the connection state between the halved through hole 26 and the ground conductors 22 and 25 can be visually confirmed, and the parent substrate 1 and the child substrate 2 can be fixed. Therefore, mechanical reliability can be improved.

実施の形態3.
図3はこの発明の実施の形態3に係る多層配線基板接続構造の構成を示す図であり、(a)側面透視図であり、(b)斜視透視図である。また、図4はこの発明の実施の形態3に係る多層配線基板接続構造の信号導体パターン11,21bを示す上面図である。図3に示す実施の形態3に係る多層配線基板接続構造は、図2に示す実施の形態2に係る多層配線基板接続構造の子基板2の信号導体パターン21を信号導体パターン21bに変更したものである。その他の構成は同様であり、同一の符号を付してその説明を省略する。
Embodiment 3 FIG.
3A and 3B are diagrams showing a configuration of a multilayer wiring board connection structure according to Embodiment 3 of the present invention. FIG. 3A is a side perspective view, and FIG. 3B is a perspective perspective view. FIG. 4 is a top view showing signal conductor patterns 11 and 21b of the multilayer wiring board connection structure according to Embodiment 3 of the present invention. The multilayer wiring board connection structure according to the third embodiment shown in FIG. 3 is obtained by changing the signal conductor pattern 21 of the child board 2 of the multilayer wiring board connection structure according to the second embodiment shown in FIG. 2 to a signal conductor pattern 21b. It is. Other configurations are the same, and the same reference numerals are given and description thereof is omitted.

信号導体パターン21bは、図3,4に示すように、子基板2の内層に配線されたものである。この信号導体パターン21bは、半割りBVH24の近傍においてパターン幅が突起状に一部広くなった幅広部分211を有している。   The signal conductor pattern 21b is wired in the inner layer of the daughter board 2 as shown in FIGS. The signal conductor pattern 21b has a wide portion 211 in which the pattern width is partially enlarged in the vicinity of the half BVH 24.

このように、信号導体パターン21bに、半割りBVH24の近傍のパターン幅を広く構成した幅広部分211を設けることで、反射損失を低減することができる。これは、信号導体パターン21bの幅広部分211が整合素子としての機能を有し、当該幅広部分211により形成される容量が半割りBVH24により発生する寄生インダクタンスを相殺するためである。   Thus, by providing the signal conductor pattern 21b with the wide portion 211 having a wide pattern width in the vicinity of the half BVH 24, the reflection loss can be reduced. This is because the wide portion 211 of the signal conductor pattern 21b has a function as a matching element, and the capacitance formed by the wide portion 211 cancels the parasitic inductance generated by the half BVH 24.

実施の形態4.
図5はこの発明の実施の形態4に係る多層配線基板接続構造の構成を示す図であり、(a)側面透視図であり、(b)斜視透視図である。図5に示す実施の形態4に係る多層配線基板接続構造は、図1に示す実施の形態1に係る多層配線基板接続構造の子基板2に信号導体パターン(第3の信号導体パターン)27及びBVH(第2のBVH)28を追加し、当該信号導体パターン27及びBVH28を介して信号導体パターン21と半割りBVH24とを電気的に接続したものである。その他の構成は同様であり、同一の符号を付してその説明を省略する。
Embodiment 4 FIG.
5A and 5B are diagrams showing a configuration of a multilayer wiring board connection structure according to Embodiment 4 of the present invention, wherein FIG. 5A is a side perspective view, and FIG. 5B is a perspective perspective view. The multilayer wiring board connection structure according to the fourth embodiment shown in FIG. 5 has a signal conductor pattern (third signal conductor pattern) 27 and a sub-board 2 of the multilayer wiring board connection structure according to the first embodiment shown in FIG. A BVH (second BVH) 28 is added, and the signal conductor pattern 21 and the half BVH 24 are electrically connected via the signal conductor pattern 27 and the BVH 28. Other configurations are the same, and the same reference numerals are given and description thereof is omitted.

信号導体パターン27は、子基板2の親基板1との対向面側の外層と信号導体パターン21が配線された内層との間の内層に配線されたものである。
BVH28は、子基板2の第2,3の信号導体パターン21,27が配線された内層間に設けられ、当該第2,3の信号導体パターン21,27を電気的に接続するものである。
また、半割りBVH24は、信号導体パターン27に電気的に接続されることで、信号導体パターン27及びBVH28を介して信号導体パターン21と電気的に接続される。
The signal conductor pattern 27 is wired in the inner layer between the outer layer of the child substrate 2 facing the parent substrate 1 and the inner layer where the signal conductor pattern 21 is wired.
The BVH 28 is provided between the inner layers where the second and third signal conductor patterns 21 and 27 of the daughter board 2 are wired, and electrically connects the second and third signal conductor patterns 21 and 27.
Further, the half-divided BVH 24 is electrically connected to the signal conductor pattern 27 through the signal conductor pattern 27 and the BVH 28 by being electrically connected to the signal conductor pattern 27.

この実施の形態4に係る多層配線基板接続構造では、親基板1に設けられた信号導体パターン11から子基板2に設けられた信号導体パターン21を半割りBVH24のみで接続する実施の形態1の構造に対して、半割りBVH24の長さが短くなる。そのため、信号導体パターン21の電気的な接続状態(半田3の状態)の目視確認を可能にしつつ、半割りBVH24からの放射損失をより低減することができる。   In the multilayer wiring board connection structure according to the fourth embodiment, the signal conductor pattern 21 provided on the sub board 2 is connected to the signal conductor pattern 11 provided on the parent board 1 by the halved BVH 24 only in the first embodiment. The length of the half BVH 24 is shortened with respect to the structure. Therefore, the radiation loss from the half BVH 24 can be further reduced while enabling visual confirmation of the electrical connection state (state of the solder 3) of the signal conductor pattern 21.

実施の形態5.
図6はこの発明の実施の形態5に係る多層配線基板接続構造の構成を示す側面透視図である。図6に示す実施の形態5に係る多層配線基板接続構造は、図1に示す実施の形態1に係る多層配線基板接続構造に、地導体(第2の地導体)25、側壁用スルーホール群29,30、給電用BVH31及び短絡構造32を追加したものである。その他の構成は同様であり、同一の符号を付してその説明を省略する。
Embodiment 5 FIG.
FIG. 6 is a side perspective view showing the configuration of the multilayer wiring board connection structure according to Embodiment 5 of the present invention. The multilayer wiring board connection structure according to the fifth embodiment shown in FIG. 6 is different from the multilayer wiring board connection structure according to the first embodiment shown in FIG. 1 in that a ground conductor (second ground conductor) 25 and side wall through-hole groups are provided. 29, 30, BVH 31 for power feeding, and a short circuit structure 32 are added. Other configurations are the same, and the same reference numerals are given and description thereof is omitted.

地導体25は、子基板2の上面に設けられたものである。
側壁用スルーホール群29,30は、信号導体パターン21の線路方向に遮断波長の1/2以下の間隔で配列されて、地導体22,25と接続されたものである。この側壁用スルーホール群29,30が2つの側壁となって、誘電体導波管を構成する。
The ground conductor 25 is provided on the upper surface of the daughter board 2.
The through-hole groups 29 and 30 for side walls are arranged in the line direction of the signal conductor pattern 21 with an interval of ½ or less of the cutoff wavelength and connected to the ground conductors 22 and 25. The through-hole groups 29 and 30 for side walls constitute two side walls to constitute a dielectric waveguide.

給電用BVH31は、信号導体パターン21、及び地導体22,25のうち一方の地導体(図6では地導体22)に電気的に接続され、子基板2の誘電体層に対して垂直に形成されたものである。この給電用BVH31により、誘電体導波管に給電を行う。   The power feeding BVH 31 is electrically connected to one of the signal conductor pattern 21 and the ground conductors 22 and 25 (the ground conductor 22 in FIG. 6), and is formed perpendicular to the dielectric layer of the daughter board 2. It has been done. Power is supplied to the dielectric waveguide by the power supply BVH 31.

短絡構造32は、給電用BVH31と半割りBVH24との間に設けられ、信号導体パターン21が貫通する窓321を有するものである。この短絡構造32により、誘電体導波管内の電磁波の進行方向を、信号導体パターン21の線路方向に沿って、半割りBVH24から遠ざかる方向に決定付けることができる。なお、短絡構造32は、図6に示すように、給電用BVH31から管内波長の1/4離れた位置に配置される。また、図7に示すように、短絡構造32を、半割りBVH24が設けられた面に設けるようにしてもよい。   The short-circuit structure 32 is provided between the power supply BVH 31 and the half BVH 24 and has a window 321 through which the signal conductor pattern 21 passes. With this short-circuit structure 32, the traveling direction of the electromagnetic wave in the dielectric waveguide can be determined in a direction away from the half BVH 24 along the line direction of the signal conductor pattern 21. As shown in FIG. 6, the short-circuit structure 32 is disposed at a position that is a quarter of the guide wavelength away from the power supply BVH 31. Further, as shown in FIG. 7, the short-circuit structure 32 may be provided on the surface on which the half BVH 24 is provided.

図8に実施の形態5に係る多層配線基板接続構造の従来例の側面透視図を示す。
従来では、図8に示すように、誘電体導波管が形成された子基板2に設けられた給電用BVH103への給電は、親基板1から行っている。そのため、親基板1の表層に設けた信号導体パターン11と内層に設けた信号導体パターン101を介して電気的に接続されるBVH102を親基板1に設け、子基板2の給電用BVH103と接続構造104を介して電気的に接続する必要があった。
FIG. 8 shows a side perspective view of a conventional example of the multilayer wiring board connection structure according to Embodiment 5. In FIG.
Conventionally, as shown in FIG. 8, power supply to the power supply BVH 103 provided on the daughter board 2 on which the dielectric waveguide is formed is performed from the parent board 1. Therefore, the signal conductor pattern 11 provided on the surface layer of the mother board 1 and the BVH 102 electrically connected via the signal conductor pattern 101 provided on the inner layer are provided on the mother board 1 and connected to the power supply BVH 103 of the child board 2. It was necessary to make an electrical connection via 104.

このように、従来では複雑な接続となり、親基板1と子基板2の接続状態の目視確認が困難であるため、接続不良が発生する恐れがあった。それに対して、図6,7に示す実施の形態5に係る多層配線基板接続構造では、親基板1と子基板2の接続状態の目視確認が可能であり、電流経路長も短くできる効果がある。   As described above, conventionally, the connection is complicated, and it is difficult to visually check the connection state between the parent board 1 and the child board 2, which may cause a connection failure. On the other hand, in the multilayer wiring board connection structure according to the fifth embodiment shown in FIGS. 6 and 7, it is possible to visually check the connection state of the parent board 1 and the child board 2, and the current path length can be shortened. .

実施の形態6.
図9はこの発明の実施の形態6に係る多層配線基板接続構造の構成を示す側面透視図である。図9に示す実施の形態6に係る多層配線基板接続構造は、図6に示す実施の形態5に係る多層配線基板接続構造に隔壁33を設けたものである。その他の構成は同様であり、異なる部分についてのみ説明を行う。
Embodiment 6 FIG.
FIG. 9 is a side perspective view showing the structure of the multilayer wiring board connection structure according to Embodiment 6 of the present invention. The multilayer wiring board connection structure according to the sixth embodiment shown in FIG. 9 is obtained by providing partition walls 33 in the multilayer wiring board connection structure according to the fifth embodiment shown in FIG. Other configurations are the same, and only different parts will be described.

隔壁33は、給電用BVH31に対して短絡構造32側とは反対側(給電用BVH31の電波方向後方側)に配置されたものである。なお、隔壁33は、給電用BVH31に対して容量性として機能する形状に構成されている。この隔壁33を設けることで、給電用BVH31と短絡構造32との距離を管内波長の1/4以下とすることが可能となる。よって、実施の形態5における効果に加え、子基板2の小型化が可能という効果がある。   The partition wall 33 is arranged on the side opposite to the short-circuit structure 32 side with respect to the power supply BVH 31 (the rear side in the radio wave direction of the power supply BVH 31). The partition wall 33 is configured in a shape that functions as a capacity with respect to the power supply BVH 31. By providing the partition wall 33, the distance between the power supply BVH 31 and the short-circuit structure 32 can be made ¼ or less of the guide wavelength. Therefore, in addition to the effect in the fifth embodiment, there is an effect that the sub board 2 can be downsized.

実施の形態7.
図10はこの発明の実施の形態7に係る多層配線基板接続構造の構成を示す側面透視図である。図10に示す実施の形態7に係る多層配線基板接続構造は、図6に示す実施の形態5に係る多層配線基板接続構造の給電用BVH31を給電用BVH31bに変更したものである。その他の構成は同様であり、同一の符号を付してその説明を省略する。
Embodiment 7 FIG.
FIG. 10 is a side perspective view showing the configuration of the multilayer wiring board connection structure according to Embodiment 7 of the present invention. The multilayer wiring board connection structure according to the seventh embodiment shown in FIG. 10 is obtained by changing the power supply BVH 31 of the multilayer wiring board connection structure according to the fifth embodiment shown in FIG. 6 to a power supply BVH 31b. Other configurations are the same, and the same reference numerals are given and description thereof is omitted.

給電用BVH31bは、給電用BVH31と同様に、信号導体パターン21、及び地導体22,25のうち一方の地導体(図10では地導体22)に電気的に接続され、子基板2の誘電体層に対して垂直に形成されたものである。この給電用BVH31bにより、誘電体導波管に給電を行う。そして、実施の形態7における給電用BVH31bは、電気的に接続された地導体(図10では地導体22)側に向かい径が大きくなるように構成されている。   Similarly to the power supply BVH 31, the power supply BVH 31 b is electrically connected to one of the signal conductor pattern 21 and one of the ground conductors 22 and 25 (the ground conductor 22 in FIG. 10). It is formed perpendicular to the layer. Power is supplied to the dielectric waveguide by the power supply BVH 31b. The power supply BVH 31b according to the seventh embodiment is configured such that the diameter increases toward the electrically connected ground conductor (ground conductor 22 in FIG. 10) side.

この径が徐々に大きくなる給電用BVH31bを用いることで、実施の形態5における効果に加え、誘電体導波管とのインピーダンスの不整合を緩和する機能が得られ、反射特性が改善する効果がある。   By using the BVH 31b for power supply whose diameter gradually increases, in addition to the effect in the fifth embodiment, the function of relaxing impedance mismatch with the dielectric waveguide can be obtained, and the effect of improving the reflection characteristics can be obtained. is there.

実施の形態8.
図11はこの発明の実施の形態8に係る多層配線基板接続構造の構成を示す側面透視図である。図11に示す実施の形態8に係る多層配線基板接続構造は、図6に示す実施の形態5に係る多層配線基板接続構造から給電用BVH31を削除し、隔壁34を追加したものである。その他の構成は同様であり、同一の符号を付してその説明を省略する。
Embodiment 8 FIG.
FIG. 11 is a side perspective view showing the structure of the multilayer wiring board connection structure according to Embodiment 8 of the present invention. The multilayer wiring board connection structure according to the eighth embodiment shown in FIG. 11 is obtained by removing the power supply BVH 31 from the multilayer wiring board connection structure according to the fifth embodiment shown in FIG. Other configurations are the same, and the same reference numerals are given and description thereof is omitted.

隔壁34は、誘電体導波管の2つの側壁間の中央に配置されて、信号導体パターン21、及び地導体22,25のうち一方の地導体(図11では地導体25)に電気的に接続されたものである。また、この隔壁34は、図11に示すように、半割りされたBVH24から遠ざかる方向に向かい厚みが薄くなる階段状に構成されている。   The partition wall 34 is disposed at the center between the two side walls of the dielectric waveguide, and is electrically connected to one of the signal conductor pattern 21 and the ground conductors 22 and 25 (the ground conductor 25 in FIG. 11). It is connected. Further, as shown in FIG. 11, the partition wall 34 is formed in a stepped shape in which the thickness decreases toward the direction away from the half-divided BVH 24.

この隔壁34を設けることで、実施の形態5における効果に加え、信号導体パターン21が形成するストリップ線路のインピーダンスと誘電体導波管のインピーダンスとのインピーダンス変成器として機能し、反射特性が改善する効果がある。   By providing this partition wall 34, in addition to the effect in the fifth embodiment, it functions as an impedance transformer between the impedance of the strip line formed by the signal conductor pattern 21 and the impedance of the dielectric waveguide, and the reflection characteristics are improved. effective.

なお、本願発明はその発明の範囲内において、各実施の形態の自由な組み合わせ、あるいは各実施の形態の任意の構成要素の変形、もしくは各実施の形態において任意の構成要素の省略が可能である。   In the present invention, within the scope of the invention, any combination of the embodiments, or any modification of any component in each embodiment, or omission of any component in each embodiment is possible. .

1 親基板、2 子基板、3 半田、4 接続構造、11 信号導体パターン(第1の信号導体パターン)、12 地導体、13 レジスト層、14 地導体、15 スルーホール、21,21b 信号導体パターン(第2の信号導体パターン)、22 地導体(第1の地導体)、23 レジスト層、24 半割りBVH、25 地導体(第2の地導体)、26 半割りスルーホール、27 信号導体パターン(第3の信号導体パターン)、28 BVH(第2のBVH)、29,30 側壁用スルーホール群、31,31b 給電用BVH、32 短絡構造、33,34 隔壁、41 クリーム半田、41b 半田、211 幅広部分、321 窓。   DESCRIPTION OF SYMBOLS 1 Parent substrate, 2 Child substrate, 3 Solder, 4 Connection structure, 11 Signal conductor pattern (1st signal conductor pattern), 12 Ground conductor, 13 Resist layer, 14 Ground conductor, 15 Through hole, 21, 21b Signal conductor pattern (Second signal conductor pattern), 22 ground conductor (first ground conductor), 23 resist layer, 24 half BVH, 25 ground conductor (second ground conductor), 26 half through hole, 27 signal conductor pattern (Third signal conductor pattern), 28 BVH (second BVH), 29, 30 Side wall through hole group, 31, 31b BVH for power feeding, 32 Short circuit structure, 33, 34 Partition, 41 Cream solder, 41b Solder, 211 Wide part, 321 window.

Claims (10)

誘電体基板からなり、上面に第1の信号導体パターンが配線された親基板と、
多層誘電体基板からなり、内層に第2の信号導体パターンが配線された子基板と、
前記子基板の前記親基板との対向面側の外層から内層にかけて設けられ、前記第1,2の信号導体パターンを電気的に接続する半割りされたBVH(Blind via hole)と、
前記親基板及び前記子基板を対向面で接続する接続構造と
を備えた多層配線基板接続構造。
A parent substrate made of a dielectric substrate and having a first signal conductor pattern wired on the upper surface;
A sub-board made of a multi-layer dielectric substrate and having a second signal conductor pattern wired on the inner layer;
BVH (blind via hole) provided from the outer layer to the inner layer on the side of the child substrate facing the parent substrate and electrically connecting the first and second signal conductor patterns;
A multilayer wiring board connection structure comprising: a connection structure for connecting the parent substrate and the child substrate on opposite surfaces.
前記子基板の上下面に設けられた第1,2の地導体と、
前記子基板に設けられ、前記第1,2の地導体を電気的に接続する半割りされたスルーホールとを備えた
ことを特徴とする請求項1記載の多層配線基板接続構造。
First and second ground conductors provided on the upper and lower surfaces of the child board;
2. The multilayer wiring board connection structure according to claim 1, further comprising a half-divided through hole provided on the sub-board and electrically connecting the first and second ground conductors.
前記第2の信号導体パターンは、前記半割りされたBVHの近傍のパターン幅が広く構成された
ことを特徴とする請求項1または請求項2記載の多層配線基板接続構造。
3. The multilayer wiring board connection structure according to claim 1, wherein the second signal conductor pattern has a wide pattern width in the vicinity of the half-divided BVH. 4.
前記子基板の前記親基板との対向面側の外層と前記第2の信号導体パターンが配線された内層との間の内層に配線された第3の信号導体パターンと、
前記子基板の前記第2,3の信号導体パターンが配線された内層間に設けられ、当該第2,3の信号導体パターンを電気的に接続する第2のBVHとを備え、
前記半割りされたBVHは、前記第3の信号導体パターンに電気的に接続された
ことを特徴とする請求項1から請求項3のうちのいずれか1項記載の多層配線基板接続構造。
A third signal conductor pattern wired in an inner layer between an outer layer of the child substrate facing the parent substrate and an inner layer wired with the second signal conductor pattern;
A second BVH provided between the inner layers where the second and third signal conductor patterns of the daughter board are wired, and electrically connecting the second and third signal conductor patterns;
4. The multilayer wiring board connection structure according to claim 1, wherein the half-divided BVH is electrically connected to the third signal conductor pattern. 5.
前記親基板及び前記子基板は、熱膨張係数が同等である
ことを特徴とする請求項1から請求項4のうちのいずれか1項記載の多層配線基板接続構造。
The multilayer wiring board connection structure according to any one of claims 1 to 4, wherein the parent substrate and the child substrate have the same thermal expansion coefficient.
前記子基板の上下面に設けられた第1,2の地導体と、
前記第2の信号導体パターンの線路方向に遮断方向の1/2以下の間隔で配列されて前記第1,2の地導体と接続され、誘電体導波管の2つの側壁を形成する側壁用スルーホール群と、
前記第2の信号導体パターン、及び前記第1,2の地導体のうち一方の地導体に電気的に接続され、前記誘電体導波管に給電する給電用BVHと、
前記給電用BVHと前記半割りされたBVHとの間に設けられ、前記第2の信号導体パターンが貫通する窓を有する短絡構造と
を備えたことを特徴とする請求項1記載の多層配線基板接続構造。
First and second ground conductors provided on the upper and lower surfaces of the child board;
For the side wall that is arranged in the line direction of the second signal conductor pattern at an interval of 1/2 or less of the cutoff direction and is connected to the first and second ground conductors to form two side walls of the dielectric waveguide Through-hole groups,
BVH for feeding that is electrically connected to one of the second signal conductor pattern and the first and second ground conductors and feeds the dielectric waveguide;
2. The multilayer wiring board according to claim 1, further comprising: a short-circuit structure provided between the feeding BVH and the half-divided BVH and having a window through which the second signal conductor pattern passes. Connection structure.
前記短絡構造は、前記半割りされたBVHが設けられた面に設けられた
ことを特徴とする請求項6記載の多層配線基板接続構造。
The multilayer wiring board connection structure according to claim 6, wherein the short-circuit structure is provided on a surface on which the half-divided BVH is provided.
前記給電用BVHに対して前記短絡構造側とは反対側に配置された隔壁を備え、
前記給電用BVHと前記短絡構造との距離は、前記管内波長の1/4以下である
ことを特徴とする請求項6記載の多層配線基板接続構造。
A partition wall disposed on the side opposite to the short-circuit structure side with respect to the power supply BVH,
The multilayer wiring board connection structure according to claim 6, wherein a distance between the power supply BVH and the short-circuit structure is ¼ or less of the in-tube wavelength.
前記給電用BVHの径は、前記電気的に接続された地導体側に向かい大きくなるように構成された
ことを特徴とする請求項6記載の多層配線基板接続構造。
The multilayer wiring board connection structure according to claim 6, wherein a diameter of the power feeding BVH is configured to increase toward the electrically connected ground conductor side.
前記子基板の上下面に設けられた第1,2の地導体と、
前記第2の信号導体パターンの線路方向に遮断方向の1/2以下の間隔で配列されて前記第1,2の地導体と接続され、誘電体導波管の2つの側壁を形成する側壁用スルーホール群と、
前記誘電体導波管の2つの側壁間の中央に配置されて、前記第2の信号導体パターン、及び前記第1,2の地導体のうち一方の地導体に電気的に接続され、前記半割りされたBVHから遠ざかる方向に向かい厚みが薄くなる階段状に構成された隔壁と、
前記隔壁と前記半割りされたBVHとの間に設けられ、前記第2の信号導体パターンが貫通する窓を有する短絡構造と
を備えたことを特徴とする請求項1記載の多層配線基板接続構造。
First and second ground conductors provided on the upper and lower surfaces of the child board;
For the side wall that is arranged in the line direction of the second signal conductor pattern at an interval of 1/2 or less of the cutoff direction and is connected to the first and second ground conductors to form two side walls of the dielectric waveguide Through-hole groups,
Disposed in the center between two side walls of the dielectric waveguide, and electrically connected to one of the second signal conductor pattern and the first and second ground conductors; A partition wall configured in a staircase shape whose thickness decreases in a direction away from the divided BVH;
The multilayer wiring board connection structure according to claim 1, further comprising: a short-circuit structure provided between the partition wall and the half-divided BVH and having a window through which the second signal conductor pattern passes. .
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017214595A (en) * 2017-08-30 2017-12-07 株式会社クラレ Adhesive composition

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09321501A (en) * 1996-05-30 1997-12-12 Mitsubishi Electric Corp Multilayer high frequency circuit board
JP2002158509A (en) * 2000-11-21 2002-05-31 Mitsubishi Electric Corp High-frequency circuit module and production method therefor
JP2006165108A (en) * 2004-12-03 2006-06-22 Asahi Glass Co Ltd Ceramic circuit board

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09321501A (en) * 1996-05-30 1997-12-12 Mitsubishi Electric Corp Multilayer high frequency circuit board
JP2002158509A (en) * 2000-11-21 2002-05-31 Mitsubishi Electric Corp High-frequency circuit module and production method therefor
JP2006165108A (en) * 2004-12-03 2006-06-22 Asahi Glass Co Ltd Ceramic circuit board

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017214595A (en) * 2017-08-30 2017-12-07 株式会社クラレ Adhesive composition

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