JP2015109336A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To thin a PoP-type stacked semiconductor device by thinning a semiconductor device on an upper stage.SOLUTION: A semiconductor device 102 includes: a wiring substrate 111 having an opening 114 defined by a first side, a second side, a third side, and a fourth side, first connection pads 115 disposed along the first and second sides, and second connection pads 116 disposed along the third and the fourth sides; a first semiconductor chip 123 having first electrode pads 125, the first electrode pads 125 each being electrically connected to the first connection pads 115, and disposed so as to face the first and second sides; a second semiconductor chip 124 having second electrode pads 126, the second electrode pads 126 each being electrically connected to the second connection pads 116, each of short sides exceeds the third and fourth sides, and stacked so that one surface faces the first semiconductor chip 123; and a sealing part 130 formed so as to cover the first semiconductor chip 123 and the second semiconductor chip 124.

Description

  The present invention relates to a semiconductor device.

  In order to increase the density of semiconductor devices, a plurality of semiconductor chips are stacked. Such a semiconductor device is also called an MCP (Multi Chip Package).

  Japanese Patent Laid-Open No. 2013-125765 (Patent Document 1) discloses an upper semiconductor device in which two memory chips are stacked and mounted on a wiring substrate on a lower semiconductor device in which a logic chip is flip-chip mounted on a wiring substrate. A stacked PoP (Package On Package) type stacked semiconductor device is disclosed.

  Further, as a technique for providing an opening in a wiring board and arranging a semiconductor chip in the opening, there are JP-A Nos. 2003-133521 (Patent Document 2) and 2010-272734 (Patent Document 3).

JP 2013-125765 A JP 2003-133521 A JP 2010-272734 A

  In recent years, there has been a demand for miniaturization and thinning of a semiconductor device mounted on a portable device due to the miniaturization and thinning of the portable device. However, since the upper semiconductor device used for PoP has two memory chips stacked on the wiring board, there is a limit to the thinness of the semiconductor device.

  Accordingly, the present invention provides a semiconductor device capable of reducing the thickness of a PoP type stacked semiconductor device by reducing the thickness of the upper semiconductor device.

A semiconductor device according to one embodiment of the present invention includes:
First and second sides facing each other, an opening that is longer than the first and second sides and defined by the third and fourth sides facing each other, and the first and second sides A wiring substrate having a plurality of first connection pads arranged along the third side and a plurality of second connection pads arranged along the third and fourth sides;
It has a substantially rectangular plate shape and has a plurality of first electrode pads arranged along the short side of one surface, and the plurality of first electrode pads are electrically connected to the plurality of first connection pads, respectively. A first semiconductor chip that is connected and arranged in the opening of the wiring board such that each of the short sides faces the first and second sides;
It has a substantially rectangular plate shape and has a plurality of second electrode pads arranged along the short side of one surface, and the plurality of second electrode pads are electrically connected to the plurality of second connection pads, respectively. A second layer connected to the first semiconductor chip and connected to the first semiconductor chip such that each of the short sides exceeds the third and fourth sides and the one surface faces the first semiconductor chip. Semiconductor chip,
And a sealing portion formed to cover the first semiconductor chip and the second semiconductor chip.

  According to the present invention, the PoP type stacked semiconductor device can be thinned by thinning the upper semiconductor device.

It is sectional drawing which shows schematic structure of the PoP type semiconductor device incorporating the semiconductor device which concerns on the 1st Embodiment of this invention. 1 is a plan view showing a schematic configuration of an upper semiconductor device (upper package 102) of PoP according to a first embodiment of the present invention. It is sectional drawing which shows schematic structure of the upper stage semiconductor device (upper package 102) of PoP based on the 1st Embodiment of this invention, (a) is a cross section which shows the cross-sectional structure between AA 'of FIG. It is a figure and (b) is sectional drawing which shows the cross-sectional structure between BB 'of FIG. It is process drawing for demonstrating the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is the figure corresponding to Drawing 3 with the sectional view showing the schematic structure of the upper semiconductor device (upper package 102) of PoP concerning the 2nd embodiment of the present invention, and (a) is between AA ' FIG. 5B is a cross-sectional view showing a cross-sectional configuration between BB ′. It is process drawing for demonstrating the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is the figure corresponding to Drawing 3 with a sectional view showing the schematic structure of the upper semiconductor device (upper package 102) of PoP concerning a 3rd embodiment of the present invention, and (a) is between AA ' FIG. 5B is a cross-sectional view showing a cross-sectional configuration between BB ′. It is sectional drawing which shows schematic structure of the PoP type semiconductor device incorporating the semiconductor device which concerns on the 3rd Embodiment of this invention. It is the figure corresponding to Drawing 3 with the sectional view showing the schematic structure of the upper semiconductor device (upper package 102) of PoP concerning the 4th embodiment of the present invention, and (a) is between AA ' FIG. 5B is a cross-sectional view showing a cross-sectional configuration between BB ′.

  Hereinafter, an example of a semiconductor device according to an embodiment to which the present invention is applied will be described with reference to the drawings.

(First embodiment)
A schematic configuration of a semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS. Here, FIG. 1 is a cross-sectional view showing a schematic configuration of a PoP type semiconductor device incorporating the semiconductor device according to the first embodiment of the present invention.

  As shown in FIG. 1, the PoP type semiconductor device 100 includes a lower package 101 and an upper package 102 stacked and mounted above the lower package 101.

  In the lower package 101, a semiconductor chip 104 (third semiconductor chip), for example, a controller chip is flip-chip mounted on the wiring substrate 103 via bump electrodes 105, and the third semiconductor chip 104 (controller chip) and the wiring are connected. An underfill material 106 is filled in a gap with the substrate 103.

  A connection land 107 for connection with the upper package 102 is disposed around the third semiconductor chip 104 on one surface of the wiring substrate 103. A plurality of mounting lands 108 are arranged on the back surface of the wiring substrate 103, and the plurality of mounting lands 108 are connected to the electrode pads 109 (third electrode pads) of the third semiconductor chip 104. The plurality of connection pads 110 (third connection pads) or the connection lands 107 connected to the upper package 102 are electrically connected.

  An upper package 102 is stacked and mounted above the lower package 101. In the upper package 102, for example, two rows of external terminals 112 (solder balls) are arranged on the outer periphery of the other surface side of the wiring substrate 111 so as to avoid the third semiconductor chip 104 of the lower package 101. In addition, external terminals 122 (solder balls) are disposed on the mounting lands 108 of the lower package 103.

  FIG. 2 is a plan view showing a schematic configuration of the upper semiconductor device (upper package 102) of PoP according to the first embodiment. FIG. 3 is a cross-sectional view illustrating a schematic configuration of the stacked semiconductor device in which the semiconductor devices of the first embodiment are stacked. FIG. 3A is a cross-sectional view illustrating a cross-sectional configuration between AA ′ in FIG. FIG. 3B is a cross-sectional view showing a cross-sectional configuration between BB ′ in FIG. 2.

  As shown in FIGS. 2 and 3, the wiring substrate 111 has, for example, an insulating base 113, for example, a glass epoxy base, and a predetermined wiring pattern is formed on both surfaces of the insulating base 113. The insulating base 113 has a through hole 114 having a predetermined size in a substantially central region. The through hole 114 has a substantially rectangular shape and is formed so as to penetrate from one surface of the wiring substrate 111 to the other surface.

  Then, on one surface side of the insulating base material 113, a plurality of first connection pads 115 disposed along the inner surface of the short side facing the through hole 114, and the inner surface of the long side of the through hole 114. A plurality of second connection pads 116 are formed. One surface of the insulating base 113 is covered with an insulating film 117, for example, a solder resist film, and an opening 118 is formed in the insulating film 117 so that the first connection pad 115 and the second connection pad 116 are exposed. Has been.

  Further, in the peripheral region on the other surface side of the insulating base 113, a plurality of lands 119 formed in, for example, two rows along the four sides are formed. The other surface of the insulating base 113 is also covered with an insulating film 120, for example, a solder resist film, and openings are formed in the solder resist film so as to expose a plurality of lands 119.

  The first connection pads 115 and the second connection pads 116 and the corresponding lands 119 are electrically connected by a predetermined wiring pattern and vias 121 of the wiring board 111. Also, solder balls 112 serving as external electrodes are mounted on the plurality of lands 119 of the wiring board 111.

  In the semiconductor device of the first embodiment, as shown in FIGS. 2 and 3, a plurality of semiconductor chips, for example, two memory chips (first semiconductor chip 123 and second semiconductor chip 124) are formed on the wiring substrate 111. Is installed. The first semiconductor chip 123 and the second semiconductor chip 124 are the same semiconductor chip having substantially the same circuit configuration and substantially the same chip size. A plurality of connected electrode pads (a first electrode pad 125 and a second electrode pad 126) are formed.

  The plurality of electrode pads (first electrode pad 125 and second electrode pad 126) of the first and second semiconductor chips 123 and 124 are arranged along the short sides of the circuit formation surface. A passivation film is formed on one surface of the first and second semiconductor chips 123 and 124 so as to expose a plurality of electrode pads (first electrode pad 125 and second electrode pad 126), thereby forming a circuit. The surface is protected.

  The first semiconductor chip 123 is mounted in the through hole 114 of the wiring board 111 so that the circuit surface faces the one surface side of the wiring board 111. The plurality of first electrode pads 125 of the first semiconductor chip 123 are electrically connected to the plurality of first connection pads 115 of the wiring substrate 111 by conductive wires 127, for example, wires made of Au or Cu. It is connected to the.

  In addition, the second semiconductor chip 124 has the circuit board facing the one surface side of the wiring board 111 and the wiring board 111 such that each short side exceeds the inner end of the long side of the through hole 114 of the wiring board 111. It is mounted on the top by flip chip mounting. The second semiconductor chip 124 is stacked on the first semiconductor chip 123 so as to cross the first semiconductor chip 123.

  On the plurality of electrode pads 126 of the second semiconductor chip 124, bump electrodes comprising a columnar body made of Cu or the like protruding from the circuit formation surface at a predetermined height and a solder layer 128 formed on the top thereof. 129 is formed. The plurality of second electrode pads 126 of the second semiconductor chip 124 are electrically connected to the plurality of second connection pads 116 of the wiring substrate 111 by the bump electrodes 129, respectively.

  A sealing resin layer 130 is formed on one surface of the wiring substrate 111, and the first semiconductor chip 123, the second semiconductor chip 124, the wires 127, and the bump electrodes 129 are covered with the sealing resin layer 130. ing. The gap between the through hole 114 of the wiring substrate 111 and the first and second semiconductor chips 123 and 124 is also filled with the sealing resin layer 130.

  Thus, in the semiconductor device of the first embodiment, the upper package 102 (upper semiconductor device) is longer than the first and second inner end portions and the first and second inner end portions facing each other. And a plurality of first holes disposed along the first and second inner end portions, and a through hole (opening portion) 114 defined by the third and fourth inner end portions facing each other. A wiring board 111 having a connection pad 115 and a plurality of second connection pads 116 arranged along the third and fourth inner end portions, and a substantially rectangular plate shape, along the short side of one surface. The first semiconductor is disposed in the through-hole 114 of the wiring substrate 111 so that each of the short sides faces the first and second inner end portions. A chip 123 and a plurality of first electrode pads 125 of the first semiconductor chip 123; A plurality of bonding wires 127 for electrically connecting the first connection pads 115 of the line substrate 111 and a plurality of second electrode pads 126 arranged in a substantially rectangular plate shape along the short side of one surface. And a second side stacked on the first semiconductor chip 123 such that each of the short sides exceeds the third and fourth inner end portions and one surface faces the first semiconductor chip 123. The semiconductor chip 124, the plurality of second electrode pads 126 of the second semiconductor chip 124, and the plurality of bump electrodes 129 that electrically connect the second connection pads 116 of the wiring substrate 111, respectively. As a result, the upper package 102 on which the plurality of first and second semiconductor chips 123 and 124 are mounted can be thinned.

  Specifically, the first semiconductor chip 123 is disposed in the through hole 114 of the wiring board 111, and the flip chip is formed so that the end of the second semiconductor chip 124 protrudes outside the through hole 114 of the wiring board 111. By disposing on the wiring substrate 111 by mounting, the sealing resin layer 130 disposed on the second semiconductor chip 124 can be reduced, so that the semiconductor device (upper package 102) can be thinned. Thus, the thickness of the PoP stacked semiconductor device 100 can be reduced.

  In addition, in the PoP upper package 102 on which the first semiconductor chip 123 and the second semiconductor chip 124 are mounted, the electrode pads 125 of the semiconductor chips 123 and 124 are provided on two opposite sides of the four sides of the wiring substrate 111. , 126 corresponding to the lands 126 are arranged.

  Therefore, by arranging the second semiconductor chip 124 on the wiring board 111 so as to cross the first semiconductor chip 123, it is easy to route the wiring on the wiring board 111, and the equal-length wiring is provided. Can be realized.

  In addition, a gap is secured between the first semiconductor chip 123 and the second semiconductor chip 124, and the through hole 114 is disposed in the wiring substrate 111. Therefore, voids can be easily released, and the sealing resin 130 can be filled. Can be improved.

  Furthermore, since the other surface of the wiring substrate 111 is configured so that the sealing resin 130 does not protrude, a standoff of the upper package 102 can be ensured. Accordingly, when the upper package 102 is stacked and mounted on the lower package 101 (lower semiconductor device), the sealing resin 130 of the upper package 102 interferes with the third semiconductor chip 123 (controller chip) of the lower package 101. Therefore, the upper package 102 can be mounted on the lower package 101 satisfactorily.

  Next, a method for manufacturing the semiconductor device (upper package 102) of the first embodiment will be described with reference to FIG. Here, FIG. 4 is a cross-sectional view showing an assembly flow of the upper package 102 of the first embodiment.

  As shown in FIG. 4A, the wiring mother board has a plurality of product forming portions (product forming regions) 131 arranged in a matrix, and each product forming portion 131 is partitioned by dicing lines 132. . Each product forming part 131 is configured as shown in FIGS. 2 and 3, for example.

  A support substrate (support body) 133 is disposed on the other surface of the wiring motherboard, and the through hole 114 is covered with the support substrate 133. The support substrate 133 is made of, for example, a metal substrate or a tape substrate, and is bonded to the wiring mother substrate via a temporary adhesive layer such as an adhesive whose adhesive strength is reduced by specific energy irradiation, for example, UV irradiation.

  Next, as shown in FIG. 4B, the first semiconductor chip 123 is mounted on the wiring substrate 111 so as to be disposed in the through hole 114 of each product forming portion 131. The first semiconductor chip 123 is held in the through hole 114 by adhering to the temporary adhesive layer of the support substrate 123.

  Thereafter, the plurality of first electrode pads 125 of the first semiconductor chip 123 and the plurality of first connection pads 115 of the product forming unit 131 are electrically connected by conductive wires 127, respectively.

  Here, a wire bonding apparatus can be used for the connection using the wire 127. The connection is performed by, for example, ball bonding using an ultrasonic thermocompression bonding method. Specifically, the tip of the wire 127 on which a ball has been formed by melting is ultrasonically thermocompression bonded onto the first electrode pad 125, and the rear end of the wire 127 is placed so that the wire 127 draws a predetermined loop shape. The ultrasonic thermocompression bonding is performed on one connection pad 115.

  Next, as shown in FIG. 4C, the second semiconductor chip 124 in which the bump electrode 129 is formed on the second electrode pad 126 is crossed with respect to the first semiconductor chip 123. Each product forming part 131 is mounted by flip chip mounting. As a result, the plurality of second electrode pads 126 of the second semiconductor chip 124 and the plurality of second connection pads 116 of the product forming unit 131 are electrically connected via the bump electrodes 129.

  Thereafter, as shown in FIG. 4D, the wiring mother board is collectively sealed with a sealing resin 130 on one surface of the wiring mother board by transfer molding in a state where the support substrate 133 is mounted. By arranging the through hole 114 in the wiring substrate 111, a sufficient gap is secured between the first semiconductor chip 123 and the second semiconductor chip 124, reducing the generation of voids and good sealing. it can.

  Thereafter, as shown in FIG. 4E, the support substrate 133 is removed from the wiring motherboard by irradiating the temporary adhesive layer of the support substrate 133 with predetermined energy to reduce the adhesive force. Thereby, the back surface of the first semiconductor chip 123 is exposed from the other surface side of the wiring substrate 11.

  Thereafter, solder balls 112 are mounted on the lands 119 on the other side of the wiring mother board. Specifically, using a suction mechanism (not shown) in which a plurality of suction holes are formed in accordance with the arrangement of the lands 119 on the wiring board 111, the solder balls 112 are held in the suction holes, and the held solder balls 112 are removed. It is collectively mounted on the land 119 of the wiring board 111 through the flux.

  After the solder balls 112 are mounted on all the product forming portions 131, the solder balls 112 are fixed by reflowing the wiring substrate 111.

  Next, as shown in FIG. 4F, the sealing resin 130 is bonded to the dicing tape, and the sealing resin 130 and the wiring mother board are supported on the dicing tape. Thereafter, the wiring mother board and the sealing resin 130 are cut vertically and horizontally along the dicing line 132 using a dicing blade (not shown). As a result, the wiring mother board is separated into pieces for each product forming part 131.

  Thereafter, the separated product forming portion 131 and the sealing resin 130 are picked up from the dicing tape, whereby the semiconductor device (upper package) 102 as shown in FIGS. 2 and 3 is obtained.

(Second Embodiment)
A schematic configuration of a semiconductor device according to the second embodiment of the present invention will be described with reference to FIG. Here, FIG. 5 is a cross-sectional view showing a schematic configuration of the semiconductor device (upper package 102) of the second embodiment.

  The semiconductor device of the second embodiment is configured in the same manner as in the first embodiment. As shown in FIG. 5, the adhesive resin layer 500 is formed in the through hole 114 so as to cover the back surface of the first semiconductor chip 123. Is different from the first embodiment in that is arranged. Since other configurations are the same as those of the first embodiment, description thereof is omitted.

  Also in the second embodiment, the same effect as in the first embodiment can be obtained, and the back surface of the first semiconductor chip 123 is covered with the adhesive resin layer 500, so that the moisture resistance of the semiconductor device 102 is improved. It can be improved.

  Next, with reference to FIG. 6, the manufacturing method of the semiconductor device (upper package 102) of 2nd Embodiment is demonstrated. Here, FIG. 6 is a cross-sectional view showing an assembly flow of the semiconductor device (upper package) 102 of the second embodiment.

  As shown in FIG. 6A, the wiring mother board has a plurality of product forming portions (product forming regions) 131 arranged in a matrix, and each product forming portion 131 is partitioned by a dicing line 132. . Each product forming part 131 is configured as shown in FIGS. 2 and 5, for example. A support substrate (support) 133 is disposed on the other surface of the wiring mother board, and the through hole (opening) 114 is covered with the support substrate 133. The support substrate 133 is made of, for example, a metal substrate or a tape substrate, and is bonded to the wiring mother substrate via a temporary adhesive layer such as an adhesive whose adhesive strength is reduced by specific energy irradiation, for example, UV irradiation.

  Next, as illustrated in FIG. 6B, a resin adhesive is supplied to the cavity formed by the through hole (opening) 114 and the support substrate 123 of the wiring substrate 11 by potting to form the resin adhesive layer 500. To do.

Next, as shown in FIG. 6C, the first semiconductor chip 123 is mounted on the resin adhesive layer 500, and the resin adhesive layer 500 is cured by heating, so that the inside of the through hole 114 of the wiring substrate 11. The first semiconductor chip 123 is fixed.

  After the first semiconductor chip 123 is fixed, the support substrate 133 is removed from the wiring motherboard by irradiating the temporary adhesive layer of the support substrate 133 with predetermined energy to reduce the adhesive force. Thereby, the back surface of the resin adhesive layer 500 is exposed from the other surface side of the wiring substrate 111.

  Thereafter, the plurality of first electrode pads 125 of the first semiconductor chip 123 and the plurality of first connection pads 115 of the product forming unit 131 are electrically connected by conductive wires 127, respectively.

  Here, a wire bonding apparatus can be used for the connection using the wire 127. The connection is performed by, for example, ball bonding using an ultrasonic thermocompression bonding method. Specifically, the tip of the wire 127 on which a ball has been formed by melting is ultrasonically thermocompression bonded onto the first electrode pad 125, and the rear end of the wire 127 is placed so that the wire 127 draws a predetermined loop shape. The ultrasonic thermocompression bonding is performed on one connection pad 115.

  Next, as shown in FIG. 6D, the second semiconductor chip 124 in which the bump electrode 129 is formed on the second electrode pad 126 is crossed with respect to the first semiconductor chip 123. Each product forming part 131 is mounted by flip chip mounting. As a result, the plurality of second electrode pads 126 of the second semiconductor chip 124 and the plurality of second connection pads 116 of the product forming unit 131 are electrically connected via the bump electrodes 129.

  Thereafter, as shown in FIG. 6E, the wiring mother board is collectively sealed with a sealing resin 130 on one surface of the wiring mother board by transfer molding. By arranging the through hole 114 in the wiring substrate 111, a sufficient gap is secured between the first semiconductor chip 123 and the second semiconductor chip 124, reducing the generation of voids and good sealing. it can.

  Thereafter, solder balls 112 are mounted on the lands 119 on the other side of the wiring mother board. Specifically, using a suction mechanism (not shown) in which a plurality of suction holes are formed in accordance with the arrangement of the lands 119 on the wiring board 111, the solder balls 112 are held in the suction holes, and the held solder balls 112 are removed. It is collectively mounted on the land 119 of the wiring board 111 through the flux.

  After the solder balls 112 are mounted on all the product forming portions 131, the solder balls 112 are fixed by reflowing the wiring substrate 111.

  Next, as shown in FIG. 6G, the sealing resin 130 is bonded to the dicing tape, and the sealing resin 130 and the wiring mother board are supported on the dicing tape. Thereafter, the wiring mother board and the sealing resin 130 are cut vertically and horizontally along the dicing line 132 using a dicing blade (not shown). As a result, the wiring mother board is separated into pieces for each product forming part 131.

  Thereafter, the separated product forming portion 131 and the sealing resin 130 are picked up from the dicing tape, whereby a semiconductor device (upper package) 102 as shown in FIG. 5 is obtained.

  As described above, the resin adhesive layer 500 is supplied into the through-hole (opening) 114 and the first semiconductor chip 123 is fixed, so that the support substrate 133 is formed at an earlier stage than in the first embodiment. Can be removed. Thereby, a temporary adhesive material layer is heated by many processes, and the risk that it becomes difficult to peel off the support substrate 133 by receiving a thermal history can be reduced.

  In the second embodiment, the case where the support substrate 133 is removed from the wiring substrate 111 after mounting the first semiconductor chip 123 on the wiring substrate 111 has been described. Alternatively, the support substrate 133 may be removed from the wiring substrate 111 after the second semiconductor chip 124 of FIG.

(Third embodiment)
A schematic configuration of a semiconductor device according to the third embodiment of the present invention will be described with reference to FIGS. FIG. 7 is a cross-sectional view showing a schematic configuration of the semiconductor device (upper package 102) of the third embodiment. FIG. 8 is a cross-sectional view showing a schematic configuration of a PoP type semiconductor device incorporating a semiconductor device according to the third embodiment of the present invention.

  The semiconductor device 102 of the third embodiment is configured similarly to the first embodiment, and a gap (gap) 700 is formed below the first semiconductor chip 123 in the through hole 114 of the wiring board 11. This is different from the first embodiment. Since other configurations are the same as those of the first embodiment, description thereof is omitted.

  In the third embodiment, the same effect as that of the first embodiment can be obtained, and a gap (gap) is formed on the other surface side of the wiring board 11 as shown in FIG. By arranging the third semiconductor chip 104 (controller chip) in the gap, the stacked semiconductor device 100 in which the upper package 102 is stacked on the lower package 101 can be further reduced in thickness.

  In addition, the third semiconductor chip 104 (controller chip) of the lower package 101 is disposed in the gap between the wiring substrates 111 of the upper package 102, so that the upper package 102 that electrically connects the upper package 102 and the lower package 101. Since the ball diameter of the solder ball 112 can be reduced, the arrangement pitch of the connection lands 107 of the lower package 101 can be reduced.

  As an assembly flow of the semiconductor device (upper package 102) of the third embodiment, a temporary adhesive that can remove the adhesive resin 500 of the second embodiment is used and assembled in the same manner as in the second embodiment. After forming the sealing resin layer 500, the temporary adhesive is also removed together with the support substrate 133, so that a gap is formed on the other surface side of the wiring substrate 111.

(Fourth embodiment)
A schematic configuration of a semiconductor device according to the fourth embodiment of the present invention will be described with reference to FIG. FIG. 9 is a cross-sectional view showing a schematic configuration of the semiconductor device (upper package 102) of the fourth embodiment.

  The semiconductor device 102 according to the fourth embodiment is configured in the same manner as in the first embodiment, and is configured such that the back surface side of the second semiconductor chip 124 is exposed from the sealing resin layer 130. Different from the first embodiment. Since other configurations are the same as those of the first embodiment, description thereof is omitted.

  Also in the fourth embodiment, the same effect as in the first embodiment can be obtained, and the semiconductor device 102 can be further thinned. Further, since the back surfaces of the first semiconductor chip 123 and the second semiconductor chip 124 are exposed, the heat dissipation of the semiconductor device 102 can be improved.

  As mentioned above, although the invention made | formed by this inventor was demonstrated based on embodiment, it cannot be overemphasized that this invention is not limited to the said embodiment, and can be variously changed in the range which does not deviate from the summary.

  For example, in the present embodiment, the configuration in which the first semiconductor chip 123 is disposed in the through hole 114 of the wiring substrate 111 has been described. However, both the first semiconductor chip 123 and the second semiconductor chip 124 are connected to the wiring substrate 111. You may arrange | position so that it may cross-stack on the through-hole 114 of this. However, in the case where both the first semiconductor chip 123 and the second semiconductor chip 124 are arranged, the wiring substrate 11 is multi-layered, leading to an increase in the cost of the wiring substrate 11, and therefore the first semiconductor chip. It is preferable to dispose 123 in the through hole 114.

100 PoP type semiconductor device 101 Lower package 102 Upper package 103 Wiring substrate 104 Semiconductor chip 105 Bump electrode 106 Underfill material 107 Connecting land 108 Mounting land 109 Third electrode pad 110 Third connecting pad 111 Wiring substrate 112 Solder ball 113 Insulating base material 114 Through hole 115 First connection pad 116 Second connection pad 117 Insulating film 118 Opening 119 Land 120 Insulating film 121 Via 122 Solder ball 123 First conductor chip 124 Second semiconductor chip 125 First Electrode pad 126 second electrode pad 127 wire 128 solder layer 129 bump electrode 130 sealing resin layer 131 product forming part 132 dicing line 133 support substrate 500 resin adhesive layer 700 gap (gap)

Claims (17)

First and second sides facing each other, an opening that is longer than the first and second sides and defined by the third and fourth sides facing each other, and the first and second sides A wiring substrate having a plurality of first connection pads arranged along the third side and a plurality of second connection pads arranged along the third and fourth sides;
It has a substantially rectangular plate shape and has a plurality of first electrode pads arranged along the short side of one surface, and the plurality of first electrode pads are electrically connected to the plurality of first connection pads, respectively. A first semiconductor chip that is connected and arranged in the opening of the wiring board such that each of the short sides faces the first and second sides;
It has a substantially rectangular plate shape and has a plurality of second electrode pads arranged along the short side of one surface, and the plurality of second electrode pads are electrically connected to the plurality of second connection pads, respectively. A second layer connected to the first semiconductor chip and connected to the first semiconductor chip such that each of the short sides exceeds the third and fourth sides and the one surface faces the first semiconductor chip. Semiconductor chip,
A semiconductor device comprising: a sealing portion formed to cover the first semiconductor chip and the second semiconductor chip. The plurality of first electrode pads of the first semiconductor chip are electrically connected to the plurality of first connection pads of the wiring board via a plurality of bonding wires, respectively.
The plurality of second electrode pads of the second semiconductor chip are electrically connected to the plurality of second connection pads of the wiring board via a plurality of bump electrodes, respectively. The semiconductor device according to claim 1.   The semiconductor device according to claim 1, wherein the opening is formed in a substantially central region of the wiring board so as to penetrate from one surface to the other surface of the wiring substrate.   4. The semiconductor device according to claim 1, wherein a plurality of lands are formed in two rows along four sides in a peripheral region on the other surface of the wiring board. 5.   5. The semiconductor device according to claim 4, wherein the lands corresponding to the first and second connection pads are electrically connected by a predetermined wiring pattern.   6. The semiconductor device according to claim 4, wherein solder balls serving as external electrodes are mounted on the plurality of lands.   7. The semiconductor device according to claim 1, wherein the first and second semiconductor chips are memory chips and have substantially the same circuit configuration and substantially the same chip size. 8.   The said 2nd semiconductor chip is laminated | stacked and arrange | positioned on the said 1st semiconductor chip so that it may cross | intersect with respect to the said 1st semiconductor chip, The any one of Claim 1 to 7 characterized by the above-mentioned. The semiconductor device described.   9. The bump electrode according to claim 2, wherein the bump electrode includes a columnar body protruding at a predetermined height from the one surface of the second semiconductor chip, and a solder layer formed on the top of the columnar body. The semiconductor device according to any one of the above.   The said sealing part is formed so that the clearance gap formed between the said opening part of the said wiring board and the said 1st semiconductor chip may be covered. 2. A semiconductor device according to item 1.   11. The second semiconductor chip is disposed on the wiring board by flip chip mounting so that the short side protrudes outside the opening of the wiring board. The semiconductor device according to any one of the above.   The semiconductor device according to claim 1, wherein a gap is formed between the first semiconductor chip and the second semiconductor chip.   The semiconductor device according to claim 1, wherein the sealing portion is formed so as not to protrude from the other surface of the wiring board.   14. The semiconductor device according to claim 1, wherein a resin layer is disposed in the opening so as to cover the other surface of the first semiconductor chip.   15. The semiconductor device according to claim 1, wherein a gap is formed below the first semiconductor chip in the opening of the wiring board.   The semiconductor device according to claim 1, wherein the other surface of the second semiconductor chip is disposed so as to be exposed from the sealing portion.   17. The semiconductor device according to claim 1, wherein the second semiconductor chip is arranged in the opening of the wiring board.

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