JP2015106900A - Ad conversion processing apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an AD conversion processing apparatus in which the data amount of map data can be reduced somewhat.SOLUTION: A map data composed of an incomplete sample data is used for both AD conversion of limited voltage range Vam1 and AD conversion of limited voltage range Vam2. More specifically, one map data is used for a plurality of limited voltage ranges, and a solution (incomplete sample data) is acquired based on one map data for any voltage range. When the information about the limited voltage ranges Vam1, Vam2 is given, this incomplete sample data becomes the complete sample data representing the all range of inspection range Vam.

Description

  The present invention relates to an AD conversion processing apparatus, and is particularly suitable for use in reducing the data configuration used for AD conversion.

  For example, Japanese Utility Model Laid-Open No. 60-064641 (Patent Document 1) introduces a technique related to a lamp type AD conversion processing apparatus. As shown in FIG. 8, the ramp type AD conversion processing device compares the ramp waveform voltage Vr and the voltage to be inspected Vin, counts the pulse period Δtk of the comparison result, and based on the count value CNT, the voltage to be inspected Vin The voltage value data is acquired.

Japanese Utility Model Publication No. 60-064641

  Depending on the A / D conversion processing, the map data (map information) in which the correspondence between the data indicating the count value CNT and the data indicating the voltage to be inspected is matrixed when acquiring the voltage value data of the voltage to be inspected Vin described above. May be used. In this case, since the data amount of the map data is affected by the number of quantization bits of the voltage to be inspected Vin, the data amount becomes enormous depending on the setting of the resolution.

  In view of the above problems, an object of the present invention is to provide an AD conversion processing apparatus that can reduce the data amount of map data to some extent.

In order to solve the above problems, the present invention has the following configuration of an AD conversion processing apparatus. That is, a voltage range specifying circuit unit that outputs a first signal in which a limited voltage range to which the voltage to be inspected belongs is output, and a waveform generation circuit that switches a reference value of the switching waveform voltage based on the first signal. A signal comparison circuit unit for outputting a second signal obtained by comparing the voltage signal representing the switched waveform voltage and the voltage signal representing the voltage to be inspected, and digital data relating to the voltage value of the voltage to be inspected. And a data creation circuit section to be created,
The data generation circuit unit generates data based on the second signal, which is the first digital data representing the voltage value of the voltage to be inspected with respect to the limited voltage range.

  Preferably, the data generation circuit unit generates second digital data corresponding to the first signal, and bit-combines the second digital data and the first digital data.

  The second digital data may be 1-bit data. The switched waveform voltage is preferably a linear ramp wave.

  According to the AD conversion processing apparatus of the present invention, one map data is used for a plurality of limited voltage ranges, and the entire range of the inspection range is calculated based on incomplete sample data created based on the map data. Create complete sample data of interest. For this reason, in the process of sampling based on the limited voltage range, it is sufficient to perform quantization for a part of the entire inspection range, and accordingly, the amount of map data can be reduced. .

The figure which shows the circuit structure of the lamp | ramp type AD conversion processing apparatus which concerns on embodiment. The time chart of the various signals etc. which concern on embodiment. The figure which compares and demonstrates the ramp waveform of a prior art example, and the ramp waveform which concerns on this Embodiment. The figure which compares the data creation process of a prior art example, and the data creation process which concerns on this Embodiment. 1 is a diagram illustrating a circuit configuration of a lamp type AD conversion processing apparatus according to Embodiment 1. FIG. FIG. 6 is a diagram illustrating a circuit configuration of a lamp type AD conversion processing apparatus according to a second embodiment. The figure explaining the state of the switching type ramp waveform which concerns on Example 2. FIG. The time chart of the various signals etc. which concern on a prior art example. The figure explaining the state of resolution concerning a conventional example.

  Hereinafter, embodiments (and Examples 1 to 2) according to the present invention will be specifically described with reference to the drawings. FIG. 1 shows a configuration of an AD conversion processing apparatus according to the present embodiment. As illustrated, the AD conversion processing apparatus 100 includes an input circuit configuration of a detected voltage Vin, a first threshold voltage generation circuit 110, a ramp wave generation circuit 120, and a programmable control unit 130.

  The voltage to be inspected Vin is a voltage to be detected or a signal representing it, and may be the same value as the voltage Vin or a value proportional to the voltage Vin. The voltage to be inspected Vin is adjusted by the input circuit configuration, and is supplied to the programmable control unit 130 via the signal line Li1.

  As shown in the figure, the first threshold voltage generation circuit 110 is a circuit that generates and outputs a threshold voltage Vth having a constant value. In the present embodiment, the constant voltage Vref1 (first constant voltage) generated by a regulator or the like is adjusted by the voltage dividing resistors R1 and R2, and the threshold voltage Vth is generated.

  The ramp wave generation circuit 120 includes a plurality of resistance elements R3 to R5 and a capacitor C, which are wired appropriately. The ramp wave generation circuit 120 receives a pulse signal via the signal line Ls1 and the resistor R5, and generates a ramp waveform voltage Vrp based on the received pulse signal. Also, the ramp wave generation circuit 120 receives a signal (first signal) for forming an offset voltage via the signal line Ls2 and the resistor R4, and forms an offset voltage ΔV based on this signal.

  These actions are performed by the capacitor C, and charges are accumulated and discharged by both the pulse signal and the first signal, and the ramp waveform voltage Vrp and the offset voltage ΔV are synthesized. Therefore, the ramp wave generation circuit 120 changes / switches the reference value of the ramp waveform voltage Vrp based on the first signal. The ramp wave generating circuit 120 outputs the switchable ramp waveform voltage Vrp (hereinafter referred to as a switchable ramp waveform voltage Vrp), and the signal Vrp is sent to the programmable control unit 130 via the signal line Li3. Sent.

  The input circuit configuration, the first threshold voltage generation circuit 110, and the ramp wave generation circuit 120 described above are mounted on the board outside the programmable control unit 130. Hereinafter, the programmable control unit 130 used in the present embodiment will be described.

  The programmable control unit 130 refers to, for example, a PLD (Programmable Logic Device) or an FPGA (Field Programmable Gate Arrays), and an element whose appropriate function is configured by a program provided corresponding thereto. Say. Such a device can calculate an appropriate result according to a given signal, and can perform this calculation processing in parallel. Therefore, even if a plurality of signals are input at a time, the programmable controller can simultaneously execute individual arithmetic processing based on the signals.

  In the present embodiment, an FPGA is used as the programmable control unit. As shown in the figure, the FPGA 130 includes I / O blocks 131a and 131b, a digital clock manager 132, a logic block 133, a RAM block, a multiplication block, and the like as an architecture.

  The I / O blocks 131a and 131b are provided with various interface functions in addition to LVDS and LVCMOS. Among these, LVDS is an abbreviation for “Low Voltage Differential Signaling” and transmits a signal having a small voltage amplitude in a differential manner. This LVDS is characterized by being capable of high-speed data transmission, and is hereinafter referred to as differential interface function units LVDS1 and LVDS2.

  In the differential interface function unit LVDS1 (one configuration of the voltage range specifying circuit unit), the voltage to be tested Vin is input to the non-inverting input terminal, and the threshold voltage Vth is input to the inverting input terminal. Then, the differential interface function unit LVDS1 (one configuration of the voltage range specifying circuit unit) outputs a comparison result between the voltage under test Vin and the threshold voltage Vth as the first signal Sh. The first signal Sh is a signal indicating which voltage range (limited voltage range) the inspected voltage Vin belongs to.

  In the differential interface function unit LVDS2 (signal comparison circuit unit), the voltage to be tested Vin is input to the non-inverting input terminal, and the switching ramp waveform voltage Vrp is input to the inverting input terminal. Then, the differential interface function unit LVDS2 (signal comparison circuit unit) compares the voltage signal representing the voltage to be inspected Vin with the voltage signal representing the switchable ramp waveform voltage Vrp, and signals the period when the ramp wave is large as a pulse waveform. Output. Hereinafter, the signal acquired in this way is referred to as a second signal Sce.

  LVCMOS is an abbreviation for “Low Voltage Complementary Oxide Semiconductor”, and is set to “HIGH level output” or “LOW level output” depending on whether or not the input signal is above a threshold value. The LVCMOS of the I / O block 131a outputs 3.3V (HIGH value) when the input signal has a HIGH value, and outputs 0V (LOW value) when the input signal has a LOW value. This “0V” is sometimes referred to as a GND level when it matches the GND potential. In the present embodiment, it is assumed that the second interface function unit LVCMOS1 and the pulse output interface function unit LVCMOS2 are configured in the I / O block 131a as LVCMOS having a function corresponding to this.

  Accordingly, the second interface function unit LVCMOS1 determines the threshold value of the input signal value, and appropriately switches the first signal to be 3.3V (HIGH value) or GND value (LOW value) to the outside. Output. Further, when a pulse signal is input, the pulse output interface function unit LVCMOS2 outputs the pulse signal composed of 3.3 V (HIGH value) and a GND value (LOW value) in the external direction.

  As described above, the I / O blocks 131a and 131b have a function of taking a certain signal into the FPGA 130 by controlling the interface function unit, and a function of outputting another certain signal to the outside of the FPGA 130. Take on. Hereinafter, a signal input to the inside of the FPGA 130 via the I / O block and its operation are referred to as internal direction input, and a signal to be output to the outside of the FPGA 130 via the I / O block Sometimes called.

  In FIG. 1, the internal configuration of the I / O block 131b is not clearly shown. However, here, it is assumed that an interface function unit similar to the I / O block 131a is configured, and output data of the logic block 133 is output via an appropriate interface function unit.

  The digital clock manager 132 is a functional unit that provides a clock signal to the entire FPGA 130, and this function realizes “Phase Lock Loop Control”. That is, each circuit unit whose function is constructed in the logic block 133 is uniformly controlled by this clock signal, and synchronous signal processing is performed.

  The logic block of the FPGA 130 is obtained by integrating a plurality of elements. The element includes a lookup table, a multiplexer, and a register, which are connected to each other by an interconnect. In this logic block, the connection path can be freely changed by controlling a switch mechanism provided in the interconnect (programmable function).

  As shown in the figure, the logic block 133 according to this embodiment has a switching command circuit unit 133a, a pulse signal generation circuit unit 133b, and a data generation circuit unit 133c that are functionally constructed. Among these, the pulse signal generation circuit unit 133b generates a predetermined pulse signal based on the input clock signal, and outputs the pulse signal to the second interface function unit LVCMOS2.

  The switching command circuit unit 133a receives the first signal Sh and outputs a value detected at each clock timing as the switching signal Sq. This switching signal Sq is given to the ramp wave generation circuit 133c through a signal line, and issues an offset voltage setting command. Further, the signal Sq is also supplied to the ramp wave generation circuit 120 via the function unit when the second interface function unit LVCMOS1 is connected to the signal line. That is, in the switching command circuit unit 133a according to the present embodiment, one signal Sq is output to a different circuit, and on the one hand, it is used for creating data of the voltage to be inspected Vin, and on the other hand, switching of the ramp waveform voltage is commanded. It will be.

  The switching command circuit unit 133a described above is configured as one configuration of the voltage range specifying circuit unit in the claims. In this embodiment, the voltage range specifying circuit unit is configured by the combination of the differential interface function unit LVDS1 and the switching command circuit unit 133a to generate and output the first signal Sq. As described above, the first signal Sq is a signal indicating which voltage range (limited voltage range) the voltage under test Vin belongs to.

  The data generation circuit unit 133c receives the second signal Sce, the switching signal Sq, and the clock signal CLK. Based on these signals, the data creation circuit unit 133c expresses the voltage value of the voltage to be inspected Vin as digital data. The details of the data creation processing in the data creation circuit unit 133c will be clarified later.

  As described above, since the ramp-type AD conversion processing apparatus 100 according to the present embodiment is a programmable control unit in which the main circuit unit is functionally constructed, it has the advantages of simultaneous processing related to AD conversion and high-speed processing associated therewith. Appears prominently.

  Further, since the lamp type AD conversion processing apparatus 100 uses the LVDS mounted on the I / O block as a comparator, the circuit configuration can be simplified both inside and outside the FPGA 130. Furthermore, since the signal amplitude of the LVDS is sufficiently narrower than that of each of the comparators, the input signal comparison process can be performed at high speed.

  FIG. 2 is a time chart showing the operation of the lamp type AD conversion processing apparatus according to the present embodiment. FIG. 2A shows the voltage state of the input terminal in the differential interface function unit LVDS1. Here, it is assumed that the voltage to be inspected Vin gradually increases from a convergence state at a low potential and then changes to a convergence state at a higher potential (simple increase). Therefore, the threshold voltage Vth is a constant value, and both voltages intersect in one scene. Hereinafter, this time is referred to as tc.

  FIG. 2B shows an output terminal in the differential interface function unit LVDS1, that is, the first signal Sh. The differential interface function unit LVDS1 outputs a signal in the LOW state (first signal Sh) when the voltage to be inspected Vin is lower than the threshold voltage Vth (50% of 3.3V, that is, 1.65V). On the other hand, when the voltage under test Vin is higher than the threshold voltage Vth, the interface function unit LVDS1 outputs a HIGH state signal (first signal Sh). In this way, the differential interface function unit LVDS1 switches the setting command signal Sh from the LOW value to the HIGH value before and after the time tc when both input values intersect.

  Note that the switching signal Sq output from the switching command circuit unit 133a is a signal obtained by tracing the input signal Sh at every clock timing, and shows a waveform substantially equivalent to the signal Sh. Thus, the switching signal Sq may be referred to as the first signal Sq where it is substantially the same as the first signal Sh.

  FIG. 2C shows the state of the input terminals in the differential interface function unit LVDS2. As shown in the figure, the voltage to be inspected Vin is applied to the non-inverting input terminal (+) of the LVDS 2, and the switching ramp waveform voltage Vrp is applied to the inverting input terminal (−) of the LVDS 2.

  Before the time tc, the switching signal Sq (first signal Sq) is set to the LOW value, so that the ramp wave generation circuit 120 in the scene where the signal Sq is input has the offset voltage ΔV in the voltage value direction. “0V” is set, and the reference value of the ramp waveform is set to “0V”. Hereinafter, the offset voltage ΔV in this state is referred to as a first offset amount ΔV1.

  After the time tc, the switching signal Sq is set to the HIGH value, and therefore the ramp wave generation circuit 120 in the scene where the signal Sq is input is substantially given the offset voltage ΔV in the voltage value direction. Thus, the switching ramp waveform voltage Vrp according to the present embodiment is offset in the voltage direction in accordance with the switching signal Sq, and the switching range of the switching ramp waveform voltage Vrp covers the variation range of the voltage to be inspected Vin. To cover. Since this switching signal Sq is a signal indicating whether or not the inspection voltage Vth has reached the intermediate point (1.65 V) of the inspection range Vam (3.3 V), it is matched with the change in the inspection voltage Vin. A ramp waveform suitable for this will be specified.

  In the future, the inspection ranges Vam1 and Vam2 that the switchable ramp waveform is in charge of will be referred to as limited voltage ranges. Since this limited voltage range is limited to a partial range of the inspection range Vam, it can be combined with a different range to cover the entire range of the inspection range Vam.

  In particular, the offset voltage ΔV according to the present embodiment includes a first offset amount ΔV1 (ΔV1 = 0V) and a second offset amount ΔV2 (ΔV2 = 1.65V) as offset amounts given to the reference value of the ramp waveform voltage. ). According to this, since the second offset amount ΔV2 substantially coincides with the limited voltage range Vam1 (1.65 V), the switching ramp waveform voltage Vrp after time tc is the switching ramp waveform voltage Vrp before time tc. Is assigned to the region of the inspection range Vam that could not be arranged. For this reason, in the present embodiment, it is possible to handle the entire range of the inspection range Vam (3.3 V) with two ramp waveform voltages, and this switching operation can be realized by one switching signal Sq.

  FIG. 2D shows the waveform of the second signal Sce output from the differential interface function unit LVDS2. The second signal Sce is a pulse waveform having a HIGH value only when “Vrp> Vin”. Therefore, the signal Sce indicates the value of the voltage to be inspected Vin according to the period for establishing this relationship, and the change in the period represents the change in the voltage to be inspected Vin.

  In particular, in the present embodiment, since the ramp wave Vrp is switched at the time tc, the pulse period of the signal Sce decreases (indicating an increase in Vin). The pulse period decreases from the increased state (indicating an increase in Vin). What is important here is that the pulse period of the signal Sce temporarily increases in the vicinity of the time tc. This is because the ramp wave Vrp is switched, which indicates a decrease in the voltage to be inspected Vin. Note that this is not the case.

  FIG. 2E shows a result value (hereinafter, a count value CNT) obtained by counting the second signal Sce at each count timing. The count value CNT is counted by the data creation circuit unit 133c of the logic block 133. In this counting process, when the second signal Sce is set to the HIGH value and the clock time (clock signal CLK) arrives, the count value CNT is incremented by one point every time this condition is satisfied. In this process, when the falling edge of the ramp wave Vrp arrives, the period measurement in the detection cycle, that is, the counting of the count value replaced as the period (creation of count data) is completed.

  The count timing described above corresponds to the timing of the control clock, that is, the clock timing. However, the clock timing may be multiplied to obtain the count timing. Similarly to the count timing, when it is called a count frequency, it means a clock frequency.

  The data creation circuit unit 133c creates data with the switching signal Sq as 1-bit data independently of the count value CNT counting process (range limited data creation process). This 1-bit data is a signal indicating whether or not the signal Sq is larger than 1.65V. For example, when the data is “0”, the voltage to be inspected Vin is “0V ≦ Vin <1.65V”. ”And when the data is“ 1 ”, it indicates that the voltage to be inspected Vin belongs to the range of“ 1.65 V ≦ Vin ≦ 3.3 V ”. Hereinafter, this 1-bit data may be referred to as second digital data.

  As described above, the data creation circuit unit 133c according to the present embodiment is capable of performing various digital data related to the voltage to be inspected Vin, such as count value CNT data, 1-bit data, and other imperfect or complete sample data described later. Create

  As shown in FIG. 1, in the element responsible for the conversion data creation process in the logic block 133, map data describing the correspondence between both the count value CNT data and the bit data obtained by quantizing the limited voltage range. Is stored and recorded. This map data is information indicating bit data (hereinafter referred to as sample data or first digital data) corresponding to the count data CNT when given.

  The sample data (first digital data) is obtained by quantizing the limited voltage range with “n−1” bit data. In this embodiment, the inspection range (3.3 V) is set to “n−”. The value divided by “1” bits is the minimum scale as the sample value. Therefore, the sample data is incomplete data representing a part of the voltage value data Sd. As shown in FIG. 4A, this incomplete sample data does not incorporate information indicating a limited voltage range, and is data expressed only in that range.

  Map data (map information) composed of such sample data is used for both the AD conversion of the limited voltage range Vam1 and the AD conversion of the limited voltage range Vam2. That is, in the present embodiment, one map data is used for a plurality of limited voltage ranges, and a solution (incomplete sample data) is acquired based on the one map data for any voltage range. The incomplete sample data becomes complete sample data expressing the entire range of the inspection range Vam if information on the limited voltage ranges Vam1 and Vam2 is given.

  As described above, according to the AD conversion processing apparatus 100 according to the present embodiment, one map data is used for a plurality of limited voltage ranges Vam1 and Vam2, and incomplete sample data created based on the map data. As a basis, complete sample data is created for the entire inspection range Vam. For this reason, in the process of sampling based on the limited voltage range, it is sufficient to perform quantization for a part of the entire inspection range, and accordingly, the amount of map data can be reduced. .

  In the data creation circuit unit 133c, the incomplete sample data and the second digital data (bit data indicating a limited voltage range) are bit-coupled. The bit data thus obtained has a data configuration in which the entire inspection range Vam is quantized with “n” bit data, and is complete sample data Sd expressing the inspection range Vam. The sample data Sd is output from the I / O block 131b of the FPGA 130 and supplied to a microcomputer memory circuit or the like via a communication line (see FIGS. 1 and 2F).

  In the present embodiment, since the second digital data is 1-bit data, information indicating the limited voltage range is expressed by the minimum bit data. Therefore, the complete sample data Sd has a simple data structure accordingly.

  In this embodiment, a ramp waveform is used, but any waveform may be used as long as it can be used for AD conversion. For example, when a linear gradient wave (sawtooth wave or the like) is used instead of the ramp wave, the correspondence between the count value and the sample data Sd is simplified, and the data amount of the map data can be further reduced. Let's go. Here, the switching-type periodic waveform voltage using the ramp waveform or the ramp waveform is referred to as a switching-type waveform voltage. A circuit that generates such a switched waveform voltage is referred to as a waveform generation circuit.

  Hereinafter, the relationship between the count frequency and the resolution related to the AD conversion process will be described with reference to FIG. As described above, in the conventional technique, the amplitude of the ramp wave Vr is set so as to substantially match the inspection range Vam (0 V to 3.3 V) (see FIG. 3A). Here, a period during which the ramp waveform Vr is maintained at the reference value is referred to as a preparation period Δtx1, and a period during which an actual ramp wave is formed in the ramp waveform Vr is referred to as a ramp period Δty1. Therefore, when the sum of the preparation period Δtx1 and the ramp period Δty1 is one cycle of the ramp waveform, this is referred to as a cycle Δt1.

  In general, in the AD conversion processing technique, a sampling frequency that is larger by a predetermined amount than the frequency of the voltage to be inspected must be set from the viewpoint of optimization of the sample rate and aliasing problems. In the AD conversion processing device, a count frequency (clock frequency) that can ensure the accuracy of sampling (setting of element time) is set, and a sample value of the voltage to be inspected is obtained at each count timing determined by the count frequency. (Quantization).

  Therefore, in the ramp type AD conversion processing apparatus, when setting the frequency of the ramp waveform high, if there is a margin in sampling of the count time, the count frequency (clock frequency) of the count value is set to be increased, thereby degrading the resolution. Can be avoided (see comparison between FIG. 9A and FIG. 9B).

  However, if there is no allowance for sampling of the count time, the count frequency (clock frequency) cannot be further increased so as not to cause a decrease in accuracy of the count time. In this case, as shown in FIG. 9 (b2), since the change in the count frequency does not correspond to the change in the cycle of the ramp waveform voltage Vr, the number of updates of the count value CNTb is smaller than in FIGS. 9 (a) and 9 (b). Will be reduced. That is, in such a case, the resolution is effectively reduced.

  As described above, in the AD conversion processing apparatus according to the related art, it has been difficult to achieve both the increase in the frequency of the ramp voltage waveform and the maintenance of the resolution. On the other hand, in the AD conversion processing apparatus according to the present embodiment, the problem is solved satisfactorily by using the switching waveform voltage. This will be described in detail below.

  FIG. 3B shows a switchable ramp waveform voltage Vrp according to the present embodiment. As shown in the figure, the inspection range Vam with respect to the voltage to be inspected Vin is 0V to 3.3V, and the amplitudes Vam1 and Vam2 of the switching ramp waveform voltage Vrp are each 1.65V. Therefore, the switching lamp waveform voltage on the lower stage side is in charge of 0V to 1.65V, and the switching lamp waveform voltage on the upper stage side is in charge of 1.65V to 3.3V.

  The switchable ramp waveform voltage Vrp is such that the preparation period Δtx2 satisfies the relationship “Δtx2 = Δtx1 / 2”, and the ramp period Δty2 satisfies the relationship “Δty2 = Δty1 / 2”. Therefore, the period Δt2 (Δtx2 + Δty2) is a half period of the period Δt1. That is, when attention is paid to two continuous switchable ramp waveform voltages Vrp, the sum of the preparation periods Δtx2 coincides with the preparation period Δtx1 of the normal ramp waveform, and the sum of the ramp periods Δty2 is the lamp period Δty1 of the normal ramp waveform. Matches. Further, the switchable ramp waveform voltage Vrp is set to be switched so that the inspection range Vam is set to 0 V to 3.3 V. The inspection range Vam also matches that of a normal ramp waveform. That is, the conditions of the two consecutive switchable ramp waveform voltages Vrp are the same for each element of the inspection range Vam, the preparation period 2 · Δtx2, the ramp period 2 · Δty2, and the cycle Δt1.

  Therefore, the switchable ramp waveform voltage Vrp according to the present embodiment is set to the half of the cycle Δt2 of the ramp waveform while keeping the inspection range Vam the same as compared with the normal ramp waveform Vr. I understand. That is, the switching-type ramp waveform voltage Vrp has its frequency set to twice that of the normal ramp waveform Vr.

  In particular, in the present embodiment, the count timing for incrementing the count value CNT is not divided. That is, in the present embodiment, the count timing of the same time interval as that in FIG. In the present embodiment, as shown in FIG. 4A, when the voltage to be inspected Vin belongs to the range of 0V to 1.65V, the count value CNT1 is acquired using the lower ramp waveform Vrp1. Further, as shown in FIG. 4B, when the voltage to be inspected Vin belongs to the range of 1.65V to 3.3V, the count value CNT2 is obtained using the ramp waveform Vrp2 on the upper stage side.

  Accordingly, since the inspection ranges of the ramp waveforms Vrp1 and Vrp2 are half of the entire inspection range Vam, each quantization process for the divided inspection ranges can be performed without dividing the count timing. This can be done without reducing the resolution. In this embodiment, since any value of the entire inspection range Vam can be detected by switching the ramp waveforms Vrp1 and Vrp2, AD conversion is performed without reducing the resolution without dividing the count timing in half. .

  On the other hand, when the switching ramp waveform voltage is not used, the same level of resolution as in the present embodiment cannot be maintained unless the count timing is divided according to the increase in the frequency of the ramp waveform Vr. 4D and 4E show the same count timing as that of the present embodiment (FIGS. 4A and 4B). According to this, even if the count timing is the same, it is different from the detection condition in the present embodiment in that the object of the inspection range that the count timing should bear is the entire range (Vam). Therefore, according to the prior art (FIGS. 4D and 4E), it means that the resolution is lowered for the sample value of the voltage to be inspected Vin. From this, it is understood that the AD conversion processing according to the present embodiment can sample data with higher resolution than the conventional technique (FIGS. 4D and 4E).

  As described above, according to the lamp type AD conversion processing apparatus 100 according to the present embodiment, the switchable ramp waveform voltage that can be switched in the voltage value direction is used, so that the frequency of the ramp waveform voltage is increased. While maintaining the count frequency of the count value, the resolution of the inspection range assigned to each ramp wave does not deteriorate. In the AD conversion processing apparatus, the switching range of the switchable ramp waveform voltage covers the variation range of the voltage to be inspected, so that the resolution does not need to decrease throughout the entire inspection range. That is, in the present invention, it is possible to increase the frequency of the ramp waveform voltage and maintain the resolution of the sample value.

  Further, according to the ramp type AD conversion processing apparatus 100, the frequency of the count timing is maintained while improving the cycle of the ramp waveform, so that the number of count values can be reduced and the memory area for recording the count value can be reduced. can do.

  In the ramp wave generation circuit 120 according to the present embodiment, the amplitude of the ramp wave is set to be smaller than the entire inspection range Vam, so that the capacitance of the capacitor can be reduced, and the circuit can be reduced in size and size. Cost reduction is achieved.

  This embodiment is based on the configuration of the above-described embodiment, and changes are made to the I / O block 131a and the ramp wave generation circuit 120. Hereinafter, such changes will be described in detail, and other configurations and operations have already been described, and thus description thereof will be omitted.

  FIG. 5 shows a lamp type AD conversion processing apparatus according to the present embodiment. In the lamp type AD conversion processing apparatus 200, an LVCMOS 3 is additionally configured for the I / O block 131a. Along with this change, a signal line is provided between the input portion of the LVCMOS 3 and the pulse signal generation circuit portion 133b, and a pulse signal is sent to the LVCMOS 3 through this signal line.

  The output part of the LVCMOS 3 is always set to the LOW level by an open drain IC or the like. The external direction output performed by the LVCMOS 3 is possible for the LOW level output, but is virtually impossible for the HIGH level output. Thus, the LVCMOS 3 performs an operation of switching the external direction output to the output non-permitted state or the ground state in accordance with the input signal. Hereinafter, a scene in which a high level output is apparently set to an output non-permitted state may be referred to as a high impedance state. The LVCMOS 3 is called a first interface function unit.

  As described in the embodiment, the LVCMOS 2 corresponds to the pulse output interface function unit in the claims. When a pulse signal is input, the pulse output interface function unit LVCMOS2 outputs a corresponding pulse signal as an external direction output. As shown in the figure, since the LVCMOS 2 receives a signal common to the first interface function unit LVCMOS 3, when the external direction output of the function unit LVCMOS 3 is disabled, the external direction output of the function unit LVCMOS 3 is input to the LVCMOS 2. Output as a pulse signal.

  The ramp wave generation circuit 120 is connected between the capacitor C, the resistance element R5 (second resistance element) connected to the signal line Ls1, the resistance element R4 connected to the signal line Ls2, and the resistance elements R4 and R5. A resistance element R3 and a resistance element R6 (first resistance element) connected to the signal line Ls3 (discharge line) are provided.

  According to such wiring, the resistance element R5 (second resistance element) is arranged in the energization path connecting the pulse output interface function unit LVCMOS2 and the capacitor C, so that the pulse signal applied thereto is relayed to the capacitor side. Will be allowed to. Further, since the resistance element R6 (first resistance element) is arranged in the energization path connecting the first interface function unit LVCMOS3 and the capacitor C, the discharge current toward the ground level is relayed in the FPGA direction. . Further, as shown in the figure, the capacitor C is connected to the contact of the resistance element 5 and the resistance element 6 immediately before, and both the pulse signal and the offset voltage ΔV are input through the contact.

  The resistance element R6 (first resistance element) according to the present embodiment has a resistance value lower than that of the resistance element R5 (second resistance element). According to this, in the ramp period Δty2, the external output in the signal line Ls3 is not substantially performed, and the pulse signal (pulse voltage) is output as the external direction output in the signal line Ls1. Immediately after expiration of the ramp period Δty2, the resistance value of the resistance element R6 (first resistance element) is low, so that the charge of the capacitor C is rapidly discharged via the signal line Ls3.

  As described above, according to the lamp-type AD conversion processing apparatus 200 according to the present embodiment, an output path to the capacitor C and a discharge path from the capacitor C are provided, and charging and discharging are performed by switching between these paths, whereby a discharge path (resistor The time constant of the path including the element R6 is suppressed, and the discharge operation immediately after the expiration of the ramp period Δty2 is completed quickly. In this way, an equivalent operation can be realized without using a functional unit that enables high-speed operation in the I / O block.

  In addition, since the preparation period Δtx2 of the ramp waveform voltage Vrp can be shortened, the period Δt1 of the ramp wave is also shortened accordingly, and as a result, the frequency of the ramp waveform voltage Vrp can be set high. . In particular, in such a case, only the preparation period Δtx2 is simply adjusted, so that the resolution is not deteriorated.

  Usually, LVDS has a limited range of common mode voltage than the power supply provided. For example, when the power supply Vps supplied to LVDS is 3.3 V, there is a common mode voltage between 0.5 V (lower limit value) and 2.5 V (upper limit value). Thus, when the inspection range Vam is limited with respect to the power supply voltage Vps, the input value of the voltage to be inspected Vin must be adjusted in the AD conversion process. Hereinafter, a technique relating to adjustment of the voltage to be inspected Vin will be described.

  As illustrated in FIG. 6, in the lamp-type AD conversion processing device 300 according to the second embodiment, an input value adjustment circuit 140 is added between the voltage to be inspected Vin and the differential interface function unit LVDS2. The input value adjustment circuit 140 includes a constant voltage Vref2 (second constant voltage) generated by a regulator or the like and resistance elements R7 to R10.

  Among these, the resistance elements R7 and R8 are connected in series, one end is connected to the constant voltage Vref2 and the other end is connected to the ground level. These constitute an offset circuit, and an offset adjustment value ΔVq is output from the voltage dividing point.

  The resistance elements R9 and R10 are also connected in series with each other, one end is connected to the voltage to be inspected Vin and the other end is connected to the voltage dividing point of the offset circuit. These constitute a voltage dividing circuit, and limit the range of the inspected voltage Vin in the voltage direction.

  The functions of the offset circuit and the voltage dividing circuit will be described with reference to FIG. In the present embodiment, since the LVDS common mode voltage is set to the inspection range Vam, only the common mode voltage range of the voltage to be inspected Vin is detected by AD conversion. On the other hand, since the voltage dividing circuit can change the input value proportionally, it compresses this in the voltage direction from the voltage to be inspected Vin, and the voltage to be inspected (correctly, the voltage to be inspected after compression adjustment) is compressed. It can be within the inspection range Vam.

  The offset circuit gives an offset adjustment value ΔVq to the lower limit value of the power supply voltage Vps. When this offset adjustment value ΔVq is set, the other end adjustment value ΔVp is also set accordingly. Therefore, the offset circuit can adjust the voltage to be inspected Vin in the voltage direction by appropriately setting the adjustment value ΔVq.

  In the present embodiment, since both the offset circuit and the voltage dividing circuit are employed, the proportional adjustment and the offset adjustment of the voltage to be inspected Vin are made possible. For example, it is assumed that the common mode voltage is in the range of 0.5 V (lower limit value) to 2.5 V (upper limit value), and the fluctuation range of the voltage under test Vin before adjustment is 0 V to 3.3 V. In this case, in this embodiment, the fluctuation range of the inspected voltage Vin before adjustment is proportionally adjusted to “middle point ± 0.83 V”, and the offset adjustment value ΔVq is set to “0.8 V (offset adjustment value)”. . According to this, the voltage to be inspected Vin fluctuates in the range of “0.8 V ≦ Vin ≦ 2.46 V”, so that it is within the common mode voltage range.

  Vin voltage to be inspected, ΔV offset voltage, CNT count value, Vrp switching type ramp waveform voltage, 100 ramp type AD converter, 133c data creation circuit unit, 130 programmable control unit (FPGA), 131a to 131b I / O block, LVDS1 ~ LVDS2 Differential interface function unit.

Claims (4)

A voltage range specifying circuit unit that outputs a first signal in which a limited voltage range to which the voltage to be inspected belongs is output; a waveform generation circuit that switches a reference value of a switchable waveform voltage based on the first signal; A signal comparison circuit unit that outputs a second signal obtained by comparing a voltage signal representing a switched waveform voltage and a voltage signal representing the voltage to be inspected, and digital data relating to the voltage value of the voltage to be inspected are created. A data creation circuit unit,
The data generation circuit unit generates data based on the second signal, which is first digital data representing the voltage value of the voltage to be inspected with respect to the limited voltage range. Processing equipment.   2. The data creation circuit unit creates second digital data corresponding to the first signal, and bit-combines the second digital data and the first digital data. The AD conversion processing apparatus according to 1.   The AD conversion processing apparatus according to claim 2, wherein the second digital data is 1-bit data.   The AD conversion processing apparatus according to claim 1, wherein the switching waveform voltage is a linear ramp wave.

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