JP2015106790A - Power amplifier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a digitally controlled power amplifier that operates with low power consumption and has high output conversion efficiency η.SOLUTION: According to the present invention, in the digitally controlled power amplifier including at least one power amplifier connected to an output line, the at least one switch part includes a first transistor for supplying a switching current to the output line, and a drive circuit for controlling an on/off operation of the first transistor. In the digitally controlled power amplifier, the driver circuit drives the first transistor on the basis of at least part of the switching current flowing through the output line.

Description

  The present invention relates to a power amplifier, and more particularly to a digitally controlled power amplifier using a MOSFET. The present invention also relates to a wireless communication apparatus using such a power amplifier.

  A digital control amplifier (power amplifier) used in a transmission module of a mobile communication terminal capable of RF communication turns on / off a current value of a pulse signal amplified and output based on a digital input signal with respect to a multi-stage thin film switching transistor element. It is a circuit that can be discretely controlled by switching control. The pulse current controlled in this way is converted into a sine wave signal by a predetermined filter circuit and transmitted through the antenna.

  For example, Patent Document 1 below discloses a drive amplifier for a wireless communication device. Specifically, Patent Document 1 discloses an apparatus including a plurality of voltage-current transducers for converting an input signal voltage into a plurality of input signal currents, and a cascode stage. The cascode stage is coupled to a voltage-current transducer to provide amplifier gain control and includes a thin gate oxide transistor and a thick gate oxide transistor.

  Patent Document 2 below discloses a high-frequency power amplifying apparatus for an information processing apparatus provided with a wireless interface. Specifically, Patent Document 2 discloses a control for controlling a power supply voltage from a power supply unit provided between a power amplifier that amplifies a high-frequency input signal and a power amplifier and a power supply unit that supplies a power supply voltage thereto. A high frequency amplifier including a circuit is disclosed. Here, the control circuit generates a control signal by correcting a signal obtained from an input signal to the power amplifier based on a distortion characteristic determined according to the power amplifier, and controls the power supply voltage by the generated control signal. To generate a power supply voltage and supply the generated power supply voltage to the power amplifier. Thereby, the high frequency amplifying apparatus realizes amplification of high frequency power with excellent energy efficiency and less distortion.

  Non-Patent Document 1 below relates to a high-frequency power amplifier for a wireless communication device, and discloses an apparatus including a plurality of transistors for converting an input signal voltage into a plurality of input signal currents and a cascode stage (same as above). Reference FIG. 4). As shown, the cascode stage is coupled to the transistor to implement amplifier gain control and is comprised of a thick gate oxide transistor.

  By the way, a polar modulation method is known as a modulation method used for RF communication. The polar modulation scheme is a modulation scheme that compensates for polar (ie, phase and amplitude) distortion of an RF signal to be transmitted from an antenna. In general, since a digitally controlled power amplifier has a circuit configuration suitable for a polar modulation scheme, use of the digitally controlled power amplifier for a transmission module of a mobile communication terminal apparatus using the polar modulation scheme is progressing.

Special table 2012-532511 gazette JP 2013-074568 A Amirpouya Kavousian, and David K. Su, and Mohammad Hekmat, and Alireza Shirvani, and Senior Member, and Bruce A. Wooley, `` A Digitally Modulated Polar CMOS Power Amplifier With a 20-MHz Channel Bandwidth '' IEEE JOURNAL OF SOLID-STATE CIRCUITS , VOL. 43, NO. 10, OCTOBER 2008

  In general, an electronic device is required to have low power consumption. In particular, a mobile communication terminal device is further reduced in power consumption so that the driving time of an installed battery is as long as possible. Desired. In order to realize low power consumption of such an electronic device, it is typically extremely effective to improve the output conversion efficiency η of a power amplifier used for an internal IC chip.

  The output conversion efficiency η of the power amplifier is a ratio of all power consumption and output power related to the power amplifier, and is caused by the total current related to the power amplifier. In order to improve the output conversion efficiency η, several approaches for reducing the amount of switching current flowing through the thin film switching transistor element have been studied.

  For example, the downsizing of the thin film switching transistor element and the wiring width are effective for reducing the switching current. However, such physical downsizing is not easy because of limitations in the manufacturing process. Setting the switching drive voltage to be low is also effective in reducing the switching current, but this requires an additional circuit including a regulator and a capacitor for controlling the output current. Therefore, power consumption by the additional circuit must be taken into consideration, and a layout area for the circuit is also required. In addition, since the switching speed of the thin film switching transistor element is very high, there is a concern that the regulator circuit cannot follow the high frequency of the RF signal band.

  Further, Patent Document 1 described above is intended to improve the linearity of gain control in the RF drive amplifier transmitter, but does not consider reduction of the switching current of the drive amplifier itself. Specifically, in the drive amplifier of Patent Document 1, the current supplied to the switch is supplied from the power supply of the drive circuit as before.

  Further, Patent Document 2 described above is intended to realize amplification of high-frequency power with excellent energy efficiency and low distortion. In the first place, however, Patent Document 2 obtains the supply power supply voltage from the input / output relationship of the power amplifier by simulation or actual measurement so as to obtain the best energy efficiency, and switches the supply power supply voltage according to the output power of the power amplifier. Thus, energy efficiency is improved, and reduction of switching current is not considered.

  Further, Non-Patent Document 1 described above is intended to improve the linearity of gain control in a high-frequency power amplifier, but does not consider reduction of switching current of the power amplifier itself. In the power amplifier of Non-Patent Document 1, the current supplied to the switch is supplied from the power source of the high-frequency power amplifier as before.

  Further, whenever the digitally controlled power amplifier outputs a short current signal to the output signal line, a current harmonic is generated there. The current harmonic generates a harmonic signal at a frequency that is an integral multiple of the frequency of the output signal. Conventionally, in order to attenuate such a harmonic signal, for example, a Butterworth filter having a large order is required, which causes an increase in component costs of the transmission module.

  Further, in recent years, since the use of digitally controlled power amplifiers for wireless communication terminal devices has been advanced, it is strongly desired to reduce the power consumption of such digitally controlled power amplifiers.

  Accordingly, an object of the present invention is to provide a digitally controlled power amplifier that operates with low power consumption and has high output conversion efficiency η.

  In addition, the present invention provides a digitally controlled power amplifier that suppresses the generation of current harmonics generated when the digitally controlled power amplifier outputs a short current signal as an output signal, thereby reducing the costs associated with harmonic suppression. The purpose is to do.

  The present invention for solving the above problems includes the following technical features or invention specific matters.

  That is, the present invention according to a certain aspect is a digitally controlled power amplifier including at least one power amplifier (switch unit) connected to an output line, and the at least one power amplifier supplies a switching current to the output line. And a drive circuit that controls an on / off operation of the first transistor, the drive circuit based on at least a part of the switching current flowing through the output line. A digitally controlled power amplifier that drives the first transistor.

  According to such a digitally controlled power amplifier, since at least a part of the switching current is used for driving the on / off operation of the first transistor, the current consumption can be reduced.

  Here, the first transistor may be a thin film transistor or a thick film transistor.

  The drive circuit may include an inverter circuit connected to the gate of the first transistor. The inverter circuit is configured to operate based on at least a part of the switching current to supply a switch control signal to the gate of the first transistor.

  The inverter circuit is configured to operate according to a potential difference between a drain and a source of the first transistor. Note that when the first transistor is a thick film transistor, the inverter circuit may be a thick film transistor.

  Further, the at least one power amplifier may include a second transistor cascode-connected to the first transistor.

  Here, the second transistor may be a thick film transistor.

  Furthermore, the digitally controlled power amplifier has a pair of differential input terminals and an output terminal, one of the pair of differential input terminals is connected to a predetermined reference potential, and the other of the at least one power amplifier. An operational amplifier connected to the source of the second transistor and having an output terminal connected to the gate of the second transistor of the at least one power amplifier may be further provided.

  The at least one power amplifier may include a third transistor cascode-connected to the first transistor.

  Further, it may further include at least one delay circuit provided between the first transistor and the inverter circuit.

  The digitally controlled power amplifier is configured to include a plurality of the power amplifiers connected in parallel to the node of the output line.

  The present invention according to another aspect is a wireless communication apparatus including a transmission module including the digitally controlled power amplifier configured as described above.

  The present invention according to another aspect further includes a bias circuit that generates and outputs a reference voltage signal and a current control voltage signal having a predetermined potential, and an operational amplifier that amplifies the reference voltage signal output from the bias circuit according to a predetermined gain. And based on the amplified reference voltage signal output from the operational amplifier and the current control voltage signal output from the bias circuit, connected to the operational amplifier and connected in parallel to the node of the output line. A plurality of power amplifiers for outputting a switching current to the output line, each of the plurality of power amplifiers controlling a turn-on / off operation of the transistor by a switch control signal. A drive circuit that outputs a switch control signal for performing the operation, wherein the drive circuit includes the output line. Wherein generating a switch control signal based on at least a portion of the switching current flowing to drive the transistor, a digitally controlled power amplifier.

  According to the present invention, the digitally controlled power amplifier can operate with low power consumption and have high output conversion efficiency η.

  In addition, according to the present invention, it is possible to suppress the generation of harmonics generated when the digitally controlled power amplifier outputs a short current signal as an output signal, thereby suppressing the harmonic suppression cost.

  Other technical features, objects, effects, and advantages of the present invention will become apparent from the following embodiments described with reference to the accompanying drawings.

It is a block diagram for demonstrating an example of a structure of the radio | wireless communication apparatus containing the digital control power amplifier which concerns on one Embodiment of this invention. It is a schematic circuit diagram which shows an example of a structure of the digital control power amplifier which concerns on one Embodiment of this invention. It is a schematic circuit diagram which shows an example of a structure of the power amplifier in the digital control power amplifier which concerns on one Embodiment of this invention. It is a figure which shows the schematic circuit diagram of a structure of the 1st power amplifier shown in FIG. FIG. 4 is a diagram showing a schematic circuit diagram of a configuration of second to Nth power amplifiers shown in FIG. 3. It is the figure which showed the relationship between the output voltage and current consumption in the digital control power amplifier which concerns on one Embodiment of this invention by numerical calculation simulation. It is a figure which shows the other example of the schematic circuit structure of the power amplifier in the digital control power amplifier which concerns on one Embodiment of this invention. It is a figure which shows the further another example of the schematic circuit structure of the power amplifier in the digital control power amplifier which concerns on one Embodiment of this invention. It is a figure which shows the other example of the schematic circuit structure of the power amplifier in the digital control power amplifier which concerns on embodiment of this invention. It is the figure which showed the relationship between output current and elapsed time by the numerical calculation simulation in the digital control power amplifier which concerns on one Embodiment of this invention.

  Next, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram for explaining an example of the configuration of a wireless communication apparatus including a digitally controlled power amplifier according to an embodiment of the present invention. As shown in the figure, the wireless communication device 1 includes, for example, a control circuit 10, a transmission module 20, a transmission / reception duplexer 30, an antenna 40, a reception module 50, and a power supply device 60. The

  The control circuit 10 includes, for example, a data processor and a memory (not shown), and is a circuit that realizes wireless communication by comprehensively controlling the transmission module 20 and the reception module 50. That is, the control circuit 10 generates a signal based on the digital signal to be transmitted, outputs the signal to the transmission module 20, and receives the reception signal from the reception module 50. The control circuit 10 also transmits the amplitude modulation signal SAMP for controlling the power amplification factor of the transmission module 20 and the frequency / phase modulation signal SFRQPHZ for controlling the frequency / phase modulation during transmission. Output to.

  The transmission module 20 includes, for example, an amplitude modulator 22, a frequency / phase modulator 24, a digital control power amplifier 26, and a signal converter 28. The transmission module 20 generates an analog sine wave signal based on the digital signal to be transmitted, the amplitude modulation signal SAMP, and the frequency / phase modulation signal SFRQPHZ input from the control circuit 10 and outputs them to the transmission / reception duplexer 30. . The analog sine wave signal generated by the transmission module 20 is transmitted through the antenna 40 as a radio signal.

  More specifically, in the transmission module 20, the digital control power amplifier 26 applies amplitude modulation from the control circuit 10 to the frequency phase control signal DIN input from the control circuit 10 via the frequency / phase modulator 24. The current is adjusted according to the amplitude control signal SEL input through the device 22, and the adjusted digital current short signal is output through the output terminal TX_OUT. That is, the digitally controlled power amplifier 26 typically has a function of digitally controlling the amount of signal current to be output. As will be described later, the digitally controlled power amplifier 26 of the present embodiment supplies at least a part of the power necessary for digitally controlling the amount of signal current to be output via the output line from the output line. This enables operation with low power consumption (see FIGS. 2 to 4). The signal amplified by the digital control power amplifier 26 is input to the signal converter 28.

  The amplitude modulator 22 generates an amplitude control signal SEL based on the digital signal to be transmitted and the amplitude modulation signal SAMP input from the control circuit 10 and outputs them to the digital control power amplifier 26.

  The frequency / phase modulator 24 generates a frequency / phase control signal DIN based on the digital signal to be transmitted and the frequency / phase modulation signal SFRQPHZ input from the control circuit 10 and outputs them to the digital control power amplifier 26. .

  The signal converter 28 is a filter circuit such as a low-pass filter, for example. The signal converter 28 converts the digital current rectangular signal to be transmitted input from the digitally controlled power amplifier 26 into a desired analog sine wave signal.

  The transmitter / receiver demultiplexer 30 is, for example, a duplexer or a diplexer, and electrically separates the transmission signal output from the transmission module 20 and the reception signal received via the antenna 40. That is, the transmission / reception duplexer 30 correctly routes the transmission / reception signal and prevents the transmission signal from entering the reception module. As an alternative example, the transmission / reception duplexer 30 may be replaced with a transmission / reception switch, for example.

  The antenna 40 transmits the transmission signal received from the transmission module 20 via the transmission / reception duplexer 30 as a radio signal, and outputs the reception signal received as the radio signal to the reception module 50 via the transmission / reception duplexer 30. To do.

  The reception module 50 includes, for example, a signal amplifier 52, a frequency converter 54, an intermediate frequency amplifier 56, and a demodulator 58. The receiving module 50 amplifies the received signal received by the antenna 40, removes noise from the received signal, converts the received signal into a digital signal, and outputs the digital signal to the control circuit 10.

  The signal amplifier 52 is, for example, a low noise amplifier, amplifies the reception signal input from the transmitter / receiver demultiplexer 30 via the antenna 40, removes unnecessary frequency components of the received signal, and outputs the signal to the frequency converter 54. To do.

  The frequency converter 54 is, for example, a mixer, converts the frequency of the reception signal input from the signal amplifier 52 to a constant low frequency, and outputs the frequency to the intermediate frequency amplifier 56.

  The intermediate frequency amplifier 56 amplifies the received signal input from the frequency converter 54 until it can be demodulated, removes unnecessary frequency components of the received signal, and outputs the signal to the demodulator 58.

  The demodulator 58 converts the reception signal input from the intermediate frequency amplifier 56 from a sine wave to a digital signal and outputs the digital signal to the control circuit 10.

  The power supply device 60 supplies necessary power to electronic circuit elements in the wireless communication device 1 such as the transmission module 20, the reception module 50, or the control circuit 10.

  FIG. 2 is a schematic circuit diagram showing an example of the configuration of a digitally controlled power amplifier according to an embodiment of the present invention. As shown in the figure, the digitally controlled power amplifier 26 of this embodiment includes, for example, a bias circuit 261, an operational amplifier 262, a plurality of power amplifiers 263 having a multi-stage configuration, and capacitors 264 and 265. . The digitally controlled power amplifier 26 is typically a circuit that adjusts the amount of current supplied to the output line TX_OUT under the control of the amplitude control signal SEL. That is, the amount of current supplied to the antenna 40 (see FIG. 1) connected to the output line TX_OUT is controlled by the digital control power amplifier 26.

  The bias circuit 261 is a circuit that supplies a necessary voltage to the operational amplifier 262 and the plurality of power amplifiers 263. That is, the bias circuit 261 generates a reference input voltage signal VREF and a current control voltage signal VB having a predetermined potential. The reference input voltage signal VREF is input to the non-inverting input terminal + of the operational amplifier 262, and the current control voltage signal VB is input to the VB terminal of the power amplifier 263.

  The operational amplifier 262 is a differential amplifier that is provided between the bias circuit 261 and, for example, the first-stage power amplifier 263 (1), and amplifies the potential of the reference input voltage signal VREF output from the bias circuit 261 according to a predetermined gain. is there. The operational amplifier 262 realizes such an amplification function by configuring a negative feedback circuit with a transistor TR1 (see FIG. 4) included in a power amplifier 263 (1) described later. That is, the operational amplifier 262 receives the reference input voltage signal VREF at the non-inverting input terminal +, the feedback input signal OPFED at the inverting input terminal −, and outputs the output signal VCAS from the output terminal Y.

  Each of the plurality of power amplifiers 263 is typically provided between the power supply line VDD and the ground line GND. The plurality of power amplifiers 263 are circuits that digitally control the current amount of the output line TX_OUT by switching the output line TX_OUT on (conductive state) / off (non-conductive state) under the control of the amplitude control signal SEL. is there. In this example, each of the plurality of power amplifiers 263 performs supply / cutoff of current to the antenna 40 connected to the output line TX_OUT. The plurality of power amplifiers 263 of the present embodiment supply a current regeneration function for supplying power necessary for the operation of the power switch driver INV (see FIG. 4) for switching the output line TX_OUT not from the power line VDD but from the output line TX_OUT. And has a function of operating with low power consumption.

  The capacitors 264 and 265 are used as bypass capacitors, for example, ceramic capacitors or capacitance cells. The capacitor 264 is provided between the output line VCAS of the operational amplifier 262 and the ground line GND, and the capacitor 265 is provided between the current control voltage signal VB and the ground line GND. Capacitors 264 and 265 remove noise components included in a signal via a signal line connected to the capacitors 265 and 265 and alleviate steep fluctuations in potential.

  3, 4A, and 4B are schematic circuit diagrams illustrating an example of the configuration of the power amplifier in the digitally controlled power amplifier according to the embodiment of the present invention. In particular, FIG. 3 illustrates the digital circuit illustrated in FIG. The configuration of the power amplifier 263 in the control power amplifier 26 will be described in detail. 4A shows a schematic circuit diagram of the first power amplifier shown in FIG. 3, and FIG. 4B shows a schematic circuit diagram of the second to Nth power amplifiers shown in FIG.

  Referring to FIG. 4A, the power amplifier 263 (1) includes a transistor TR1, a transistor TR2, a transistor TR3, a selection circuit MUX, and a power switch driver INV.

  The transistor TR1 functions as a power switch, and includes, for example, a thin film N-type MOSFET. That is, the drain D1 of the transistor TR1 is connected to the source S2 of the transistor TR2, and the source S1 is connected to the drain D3 of the transistor TR3. The gate G1 of the transistor TR1 is connected to the output terminal of a power switch driver INV described later. Thereby, the transistor TR1 switches on / off of current supply to the output line TX_OUT. In this example, the transistor TR1 is formed of a thin film N-type MOSFET, but is not limited thereto, and may be a thin film P-type MOSFET or a thick film transistor, for example. May be.

  The transistor TR2 includes, for example, a thick film N-type MOSFET. The drain D2 of the transistor TR2 is connected to the output line TX_OUT, the source S2 is connected to the drain D1 of the transistor TR1 and the inverting input terminal − of the operational amplifier 262 (see FIG. 2), and the gate G2 is connected to the power supply line VCAS. Thus, the transistor TR2 forms a negative feedback with the operational amplifier 262 (see FIG. 2), amplifies the potential of the reference input voltage signal VREF (see FIG. 2), and outputs it to the output line TX_OUT. The transistor TR2 functions as a cascode circuit by forming a negative feedback circuit with the operational amplifier 262 (see FIG. 2). The cascode circuit composed of the transistor TR2 and the operational amplifier 262 maintains the potential of the source D2 of the transistor TR2 within a certain range, so that the drain D1 and the source S1 of the transistor TR1 and the drain D2 and the source of the transistor TR2 are maintained. The modulation effect of the output current due to the channel length modulation effect caused by the change of the voltage applied during S2 is suppressed. As a result, the output voltage of the digitally controlled power amplifier 26 is proportionally controlled by the amplitude control signal SEL. In this example, the transistor TR2 is configured by a thick film N-type MOSFET, but is not limited thereto, and may be, for example, a thick film P-type MOSFET.

  The transistor TR3 includes, for example, a thin film N-type MOSFET. That is, the drain D3 of the transistor TR3 is connected to the source S1 of the transistor TR1, and the source S3 is connected to the ground line GND. Further, the current control voltage signal VB of the bias circuit 261 (see FIG. 2) is input to the gate G3 of the transistor TR3. Thus, the transistor TR3 controls the current flowing through the output line TX_OUT connected to the drain D3. In this example, the transistor TR3 is formed of a thin film N-type MOSFET, but is not limited thereto, and may be, for example, a thin film P-type MOSFET or a thick film transistor. May be.

  The selection circuit MUX is, for example, a multiplexer, and switches on / off the transistor TR1. The power supply line VDD is connected to the power supply terminal of the selection circuit MUX, and the ground line GND is connected to the ground terminal. Therefore, the selection circuit MUX receives the frequency phase control signal DIN and the ground signal GND through the data input terminals A1 and A0, respectively, and the frequency phase control signal DIN or the ground signal according to the amplitude control signal SEL received through the selection terminal SL. GND is selected and output from the output terminal Y via logical negation.

  When the potential of the amplitude control signal SEL is the power supply line VDD, that is, “H”, the selection circuit MUX selects the frequency phase control signal DIN input to the data input terminal A1 as an input signal. In this case, the selection circuit MUX outputs the output signal as a logic negation to the frequency phase control signal DIN. That is, when the potential of the frequency phase control signal DIN is “H”, the selection circuit MUX outputs “L” from the output terminal Y, and the potential of the frequency phase control signal DIN is the potential of the ground line GND, that is, “L”. In this case, “H” is output from the output terminal Y.

  On the other hand, when the potential of the amplitude control signal SEL is “L”, the selection circuit MUX selects the ground signal GND input to the data input terminal A0 as an input signal. In this case, since the selection circuit MUX outputs the ground signal GND as an output signal via a logical negation, the potential of the output signal is always “H”.

  The power switch driver INV is, for example, an inverter circuit. The power switch driver INV is provided between the selection circuit MUX and the transistor TR1. The power switch driver INV receives the switch control input signal SWIN transmitted from the selection circuit MUX at the input terminal, outputs the switch control signal SWOUT from the output terminal, and switches on / off the transistor TR1. In the power switch driver INV, the power terminal is connected to the drain D1 of the transistor TR1, and the ground terminal is connected to the source S1 of the transistor TR1. That is, in the present embodiment, the power switch driver INV is configured to be able to obtain power necessary for its own operation from the output line TX_OUT of the transistor TR1 that it drives.

  Thus, since the output terminal of the power switch driver INV is connected to the gate G1 of the transistor TR1, the transistor TR1 obtains power for driving itself from the output line TX_OUT instead of from the power line VDD. Therefore, the switching current supplied from the power supply line VDD in the transistor TR1 is reduced.

  Further, since the switching current of the transistor TR1 is added to the output current, the output current flowing through the output line TX_OUT increases.

  As described above, the output conversion efficiency η is a ratio between the total power consumption of the digitally controlled power amplifier 26 and the output power. The conventional digital control power amplifier is configured so that power necessary for the operation of the power switch driver INV is supplied from the power line VDD. On the other hand, the present embodiment is configured such that power necessary for the operation of the power switch driver INV is supplied from the output line TX_OUT. Therefore, according to this embodiment, the reduction in power consumption in the digitally controlled power amplifier 26 and the increase in the output current flowing through the output line TX_OUT are realized, thereby improving the output conversion efficiency η. Further, according to the present embodiment, since a thin film transistor can be used as the transistor TR1, a high-speed switching operation of the transistor TR1 that controls the amount of current flowing through the output line TX_OUT is enabled.

  The power amplifiers 263 (2) to (n) shown in FIG. 4B are obtained by removing the output line that transmits the feedback input signal OPFED from the configuration of the power amplifier 263 (1) shown in FIG. 4A. In the power amplifiers 263 (2) to (n), the drain D2 of the transistor TR2 is connected to the output line TX_OUT, the source S2 is connected to the drain D1 of the transistor TR1, and the gate G2 is connected to the power supply line VCAS. That is, the transistor TR2 in the power amplifiers 263 (2) to (n) does not constitute the operational amplifier 262 and the negative feedback circuit. The transistor TR2 receives the output signal VCAS of the operational amplifier 262 generated by the negative feedback circuit composed of the transistor TR2 and the operational amplifier 262 in the power amplifier 263 (1) at the gate G2, so that the potential of the source D2 of the transistor TR2 is constant. Keeping the value in the range, the modulation effect of the output current due to the channel length modulation effect caused by the change of the voltage applied between the drain D1 and the source S1 of the transistor TR1 and between the drain D2 and the source S2 of the transistor TR2 is suppressed. To do.

  The functions and configurations of the transistors TR1 and TR3, the selection circuit MUX, and the power switch driver INV in the power amplifier 263 (2) to (n) are the same as the circuit elements in the power amplifier 263 (1). Omitted.

  FIG. 5 is a diagram showing the relationship between the output voltage and current consumption in the digitally controlled power amplifier 26 according to one embodiment of the present invention by numerical calculation simulation. For comparison, the relationship between output voltage and current consumption in a digitally controlled power amplifier having a conventional configuration is also shown (dotted line). As shown in the figure, the total current consumption in the digitally controlled power amplifier 26 configured to supply the power for driving the transistor TR1 from the output line TX_OUT of the transistor TR1 is the total current consumption in the digitally controlled power amplifier using the conventional configuration. The current consumption is reduced.

  The power amplifier 263 of the present embodiment is not limited to the configuration shown in FIG. 3 and the like, and various modifications can be made. FIG. 6A is a diagram showing another example of a schematic circuit configuration of the power amplifier 263 in the digitally controlled power amplifier according to the embodiment of the present invention. That is, this modification shows a configuration in which the transistor TR2 (that is, the thick film N-type MOSFET) is removed from the configuration of the above embodiment. In addition, the transistors TR1 and TR3 of the above embodiment are configured as, for example, thick film transistors TR1A and TR3A, respectively.

  That is, in this modification as well, the power switch driver INV is configured so that the power necessary for its operation can be obtained from the output line TX_OUT of the transistor TR1A that it drives.

  Further, in the digitally controlled power amplifier 26 of the present modification, the transistor TR2 of the power amplifier 263 is removed, so that the operational amplifier 262 and the capacitor 264 are removed or electrically separated. Become.

  FIG. 6B is a diagram showing still another example of the schematic circuit configuration of the power amplifier 263 in the digitally controlled power amplifier according to the embodiment of the present invention. That is, the present modification shows a configuration in which the transistor TR2 is removed from the configuration of the above embodiment, and the arrangement of the transistors TR1 and TR3 is replaced. Further, the transistors TR1 and TR3 of the above embodiment are configured as, for example, thick film transistors TR1B and TR3B, respectively.

  That is, in the present modification as well, the power switch driver INV is configured such that the power necessary for its own operation can be obtained from the output line TX_OUT of the transistor TR1B that it drives.

  Further, in the digitally controlled power amplifier 26 of the present modification, the transistor TR2 of the power amplifier 263 is omitted, so that the operational amplifier 262 and the capacitor 264 are also removed or configured to be electrically separated. Become.

  In the configuration of the power amplifier 263 shown in FIGS. 6A and 6B, all the transistors connected to the output line TX_OUT are thick film transistors. And an improvement in output conversion efficiency η can be achieved.

  FIG. 7 is a diagram showing another example of a schematic circuit configuration of the power amplifier 263 in the digitally controlled power amplifier 26 according to the embodiment of the present invention. In other words, in the present embodiment, a plurality of transistors TR1 of the above embodiment are configured to be connected in parallel to the output line TX_OUT. In the present embodiment, the output signal of the power switch driver INV arrives at each gate G1 of the plurality of transistors TR1 with a delay in stages, for example, via the signal delay unit 2631.

  More specifically, the power switch driver INV is, for example, an inverter circuit. The power switch driver INV is provided between the selection circuit MUX and the transistor TR1 (1). The power switch driver INV receives the switch control input signal SWIN transmitted from the selection circuit MUX at the input terminal, receives the switch control signal SWOUT (1) from the output terminal, the gate of the transistor TR1 (1) and the signal delay unit 2631 (1 ) Is output.

  The signal delay unit 2631 is, for example, a signal wiring or a buffer circuit, and has a function of outputting a signal input thereto after a predetermined time has elapsed. The signal delay unit 2631 (1) receives the switch control signal SWOUT (1) output from the power switch driver INV, and after a predetermined time has elapsed, the signal delay unit 2631 (1) is connected to the transistor TR1 (2) and the signal delay unit 2631 (2). Output. The signal delay unit 2631 (2) receives the switch control signal SWOUT (2) output from the signal delay unit 2631 (1), and after a predetermined time has elapsed, the transistor TR1 (3) and the signal delay unit 2631 (3). ) Is output. Thus, in this embodiment, the signal delay unit (n) receives the output signal of the signal delay unit (n-1), and after a predetermined time has elapsed, the transistor TR1 (n + 1) and the signal delay unit It is configured to output to (n + 1).

  The transistor TR1 functions as a power switch, and includes, for example, a thin film N-type MOSFET. That is, the drain D1 of the transistor TR1 is connected to the source S2 of the transistor TR2, and the source S1 is connected to the drain D3 of the transistor TR3. The gate G1 (1) of the transistor TR1 (1) is connected to the output terminal of the switch drive circuit INV. The gate G1 (2) of the transistor TR1 (2) is connected to the output terminal of the signal delay 2631 (1), and the gate G1 (3) of the transistor TR1 (3) is connected to the output terminal of the signal delay 2631 (2). Connected to. Thus, in this embodiment, the transistor TR1 (n) has the drain D1 (n) connected to the source S2 of the transistor TR2, the source S1 (n) connected to the drain D3 of the transistor TR3, and the gate G1 (n ) Is connected to the output terminal of the signal delay device (n-1). In this example, the transistor TR1 is formed of a thin film N-type MOSFET, but is not limited thereto, and may be a thin film P-type MOSFET or a thick film transistor, for example. May be.

  Since the functions and configurations of the transistor TR2, the transistor TR3, and the selection circuit MUX are the same as those in the above embodiment, the description thereof is omitted.

  The present embodiment has a function of suppressing current harmonics in the output line TX_OUT that is generated each time the digitally controlled power amplifier 26 outputs a current short signal as an output signal. In other words, in the present embodiment, the signal output from the power switch driver INV is transmitted to the plurality of transistors TR1 (1) to (n) via several signal delay units 2631 (1) to (n-1). , Each of the plurality of transistors TR1 (1) to (n) is delayed by an amount corresponding to the delay amount of the signal delay unit 2631. Drive at the right timing.

  As a result, when viewed from the output line TX_OUT, the total value of the mutual conductances of the plurality of transistors TR1 (1) to (n) changes stepwise, and a steep change in the output current flowing through the output line TX_OUT is alleviated. The Therefore, since a steep change in the current flowing through the output line TX_OUT is alleviated, generation of pulsed current harmonics injected into the output line TX_OUT is suppressed.

  FIG. 8 is a diagram showing the relationship between the output current and the elapsed time in the digitally controlled power amplifier according to one embodiment of the present invention by numerical calculation simulation. As shown in the figure, a plurality of transistors TR1 are connected in parallel to the output line TX_OUT, and each of the transistors TR1 (1) to (n) is driven stepwise, thereby providing a digitally controlled power amplifier 26. It can be seen that generation of current harmonics that occur when a short current signal is output as an output signal to the output line TX_OUT is suppressed.

  Each of the above embodiments is an example for explaining the present invention, and is not intended to limit the present invention only to these embodiments. The present invention can be implemented in various forms without departing from the gist thereof.

  For example, in the method disclosed herein, steps, operations, or functions may be performed in parallel or in a different order, as long as the results do not conflict. The steps, operations, and functions described are provided as examples only, and some of the steps, operations, and functions may be omitted and combined with each other without departing from the spirit of the invention. There may be one, and other steps, operations or functions may be added.

  Further, although various embodiments are disclosed in this specification, specific features (technical matters) in one embodiment are added to other embodiments while appropriately improving the other features, or other Specific features in the embodiments can be replaced, and such forms are also included in the gist of the present invention.

  The present invention can be widely used in the field of semiconductor integrated circuits including amplifiers using MOSFETs.

DESCRIPTION OF SYMBOLS 1 ... Wireless communication apparatus 10 ... Control circuit 20 ... Transmitting module 22 ... Amplitude modulator 24 ... Frequency / phase modulator 26 ... Digital control power amplifier 28 ... Signal converter 30 ... Transmitting / receiving duplexer 40 ... Antenna 50 ... Receiving module 52 Signal amplifier 54 Frequency converter 56 Intermediate frequency converter 58 Demodulator 60 Power supply 261 Bias circuit 262 Operational amplifier 263 Power amplifier 264 Capacitor 265 Capacitor 2631 Signal delay

Claims (12)

A digitally controlled power amplifier comprising at least one power amplifier connected to an output line,
The at least one power amplifier comprises:
A first transistor for supplying a switching current to the output line;
A drive circuit for controlling the on / off operation of the first transistor,
The drive circuit drives the first transistor based on at least a part of the switching current flowing through the output line;
Digitally controlled power amplifier.   The digitally controlled power amplifier according to claim 1, wherein the first transistor is a thin film transistor. The drive circuit includes an inverter circuit connected to a gate of the first transistor,
The inverter circuit operates based on at least a part of the switching current to supply a switch control signal to a gate of the first transistor;
The digitally controlled power amplifier according to claim 2.   The digitally controlled power amplifier according to claim 3, wherein the inverter circuit operates by a potential difference between a drain and a source of the first transistor.   The digitally controlled power amplifier of claim 1, wherein the at least one power amplifier includes a second transistor cascode-connected to the first transistor.   The digitally controlled power amplifier of claim 5, wherein the second transistor is a thick film transistor. A pair of differential input terminals and an output terminal are provided, one of the pair of differential input terminals is connected to a predetermined reference potential, and the other is connected to the source of the second transistor of the at least one power amplifier. , Further comprising an operational amplifier whose output terminal is connected to the gate of the second transistor of the at least one power amplifier;
The digitally controlled power amplifier according to claim 6.   The digitally controlled power amplifier of claim 6, wherein the at least one power amplifier includes a third transistor cascode-connected to the first transistor.   The digitally controlled power amplifier according to claim 3, further comprising at least one delay circuit provided between the first transistor and the inverter circuit.   The digitally controlled power amplifier according to claim 1, wherein the power amplifier includes a plurality of the power amplifiers connected in parallel to a node of the output line.   A wireless communication apparatus comprising a transmission module including the power amplifier according to claim 1. A bias circuit that generates and outputs a reference input signal and a current control signal of a predetermined potential;
An operational amplifier that amplifies the reference input signal output from the bias circuit according to a predetermined gain;
Based on the amplified reference input signal output from the operational amplifier and the current control signal output from the bias circuit, connected to the operational amplifier and connected in parallel to the node of the output line, the switching current A plurality of power amplifiers that output to the output line, each of the plurality of power amplifiers,
A transistor that is turned on and off by a switch control signal;
A drive circuit for outputting a switch control signal for controlling the on / off operation of the transistor,
The drive circuit generates the switch control signal based on at least a part of the switching current flowing through the output line, and drives the transistor;
Digitally controlled power amplifier.