JP2015106751A - Image processing apparatus, and control method and program of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve a problem that RAM access for reconfiguration is kept waiting during real-time processing to decrease processing efficiency when circuit configuration information is stored in a high-speed RAM and dynamic reconfiguration is performed by using the RAM.SOLUTION: In an image processing apparatus which comprises an FPGA in which at least a part of a circuit is dynamically reconfigured, a ROM 104 for storing circuit configuration information for reconfiguring at least a part of the circuit in the FPGA, and a RAM 111, capable of reading at a higher speed than the ROM 104, for storing circuit configuration information stored in the ROM 104, at least a part of the FPGA is reconfigured depending on a job to execute to a circuit which can execute processing necessary for the job by using the circuit configuration information, and the FPGA is reconfigured by using the circuit configuration information stored in the RAM 111 when real-time processing using the RAM 111 is not in execution and the FPGA is reconfigured by using the circuit configuration information stored in the ROM 104 when the real-time processing using the RAM 111 is in execution.

Description

  The present invention relates to an image processing apparatus, a control method thereof, and a program.

  Reconfigurable circuits such as PLD (Programmable Logic Device) and FPGA (Field Programmable Gate Array) capable of changing the configuration of the logic circuit are well known. Generally, PLD and FPGA logic circuits are changed by writing circuit configuration information stored in non-volatile memory such as ROM into configuration memory that is volatile memory inside PLD or FPGA at startup. Is done. Since the information in the configuration memory is cleared when the power is turned off, it is necessary to write the circuit configuration information stored in the ROM again in the configuration memory when the power is turned on. In this way, a method of configuring a PLD or FPGA logic circuit only once while power is supplied is called static reconfiguration. On the other hand, an FPGA or the like that can dynamically change the configuration of a logic circuit while the logic circuit is operating has been developed, and such a method of dynamically changing a logic circuit is called dynamic reconfiguration.

  Some FPGAs can rewrite only the circuit configuration of a specific area, not the circuit configuration of the entire FPGA chip, and such rewriting is called partial reconfiguration. In particular, changing other circuit configurations without stopping the operation of the circuit in operation is called dynamic partial reconfiguration. In dynamic partial reconfiguration, it is possible to partially reconfigure the FPGA logic circuit by rewriting only a partial area of the configuration memory instead of rewriting the entire configuration memory at the time of dynamic reconfiguration. it can. By using such dynamic partial reconfiguration, for example, a plurality of logic circuits can be switched and mounted in a certain area of the FPGA in a time division manner. As a result, with a small amount of hardware resources, various functions can be flexibly realized while maintaining high-speed computing performance by hardware.

  Incidentally, a non-volatile memory such as a serial ROM used for storing circuit configuration information of the FPGA has a slower access speed than a volatile memory such as a RAM. Therefore, generally, the time required for reconfiguration of the logic circuit of the FPGA becomes long, and the time is proportional to the data size of the circuit configuration information written in the configuration memory. In order to shorten the time required for such reconfiguration, necessary circuit configuration information is stored in a RAM having a high access speed, and the circuit configuration information is read from the high-speed RAM at a high speed during reconfiguration. A method for writing data into the FPGA is known.

  Japanese Patent Application Laid-Open No. 2004-228561 is a technology in which, in a reconfigurable circuit, circuit configuration information is stored in advance in a main memory, and a CPU selects necessary circuit configuration information according to the processing contents of the circuit and performs reconfiguration. Is described. Further, Patent Document 1 further describes a technique for selecting and reconfiguring necessary circuit configuration information in a system having a dedicated local memory for storing a plurality of circuit configuration information. However, in general, the FPGA does not have a dedicated memory for holding a plurality of pieces of circuit configuration information. Further, when processing a large amount of image data in a copying machine system or the like, the internal memory of the FPGA cannot be used as a dedicated memory for storing circuit configuration information. Therefore, from the viewpoint of cost, a configuration in which a large-capacity RAM used by the CPU is used as a main memory of the system, a working memory for image processing, and a memory for storing circuit configuration information can be considered.

JP 2010-232801 A

  Consider a case where dynamic partial reconfiguration of an FPGA is performed in a state where the above-described large-capacity RAM is used as a circuit configuration information storage memory and an image processing working memory. In this case, the access for reading out the circuit configuration information from the RAM competes with the access for the operating image processing circuit to read out the image data from the RAM. In particular, when executing processing that is combined with paper transportation of a scanner or printer in a copying machine or the like, if real-time processing that must be completed within a predetermined time is performed in accordance with paper transportation, access to the RAM is reduced. Occupied by its real-time processing. This is because if real-time processing is processing a large amount of image data and another access is accepted when the memory bandwidth of the RAM is tight, real-time processing will be delayed from paper transport, and image data on the transported paper This is in order to prevent the printing in time from being missed. As a result, during real-time processing, there is a problem that RAM access for reconfiguration is awaited and processing efficiency decreases.

  Further, when the circuit configuration information stored in the RAM is damaged, the circuit configuration information stored in the ROM must be transferred to the RAM again, and the overhead time for transferring the circuit configuration information from the ROM to the RAM is reduced. The problem of occurring occurs.

  An object of the present invention is to solve the above-mentioned problems of the prior art.

  A feature of the present invention is to provide a technique for efficiently reconfiguring a dynamic partial reconfiguration unit according to a job status in an image processing apparatus including a dynamic partial reconfiguration unit capable of dynamic reconfiguration. is there.

In order to achieve the above object, an image processing apparatus according to an aspect of the present invention has the following arrangement. That is,
A dynamic reconfiguration unit that dynamically reconfigures at least part of the circuit;
Configuration information storage means for storing circuit configuration information for reconfiguring at least a part of the circuit in the dynamic reconfiguration unit;
A storage unit that stores a copy of the circuit configuration information stored in the configuration information storage unit, and that can be read faster than the configuration information storage unit;
Control means for controlling to reconfigure at least a part of the circuit of the dynamic reconfiguration unit according to a job to be executed into a circuit capable of executing processing necessary for the job using the circuit configuration information; Have
The control means reconfigures the dynamic reconfiguration unit using the circuit configuration information stored in the storage means when real-time processing using the storage means is not being executed, and the storage means When the real-time processing using is being executed, the dynamic reconfiguration unit is controlled to be reconfigured using the circuit configuration information stored in the configuration information storage means.

  According to the present invention, a dynamic partial reconfiguration unit can be efficiently reconfigured according to the status of a job to be executed.

1 is a block diagram illustrating a configuration of an image processing apparatus according to a first embodiment of the present invention. FIG. 3 is a diagram illustrating a correspondence between a job executed by the image processing apparatus according to the first embodiment and an image processing function necessary for each job. 6 is a flowchart for explaining processing when the image processing apparatus according to the first embodiment executes a job using the image processing unit 132 or the image processing unit 133; 4 is a flowchart for explaining FPGA reconfiguration processing in S306 of FIG. 3; FIG. 5 is a conceptual diagram illustrating switching of reading source of circuit configuration information described in the flowchart of FIG. 4. 6 is a time chart for explaining operations of a scanner I / F, a printer I / F, and an image processing unit when a SEND and a print job are executed in competition in the image processing apparatus, as compared with a conventional example. 9 is a flowchart for describing processing when the image processing apparatus according to the second embodiment executes a job using the image processing unit 132 or the image processing unit 133. FIG. 8 is a flowchart for explaining details of a reconstruction process in S706 of FIG. 7; FIG.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments do not limit the present invention according to the claims, and all combinations of features described in the embodiments are not necessarily essential to the solution means of the present invention. .

[Embodiment 1]
FIG. 1 is a block diagram illustrating a configuration of an image processing apparatus 100 according to the first embodiment of the present invention. In the first embodiment, the image processing apparatus 100 will be described as a multi-function machine (multifunctional processing apparatus) having a scanner unit and a printer unit.

  The image processing apparatus 100 includes an operation unit 103 for a user using the image processing apparatus 100 to perform various operations, a scanner unit 109 that reads image information of a document, and a printer that prints an image on a sheet based on image data. Part 107. The scanner unit 109 includes a CPU (not shown) that controls the scanner unit 109, an illumination lamp for reading a document, a scanning mirror (none of which are shown), and the like. The printer unit 106 includes a CPU (not shown) that controls the printer unit 106, a photosensitive drum and a fixing device (all not shown), and the like that perform image formation (printing) and fixing.

  The image processing apparatus 100 includes an FPGA 140 including a dynamic reconfiguration unit as a controller that controls the image processing apparatus 100. In this example, the FPGA 140 includes a CPU 101 that comprehensively controls the operation of the image processing apparatus 100. The CPU 101 executes a program for controlling the FPGA 140, the configuration controller 130 for controlling reconfiguration, and the like. Note that the FPGA 140 includes the CPU 101 is merely an example, and the CPU may be provided outside the FPGA 140.

  The ROM 104 stores a program executed by the CPU 101, and also functions as a configuration information storage unit that stores circuit configuration information of the FPGA 140. The RAM 111 is also used as a system work memory for the operation of the CPU 101 and an image memory for temporarily storing image data. Further, the RAM 111 duplicates and stores the circuit configuration information stored in the ROM 104, and the CPU 101 can read out the circuit configuration information from the RAM 111 at high speed.

  The FPGA 140 is a dynamic partial reconfiguration unit 131 that can dynamically reconfigure at least a part of a circuit as a dynamic reconfiguration unit, and a configuration that controls a change in the circuit configuration (configuration) of the dynamic partial reconfiguration unit 131. Controller 130. The dynamic partial reconfiguration unit 131 is dynamically rewritable and partially rewritable. That is, while a part of the circuit of the dynamic part reconfiguration unit 131 is operating, another circuit can be reconfigured in another part that does not overlap with the part occupied by the operating circuit. . The dynamic partial reconfiguration unit 131 includes an image processing unit 132 and an image processing unit 133 that can partially reconfigure a logic circuit for performing image processing. In the first embodiment, the number of image processing units configured in the dynamic partial reconstruction unit 131 is two, but the number of image processing units is not limited to two. The FPGA 140 includes a scanner I / F 108 that inputs image data from the scanner unit 109 and a printer I / F 106 that outputs image data to the printer unit 107. The image processing unit 132, the image processing unit 133, the scanner I / F 108, and the printer I / F 106 of the dynamic partial reconstruction unit 131 are connected to the image bus 121.

  The CPU 101 controls the overall operation of the image processing apparatus 100 in accordance with a program stored in the ROM 104. Further, it is connected to a network (not shown) via the network I / F 102 and communicates (transmits / receives) with a general-purpose computer (not shown) on the network. The ROM I / F 112 controls access to the ROM 104. The operation unit I / F 113 controls an interface with the operation unit 103. The system bus 120 connects the CPU 101, the network I / F 102, the memory controller 110, the operation unit I / F 113, the ROM I / F 112, the configuration controller 130, and the dynamic partial reconfiguration unit 131 to each other. The CPU 101 performs register settings for the image processing units 132 and 133, the scanner I / F 108, and the printer I / F 106 configured in the dynamic partial reconfiguration unit 131 via the system bus 120. The memory controller 110 controls data writing to the RAM 111 and data reading from the RAM 111. The memory controller 110 is connected to the system bus 120 and the image bus 121. The memory controller 110 exclusively switches the access to the RAM 111 from the bus master connected to the image bus 121 and the access to the RAM 111 from the bus master connected to the system bus 120.

  FIG. 2 is a diagram illustrating a correspondence between a job executed by the image processing apparatus 100 according to the first embodiment and an image processing function necessary for each job.

  The image processing apparatus 100 can execute a copy job, a print job, and a SEND job. In the copy job, the scanner unit 109 reads an original and copies it. The print job is printed by the printer unit 107 based on print data sent from a printer driver such as a PC. In the SEND job, image data of a document obtained by the scanner unit 109 is transmitted to an external file server or an e-mail address.

  The processing orders 1 to 3 indicate the processing executed in each job and the execution order. In the copy job, first, in the processing order 1, scan image processing for performing scanner correction processing on image data input from the scanner unit 109 is executed. Subsequently, in processing order 2, an image editing process for performing rotation processing, scaling processing, trimming processing, and the like on the image data is executed. Finally, in the processing order 3, print image processing for correcting, converting the resolution and the like on the image data printed by the printer unit 107 is executed.

  In the print job, a raster image process (RIP) process for developing a page description language (PDL) code included in the print job received via the network I / F 102 into a bitmap image is executed in the processing order 1. Next, the image editing process is executed in the processing order 2, and the print image process is executed in the processing order 3. In the SEND job, scan image processing, image editing processing, and SEND image processing for performing high compression processing for transmitting an image to the network are sequentially executed. Note that all the circuit configuration information for performing the image processing is copied from the ROM 104 to the RAM 111 when the power is turned on.

  The jobs that can be executed by the image processing apparatus 100 are not limited to the jobs shown in FIG. Further, the unit of image processing is not limited to that shown in FIG. 2, and the processing included in each job can be further divided into finer processing. In addition, for example, in the case of scanning image processing, each image processing is not necessarily performed in the same manner for a copy job and a SEND job, and is configured so that appropriate processing is performed according to each job. Also good.

  FIG. 3 is a flowchart illustrating processing when the image processing apparatus 100 according to the first embodiment uses the image processing unit 132 or the image processing unit 133 to execute, for example, the job illustrated in FIG. Each process shown in this flowchart is achieved by the CPU 101 executing a program stored in the ROM 104.

  In step S301, when the CPU 101 receives a job start instruction via the operation unit 103 or the network I / F 102, the process advances to step S302, and the CPU 101 determines the type of the input job and identifies the job. In step S303, the CPU 101 determines whether the job requires a document reading process by the scanner unit 109, such as a copy job or a SEND job. If it is necessary to read the document by the scanner unit 109, the process advances to step S <b> 304, and the CPU 101 outputs an instruction to start reading the document to the scanner unit 109. As a result, writing of the image data of the document into the RAM 111 is started in units of pages via the scanner I / F 108. Then, the process proceeds to S305.

  On the other hand, in step S303, the CPU 101 proceeds to step S305 if processing for reading an original by the scanner unit 109 is not required, such as a print job. In step S305, the CPU 101 determines the content of the process to be executed next (see FIG. 2) according to the type of the input job, and proceeds to step S306. In step S <b> 306, the CPU 101 configures the circuit necessary for the image processing determined in step S <b> 305 in the image processing unit 132 or the image processing unit 133. For this purpose, the CPU 101 controls the configuration controller 130 to reconfigure the image processing unit 132 or the image processing unit 133 into a scan image processing circuit. This corresponds to processing in a period T1 described later with reference to FIG. Details of this control will be described later with reference to the flowchart of FIG.

  In step S307, the CPU 101 determines whether the scanner I / F 108 or printer I / F 106 has completed real-time processing (real-time processing) for one page, and waits until the real-time processing is completed. Then, it progresses to S308. This real-time processing is, for example, processing in which a document must be read or printed within a predetermined time in accordance with the paper conveyance of the scanner unit 109 or the printer unit 107 in a copying machine or the like. . In other words, if the processing is not completed within a predetermined time, the subsequent processing is broken, and as a result, the job cannot be executed.

  In step S308, the CPU 101 outputs a processing start instruction to the image processing circuit configured in the image processing unit 132 or the image processing unit 133, and the process proceeds to step S309. In step S309, the CPU 101 stands by until the image processing unit 132 or the image processing unit 133 completes the image processing. When the image processing is completed, the CPU 101 proceeds to step S310. In step S <b> 310, the CPU 101 determines whether all the image processing to be processed by the image processing unit 132 or the image processing unit 133 has been completed for the currently executed job.

  Here, for example, in the case of a SEND job, scan image processing, image editing processing, and SEND image processing are sequentially executed as shown in FIG. Accordingly, if all of these processes are completed in S310, the process proceeds to S311. If there is an unexecuted process, the process proceeds from S310 to S305.

  On the other hand, if the CPU 101 determines in S310 that all the processes to be executed for the job have been completed, the process proceeds to S311. In step S <b> 311, the CPU 101 determines whether printing processing for executing printing using the printer unit 107 is required, such as a print job or a copy job. If so, the process proceeds to step S <b> 312, and printing processing is not necessary. If there is, the process proceeds to S313. In step S <b> 312, the CPU 101 issues a print start instruction to the printer unit 107, and outputs image data stored in the RAM 111 via the printer I / F 106 in units of pages. In step S313, the CPU 101 determines whether all the pages have been processed. If the next page needs to be processed, the process returns to step S303, and if there is no next page, the process ends.

  Through such processing, in order to execute the received job, the image processing unit 132 or 133 dynamically configured in the dynamic partial reconfiguration unit 131 can execute processing necessary for the job. Here, since a processing circuit capable of executing processing necessary to execute a job is dynamically configured, more processing can be executed with fewer circuits.

  FIG. 4 is a flowchart for explaining the FPGA reconfiguration processing in S306 of FIG.

  In S401, the CPU 101 determines whether or not real-time processing is being executed. If it is being executed, the process proceeds to S402. If not, the process proceeds to S403. In step S <b> 402, the CPU 101 determines that the circuit configuration information cannot be read from the RAM 111 because real-time processing is being executed. Then, the configuration is set in the configuration controller 130 so as to transfer the circuit configuration information directly from the ROM 104 to the dynamic partial reconfiguration unit 131, and the process proceeds to S404. During the execution of real-time processing, the scanner I / F 108 or the printer I / F 106 accesses the RAM 111 via the image bus 121. On the other hand, the configuration controller 130 reads circuit configuration information from the ROM 104 via the system bus 120 and transfers it to the dynamic partial reconfiguration unit 131. Thereby, the transfer of the circuit configuration information by the configuration controller 130 can be executed without hindering access to the RAM 111 by a circuit or the like that is executing real-time processing.

  On the other hand, in step S403, since the real-time processing is not being executed, the CPU 101 sets the configuration controller 130 to read the circuit configuration information from the RAM 111 at a high speed and transfer it to the dynamic partial reconfiguration unit 131, and proceeds to step S404. In step S <b> 404, the CPU 101 determines whether the configuration controller 133 has transferred the circuit configuration information to the image processing unit 132 or the image processing unit 133, and waits until the transfer is completed. When the transfer of the circuit configuration information is completed in this way, the process advances to step S405, and the CPU 101 receives a CRC determination result indicating whether or not the circuit configuration information is missing or the like by the configuration controller 133. Here, the circuit configuration information includes a CRC code, and the circuit configuration information is transferred via a CRC arithmetic circuit (not shown) provided in the configuration controller 133 to detect an error due to the CRC code. If it is determined here that no CRC error has occurred, this process is terminated. On the other hand, if the CPU 101 determines in step S405 that a CRC error has occurred, the process advances to step S402, and the original circuit configuration information stored in the ROM 104 is retransferred.

  By such control, when an error occurs, the circuit configuration information can be read from the ROM 104 and the reconfiguration can be completed before the original circuit configuration information stored in the ROM 104 is copied back to the RAM 111. If the circuit configuration information is broken, the process of copying the original circuit configuration information stored in the ROM 104 back to the RAM 111 again after the reconfiguration is completed or after the job is completed. Is required. If the original circuit configuration information stored in the ROM 104 is damaged, a system error is returned and displayed on the operation unit 103 to execute a process such as prompting the user to take a countermeasure.

  When it is expected that the RAM 111 is frequently accessed by such processing, the circuit configuration information stored in the ROM 104 is used to construct a circuit necessary for processing in the dynamic partial reconfiguration unit 131. . As a result, it is possible to prevent the occurrence of problems such as a delay in normal real-time processing due to waiting for access to the RAM 111 due to the construction of a processing circuit for the dynamic partial reconfiguration unit 131. When real-time processing is not executed and access to the RAM 111 is expected to be small, circuit configuration information is transferred from the RAM 111 to the dynamic partial reconfiguration unit 131, so that the image processing unit 132 or the image processing unit 133 reconfigurations can be performed quickly.

  FIG. 5 is a conceptual diagram illustrating switching of the circuit configuration information reading source described with reference to the flowchart of FIG.

  FIG. 5A shows a case where the circuit configuration information is read from the RAM 111 when the real-time processing (here, the scanner I / F 108) is not being executed. In this case, since the real-time processing is not being executed, the memory bandwidth of the RAM 111 is not occupied. Therefore, the configuration controller 130 can read out the circuit configuration information from the RAM 111 via the transfer path 50 at high speed and set it in the dynamic partial reconfiguration unit 131.

  FIG. 5B illustrates a case where the circuit configuration information is read from the ROM 104 when real-time processing (here, the scanner I / F 108) is being executed. In this case, since the image data obtained by reading the document is written to the RAM 111 via the path 51, the memory band of the RAM 111 is occupied. Accordingly, in this case, the configuration controller 130 cannot read circuit configuration information from the RAM 111 via the transfer path 50. Therefore, the configuration controller 130 reads the circuit configuration information from the ROM 104 via the transfer path 52 and sets it in the dynamic partial reconfiguration unit 131.

  FIG. 6 is a time chart for explaining operations of the scanner I / F, the printer I / F, and the image processing unit when the SEND and the print job are executed in competition in the image processing apparatus as compared with the conventional example. is there. In FIG. 6, the SEND job is started using the image processing unit 132 in the period T1, and the print job is started using the image processing unit 133 in the period T3 during which the SEND job is being executed. Is shown.

  FIG. 6A shows an example in which reconstruction of the image processing units 132 and 133 is executed at high speed using the RAM 111 without considering real-time processing. In a period T5 in FIG. 6A, the SEND job starts scanning the second page of the document, and the scanner I / F 108 performs real-time processing and writes the scanned image data to the RAM 111. In the same period T5, when a print job competingly executing is reconfigured for print image processing using the circuit configuration information stored in the RAM 111, it is transferred to the RAM 111 by the scanner I / F 108. The writing of image data is hindered. As a result, it becomes impossible to read the original and store the image data in the RAM 111 in accordance with the paper conveyance of the scanner unit 109, and the scanned image data may be lost. Therefore, such processing cannot be performed.

  6B, as in FIG. 6A, the image processing unit is reconfigured at high speed using the circuit configuration information stored in the RAM 111, but reconfiguration is performed during real-time processing. The conventional case of waiting without waiting is shown. In FIG. 6B, since the processing for reconfiguring the image processing unit 133 for print image processing is not executed in the period T5, the occurrence of the problem as shown in FIG. 6A can be prevented. However, downtime for reconstruction occurs in the processing of the image processing unit 132 in the period T2 and the processing of the image processing unit 132 and the image processing unit 133 in the period T6. This will be described by taking the processing of the image processing unit 132 in the period T2 as an example.

  The image processing unit 132 is not executing processing in the period T1. Since what kind of processing is required next is known in advance as shown in FIG. 2 depending on the type of job, the reconfiguration of the image processing unit 132 is completed in the period T1, so that the period T2 is completed. The start of the process can be accelerated. However, the circuit configuration information cannot be read from the RAM 111 during the period T1 because the RAM 111 is used by real-time processing. As a result, downtime due to reconstruction always occurs at the beginning of each period.

  FIG. 6C is a diagram for explaining the reconfiguration of the FPGA in the image processing apparatus according to the first embodiment. Here, an example in which the reading source of the circuit configuration information is switched between the RAM 111 and the ROM 104 is shown.

  In FIG. 6C, the reconstruction is completed by reading out circuit configuration information of the next required scan image processing from the ROM 104 in the period T1. When the circuit configuration information is read from the ROM 104 and reconfigured, more time is required than when the circuit configuration information stored in the RAM 111 is read and reconfigured. However, even when the circuit configuration information is read from the ROM 104, the reconfiguration of the image processing unit 132 can be completed while the scanner I / F 108 is writing the image data for one original in the RAM 111. Accordingly, the image processing unit 132 can immediately start image processing on the scanned image data in the period T2.

  Similarly, in the period T5, the image processing unit 132 and the image processing unit 133 are reconfigured for the next necessary scan image processing and print image processing. However, during this period T5, since image data input processing from the scanner unit 109, which is real-time processing, is executed, the circuit configuration information is read from the ROM 104, and the image processing unit 132 and the image processing unit 133 are restored. Configure. Thereby, in the period T6, the image processing unit 132 can immediately start image processing on the scanned image data, and the image processing unit 133 can start print image processing.

  As described above, according to the first embodiment, the image processing apparatus having the dynamic partial reconfiguration unit 131 can perform reconfiguration without hindering real-time processing, and can reduce processing time. it can. Further, when the circuit configuration information copied and stored in the RAM 111 is damaged, the downtime of the process during the copying from the ROM 104 to the RAM 111 again can be reduced.

[Embodiment 2]
In the first embodiment described above, the circuit configuration information stored in the ROM is all copied and stored in the RAM when the power is turned on, and the circuit configuration information is read from the ROM or RAM depending on whether or not the real-time processing is executed. explained. However, when there are many jobs that can be executed by the image processing apparatus 100 and the number of circuit configuration information corresponding to the processing executed by these jobs increases, the data size of the circuit configuration information stored in the RAM 111 increases. Therefore, depending on the memory capacity of the RAM 111 and the capacity of image data to be processed, all circuit configuration information may not always be held in the RAM 111 after the power is turned on.

  Therefore, in the second embodiment, control when all circuit configuration information cannot be duplicated and held in the RAM 111 will be described. Since the hardware configuration of the image processing apparatus 100 according to the second embodiment is the same as that of the first embodiment, the description thereof is omitted. The difference between the second embodiment and the first embodiment is that circuit configuration information is copied and stored in the RAM 111 after the job starts. This will be described in detail below.

  FIG. 7 is a flowchart illustrating processing when the image processing apparatus 100 according to the second embodiment uses the image processing unit 132 or the image processing unit 133 to execute, for example, the job illustrated in FIG. Each process shown in this flowchart is achieved by the CPU 101 executing a program stored in the ROM 104. In FIG. 7, S701 to S708 are basically the same as S301 to S308 in FIG. The reconstruction process in S706 is different from S306 in the first embodiment, and will be described later with reference to FIG.

  3 is different from the flowchart of FIG. 3 in the first embodiment in that a copied flag indicating whether each of the circuit configuration information corresponding to a plurality of processes stored in the ROM 104 has been copied to the RAM 111 is displayed in the circuit configuration. It is in the point prepared for every information. This duplicated flag is set in the RAM 111, and the flags corresponding to all the circuit configuration information are off at the start of the job. This indicates that the corresponding circuit configuration information has not been copied to the RAM 111.

  Therefore, after the processing by the reconstructed image processing unit is started in S708, the process proceeds to S709, and the CPU 101 determines whether the copied flag of the circuit configuration information for scan image processing is on. If it is determined that the copied flag is on, that is, it has already been copied to the RAM 111, the process proceeds to S711 without performing the copy process. On the other hand, if the CPU 101 determines that the copied flag is OFF, the process proceeds to S710. In step S710, the CPU 101 copies the circuit configuration information for the currently executed image processing from the ROM 104 to the RAM 111 in a state in which image processing is being performed in the image processing unit 132 or the image processing unit 133, and proceeds to step S711. At this time, the CPU 101 turns on the copied flag of the copied circuit configuration information. Since the processing of S711 to S715 is the same as S309 to S313 of FIG. 3, the description thereof is omitted.

  In the second embodiment, the example in which only one job is executed in the image processing apparatus 100 has been described. However, it is also conceivable that other jobs may be executed in competition using an empty image processing unit. It is done. In this case, it is naturally necessary to perform processing such as determining whether or not real-time processing is performed in S710, and skipping circuit configuration information duplication processing if real-time processing of a competing job is being executed. Further, the timing for performing the process of copying the circuit configuration information to the RAM 111 is not limited to the example shown in FIG. 7, and the same can be realized by performing the process between other processes.

  FIG. 8 is a flowchart for explaining details of the reconfiguration processing in S706 of FIG.

  The difference from the first embodiment is whether or not the duplicated flag is turned on in S801, and if it is turned on, the process proceeds to S802, and the reading source of the circuit configuration information is set as the RAM 111 depending on whether or not the real-time processing is being executed. Alternatively, control for switching to the ROM 104 is performed.

  On the other hand, if the CPU 101 determines in S801 that the duplicated flag is OFF, the process proceeds to S803, and the CPU 101 controls to read circuit configuration information from the ROM 104. Note that the processing of S802 to S806 in FIG. 8 is the same as S401 to S405 in FIG.

  As described above, according to the second embodiment, in an image processing apparatus having a dynamic partial reconfiguration unit, circuit configuration information can be copied to a RAM while considering the presence or absence of real-time processing before starting a job. It becomes possible. Thus, even when all circuit configuration information cannot be copied in advance to the RAM due to the memory capacity of the RAM, the processing time can be reduced as in the first embodiment.

(Other embodiments)
The present invention can also be realized by executing the following processing. That is, software (program) that realizes the functions of the above-described embodiments is supplied to a system or apparatus via a network or various storage media, and a computer (or CPU, MPU, etc.) of the system or apparatus reads the program. It is a process to be executed.

Claims (11)

A dynamic reconfiguration unit that dynamically reconfigures at least part of the circuit;
Configuration information storage means for storing circuit configuration information for reconfiguring at least a part of the circuit in the dynamic reconfiguration unit;
A storage unit that stores a copy of the circuit configuration information stored in the configuration information storage unit, and that can be read faster than the configuration information storage unit;
Control means for controlling to reconfigure at least a part of the circuit of the dynamic reconfiguration unit according to a job to be executed into a circuit capable of executing processing necessary for the job using the circuit configuration information; Have
The control means reconfigures the dynamic reconfiguration unit using the circuit configuration information stored in the storage means when real-time processing using the storage means is not being executed, and the storage means When the real-time processing using is performed, the dynamic reconfiguration unit is controlled to be reconfigured using the circuit configuration information stored in the configuration information storage unit Processing equipment. In the control by the control means, further comprising a detection means for detecting the presence or absence of an error in the circuit configuration information,
The control unit reconfigures the dynamic reconfiguration unit using the circuit configuration information stored in the configuration information storage unit when an error is detected by the detection unit. Item 8. The image processing apparatus according to Item 1.   When the process being executed in the job is a process that does not use the dynamic reconfiguration unit, the control unit executes at least a part of the circuit of the dynamic reconfiguration unit in the job. The image processing apparatus according to claim 1, wherein the image processing device is controlled so as to be reconfigured into an executable circuit.   4. The image processing apparatus according to claim 1, further comprising a duplication unit that copies the circuit configuration information stored in the configuration information storage unit to the storage unit. 5. The circuit configuration information is stored in the configuration information storage unit corresponding to each of a plurality of processes corresponding to jobs that can be executed by the image processing apparatus,
The image processing apparatus according to claim 4, wherein the duplicating unit stores the circuit configuration information in the storage unit in units of circuit configuration information corresponding to each of the plurality of processes.   6. The image processing apparatus according to claim 4, wherein the copying unit copies the circuit configuration information stored in the configuration information storage unit to the storage unit when the image processing apparatus is activated. .   6. The image processing apparatus according to claim 4, wherein the copying unit copies the circuit configuration information stored in the configuration information storage unit to the storage unit before starting a job.   The copy means stores information indicating whether or not the circuit configuration information has been copied to the storage means in units of circuit configuration information corresponding to each of the plurality of processes when the circuit configuration information is stored in the storage means. The image processing apparatus according to claim 5, wherein the image processing apparatus is changed.   The control unit is configured to change a reading destination of the circuit configuration information for reconfiguring the dynamic reconfiguration unit based on whether real-time processing using the storage unit is being executed and the information. The image processing apparatus according to claim 8. A dynamic reconfiguration unit in which at least a part of a circuit is dynamically reconfigured, and configuration information storage means for storing circuit configuration information for reconfiguring at least a part of the circuit in the dynamic reconfiguration unit, A method for controlling an image processing apparatus, comprising: a storage unit that stores a copy of the circuit configuration information stored in a configuration information storage unit, and that can be read at a higher speed than the configuration information storage unit.
When the real-time processing using the storage means is not being executed, the dynamic reconfiguration unit is reconfigured using the circuit configuration information stored in the storage means,
When real-time processing using the storage unit is being executed, the dynamic reconfiguration unit is reconfigured using the circuit configuration information stored in the configuration information storage unit, thereby executing a job to be executed. Accordingly, at least a part of the circuit of the dynamic reconfiguration unit is reconfigured into a circuit that can execute processing necessary for the job by using the circuit configuration information.   A program for causing a computer to function as the image processing apparatus according to any one of claims 1 to 9.

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