JP2015104094A - Pulse generation device and image formation apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent disorder at a point of time when a clock of relatively low frequency for multiplication has rise/fall change by generating pulses for counter which has a finer width by using the clock for multiplication.SOLUTION: A pulse generation device includes: a gray code counter 120 which outputs a count value represented in gray code with clocks (C0) to (C3) of PLLs 1 to 4 obtained from a reference clock (1); a conversion circuit 130 including a gray code conversion part 9 which converts density data (8) of each pixel in a main scanning direction into an on-timing gray code and an off-timing gray code made to correspond to a period from on timing to off timing; and a pulse generation circuit 140 which generates a pulse signal (23) for a period of counting from the on-timing gray code to the off-timing gray code obtained by the conversion circuit 130.

Description

  The present invention relates to a pulse generator and an image forming apparatus for forming an image by performing pulse width modulation on an image having gradation.

  2. Description of the Related Art Conventionally, in an electrophotographic copying machine or the like, the exposure amount of a photoconductor is changed in accordance with the image density in order to reproduce the gradation of an image. A general method for changing the exposure amount is to generate a PWM (Pulse Width Modulation) signal from the image data, and to change the on / off time of the laser for exposing the photosensitive member with this PWM signal. Various methods have been proposed today. In addition, in order to suppress the jitter of the image printing position with respect to the main scanning direction, the generation start position of the pulse is controlled in synchronization with the detection timing of the synchronization signal in the main scanning direction. In order to adjust the magnification, the frequency of the clock for generating the pulse is changed using a PLL circuit.

  Patent Document 1 describes a method of converting and generating a clock having a plurality of phases from a reference clock using a plurality of constant current sources, and generating a PWM signal based on these types of clocks. According to this method, by increasing the number of constant current sources, it is possible to generate only a desired type of clock having a phase intermediate between the two types of original clocks. Therefore, the clock for generating the PWM signal can be finely divided. It is possible to generate with timing difference, and it is possible to increase gradation by increasing the number of division of one pixel by PWM. Patent Document 2 describes a method of generating a PWM signal with a simple configuration by generating binary data of a plurality of bits according to image density and sequentially sending it out by a shift register that supplies a high-speed clock. Has been. Patent Document 3 relates to a liquid crystal electrode drive circuit, which expresses image data itself as a gray code, thereby preventing malfunction caused by glitches when image data is generated by a general pulse signal of a plurality of bit strings. Is described. According to this method, it is possible to suppress the occurrence of glitches even if there is a subtle difference in the operation timing of each bit counter.

Japanese Patent No. 4563737 Japanese Patent No. 5110867 JP 2006-284737 A

  In the invention described in Patent Document 1, it is necessary to provide a large number of constant current sources for performing an analog operation, and there are problems that an increase in circuit scale and a demand for operation accuracy of a circuit become severe. The invention described in Patent Document 2 does not require a large-scale circuit as in Patent Document 1, but it is necessary to operate the shift register with a very high-speed clock in order to finely control the pulse width. In principle, it is difficult to increase the number of divisions per pixel by PWM. Further, since the invention described in Patent Document 3 operates the gray code counter using a higher-speed original clock, the gray code counter can be configured at a practical frequency for a liquid crystal display or the like. When using a high-speed pixel clock such as a copying machine, the operation speed of the flip-flop of the Gray code counter unit is exceeded, and the circuit cannot be configured, or some high-speed circuit must be devised. There is.

  The present invention has been made in view of the above, and generates a pulse for a counter with a finer width by using a relatively low frequency multiplication clock, so that the clock rises and falls at the time of change. An object of the present invention is to provide a pulse generator and an image forming apparatus that can prevent the occurrence of disturbance.

  A pulse generator according to the present invention includes a gray code counter that outputs a count value represented by a gray code by phase-controlling a plurality of types of PLL clocks obtained from a multiplication clock, and a pixel in each main scanning direction. A conversion circuit that converts density data into an on-timing gray code that sets a period from the corresponding on-timing to off-timing and an off-timing gray code; and the gray code counter that is obtained by the conversion circuit. A pulse generation circuit for generating a pulse signal during a period from the timing gray code to the off-timing gray code.

  According to a sixth aspect of the present invention, there is provided a photosensitive member comprising: the pulse generator according to any one of the first to fifth aspects; and a laser from a laser light emitting element driven by a pulse signal output from the pulse generator. An image forming apparatus having a laser scanning unit that scans in the main scanning direction.

  According to these inventions, the count output represented by the Gray code is obtained by controlling the phase of the multiplying clock and the PLL clock having a plurality of frequencies obtained from the multiplying clock. Using a gray code indicating on / off timing converted to set a period corresponding to density data, a fine pulse signal whose width is modulated is generated with a clock having a relatively low frequency. The generated pulse signal can be applied as a signal for turning on and off an image forming laser at high speed, for example. As described above, in the present invention, a PLL clock is generated using a relatively low frequency multiplying clock and the phase is controlled, so that a pulse with a finer width can be generated, which is configured by a normal counter. If the clock rises or falls, there will be no disturbance at the time of change. In addition, the occurrence of glitches can be suppressed by employing the Gray code.

  According to a second aspect of the present invention, in the pulse generator according to the first aspect, one bit of the Gray code counter is the multiplication clock.

  As a mode of outputting the count value represented by the gray code by controlling the phase of the multiplying clock and the PLL clock having a plurality of types of frequencies obtained from the multiplying clock, it is represented by the gray code using the plurality of types of PLL clocks. In addition to a mode in which a count value is generated, a count represented by a Gray code using both a multiplication clock and a multiplied PLL clock, such as replacing one bit of the Gray code counter with a multiplication clock A mode of generating a value can be adopted. In the aspect of generating the count value represented by the Gray code including the multiplication clock as in the latter, it is possible to reduce the number of PLL circuits.

  According to a third aspect of the present invention, in the pulse generator according to the first or second aspect, a synchronization signal for synchronization in the main scanning direction is detected, and a count value of the Gray code counter at the time of detection is detected. And the conversion circuit changes each of the converted gray codes in accordance with a count value of the gray code counter when the synchronization signal is detected. According to this configuration, by changing the gray code of the conversion circuit according to the generation timing of the main scanning synchronization signal, the pulse signal is synchronized with the synchronization signal without changing the phase of the multiplication clock and the PLL clock. Is generated, and jitter of the formed image is suppressed.

  According to a fourth aspect of the present invention, in the pulse generator according to any one of the first to third aspects of the present invention, the pulse generator includes timing adjustment means for setting an adjustment value of a timing within one round cycle by the Gray code counter, and the conversion The circuit is characterized in that each of the converted gray codes is changed corresponding to the adjustment value. According to this configuration, the print position of the image in the main traveling direction can be adjusted in units of one pixel or less.

  A fifth aspect of the present invention is the pulse generator according to any one of the first to fourth aspects, further comprising a magnification setting means for setting a magnification with respect to a main scanning direction, wherein the conversion circuit converts each of the converted gray signals. The code is changed according to the set magnification. According to this configuration, even if the frequency of the PLL clock is kept constant by adjusting the generation position of the pulse signal on the main scan according to the print magnification of the image in the main scan direction, it is possible to substantially print. Therefore, the same effect as when the clock frequency is changed is obtained, and the circuit configuration is simplified.

  According to the present invention, a counter pulse having a finer width is generated using a relatively low frequency multiplication clock, so that it is possible to prevent the occurrence of a disturbance at the rising or falling of the clock.

It is a block diagram which shows 1st Embodiment of a pulse generator, (A) is a figure of a pulse generation circuit, (B) is a figure of a phase shifter. It is a timing chart of FIG. It is a block diagram which shows 2nd Embodiment of a pulse generator, (A) is a figure of a pulse generation circuit, (B) is a figure of a pulse generator, (C) is a figure of a binary conversion circuit. It is a timing chart of FIG. It is a block diagram which shows 3rd Embodiment of a pulse generator. 6 is a timing chart of FIG. It is a block diagram which shows 4th Embodiment of a pulse generator. It is a timing chart of FIG. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram illustrating a schematic configuration of an image forming apparatus to which a pulse generator according to the present invention is applied, in which (A) is a front view and (B) is a top view illustrating a schematic configuration of a laser output device. A chart showing the relationship between the decimal, hexadecimal and binary count values and the gray code value, where (A) is the relationship between the image density value and the gray code, and (B) is the value obtained by inverting the upper 2 bits of the gray code. Is shown.

  Hereinafter, a case where the present invention is applied to image data having a 4-bit density gradation will be described.

(First embodiment)
As shown in FIG. 1A, the first embodiment of the pulse generator includes four-stage PLLs 111 to 114 having the same number as the number of bits of image data. The PLL 111 includes a phase comparator 2, a filter 3, a VCO (voltage controlled oscillator) 4, a frequency divider 5, and a phase shifter 6. The PLL 111 receives a clock (C0) having a frequency determined by the frequency division ratio of the frequency divider 5 and a phase clock (C0) determined by the phase control values of the phase shifter 6 and the phase comparator 2 with respect to the input reference clock (1). The VCO 4 is controlled to generate.

  As shown in FIG. 1B, the phase shifter 6 includes a plurality of delay elements 61 and a selector 62 connected in series. The phase shifter 6 is configured so that the corresponding phase adjustment value is set in the selector 62 so that a PLL output having a required phase is obtained, and the input clock is displaced to the set phase and output. It has become. As shown in FIG. 2, the reference clock (1) is a multiplication clock, the clock (C0) is multiplied by four times, and the phase is displaced by 90 degrees. In the following description, when a signal or value (code or the like) is indicated, it is indicated by parentheses such as a clock (C0).

  The PLL 112 to PLL 114 have the same configuration as the PLL 111, and the phase shift value, the phase comparator, and the frequency divider are set so that the phase control value and the frequency division value are different from each other. As shown in FIG. 2, the output clocks (C0) to (C3) of the PLLs 111 to 114 have their respective frequencies and phases set. That is, here, the clocks (C0) to (C3) are generated from the reference clock (1) having a predetermined frequency, for example, 20 MHz, under the following conditions.

(C0) = frequency: reference clock (1) × 4 multiplication (80 MHz) / phase: 90 degrees (C1) = frequency: reference clock (1) × 2 multiplication (40 MHz) / phase: 90 degrees (C2) = frequency: Reference clock (1) × 1 multiplication (20 MHz) / phase: 90 degrees (C3) = Frequency: Reference clock (1) × 1 multiplication (20 MHz) / phase: 180 degrees And the clock (C0) is the least significant bit (bit0) ), And the clock (C3) side has higher parallel bits, and each clock is input to the input terminals of comparators 16 and 20, which will be described later. In FIG. 2, the value indicated as the signal (19) C3: C0 code represents the output state of the clocks (C0) to (C3) as a 4-bit hexadecimal number (gray in FIG. 10A). See code). Here, the reference clock (1) and the PLLs 111 to PLL 114 constitute a gray code counter 120.

  The gray code conversion unit 9 converts the density gradation of the image data (8) into a predetermined gray code. Here, the gray code is continuous in the numerical value expressed by a predetermined bit (4 bits in FIG. 10A) as shown in the vertical direction of the binary code field of the gray code in FIG. 10A. This is a code expression method in which the hamming distance between bits is always 1, and is used for the purpose of stably latching one value even when jitter occurs in the latch timing. The gray code has a predetermined relationship as shown in FIG. 10A with respect to the density of the image data, and the gray code conversion unit 9 calculates a gray code corresponding to the density of the image data. As will be described later, the laser diode (LD) 25 emits a laser that is time-modulated with image density data, that is, a width-modulated laser. That is, the image data (8) is input with 4 bits, and the density from white to black is expressed by hexadecimal numbers “0” to “F”, and the LD25 is turned on for a longer time as the density is closer to black. Be controlled. The on time of the LD 25 is set by an on timing and an off timing.

  The Gray code conversion unit 9 includes a NOR circuit 26 that negates the logical sum of each bit of the image data, and three exclusives that take the exclusive OR of bit3 and bit2, bit2 and bit1, and bit1 and bit0 of the image data. A logical OR circuit 27, and flip-flop circuits (FF) 28 and 29 provided on the output side of the NOR circuit 26 and the exclusive OR circuit 27.

  The comparator 16 sets on-timing, and at one input end thereof, a 4-bit gray code (19) of the clocks (C0) to (C3) is added to a fixed value “0” corresponding to 1 bit (12). ”Are combined so as to be the most significant bit and input as a total of 5 bits of code (14). On the other hand, at the other input terminal of the comparator 16, a control signal (10) for 1 bit from the Gray code conversion unit 9 is added to a fixed value “0000” of 4 bits as a preset signal (13). It is synthesized so as to be the most significant bit, and is input as a code of a total of 5 bits. The NOR circuit 26 calculates a 1-bit control signal (10) necessary for setting the ON timing of the LD 25 and outputs the control signal (10) to the comparator 16 via the FF. The comparator 16 outputs a signal “1” while the code (14) input to one input terminal matches the code set to the other input terminal.

  The comparator 20 sets an off timing, and a gray code (19) of a 4-bit value of the clocks (C0) to (C3) is input to one input terminal thereof. On the other hand, the gray code (18) corresponding to the image data (8) is input to the other input terminal of the comparator 20. That is, a total of 4 bits of the bit 3 of the image data (8) and the three output bits calculated by each exclusive OR circuit 27 are set so that the bit 3 of the image data (8) is on the high bit side. This is output as a gray code (18) indicating the off timing, and is output to the comparator 20 via the FF 29. The comparator 20 outputs a signal “1” while the gray code (19) input to one input terminal coincides with the gray code (18) set to the other input terminal. The FFs 28 and 29 output the input signal in synchronization with the next reference clock.

  Further, the RS flip-flop (RS-FF) 22 has a pulse output (23) from the Q terminal of "1" when the S terminal is "1", and from the Q terminal when the R terminal is "1". The pulse output (23) is “0”. The Q terminal of the RS-FF 22 is connected to the laser driver 24, and the LD 25 is turned on / off according to "1" / "0" of the pulse output (23).

  Accordingly, when the control signal (10) from the FF 28 of the gray code conversion unit 9 is “0”, the signal (17) from the comparator 16 at the timing when all the clocks (C0) to (C3) become “0”. ), That is, the S terminal of the RS flip-flop (RS-FF) 22 becomes “1”, and the pulse output (23) becomes “1”, that is, is turned on. Thereafter, the signal (21) from the comparator 20, that is, the R terminal of the RS-FF 22 is “1” at the timing when the gray code (19) represented by the clocks (C0) to (C3) coincides with the gray code (18). ", And the pulse output (23) is" 0 ", that is, turned off. The laser driver 24 drives the LD 25 while the pulse output (23) is on to off, and emits light for a time width corresponding to the image density. Here, the comparators 16 and 20 and the RS-FF 22 constitute a pulse generation circuit 140.

  Also, in the above, the gray code conversion unit 9 and the generation circuit unit of the 1-bit signal (12) and 4-bit signal (13) to each input terminal of the comparator 16 are used to convert the image density data from the corresponding on-timing. A conversion circuit 130 configured to convert an on-timing gray code for setting a period until the off-timing and an off-timing gray code is configured.

  Such a circuit configuration unit makes the comparator 16 distinguish between processing at the on-timing and processing when the density of the image data (8) itself is “0” (white). That is, when the density of the image data is other than “0” (white), when the control signal (10) from the NOR circuit 26 becomes “0” in order to ensure the on-timing process, as described above. The laser is emitted by performing various operations. On the other hand, when the density of the image data itself is “0” (white), the control signal is set to “1” from the NOR circuit 26, so that the clocks (C0) to (C3) are all “0”. However, "1" is not output from the comparator 16 to the S terminal. That is, in this case, since the coincidence condition is not satisfied, the comparator 16 does not output “1” to the S terminal even when the clocks (C0) to (C3) are all “0”, and laser emission is not performed. It will be.

  As a result, the comparator 20 sets the R terminal to “1” when the clocks (C0) to (C3) are all “0”, but the comparator 16 does not set the S terminal to “1”. At the same time, it becomes “1” and the output of the RS-FF 22 does not become unstable. Here, a configuration is adopted in which the comparison operation of the comparator 16 is controlled so that both the R and S terminals of the RS-FF 22 do not become “1” at the same time. When “1” is set, FFs may be assembled so that the R terminal is prioritized.

  Next, the operation of the circuit of FIG. 1 will be described using the timing chart of FIG. In FIG. 2, the main signals are gray codes represented by the reference clock (1), clocks (C0) to (C3), and clocks (C0) to (C3) [(19) C3: C0 code]. The image data (8), the outputs (10, 18) of the gray code converter 9, the outputs (17, 21) of the comparator 16 and the comparator 20, and the pulse output (23) are shown. Here, the reference clock (1) is 20 MHz.

  In FIG. 2, the density of the image data (8) of each pixel changes, for example, from “3” → “8” → “F” → “C” → “0” → “4” → “2”. To do. The gray code conversion unit 9 converts the image data (8) into a gray code and outputs it after delaying by one cycle of the reference clock (1). The image data (8) is delayed by one cycle of the reference clock (1), and the gray code (18) is “2” → “C” → “8” → “A” → “0” → “ 6 ″ is output to the comparator 20.

  When the control signal (10) of the FF 28 is “0”, “1” is output as the output signal (17) from the comparator 16 at the timing of [(19) C3: C0 code] = “0000” ( For example, see pulses (31) and (34) shown in output (17) in FIG.

  Further, the output (21) of the comparator 20 becomes “1” at the timing when the gray code (18) = [(19) C3: C0 code] of the image data, so that the image data (8) With respect to the change of “3” → “8” → “F” →..., (3 + 1) th, (8 + 1) th of 1/16 period (minimum control width, eg 320 MHz) of the reference clock (1), It becomes “1” at the (15 + 1) th... (For example, refer to the pulses (32) and (35) shown in the output (21) in FIG. 2).

  Thereby, the pulse output (23) of the RS-FF 22 is from the timing when the output (17) of the comparator 16 becomes “1” to the timing when the output (21) of the comparator 20 becomes “1”. The pulse having a width corresponding to the image density value can be generated by turning on for a while (see, for example, pulses (33) and (36) shown in the output (21) in FIG. 2).

  On the other hand, if the control signal (10) of the FF 28 is “1” by the “white” determination of the gray code conversion unit 9 (see the signal (39) shown in the control signal (10) of FIG. 2), During this time, the output (17) of the comparator 16 remains “0” as shown in FIG. That is, when the image data (8) is “0” (see the pixel signal (37) in FIG. 2), the gray code output (18) after one cycle becomes “0” (the signal ( 38)), the control signal (10) from the FF 28 becomes a signal (39) indicating "1", so that the comparator 16 outputs "0" and the pulse signal (23) is not output, The LD 25 does not emit light.

  In FIG. 2, clocks (700) and (700A) to (700D) are replaced with clocks (1) and (C0) to (C3), and a comparative example in which a code is generated by a general binary counter. It is shown. In a general binary counter, the counter output changes in synchronization with the rising edge of the reference counter clock. In the comparative example, the reference clock (700) is the counter clock, and the clocks (700A) to (700D) are output from the binary counters. In the clocks (C0) to (C3), the clock (C0) is the fastest clock, but the minimum control width is a clock for four periods corresponding to 320 MHz. In the general binary counter method shown in (3), a 320 MHz clock is required.

  In the clocks (C0) to (C3), the hamming distance between codes that are continuous in the time direction with the minimum control width is 1, but in the clocks (700A) to (700D) from the binary counter, for example, in the time direction A plurality of signals (702) can be changed simultaneously, such as a signal (701) partially enlarged in FIG. In such a case, although the clocks (C0) to (C3) and the clocks (700A) to (700D) from the binary counter are not actually changed at the same time due to variations in circuit delay time. In the case of the clocks (C0) to (C3) that are gray codes, since the number of clocks that change is one, the comparators 16 and 20 may malfunction even with a simple configuration as shown in FIG. Absent. However, in the clocks (700A) to (700D) from the binary counter, due to delay variations, for example, between the values “7” and “8”, the false values “6”, “2”, “A” (signal ( 702)) may be detected as a glitch, and thus misdetection cannot be prevented.

  Next, as shown in FIG. 3, the second embodiment of the pulse generator includes a synchronization processing circuit 150 that changes the output of the Gray code conversion unit 9 according to the detection timing of the synchronization signal (49) for main scanning. It is a thing. In addition, the same number is attached | subjected about the same structure as FIG.

  The synchronization processing circuit 150 includes an FF 40, an inverter 41, a pulse generation circuit 42, a binary conversion circuit 47, and an adder 48.

  The synchronization signal (49) is input to the clock terminal of the FF 40, and the gray code values represented by the clocks (C0) to (C3) are latched at the rising edge of the synchronization signal (49), and the synchronization timing value is obtained. (50). The synchronization timing value (50) is held until the rising edge of the next synchronization signal (49) occurs.

  The pulse generation circuit 42 has the same configuration as the pulse generation circuit 140 including the comparators 16 and 20 and the RS-FF 22, as shown in FIG. The pulse generation circuit 42 includes clocks (C0) to (C3) (see code (43) in FIG. 3), a synchronization timing value (50), and bit3 which is an upper bit of the synchronization timing value (50). A value (45) obtained by inverting bit2 by the inverter 41 is compared, and a pixel clock (46) as a result of the comparison is generated. When the upper 2 bits of the 4-bit gray code are inverted, a gray code value shifted by +8 is obtained as shown in FIG. 10B. Therefore, the pulse generation circuit 42 generates the synchronization signal (49) at the generation timing. The output is set to “1”, and the output is set to “0” at a timing delayed by ½ period of the reference clock (1) from the generation timing of the synchronization signal (49) (corresponding to a Gray code value shifted by +8). . Therefore, the pixel clock (46) becomes a pixel clock synchronized with the generation timing of the synchronization signal (49), and the pixel is sent to a higher-level device that sequentially supplies image data in the main scanning direction, for example, an image forming apparatus (see FIG. 9). At the same time as being transmitted as a pixel clock indicating timing, it is used as drive timing for the FF 28 and FF 29 of the Gray code conversion unit (9).

  As shown in FIG. 3C, the binary conversion circuit 47 performs exclusive OR (XOR) on the 4-bit synchronization timing value (50) that is output from the FF 40 by two adjacent bits. Output. Thus, the gray code value at the timing when the synchronization signal (49) is detected is converted into normal binary 4-bit data and output to the adder (48). In the adder 48, the gray code value at the timing when the synchronization signal (49) is detected is added to the image data (8) as a constant offset. Note that the circuits 42 and 47 shown in FIGS. 3B and 3C are also applied to third and fourth embodiments described later.

(Second Embodiment)
In the first embodiment, the pulse output (23) is turned on during the period from the state where the gray code is “0000” to the gray code determined by the image density value. However, in the second embodiment, the gray code is the synchronization signal ( 49) Turns on from the value at the time of detection, and turns off at the value obtained by adding the image density value. According to the second embodiment, the pulse (23) having a width determined by the image density value is generated from the timing at which the synchronization signal (49) is detected within one cycle of the reference clock (1), and the main scanning of the image is performed. The printing position in the direction is controlled according to the synchronization signal (49), and jitter in the main scanning direction is suppressed.

  Next, the operation of the circuit of FIG. 3 will be described with reference to the timing chart of FIG. In addition, the same code | symbol is attached | subjected about the same signal as FIG. In addition, in general, there are several thousand or more pixels in one cycle of the synchronization signal (49), but here, for convenience of explanation, only a few pixels are shown.

  The synchronization signal (49) indicates the synchronization timing by its rising edge (60, 61). The synchronization detection FF 40 latches the clocks (C0) to (C3) at the rising edges (60, 61) of the synchronization signal (49). At the rising edge (60), “B” of the Gray code (19) is latched as an example (see arrow (62) and value (63) in FIG. 4).

  The pulse generation circuit 42 has a latched value “B” (see value (63)) and a value “7” (value (64) obtained by inverting the upper 2 bits of this value “B” (see value (63)). )) Is entered. Accordingly, the pulse generation circuit 42 outputs a pixel clock (46) such that the gray code represented by the clocks (C0) to (C3) rises at “B” and falls at “7”. When the rising edge (61) of the synchronization signal (49) is generated next time, the value “C” is latched, and the clocks (C0) to (C3) are determined by the value “0” obtained by inverting the upper 2 bits. Is a signal (461) of the pixel clock (46) rising at "C" and falling at "0".

  The values “B” and “C” latched at the rising edges (60, 61) of the synchronization signal (49) are converted into “D” and “8” by the binary conversion circuit 47, and the image data (8). Is added to Usually, before the rising edge of the synchronization signal (49), the image data (8) is in an invalid period, and the value is fixed to “0”. Since the image data (8) is “0” during this period, the control signal (10) of the comparator 16 is “1” during this invalid period.

  For example, when the image data (8) is “C” (see signal (65) in FIG. 4), the value “B” latched by the FF 40 (see signal (63) in FIG. 4) is binary. It is converted to the value “D” (see signal (68) in FIG. 4), and added to the image data “C” (see signal (65) in FIG. 4). It is converted (see signal (66) in FIG. 4) and output as “D” (see signal (67) in FIG. 4).

  When the control signal (10) of the comparator 16 is “0”, the output (17) of the comparator 16 is synchronized with the synchronization timing value latched by the synchronization signal (49) and the clocks (C0) to (C3). "1" at the timing when the value of the gray code represented by For example, when the above-described image data is “C” (see the signal (65) in FIG. 4), the latched value is “B” and is represented by clocks (C0) to (C3). It becomes “1” at the timing when the gray code becomes “B” (see signal (69) in FIG. 4).

  The output (21) of the comparator 20 is equal to the gray code value (18) generated from the image data and the value latched by the FF 40 with the gray code represented by the clocks (C0) to (C3). It becomes “1” at the timing (see signal (70) in FIG. 4). As a result, the pulse output (23) is not changed until the output of the comparator 16 becomes "1" after the output of the comparator 16 becomes "1" (that is, the signals (69) to (70) in FIG. ) Period) Turn on.

  Also, the time (see time (73) in FIG. 4) from the rising edge (60) of the synchronization signal (49) to the first pixel rising edge (see signal (71) in FIG. 4) of the pulse output (23). ) And the next rising edge of the synchronizing signal (49) (see signal (61) in FIG. 4) to the rising edge of the first pixel of the next pulse output (23) (see signal (72) in FIG. 4). ) (See time (74) in FIG. 4), it can be seen that both are the same time by being controlled as described above.

(Third embodiment)
Next, the third embodiment of the pulse generator includes a timing adjustment unit 160 as shown in FIG. The timing adjustment unit 160 includes an adder 81 and a code conversion circuit 82 for adding the timing adjustment value (80). The adder 81 adds the timing adjustment value (80) to the binary conversion value of the Gray code latched at the timing of the synchronization signal (49). In addition, the same code | symbol is attached | subjected to the structure same as FIG.

  In the third embodiment, the print position is controlled so as to suppress the jitter of the print position of the image by the detection timing of the synchronization signal (49) of the main scan, and the print position is set by the set timing adjustment value (80). Can be shifted in the unit of the minimum control width in the main scanning direction so that fine adjustment is possible.

  That is, the timing adjustment value (80) is a 4-bit value set by the CPU of the control unit (not shown) through the operation unit (not shown) of the image forming apparatus 200 (see FIG. 9A). The value of the gray code represented by the clocks (C0) to (C3) at the generation timing of the synchronization signal (49) is held in the FF 40, and this value is once converted into a normal binary number by the binary conversion circuit 47. The timing adjustment value (80) is added to this value as an offset by the adder 81. In the second embodiment shown in FIG. 3, the output of the binary conversion circuit 47 is input to the Gray code conversion unit 9, but here the result of adding the timing adjustment value (80) is input to the Gray code conversion unit 9. Entered.

  The code conversion circuit 82 is configured by the same circuit as the circuit within the broken line 47 of the gray code conversion unit 9 and converts a normal binary number into a gray code value. The output (85) of the code conversion circuit 82 is used for processing in the pulse generation circuit 42 and the comparator 16 in the same manner as the synchronization timing value (50) latched by the FF 40 in FIG.

  In this way, by making it possible to set the position offset in the main scanning direction with the timing adjustment value (80) in units of the minimum control width, fine adjustment of the exposure position in the main scanning direction between the lasers from the LD 25 of each color can be performed. Further, it is possible to finely adjust a problem that occurs in an LD of a type in which a plurality of laser beams are generated from one element and a difference occurs in an exposure position in the main scanning direction between the beams.

  Next, the operation of the circuit of FIG. 5 will be described using the timing chart of FIG. In addition, the same code | symbol is attached | subjected about the same signal as FIG. FIG. 6 shows the timing when the timing adjustment value (80) is set to a predetermined value, for example, “5”. Other conditions include the generation timing of the synchronization signal and the image data shown in FIG. It is the same.

  As in FIG. 4, the synchronization timing value (50) becomes “B” by the first rising edge of the synchronization signal (49). The value “B” (see the signal (63) in FIG. 6) is once converted into the value “D” by the binary conversion circuit 47. Next, the value “5” of the timing adjustment value (80) is added to the value “D” by the adder 81 to obtain the value “2” (see reference numeral (86) in FIG. 6). (That is, the lower one digit of “D” + “5” = “12” is valid.) This value “2” is converted to the value “3” by the Gray code conversion circuit 82 (the sign ( 87)) and input to the pulse generation circuit 42 and the comparator 16. As a result, the effective edge of the pixel clock (46) moves to a position offset by +5, and the pulse ON timing by the comparator 16 also moves by +5.

  The input timing of the image data (8) is changed by changing the timing of the pixel clock (46), but the data itself is the same as in FIG. Since the value added to the image data (8) has a form in which the timing adjustment value (80) is added as compared with FIG. 4, the processing in the gray code conversion unit 9 is only "5" corresponding to the timing adjustment value. The shifted value is output to the comparator 20. The pulse output (23) is generated by the comparators 16, 20 and the RS-FF 22 in the same manner as in FIG. 4, but the time from the rising edge of the synchronization signal (49) to the first pulse output (in FIG. 6). The time (see 73, 74) is longer by the value “5” of the timing adjustment value (80) than in FIG. 4, and printing from the synchronization signal (49) is performed in accordance with the timing adjustment value (80). It can be seen that the position can be adjusted.

  In the third embodiment, the timing adjustment value (80) is added to the latch value of the synchronization signal (49). However, the third embodiment is applied to the first embodiment regardless of the synchronization signal (49). It may be a configuration.

(Fourth embodiment)
Next, the fourth embodiment of the pulse generator includes a magnification setting unit 90 as shown in FIG. The fourth embodiment sequentially corrects the print position of the pixel in the main scanning direction according to the print magnification value set from the outside, and a magnification setting unit is added to the timing adjustment value (80) input portion of FIG. 90 is added. However, the synchronization signal (49) is different from FIG. 5 in that the falling edge is used as the synchronization timing, and the rising edge is used for pre-processing for the synchronization processing.

  The magnification setting unit 90 includes a synchronous differentiating circuit 91, a 9-bit adder 92, an 8-bit FF 93, and a counter 94. The magnification adjustment value (95) is a value corresponding to the print magnification set by the CPU of the control unit (not shown) via the operation unit (not shown) of the image forming apparatus 200 (see FIG. 9). 92. At this time, the magnification adjustment value (95) is input to the adder 92 by adding “0” to the most significant bit to be 9 bits.

  The synchronous differentiation circuit 91 outputs “1” only for one clock period in synchronization with the pixel clock (46) after the synchronization signal (49) becomes “1”. The 8-bit FF 93 latches the output value of the adder 92 in synchronization with the pixel clock (46). The FF 93 sets all bits to “0” when “1” is input from the synchronous differentiation circuit 91 to the CL terminal. Therefore, the FF 93 becomes “0” after the rising edge of the synchronizing signal (49), and thereafter latches the cumulative addition of the magnification adjustment value (95) in synchronization with the pixel clock (46). The output of the FF 93 is made 9 bits by adding “0” to the most significant bit and returned to the adder 92.

  The output of the synchronous differentiation circuit 91 is also input to the clear terminal of the 4-bit counter 94, and the counter 94 is simultaneously cleared to “0”. The counter 94 has a count operation enable terminal EN. When the most significant bit (bit 8) of the addition result of the adder 92 is “1”, the counter 94 counts “1” in synchronization with the pixel clock (46). The output value is input to the adder 81.

  Next, the operation of the circuit of FIG. 7 will be described using the timing chart of FIG. Here, it is assumed that the magnification adjustment value (95) is set to a predetermined value, for example, “4”.

  Due to the rising edge of the synchronizing signal (49) (see signal (100) in FIG. 8), the output of the synchronizing differentiation circuit 91 outputs a pulse of “1” only for one clock period of the pixel clock (46) (FIG. 8). Middle signal (102)). With this pulse, the values of the 8-bit FF 93 and the 9-bit adder 92 become “00” and “004”, respectively, in the next pixel clock period (see signals (103, 104) in FIG. 8). At this time, since the falling edge of the synchronizing signal (49) (see the signal (101) in FIG. 8) has not yet occurred and is an invalid image period at the end of one line, the counter in FIG. Each signal drawn below the output of 94 repeats the processing of the last invalid period (white pixel state) of the previous line.

  As described with reference to FIGS. 4 and 6, the synchronization timing value (50) is represented by the clocks (C0) to (C3) by the falling edge of the synchronization signal (49) (see the signal (101) in FIG. 8). The gray code value “3” to be latched is latched (see signal (111) in FIG. 8), each unit is set according to the value, and the comparator is set to the print position according to the synchronization signal (49). 16. The input value to the comparator 20 is controlled. Immediately after the start of printing of one line, the output of the counter 94 is “0”, so at this timing, the operation is the same as in FIG.

  As the holding value of the FF 93, “4” of the magnification adjustment value (95) is sequentially added, the FF 93 is “FC” (see the signal (106) in FIG. 8), and the adder 92 is “100” (FIG. 8). Bit 8 becomes “1” (see signal (108) in FIG. 8) and the output of the counter 94 counts up from “0” to “1” (see FIG. 8). 8 (see 110).

  Since the output side of the counter 94 is connected to the adder 81, the output of the adder 81 changes from “2” to “3” (see the signal (113) in FIG. 8), and the output of the code conversion circuit 82 Changes from “3” to “2”, and the input to the pulse generation circuit changes from “F” to “E”.

  In FIG. 8, the image data immediately before the change in the signal (110) changes from “F” to “F”, and the pulse output (23) has a value corresponding to the minimum control width of 15 pieces. The signal (114) indicating the period of the pulse corresponding to “F” in the first half is 16 signals, whereas the signal (14) indicating the period of the pulse corresponding to “F” in the second half is controlled. 115), it can be seen that the added value by the counter output has increased to 17 pieces. In the subsequent signal (116), the pulse period has returned to 16 again, and a 1/16 fine period of one pixel clock is inserted only in the signal (115) portion. In accordance with the output magnification adjustment value (95) of 94, the print position is moved by 1/16 each time counting up in a certain cycle, so that the actual print magnification is increased (enlarged). Fine adjustment of the magnification becomes possible.

  Here, for simplicity of explanation, the reference clock (1) is set to the frequency for the most reduced printing, and the print magnification is increased in the enlargement direction as the magnification adjustment value (95) is set larger. It is configured to change. Therefore, the magnification adjustment value (95) can be changed in a smaller direction or a larger or smaller direction depending on the setting of the reference clock (1).

  In the fourth embodiment, the magnification adjustment value (95) is set instead of the timing adjustment value (80). However, the timing adjustment value (80) may be set.

  In the above embodiment, the clocks (C0) to (C3) from the PLLs 111 to 114 are used as the gray code generation clocks. Instead, for example, the reference pulse (1) is used for multiplication. For example, clocks (C2) and (C3) may be generated by adjusting the phase. In this way, the number of PLL circuit configurations can be reduced.

  Further, the gray code is not limited to 4 bits, and may be 3 bits or 5 bits or more. Further, in this embodiment, a phase shift is added to a general analog PLL, but a plurality of PLL clocks that are gray codes can be generated in a digital PLL used in a large-scale IC or the like. .

  The pulse generator described above can be applied to the image forming apparatus 200 including the laser scanning unit 290. As shown in FIG. 9A, the image forming apparatus 200 includes an image forming unit 210, an intermediate transfer unit 220, a secondary transfer unit 230, a fixing unit 240, a paper feeding unit 250, a paper conveyance path 260, and an image reading unit 270. And an automatic document feeder 280 is mounted on the upper part of the apparatus main body. Further, the image forming apparatus 200 includes an operation unit (not shown) that receives an instruction from the user and the like, and also includes a control unit (not shown) having a CPU (Central Processing Unit). By controlling the operation of each unit, the image data is subjected to multicolor or single color image forming processing on the paper.

  The image forming unit 210 includes a laser scanning unit 290, which is a laser output device, and image forming units 210A to 210D for each color having the same structure. The laser scanning unit 290 has a housing, and necessary optical components for each color are arranged therein. The laser scanning unit 290 converts the image data read by the image reading unit 270 into Bk, C, M, and Y colors, and the laser beam modulated by the converted image data of each color is used by the image forming units 210A to 210D. The surfaces of the photosensitive drums 202A to 202D are exposed and scanned along the axial direction (main scanning direction) to form respective electrostatic latent images. The image forming unit 210A, which is representatively described, includes a photosensitive drum 202A, and includes a charger 203A, a developing unit 204A, and a cleaner unit 205A around the rotation direction (sub-scanning direction). The intermediate transfer unit 220 includes an intermediate transfer belt 221, a driving roller 222, a driven roller 223, and primary transfer rollers 224A to 224D. The secondary transfer unit 230 secondarily transfers the toner image on the surface of the intermediate transfer belt 221 to a sheet and sends it to the fixing unit 240.

  9B, the laser scanning unit 290 includes an LD 25, a polygon mirror 291 that is a rotating polygon mirror, a motor 292, an Fθ lens 293, and a reflection mirror 294 that directs the laser toward the photosensitive drum 202A. Further, the laser scanning unit 290 includes a reflection mirror 295 and a BD (Beam Detector) sensor 296 such as a photodiode that functions as a detection unit for a synchronization signal.

  The LD 25 is in charge of one color, and is a light source that emits a beam-shaped laser L so as to be directed to the polygon mirror 291 through a lens (not shown) that forms a parallel light flux. The laser L emitted from the LD 25 is reflected by each surface of the polygon mirror 291 that is rotated at a constant speed by a motor 292. The laser L is scanned by the rotation of the polygon mirror 291. Optical components including the Fθ lens 293 are disposed within a predetermined scanning range. The laser L that has passed through the Fθ lens 293 and the reflection mirror 294 is scanned in the axial direction indicated by the arrow X on the photosensitive drum 202A. The laser L starts a width modulation operation according to the density of the pixel data when a predetermined time has elapsed after the synchronization signal is detected by the BD sensor 296, and thereby, a fixed position in the main scanning direction on the photosensitive drum 202A. Then, image formation is performed. The photosensitive drum 202A is rotated at a constant speed around an axis by a motor (not shown), and is exposed in the rotation direction (sub-scanning direction) in order to form an electrostatic latent image corresponding to image data on the surface.

  In addition, it should be thought that description of the above-mentioned embodiment is an illustration in all the points, Comprising: It is not restrictive. The scope of the present invention is shown not by the above embodiments but by the claims. Furthermore, the scope of the present invention is intended to include all modifications within the meaning and scope equivalent to the scope of the claims.

111-114 PLL
120 Gray code counter 130 Conversion circuit 9 Gray code conversion unit 140 Pulse generation circuit 16, 20 Comparator 22 RS-FF
25 Laser diode (laser light emitting element)
150 synchronization processing circuit 160 timing adjusting unit 90 magnification setting unit 1 reference clock C0 to C3 PLL clock 200 image forming apparatus

Claims (6)

A gray code counter that outputs a count value represented by a gray code by phase-controlling a plurality of types of PLL clocks obtained from the multiplication clock;
A conversion circuit that converts density data of each pixel in the main scanning direction into an on-timing gray code and an off-timing gray code that sets a period from the corresponding on-timing to off-timing;
A pulse generation device comprising: a pulse generation circuit that generates a pulse signal during a period in which the Gray code counter counts from an on-timing Gray code to an off-timing Gray code obtained by the conversion circuit. 2. The pulse generator according to claim 1, wherein one bit of the Gray code counter is the multiplication clock. A synchronization processing circuit for detecting a synchronization signal for synchronization in the main scanning direction and obtaining a count value of the Gray code counter at the time of detection;
3. The pulse generation device according to claim 1, wherein the conversion circuit changes each of the converted gray codes in accordance with a count value of the gray code counter when the synchronization signal is detected. Timing adjustment means for setting an adjustment value of timing within a round cycle of counting by the Gray code counter,
The pulse conversion device according to claim 1, wherein the conversion circuit changes each of the converted gray codes in accordance with the adjustment value. A magnification setting means for setting a magnification with respect to the main scanning direction is provided.
5. The pulse generation device according to claim 1, wherein the conversion circuit changes each of the converted gray codes in accordance with the set magnification. 6. The pulse generator according to claim 1, and a laser scanning unit that scans a laser from a laser light emitting element driven by a pulse signal output from the pulse generator in a main scanning direction on a photosensitive member. An image forming apparatus.

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