JP2006150696A - Image forming apparatus and method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To measure the light beam main scanning time between two points with high precision by an inexpensive arrangement. <P>SOLUTION: In the image forming apparatus for forming an electrostatic latent image on a photosensitive drum 4 by irradiating the photosensitive drum 4 with a laser beam a modulated based on image data h while polarizing in the main scanning direction, when the scanning time after the laser beam a is detected by a first BD sensor 5 until being detected by a second BD sensor 6 is measured by counting a reference clock signal d and a PWM modulation clock signal e obtained by multiplying the frequency of the reference clock signal d 16 times, a component having a scanning time longer than one period of the reference clock signal d is measured by counting the reference clock signal d, and component having a scanning time shorter than one period of the reference clock signal d is measured by counting the PWM modulation clock signal e. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an image forming apparatus and an image forming method, and more particularly to an electrophotographic image forming apparatus and the like.

  Conventionally, an image forming apparatus is a charging device that uniformly charges the photosensitive surface of a photosensitive drum, a latent image forming device that forms an electrostatic latent image according to image data on the charged photosensitive surface, and develops the electrostatic latent image. And a transfer device that transfers the developed latent image onto a recording sheet, and image forming processing is performed while rotating the photosensitive drum.

  In addition, the latent image forming apparatus polarizes the light beam modulated based on the image data in the main scanning direction by rotating, for example, a polygon mirror, and irradiates the photosensitive drum with correction by an optical lens such as an fθ lens. By doing so, an electrostatic latent image is formed on the photosensitive surface of the photosensitive drum.

  At this time, the polygon mirror is normally rotated at a constant angular velocity, whereas the optical path length of the polygon mirror and the photosensitive drum is the shortest in the central portion in the main scanning direction and gradually becomes longer toward both ends. The main scanning speed on the photosensitive drum will change. Therefore, an fθ lens is used to correct the change in the main scanning speed so that the main scanning speed becomes constant.

However, when a plastic lens is used as a lens such as an fθ lens used in a scanning optical system for a light beam, the shape and refractive index of the plastic lens change due to changes in photosensitive temperature and in-machine temperature. Due to such magnification error of the optical system, one pixel per pixel becomes larger or smaller, and as a result, a main scanning magnification error that the length of one main scanning line differs from a predetermined length occurs . A quality image cannot be obtained.

  In addition to this, errors in the main scanning magnification are also caused by errors in the write clock signal, wavelength difference of the light beam light source, component mounting accuracy, positional deviation between the photoconductor and optical scanning device, and variations in the accuracy of each surface of the polygon mirror. Will occur.

  This error in the main scanning magnification causes variations in the image writing position by a laser beam modulated based on the image data, or in a color copying machine that forms an image using a plurality of laser beams, photosensitive drums, etc. This may cause color misalignment and cause image quality degradation.

  As a countermeasure to such a problem, the scanning time is detected using signals obtained from the two photodetectors, and the amount of deviation between the detected scanning time and the reference scanning time obtained in advance is obtained, There has been proposed a scanning optical device that adjusts the main scanning time by moving at least one of the lenses constituting the scanning optical system in accordance with the amount of deviation (see Patent Document 1).

  The main scanning magnification is automatically corrected by detecting the laser beam between two points on the main scanning line and controlling the polygon motor so that the deflection speed of the laser beam between the two detected points is constant. An image forming apparatus has been proposed (see Patent Document 2).

Further, for each of the plurality of laser beams, the laser beam is detected at at least two locations of the main scanning line, and a predetermined clock signal is counted while the laser beams are detected at the first and second locations. In response to this, there has been proposed a method of correcting the image writing modulation frequency of the laser beam and further correcting the timing from the synchronization position of the plurality of laser beams to the image writing (see Patent Document 3).
Japanese Patent Laid-Open No. 5-19204 JP-A-8-136838 Japanese Patent Laid-Open No. 9-58053

  However, in Patent Documents 1 to 3, in order to adjust the main scanning magnification with high accuracy, it is necessary to measure the laser beam scanning time between two points with high accuracy.

  In order to measure the laser beam scanning time between two points with high accuracy, the frequency of the clock signal used for the measurement may be increased. However, if a high-frequency clock signal is used, the laser beam scanning time between the two points can be measured. As the number of bits of the count value increases, the size of the measurement circuit increases accordingly, and there is a problem that there is a high possibility of causing malfunctions, such as failure to synchronize between flip-flops in the measurement circuit.

  In addition, stable circuit operation can be obtained at a high frequency by designing a circuit with high accuracy using high-accuracy components, but there is a limit to this and the cost is also increased.

  Therefore, an object of the present invention is to provide an image forming apparatus and an image forming method capable of measuring the light beam main scanning time between two points with a low cost and high accuracy.

  In order to achieve the above object, the present invention provides an image for forming an electrostatic latent image on a photoconductor by irradiating the photoconductor with a light beam modulated based on image data being polarized in the main scanning direction. A first generation unit that generates a reference clock signal; a second generation unit that generates a sub-clock signal having a frequency higher than that of the reference clock signal based on the reference clock signal; Measuring means for measuring a scanning time between two points on the main scanning line of the beam by using the reference clock signal and the sub clock signal, and the measuring means has a scanning time shorter than one period of the reference clock signal. Are measured using the sub-clock signal.

  According to the present invention, an existing reference clock signal and a sub-clock signal generated based on the reference clock signal and having a frequency higher than that of the reference clock signal are used to connect two points on the main scanning line of the light beam. By measuring the scanning time and measuring the scanning time component shorter than one cycle of the reference clock signal using the sub clock signal, the optical beam main scanning time between the two points can be measured with high accuracy with an inexpensive configuration. It is possible to provide an obtained image forming apparatus and an image forming method.

  Hereinafter, the best mode for carrying out the present invention will be described with reference to the drawings.

[First Embodiment]
FIG. 1 is a diagram showing a schematic configuration of an exposure scanning system of the image forming apparatus according to the first embodiment of the present invention.

  In FIG. 1, a laser beam a emitted from a semiconductor laser 1 is deflected by a polygon mirror 2, optically corrected by an fθ lens 3 and an optical lens group (not shown), and exposed and scanned on a photosensitive drum 4. The At this time, the fθ lens 3 performs optical correction so that the laser beam a is exposed and scanned on the photosensitive drum 4 at a constant speed.

  By such exposure scanning, an electrostatic latent image is formed on the photosensitive surface of the photosensitive drum 4. Thereafter, a print image is formed through development, transfer, and fixing processes by a unit group (not shown).

  The counting device 7 detects when the laser beam a passes through the BD sensor 6 from the time when the first BD signal b detected when the laser beam a passes through the BD (beam detect) sensor 5 is input. The time until the second BD signal c is input is measured.

  In this time measurement, the image clock signal d (reference clock signal) output from the reference clock generator 8 and the PWM clock signal e for PWM modulation (multiplied clock) having a frequency obtained by multiplying the frequency of the image clock signal d by 16 times. The component of the scanning time that cannot be measured with the image clock signal d is measured with the PWM clock signal e.

  In other words, a component having a scanning time longer than one cycle of the reference clock signal d is measured by counting the reference clock signal d, and a component having a scanning time shorter than one cycle of the reference clock signal d is used for PWM modulation. This is measured by counting the clock signal e.

  The count value f counted by the counting device 7 (that is, the laser beam scanning time between the two BD sensors 5 and 6) is stored in the storage device 10 and output to the laser drive control device 11. The laser drive control device 11 drives and controls the semiconductor laser 1 so as to emit a laser beam a that has been subjected to pulse width modulation (PWM) based on the input image data h.

  At this time, the laser drive control device 11 corrects the main scanning magnification using the laser beam scanning time between the two BD sensors 5 and 6, and PWM-modulates the image signal i (for example, the image data h) at a predetermined timing. Signal) is output to the semiconductor laser 1. As a correction method when the laser drive control device 11 corrects the main scanning magnification using the laser beam scanning speed between the two BD sensors 5 and 6, the correction method disclosed in Patent Documents 1 to 3 is used. Can be adopted.

  FIG. 2 is a circuit diagram of the reference clock generation device 8, the multiplied clock generation device 9, and the count device 7 shown in FIG. 1, that is, a measurement circuit that measures the laser beam scanning time between two points.

  In FIG. 2, an oscillator 100 is an oscillator that generates an image clock signal d, and corresponds to the reference clock generation device 8 of FIG. The PLL circuit 101 is a circuit that generates a PWM clock signal (16-fold clock signal) e, and corresponds to the multiplied clock generator 9 in FIG. The other part of FIG. 2 corresponds to the counting device 7 of FIG.

  The image clock signal d from the oscillator 100 is supplied to the PLL circuit 101, the D flip-flop 1000, the 14-bit counter 104, and the one-shot pulse generation circuit 103, and is not shown in the laser drive control device 11 of FIG. It is also supplied to a PWM circuit, a video data generation circuit, and the like. The PLL circuit 101 multiplies the frequency of the image clock signal d from the oscillator 100 by 16 and supplies it to the D flip-flops 1000 to 1015 and the D flip-flops 102 and 108 as a 16-fold clock signal. Also supplied as a PWM clock signal e.

  The D flip-flop 102 is provided to stabilize the operation using the output signal BD1 (corresponding to the first BD signal b) of the first BD sensor 5 as a synchronization signal, and the D flip-flop 108 is provided with the second BD sensor 6. The output signal BD2 (corresponding to the second BD signal c) is used as a synchronizing signal to stabilize the operation. The OR logic circuit 109 collectively outputs the two synchronous BD signals from the D flip-flops 102 and 108. The one-shot pulse generation circuit 103 receives the synchronous BD signal from the OR logic circuit 109, generates a one-shot pulse corresponding to one cycle of the image clock signal d, and D flip-flops 1200 to 1215 as latch signals, This is supplied to the 14-bit latch circuit 16.

  The 14-bit counter 104 counts the image clock signal d from the oscillator 100 endlessly, and outputs the count value to the 14-bit latch circuit 105. The gate input terminal of the 14-bit latch circuit 105 is connected to the output terminal of the OR logic circuit 109, and the 14-bit latch circuit 105 displays the image from the 14-bit counter 104 when the synchronous BD signal from the OR logic circuit 109 is Low. The count value of the clock signal d is latched.

  The count value of the image clock signal d latched by the 14-bit latch circuit 105 is supplied to the 14-bit latch circuit 106. The gate input terminal of the 14-bit latch circuit 106 is connected to the output terminal of the one-shot pulse generation circuit 103, and the 14-bit latch circuit 106 is an image clock signal for one period of the synchronous BD signal (that is, one main scanning period). The integer count value of d is held.

  The output terminal of the oscillator 100 is connected to the input terminal of the D flip-flop 1000, the output terminal of the D flip-flop 1000 is connected to the input terminal of the D flip-flop 1001, and sequentially the D flip-flop 1002 in the same manner. -1015. Further, the output terminals of the PLL circuit 101 are connected to the clock input terminals of the D flip-flops 1000 to 1015, and the D flip-flops 1000 to 1015 are at the falling edge of the 16-fold clock signal e from the PLL circuit 101. The image clock signal d is sequentially output to the D flip-flop at the next stage.

  The output signals of the D flip-flops 1000 to 1015 are supplied to the latch circuits 1100 to 1115, respectively. Since the gate input terminals of the latch circuits 1100 to 1115 are connected to the output terminal of the OR logic circuit 109, the latch circuits 1100 to 1115 perform a latch operation when the synchronous BD signal from the OR logic circuit 109 is Low. Thus, the states of the D flip-flops 1100 to 1115 are held.

  The output terminals of the latch circuits 1100 to 1115 are further connected to the input terminals of the latch circuits 1200 to 1215, and the gate input terminals of the latch circuits 1200 to 1215 are connected to the output terminal of the one-shot pulse generation circuit 103. Accordingly, the latch circuits 1200 to 1215 indicate that the state of the image clock signal d delayed by the clock signal e having a frequency obtained by multiplying the frequency of the image clock signal d by 16 from the one-shot pulse generation circuit 103 to the other synchronous BD (latch). Signal) until it is input.

  Next, the output signals of the latch circuits 1200 to 1215 are input to the arithmetic circuit 107 as 16-bit signals (in0 to in15) via the AND gate circuits 1300 to 1315. The arithmetic circuit 107 converts the 16-bit output signal (a signal corresponding to one pixel) from the AND gate circuits 1300 to 1315 into a 4-bit signal corresponding to 1/16 pixel and outputs it. That is, the arithmetic circuit 107 converts the 1/16 pixel count value (state) latched by the latch circuits 1100 to 1115 into a 4-bit count value and outputs it.

  This 1/16 pixel count operation will be described with reference to FIGS. In FIG. 4, Q0 to Q15 are output signals of the D flip-flops 1000 to 1015. The output signals of the D flip-flops 1000 to 1015 are sequentially latched circuits 1100 to 1115 and a latch circuit 1200 as clock signals obtained by sequentially delaying the image clock signal d by a period that is 1/16 of the period of the image clock signal d. Latched by ~ 1215.

  FIG. 5 shows the above input / output conversion state by the arithmetic circuit 107. In FIG. 5, Q0 to Q15 are output signals of the D flip-flops 1000 to 1015, in0 to in15 are output signals of the AND gate circuits 1300 to 1315, and A0 to A3 are 4 output from the arithmetic circuit 107. This is the bit count value. The arithmetic circuit 107 determines the output values (4-bit count value) of A0 to A3 as shown in FIG. 5 based on the High bits in the input signals of in0 to in15.

  As shown in FIGS. 2 and 3, the output signal of the 14-bit latch circuit 106 is the upper bit of the count value of the main scanning time between the two BD sensors 5 and 6, and the output signal of the arithmetic circuit 107 is the count value. Is stored in the storage device 10.

  In this embodiment, the main scanning time between the two BD sensors 5 and 6 is measured with high resolution with 16 times the resolution of the image clock signal d in this way. Since the clock signal d and the clock signal e having a frequency obtained by multiplying the frequency of the image clock signal d by 16 are both existing clock signals and not newly generated, it can be configured at low cost.

  Further, since the 14-bit counter 104 performs an endless count operation, the count value corresponding to the scanning time when the laser beam a scans between the first BD sensor 5 and the second BD sensor 6, and After the laser beam a passes through the second BD sensor 6, two count values corresponding to the non-scanning time until reaching the first BD sensor 5 are output. Only a count value corresponding to the scanning time is stored by a selection unit (not shown).

  For example, the count value when the laser beam a passes through the first BD sensor 5 is 0 (H), and the count value when the laser beam a passes the second BD sensor 6 next is 2B729 (H ), The count value stored in the storage device 10 is 2B729 (H) when 2B729 (H) -0 (H) = 2B729 (H). Further, when the count value when the laser beam a passes through the first BD sensor 5 is 2B729 (H) and the count value when it passes through the second BD sensor 6 is 16E48 (H), If the former count value is similarly decreased from the latter count value, the result becomes “0” or less. Therefore, by adding 40000 (H) to the latter count value, 40000 (H) + 16E48 (H) −2B729 2B71F (H) is stored in the storage device 10 as (H) = 2B71F (H).

  By repeating the above operation, it is possible to measure the time during which the laser beam a scans between the two BD sensors 5 and 6 with higher resolution than the image clock signal d.

  The measurement circuit is divided into a block (time component) that performs a counting operation with the image clock signal d and a block (time component) that performs a counting operation with a clock signal e having a frequency 16 times that of the image clock signal d. However, the same effect can be obtained even when the laser beam scanning time between the BD sensors 5 and 6 is simply counted only by the clock signal e having a frequency 16 times the image clock signal d.

  However, as in the first embodiment, the block that operates with the image clock signal d and the block that operates with the clock signal e having a frequency 16 times that of the image clock signal d are separated, and the block that is driven at a high frequency is made as small as possible. By doing so, it is possible to prevent erroneous operation of the count operation, increase the reliability, and measure the scanning time between two points with high accuracy.

[Second Embodiment]
FIG. 6 is a diagram showing a schematic configuration of the exposure scanning system of the image forming apparatus according to the second embodiment of the present invention, which is the same as the exposure scanning system according to the first embodiment shown in FIG. Constituent elements and the like are denoted by the same reference numerals and description thereof is omitted.

  The delay clock generation device 20 shown in FIG. 6 generates a clock signal k obtained by delaying the image clock signal d. This clock signal k is a clock signal whose phase is shifted at the same frequency as the image clock signal d.

  FIG. 7 is a circuit diagram of the reference clock generation device 8, the delay clock generation device 20, and the count device 7 shown in FIG. 6, that is, a measurement circuit that measures the laser beam scanning time between two points. In FIG. 7 as well, the same components as those in FIG. 2 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  In FIG. 7, an oscillator 100 is an oscillator that generates an image clock signal d, and corresponds to the reference clock generation device 8 of FIG. Further, the NOT gate 200, the AND gate 203, and the gate circuits 2000 to 2015 constitute a ring oscillation circuit (ring counter) as will be described later, and correspond to the delay clock generation device 20 of FIG. The other part of FIG. 7 corresponds to the counting device 7 of FIG.

  The image clock signal d from the oscillator 100 is supplied to the one-shot pulse generation circuit 103 and also to a PWM circuit, a video data generation circuit, etc. (not shown) in the laser drive control device 11.

  The OR logic circuit 204 has one output signal BD1 (corresponding to the first BD signal b) of the first BD sensor 5 and one output signal BD2 (corresponding to the second BD signal c) of the second BD sensor 6. And output to the multiplexer 202. The reference BD signal generation circuit 201 generates a pseudo BD signal having a predetermined period and outputs the pseudo BD signal to the multiplexer 202 as a reference BD signal. The multiplexer 202 selects and outputs one of the reference BD signal and the BD signal from the OR logic circuit 204. The output signal of the multiplexer 202 is supplied to the AND gate 203 via the NOT gate 200, and is also supplied to the latch circuits 1100 to 1115, the one-shot pulse generation circuit 103, and the 14-bit latch circuit 105.

  The one-shot pulse generation circuit 103 receives the BD signal from the multiplexer 202, generates a one-shot pulse corresponding to one period of the image clock signal d, D flip-flops 1200 to 1215 as latch signals, and a 14-bit latch circuit 106.

  The output terminal of the AND gate 203 is connected to the input terminal of the gate circuit 2000 that is a delay element. The output terminal of the gate circuit 2000 is connected to the input terminal of the gate circuit 2001, and is sequentially connected to the gate circuits 2002 to 2015 in the same manner. The output terminal of the gate circuit 2015 is connected to the input terminal of the AND gate 203. In this configuration, the NOT gate 200, the AND gate 203, and the gate circuits 2000 to 2015 form a ring oscillation circuit, and perform an oscillation operation when the output of the multiplexer 202 is High.

  The output terminal of the AND gate 203 is also connected to the clock input terminal of the 14-bit counter 104. The output signals of the gate circuits 2000 to 2015 are input to the latch circuits 1100 to 1115, respectively. Others are the same as FIG.

  Under such a configuration, when the multiplexer 202 selects the BD signal (A input) and the BD signal is High, the ring oscillation circuit performs an oscillation operation, and the oscillation output signal (AND gate) The 14-bit counter 104 counts the output signal 203 (count clock signal) 203. The output signal (count clock signal) of the AND gate 203 is a signal corresponding to the clock signal k described above and is a delayed version of the image clock signal d, but its frequency is different from that of the image clock signal d. It will be.

  That is, one cycle of the signal output from the ring oscillation circuit is (the sum of the output delay times of the elements of the AND gate 203 and the gate circuits 2000 to 2015 + the total delay time until the signal is input from the previous stage to the subsequent stage. ) × 2, that is, a time corresponding to two cycles of the ring oscillation circuit. More specifically, when the output from the multiplexer 202 is Low, the AND gate 203 always outputs Low. Here, when the output of the multiplexer 202 becomes High, the output of the AND gate 203 also becomes High, and in order of the gate circuits 2000 → 2001 → 2002 →. When the output of the gate circuit 2015 becomes High, the output of the AND gate 203 becomes Low, and in turn, the Gate circuits 2000 → 2001 →. By repeating such signal changes, the output (count clock signal) from the AND gate 203 becomes a clock signal having one cycle corresponding to two cycles of the ring oscillation circuit.

  Further, as described above, since the total delay time of the gate elements becomes the frequency of the count clock signal, the frequency of the count clock signal changes depending on the variation and temperature of the gate elements. Therefore, a reference BD signal generation circuit 201 is provided to cope with this frequency change. That is, the reference BD signal generation circuit 201 always outputs a reference BD signal having the same cycle. By comparing the value obtained by counting the reference BD signal with the ring oscillation circuit and the value obtained by counting the BD signal from the OR logic circuit 204 with the ring oscillation circuit, the absolute time of the scanning time which is not influenced by the environmental change or the like is obtained. Can do.

  Note that the count of the reference BD signal from the reference BD signal generation circuit 201 and the count of the BD signal from the OR logic circuit 204 are counted at intervals such that changes in the delay time of the ring oscillation circuit due to factors such as temperature can be almost ignored. There is a need to.

  Further, as described above, since the output (count clock signal) from the AND gate 203 is a clock signal having one cycle corresponding to two cycles of the ring oscillation circuit, the output signals of the gate circuits 2000 to 2015 are as shown in FIG. The clock cycle of Q0 to Q15 shown in (2) is doubled.

  When the next BD signal is input from the multiplexer 202, the 14-bit latch circuit 105 and the latch circuits 1100 to 1115 perform a latch operation, and hold the count value of the 14-bit counter and the output signals of the gate circuits 2000 to 2015, respectively.

  The count value and the output signal held in the 14-bit latch circuit 105 and the latch circuits 1100 to 1115 are respectively latched in the 14-bit latch circuit 106 and the latch circuits 1200 to 1215 in the next stage by the latch signal from the one-shot pulse generation circuit 103. , One period of the BD signal is held. A timing chart of the above operation is shown in FIG.

  Since the delay time of the gate circuits 2000 to 2015 is shorter than the cycle of the clock signal e in the first embodiment, in the second embodiment, the distance between the two BD sensors 5 and 6 is larger than that in the first embodiment. Can be measured with high accuracy.

  Further, the delay time of the gate circuits 2000 to 2015 is not determined to be a constant value due to environmental changes or product variations, but the reference BD signal generated by the reference BD generation circuit 201 is used before or after the scan time measurement. By measuring the scanning time between the above two points and correcting the scanning time measured using the BD signals from the first and second BD sensors 5 and 6 based on this scanning time, the environmental change, etc. The absolute time can be measured regardless of the time.

  The present invention is not limited to the above embodiment, and can be applied to a case where the scanning speed is made constant by controlling the rotational speed of the polygon mirror without using, for example, an fθ lens. It is.

1 is a diagram showing a schematic configuration of an exposure scanning system of an image forming apparatus according to a first embodiment of the present invention. It is a figure which shows the measurement circuit which measures the laser beam scanning time between two points (1st Embodiment). 3 is a timing chart showing a count operation of a clock signal (first embodiment). 6 is a timing chart showing a count operation of 1/16 pixel (first embodiment). It is a figure for demonstrating the input-output conversion by an arithmetic circuit (1st Embodiment). It is a figure which shows schematic structure of the exposure scanning system of the image forming apparatus which concerns on the 2nd Embodiment of this invention. It is a figure which shows the measurement circuit which measures the laser beam scanning time between two points (2nd Embodiment). 6 is a timing chart illustrating a clock signal counting operation (second embodiment);

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor laser, 2 ... Polygon mirror, 4 ... Photosensitive drum, 5 ... 1st BD sensor, 6 ... 2nd BD sensor, 7 ... Count apparatus, 8 ... Reference clock generator, 9 ... Multiplication clock generator, DESCRIPTION OF SYMBOLS 11 ... Laser drive control apparatus, 20 ... Delay clock generation apparatus

Claims (14)

An image forming apparatus that forms an electrostatic latent image on a photoconductor by irradiating the photoconductor with a light beam modulated based on image data while polarizing the light beam in the main scanning direction.
First generating means for generating a reference clock signal;
Second generating means for generating a sub clock signal having a frequency higher than that of the reference clock signal based on the reference clock signal;
Measuring means for measuring a scanning time between two points on the main scanning line of the light beam by using the reference clock signal and the sub clock signal;
The image forming apparatus, wherein the measuring unit measures a component of a scanning time shorter than one cycle of the reference clock signal by using the sub clock signal. First detection means for detecting the light beam traveling at a predetermined position on the main scanning line, and second detecting means for detecting the light beam traveling at a position downstream of the predetermined position on the main scanning line. Detecting means,
The measuring unit measures a scanning time from when the light beam is detected by the first detecting unit to when it is detected by the second detecting unit, using the reference clock signal and the sub clock signal. The image forming apparatus according to claim 1.   The image forming apparatus according to claim 1, wherein the second generation unit generates the sub clock signal by multiplying a frequency of the reference clock signal.   The image forming apparatus according to claim 3, wherein the sub clock signal is a clock signal used for modulation of the light beam.   The image forming apparatus according to claim 1, wherein the second generation unit generates the sub clock signal by delaying the reference clock signal.   The image forming apparatus according to claim 5, wherein the second generation unit generates the sub clock signal by delaying the reference clock signal using a ring counter.   The image forming apparatus according to claim 1, further comprising a correcting unit that corrects a main scanning magnification using a scanning time measured by the measuring unit. An image forming method for forming an electrostatic latent image on a photoconductor by irradiating the photoconductor with a light beam modulated based on image data being polarized in the main scanning direction,
A first generating step for generating a reference clock signal;
A second generation step of generating a sub clock signal having a frequency higher than that of the reference clock signal based on the reference clock signal;
Measuring a scanning time between two points on the main scanning line of the light beam using the reference clock signal and the sub clock signal,
The image forming method according to claim 1, wherein the measuring step measures a component of a scanning time shorter than one cycle of the reference clock signal by using the sub clock signal. A first detecting step for detecting the light beam traveling at a predetermined position on the main scanning line; and a second detecting step for detecting the light beam traveling at a position downstream of the predetermined position on the main scanning line. And a detection process of
The measuring step measures a scanning time from when the light beam is detected by the first detecting step to when it is detected by the second detecting step, using the reference clock signal and the sub clock signal. The image forming method according to claim 8.   The image forming method according to claim 8, wherein the second generation step generates the sub clock signal by multiplying a frequency of the reference clock signal.   The image forming method according to claim 10, wherein the sub clock signal is a clock signal used for modulation of the light beam.   The image forming method according to claim 8, wherein the second generation step generates the sub clock signal by delaying the reference clock signal.   13. The image forming method according to claim 12, wherein in the second generation step, the sub clock signal is generated by delaying the reference clock signal using a ring counter.   9. The image forming method according to claim 8, further comprising a correcting step of correcting the main scanning magnification using the scanning time measured in the measuring step.

Images