JP2015104006A - Negative resistance generation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a negative resistance generation circuit capable of preventing undesired oscillation.SOLUTION: The negative resistance generation circuit includes: a source-grounded FET 1, which has a circuit including an inductor component in a transmission line 2, a capacitor 3 and a thin film resistor 4 and is connected between a gate terminal and a drain terminal thereacross, is applied with a bias voltage to the gate terminal and the drain terminal; a parallel resonance circuit (a circuit including the inductor component and capacitor 6 in the transmission line 5) which is connected to the drain terminal of the FET 1 being branched therefrom; and a thin film resistor 7 connected to the parallel resonance circuit in parallel.

Description

  The present invention relates to a negative resistance generation circuit in which negative conductance is substantially constant.

FIG. 9 is a configuration diagram showing a negative resistance generation circuit disclosed in Non-Patent Document 1 below.
This negative resistance generation circuit is configured using an active element such as a transistor, and an inductor or a capacitor is used as a parallel feedback circuit.
Since the real part component of the impedance Zin expected from the input terminal takes a negative value, FIG. 9 functions as a negative resistance generation circuit.
However, depending on the load connected to the outside, an active element such as a transistor may cause unnecessary oscillation. In order to suppress the unnecessary oscillation, it is desirable to cancel the negative resistance of the negative resistance generation circuit and the positive resistance component of the load connected to the outside.

U. Karacaoglu et al. , MMIC Active Bandpass Filters Using Variable-Tuned Negative Resistance Elements, "IEEE Trans. On Microwave Theory and Technologies No. 19, Vol.

Since the conventional negative resistance generation circuit is configured as described above, in order to cancel the negative resistance of the negative resistance generation circuit and the positive resistance component of the load connected to the outside, It is preferable that the frequency dependence of the negative resistance exhibited by the resistance generation circuit is small. However, since the negative resistance component of the negative resistance generation circuit has frequency dependence, there is a problem that unnecessary oscillation is likely to occur.
Moreover, since the inductor or the capacitor used in the parallel feedback circuit includes a parasitic resistance component, there is a problem that the passage loss increases.

  The present invention has been made to solve the above-described problems, and an object thereof is to obtain a negative resistance generating circuit capable of suppressing unnecessary oscillation.

  A negative resistance generation circuit according to the present invention includes a common-source FET in which a circuit including an inductor, a capacitor, and a first resistance element is connected between a gate terminal and a drain terminal, and a bias voltage is applied to the gate terminal and the drain terminal. A parallel resonant circuit connected in shunt to the drain terminal of the common-source FET, and a second resistance element connected in series with the parallel resonant circuit are provided.

  According to the present invention, a circuit including an inductor, a capacitor, and a first resistance element is connected between a gate terminal and a drain terminal, and a source grounded FET in which a bias voltage is applied to the gate terminal and the drain terminal. Since the parallel resonance circuit connected in shunt with respect to the drain terminal and the second resistance element connected in series with the parallel resonance circuit are provided, there is an effect that unnecessary oscillation can be suppressed.

It is a block diagram which shows the negative resistance production | generation circuit by Embodiment 1 of this invention. 2 is a high-frequency equivalent circuit of the negative resistance generation circuit of FIG. 1. 3 is a simplified equivalent circuit of FET 1 of the negative resistance generation circuit according to the first embodiment of the present invention. It is a graph which shows the specific calculation example of the input admittance Yin in the high frequency equivalent circuit of FIG. It is a block diagram which shows the negative resistance production | generation circuit by Embodiment 2 of this invention. This is an equivalent circuit of the patch antenna 23 connected to the drain terminal of the FET 1. (A) An example of the equivalent circuit of the impedance matching circuit for transforming the impedance of the patch antenna 23 to the signal source impedance of 50 [Ω] is shown, and (b) is an explanatory diagram showing pass characteristics and reflection characteristics. (A) The equivalent circuit of the negative resistance generation circuit of FIG. 5 is shown, (b) It is explanatory drawing which shows the passage characteristic and reflection characteristic of the negative resistance generation circuit of FIG. It is a block diagram which shows the negative resistance production | generation circuit currently disclosed by the nonpatent literature 1.

Embodiment 1 FIG.
1 is a block diagram showing a negative resistance generating circuit according to Embodiment 1 of the present invention.
In FIG. 1, FET 1 is a grounded-source FET configured on a semiconductor substrate 10, and an appropriate bias voltage is applied to the gate terminal and drain terminal of FET 1.
The transmission line 2 has one end connected to the gate terminal of the FET 1 and the other end connected to the drain terminal of the FET 1, and the transmission line 2 functions as an inductor.
The capacitor 3 is a DC blocking capacitor inserted in the middle of the transmission line 2.
The thin film resistor 4 is a first resistance element inserted in the transmission line 2.

One end of the transmission line 5 is connected to the drain terminal of the FET 1, and the transmission line 5 functions as an inductor.
One end of the capacitor 6 is connected to the drain terminal of the FET 1, and a parallel resonance circuit is constituted by the inductor component in the transmission line 5 and the capacitor 6.
The thin film resistor 7 is a second resistance element inserted in the middle of the transmission line 5.
The capacitor 8 is a DC blocking capacitor having one end connected to the other end of the transmission line 2 and the other end connected to the via hole 9.

The FET 1, the transmission line 2, the capacitor 3, the thin film resistor 4, the transmission line 5, the capacitor 6, the thin film resistor 7, the capacitor 8, and the via hole 9 are all formed on the semiconductor substrate 10, so-called MMIC (Monolithic). Microwave Integrated Circuit).
The capacitors 3, 6, and 8 are all configured as MIM (Metal-Insulator-Metal) capacitors.

Next, the operation will be described.
In the negative resistance generation circuit of FIG. 1, when a high frequency is input, the impedance of the DC blocking capacitors 3 and 8 is sufficiently small in frequency and can be ignored.
Therefore, the high-frequency equivalent circuit of the negative resistance generation circuit of FIG. 1 can be expressed as shown in FIG.
In FIG. 2, R is a resistance component of the thin film resistor 4, L is an inductor component of the transmission line 2, Lb is an inductor component of the transmission line 5, Cb is a capacitance component of the capacitor 6, and Rb is a resistance component of the thin film resistor 7.

FIG. 3 is a simplified equivalent circuit of the FET 1 of the negative resistance generation circuit according to the first embodiment of the present invention.
2 and 3, when the input admittance of the portion excluding the circuit composed of (Lb, Cb, Rb) in the high frequency equivalent circuit of FIG. 2 is Y1, the input admittance Y1 is expressed by the following equation (1). It can be expressed as
Y1≈ [(R−gmL / Cgs) −j (ωL + gmR / (ωCgs))
/ [R2 + (ωL) 2]
(1)
In equation (1), ω is the operating angular frequency.
In formula (1), in order to simplify the formula, it is assumed that 1 / (ωCgs) is sufficiently smaller than | R + jωL |, and Cgd = 0, Cds = 0, and Rds = ∞.

From the equation (1), if the following equation (2) is satisfied, Re [Y1] which is the real part of the input admittance Y1 becomes Re [Y1] <0, and Y1 which is the output admittance of the FET1 is negative It can be seen that conductance (negative resistance) can be generated.
R <gmL / Cgs (2)
Further, it can be seen from Equation (1) that the real part Re [Y1] of Y1 increases from a negative value toward 0 as the operating angular frequency ω increases.

On the other hand, the admittance Yb of the circuit composed of (Lb, Cb, Rb) in the high-frequency equivalent circuit of FIG. 2 can be expressed as the following equation (3).
Yb≈1 / [Rb + 1 / {j2Cb (ω−ωb)}]
= [4Cb2Rb (ω−ωb) 2 + j2Cb (ω−ωb)]
/ [1 + 4 (CbRb) 2ω−ωb) 2]
(3)
In Expression (3), ωb is the resonance angular frequency of the parallel resonance circuit composed of (Lb, Cb), and ωb2 = 1 / (LbCb) is established.

Here, by making the resonance angular frequency ωb of the parallel resonant circuit composed of (Lb, Cb) larger than the operating angular frequency ω of the negative resistance generation circuit, the admittance Yb of the circuit composed of (Lb, Cb, Rb) is actualized. The portion Re [Yb] decreases as the operating angular frequency ω increases.
Therefore, since the input admittance Yin of the entire circuit of FIG. 2 is expressed by the following equation (4), the real part Re [Yb] of the admittance Yb is constant regardless of the operating angular frequency ω.
Yin = Y1 + Yb (4)
Therefore, the negative resistance generation circuit of FIG. 1 is a circuit whose negative conductance is substantially constant.

FIG. 4 is a graph showing a specific calculation example of the input admittance Yin in the high-frequency equivalent circuit of FIG.
By giving the circuit element value to each circuit element of the high-frequency equivalent circuit of FIG. 2 as shown in FIG. 4, the real part Re [Yin] of the input admittance Yin is substantially −0.02 regardless of the frequency. It can be seen that [S] is constant.

  As apparent from the above, according to the first embodiment, a circuit including the inductor component, the capacitor 3 and the thin film resistor 4 in the transmission line 2 is connected between the gate terminal and the drain terminal, and the bias voltage is applied to the gate terminal and the drain. The source-grounded FET 1 applied to the terminal, a parallel resonant circuit (circuit composed of the inductor component in the transmission line 5 and the capacitor 6) connected in shunt to the drain terminal of the FET 1, and the parallel resonant circuit connected in series Since the thin film resistor 7 is provided, it is possible to suppress unnecessary oscillation.

  That is, according to the first embodiment, a negative resistance generation circuit having a small frequency dependence of negative conductance (negative resistance) can be configured, and a passive connected to the outside of the negative resistance generation circuit. Since the conductance component having a positive value and generally having a low frequency dependency can be canceled over a wider band, unnecessary oscillation caused by the remaining unnecessary negative conductance component can be more easily suppressed.

In the first embodiment, the source grounded FET 1 is configured on the semiconductor substrate 10. However, instead of the source grounded FET 1, a grounded emitter bipolar transistor is configured on the semiconductor substrate 10. May be.
In this case, one end of the transmission line 2 is connected to the base terminal of the grounded emitter bipolar transistor, and the other end of the transmission line 2 is connected to the collector terminal of the grounded emitter bipolar transistor.
An appropriate bias voltage is applied to the base terminal and the collector terminal of the common emitter bipolar transistor.

Embodiment 2. FIG.
FIG. 5 is a block diagram showing a negative resistance generation circuit according to Embodiment 2 of the present invention. In FIG. 5, the same reference numerals as those in FIG.
The capacitor 21 is a second capacitor having one end connected to the drain terminal of the FET 1 and the other end connected to the via hole 22. The capacitor 21 is configured as an MIM capacitor.
The patch antenna 23 is connected to the drain terminal of the FET 1 and is configured by a rectangular conductor pattern.
One end of the transmission line 24 is connected to the gate terminal of the FET 1, and the transmission line 24 functions as a quarter wavelength impedance transformer.

Next, the operation will be described.
In the second embodiment, a capacitor 21 is further connected to a shunt with respect to the drain terminal of the FET 1 in the negative resistance circuit of FIG.
The portion excluding the capacitor 21 functions as a negative resistance generation circuit according to the operation principle described in the first embodiment.

In the case of the high frequency equivalent circuit (FIG. 2) of the negative resistance generation circuit in the first embodiment, for example, at a center frequency of 10 [GHz], as shown in FIG. 4, the imaginary part (susceptance component) of the input admittance Yin Im [Yin] becomes Im [Yin] <0 and exhibits inductive susceptance.
Therefore, as shown in FIG. 5, the negative resistance generation circuit of FIG. 5, except for the patch antenna 23, connects the appropriate capacitor 21 to the shunt with respect to the drain terminal of the FET 1. ], The imaginary part Im [Yin] of the input admittance Yin can be set to 0, and this negative resistance generation circuit exhibits characteristics as a parallel resonance circuit.

FIG. 6 is an equivalent circuit of the patch antenna 23 connected to the drain terminal of the FET 1.
As shown in FIG. 6, the patch antenna 23 is expressed by a series resonance circuit composed of (Rp, Lp, Cp). Here, it is assumed that the resonance frequency of the series resonance circuit is 10 [GHz].
FIG. 7A shows an example of an equivalent circuit of an impedance matching circuit for transforming the impedance of the patch antenna 23 to the signal source impedance 50 [Ω], and FIG. 7B shows pass characteristics and reflection characteristics. .

In FIG. 7A, an impedance matching circuit including a parallel resonance circuit (Lm, Cm) and a quarter wavelength impedance line Zm is used as an impedance matching circuit for the patch antenna 23 exhibiting series resonance characteristics.
Considering the parasitic resistance Rm inevitably generated when realizing the parallel resonant circuit (Lm, Cm), here, as an example, Rm = 50 [Ω].
At this time, as shown in FIG. 7B, it can be seen that a passage loss is caused by the parasitic resistance Rm.

8A shows an equivalent circuit of the negative resistance generation circuit of FIG. 5, and FIG. 8B shows pass characteristics and reflection characteristics of the negative resistance generation circuit of FIG.
FIG. 8A is a diagram in which a parallel resonance circuit (Lm, Cm) included in the impedance matching circuit of FIG. 7A is replaced with a circuit composed of a negative resistance generation circuit and a capacitor, and a newly added capacitor 21 is accompanied by the same parasitic resistance Rm as in FIG.
From FIG. 8B, the reflection characteristic in the equivalent circuit of FIG. 8A is almost the same as the reflection characteristic shown in FIG. 7B, but the pass characteristic in the equivalent circuit of FIG. It can be seen that the loss is lower than the pass characteristic shown in FIG.
This is because the impedance matching circuit shown in FIG. 7 (a) assumes that the parallel resonant circuit (Lm, Cm) is composed of passive circuit elements and assumes the parasitic resistance Rm, so that the passage loss In contrast, in the circuit of FIG. 8A, the same parasitic resistance Rm is canceled out by the negative resistance generation circuit, which indicates that the passage loss is reduced.

According to the second embodiment, the negative resistance generation circuit having a small frequency dependence of the negative conductance (negative resistance) shown in the first embodiment is used as a component of the impedance matching circuit, thereby forming a passive circuit. Compared with a conventional impedance matching circuit composed only of elements, it is possible to reduce the loss.
In the second embodiment, the impedance matching circuit is shown as an example. However, it is possible to reduce the parasitic resistance component of various passive circuits such as a filter and to reduce the loss by a similar method.

In the second embodiment, the capacitor 21 is connected to the shunt with respect to the drain terminal of the FET 1 in the negative resistance circuit of FIG. 1, but the transmission line 2 is connected to the drain terminal of the FET 1. A second inductor different from the inductance component may be connected to the shunt, and the same effect can be obtained.
In addition, a second parallel resonant circuit different from the parallel resonant circuit composed of the inductor component and the capacitor 6 in the transmission line 5 may be connected to the shunt with respect to the drain terminal of the FET 1. There is an effect.

In the second embodiment, the patch antenna 23 is represented by a series resonant circuit composed of (Rp, Lp, Cp). However, the inductor component in the transmission line 2 and the drain terminal of the FET 1 Another second inductor may be connected in series, and the same effect can be obtained.
Further, a second capacitor different from the capacitor 3 may be connected in series to the drain terminal of the FET 1, and the same effect can be obtained.

In the second embodiment, the source grounded FET 1 is configured on the semiconductor substrate 10. However, the emitter grounded bipolar transistor is configured on the semiconductor substrate 10 instead of the source grounded FET 1. May be.
In this case, one end of the transmission line 2 is connected to the base terminal of the grounded emitter bipolar transistor, and the other end of the transmission line 2 is connected to the collector terminal of the grounded emitter bipolar transistor.

  In the present invention, within the scope of the invention, any combination of the embodiments, or any modification of any component in each embodiment, or omission of any component in each embodiment is possible. .

  1 FET (grounded source FET), 2 transmission line (inductor), 3 capacitor, 4 thin film resistor (first resistance element), 5 transmission line (parallel resonance circuit), 6 capacitor (parallel resonance circuit), 7 thin film resistance ( 2nd resistive element), 8 capacitors, 9 via holes, 10 semiconductor substrate, 21 capacitors (second capacitors), 22 via holes, 23 patch antennas, 24 transmission lines.

Claims (6)

A circuit comprising an inductor, a capacitor, and a first resistance element is connected between the gate terminal and the drain terminal, and a source grounded FET in which a bias voltage is applied to the gate terminal and the drain terminal;
A parallel resonant circuit connected in shunt to the drain terminal of the common source FET;
And a second resistance element connected in series with the parallel resonant circuit.   The negative resistance generation circuit according to claim 1, wherein a second capacitor, a second inductor, or a second parallel resonant circuit is connected to the shunt with respect to a drain terminal of the common source FET.   2. The negative resistance generation circuit according to claim 1, wherein a second capacitor, a second inductor, or a series resonance circuit is connected in series to the drain terminal of the common source FET. A circuit composed of an inductor, a capacitor, and a first resistance element is connected between a base terminal and a collector terminal, and a grounded-emitter bipolar transistor in which a bias voltage is applied to the base terminal and the collector terminal;
A parallel resonant circuit connected in shunt to the collector terminal of the common emitter bipolar transistor;
And a second resistance element connected in series with the parallel resonant circuit.   5. The negative resistance generation circuit according to claim 4, wherein a second capacitor, a second inductor, or a second parallel resonant circuit is connected to the shunt with respect to the collector terminal of the common emitter bipolar transistor. .   The negative resistance generation circuit according to claim 4, wherein a second capacitor, a second inductor, or a series resonance circuit is connected in series to the collector terminal of the common emitter bipolar transistor.

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