JP2015088704A - Device and method for inspecting semiconductor wafer circumference part - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an inspection device capable of inspecting the circumference part of a semiconductor wafer in a short time.SOLUTION: The semiconductor wafer inspection device includes: a camera 13 for imaging the circumference part of each SOI wafer within 10 mm from an outer edge, among a plurality of SOI wafers 1 laminated mutually separately; and a movement mechanism 14 for moving at least one of the plurality of SOI wafers 1 and the camera 13 in a manner to cause the camera 1 to relatively move to the plurality of SOI wafers 1 along the lamination direction of the plurality of SOI wafers 1.

Description

  The present invention relates to an apparatus and method for inspecting an outer peripheral portion (edge) of a semiconductor wafer.

  The outer peripheral portion of a semiconductor wafer, for example, a silicon wafer is different in quality state and quality specification compared to the inner region. For this reason, the outer peripheral portion may be inspected differently from the inner region. Conventionally, various techniques for inspecting the outer peripheral portion of a silicon wafer have been proposed.

  Patent Document 1 and Patent Document 2 disclose an apparatus for inspecting an outer peripheral edge portion including a bevel surface inclined with respect to a main surface by an optical method in a plate-like member such as a wafer. In these apparatuses, a part of the outer peripheral edge portion of the wafer set on the turntable is imaged. By rotating the wafer with the turntable, the outer peripheral edge portion can be imaged over the entire circumference of the wafer. Thereby, it is supposed that it is possible to inspect whether there are scratches, protrusions, cracks, particles or the like on the outer peripheral edge of the wafer.

Even in an SOI wafer having an SOI structure in which a silicon layer (SOI (Silicon on Insulator) layer) is formed on an insulator, the outer peripheral portion is inspected.
1A to 1F are cross-sectional views for explaining a method of manufacturing an SOI wafer. FIG. 2 is a plan view showing the structure of the SOI wafer.

  The SOI wafer 1 is manufactured as follows. First, an active layer wafer 3 is bonded onto a support wafer 2 on which an oxide film (thermal oxide film (box layer)) 2a is formed in advance (see FIG. 1A). For example, the support wafer 2 and the active layer wafer 3 may have notches N formed in the peripheral edge thereof, and may be formed with an orientation flat (hereinafter referred to as “orientation flat”) O. (See FIG. 2). Further, after aligning and bonding the support wafer 2 and the active layer wafer 3 with the notch N formed in the peripheral portion, chamfering may be performed so that the orientation flat O is formed in the peripheral portion of the support wafer 2. Good.

  Next, the bonded support wafer 2 and active layer wafer 3 are heat-treated to strengthen the bonding between the support wafer 2 and the active layer wafer 3. As a result, an oxide film (thermal oxide film) 3a is also formed on the surface of the active layer wafer 3 (see FIG. 1B). In this state, an unbonded region exists in the outer peripheral portion of the facing portion between the support wafer 2 and the active layer wafer 3.

  Next, in order to remove the unbonded region, first, the peripheral portion of the active layer wafer 3 is ground and thinned (see FIG. 1C). As a result, the oxide film 3a is removed at the peripheral edge of the active layer wafer 3, and silicon is exposed. Subsequently, silicon exposed at the peripheral edge of the active layer wafer 3 is removed by selective etching. Further, the remaining part of the oxide film 3a at the periphery of the active layer wafer 3 is removed by a physical method (see FIG. 1D).

  Thereafter, the active layer wafer 3 is thinned by surface grinding (see FIG. 1E), and thereby the oxide film 3a in the inner region of the surface of the active layer wafer 3 is removed. Subsequently, the active layer wafer 3 is further thinned by polishing, and the surface of the active layer wafer 3 is smoothed (see FIG. 1F), whereby the SOI wafer 1 is obtained. In the SOI wafer 1 obtained in this way, silicon is exposed on the surface of the active layer wafer 3, and the active layer wafer 3 is not present on the outer periphery of the support wafer 2. There is a terrace 4 (see FIG. 2).

  The oxide film 2 a needs to remain on the terrace 4 of the SOI wafer 1. This is because if there is a region where the oxide film 2a does not exist on the terrace 4, that region can become a dust generation source in the device formation process.

  3 and 4 are photographs of the outer peripheral portion of the SOI wafer 1. FIG. 2 shows the field of view V of the photographs of FIGS. In the field of view of these photographs, the region of the active layer wafer 3 (the region indicated by the symbol “A” in FIGS. 3 and 4) and the region of the terrace 4 (the symbol “B” in FIGS. 3 and 4) And a part of the notch N formed in the outer peripheral portion of the terrace 4 is included.

  In the SOI wafer 1 shown in FIG. 3, an oxide film remains in the entire area of the terrace 4. As a result, in the photograph of FIG. 3, the area of the terrace 4 has almost the same brightness, and the active layer wafer 3. The brightness is lower (darker color) than the area of. On the other hand, in the SOI wafer 1 shown in FIG. 4, an oxide film remains on the terrace 4 except for the outer edge portion (the region indicated by the symbol “C” in FIG. 4). It is not present and silicon is exposed. Thereby, in the photograph of FIG. 4, the outer edge portion has higher brightness (closer to white) than the other portions, and has the same brightness as the region of the active layer wafer 3.

  As described above, depending on the manufacturing conditions of the SOI wafer 1, there may be obtained a structure in which an oxide film does not exist on a part of the terrace 4 as shown in FIG. For this reason, it is necessary to confirm the presence of the oxide film 2a of the terrace 4 in the manufactured SOI wafer 1.

International Publication No. 2008/1223459 International Publication No. 2008/136432

  However, when the presence of the oxide film on the terrace 4 is confirmed over the entire circumference of the SOI wafer 1, a long time is required. The present invention has been made in view of such a situation, and an object thereof is to provide an inspection apparatus and an inspection method capable of inspecting an outer peripheral portion of a semiconductor wafer in a short time.

  In the SOI wafer 1 in which the oxide film does not exist on a part of the terrace 4 as shown in FIG. 4, the present inventors have an oxide film at substantially the same radial position over the entire circumference of the SOI wafer 1. I found out that I would not. This suggests that when the wafer is processed while rotating around its central axis, the oxide film is removed, so that an SOI wafer 1 in which no oxide film exists in a part of the terrace 4 is obtained. . For example, when the active layer wafer 3 is polished (see FIG. 1F), the oxide film 2a is considered to be removed by polishing the outer peripheral portion of the terrace 4 as well.

  In the terrace 4, when it is confirmed that an oxide film is not present in a part of the SOI wafer 1 in the circumferential direction of the SOI wafer 1, the SOI wafer 1 extends over the entire circumference. Thus, there is a high probability that no oxide film exists on the terrace 4 at the radial position. In addition, when it is confirmed that an oxide film is present in the entire area in the radial direction of the SOI wafer 1 in a partial region in the circumferential direction of the SOI wafer 1 in the terrace 4, the entire area of the terrace 4 is in the SOI wafer 1. There is a high probability that an oxide film exists on the surface. Therefore, the presence or absence of the oxide film on the terrace 4 may be confirmed in a part of the circumferential direction of the SOI wafer 1, and is not necessarily performed over the entire circumference of the SOI wafer 1.

The present invention has been completed by obtaining such knowledge, and the gist thereof is a semiconductor wafer inspection apparatus (1) below and a semiconductor wafer inspection method (2) below.
(1) For a plurality of semiconductor wafers stacked apart from each other, for each semiconductor wafer, a camera for photographing an outer peripheral portion within 10 mm from the outer edge;
A moving mechanism for moving at least one of the plurality of semiconductor wafers and the camera so that the camera moves relative to the plurality of semiconductor wafers along a stacking direction of the plurality of semiconductor wafers; An inspection apparatus for semiconductor wafers.

(2) a step of laminating a plurality of semiconductor wafers apart from each other;
Moving at least one of the plurality of semiconductor wafers and the camera so as to move the camera relative to the plurality of semiconductor wafers along a stacking direction of the plurality of semiconductor wafers;
With each camera, for each semiconductor wafer, photographing the outer peripheral portion within 10 mm from the outer edge;
And a step of determining the quality of each semiconductor wafer based on an image obtained by photographing with the camera.

  In the present invention, the “outer peripheral portion” includes not only a portion inclined with respect to the main surface of the semiconductor wafer at the end surface of the semiconductor wafer but also a peripheral portion of the main surface.

The inspection apparatus of the present invention is suitable for carrying out the inspection method of the present invention, and can exhibit the following effects by the inspection method of the present invention.
According to the inspection method of the present invention, it is not necessary to rotate the semiconductor wafer, and the outer peripheral portion of each semiconductor wafer can be inspected only for a part in the circumferential direction. Further, since it is not necessary to rotate the semiconductor wafer, the semiconductor wafer does not need to be set on the turntable. Since the outer peripheral portion of the semiconductor wafer only needs to be inspected for a part in the circumferential direction, if the inspection target portion is exposed in the semiconductor wafer, for example, the semiconductor wafer can be inspected while being accommodated in a cassette. It is. For this reason, a semiconductor wafer can be inspected in a short time.

It is sectional drawing for demonstrating the method to manufacture an SOI wafer, and shows the process of bonding a support wafer and the wafer for active layers. It is sectional drawing for demonstrating the method to manufacture an SOI wafer, and shows the process of heat-processing the bonded support wafer and the wafer for active layers. It is sectional drawing for demonstrating the method to manufacture an SOI wafer, and shows the process of grinding the peripheral part of the wafer for active layers. It is sectional drawing for demonstrating the method to manufacture an SOI wafer, and shows the process of etching the peripheral part of the wafer for active layers. It is sectional drawing for demonstrating the method to manufacture an SOI wafer, and shows the process of surface-grinding the wafer for active layers. It is sectional drawing for demonstrating the method to manufacture an SOI wafer, and shows the process of grind | polishing the wafer for active layers. It is a top view which shows the structure of an SOI wafer. It is the photograph of the outer peripheral part of the SOI wafer in which an oxide film exists in the whole area on a terrace. It is the photograph of the outer peripheral part of the SOI wafer in which an oxide film does not exist in a part of terrace. It is a front view which shows the structure of the inspection apparatus of the outer peripheral part of a silicon wafer based on one Embodiment of this invention. It is a top view which shows a part of test | inspection apparatus shown in FIG. It is sectional drawing which shows the structure inside a cassette. It is a side view which shows the upper end vicinity of several SOI wafers, and a camera. It is a front view which shows the structure of the notch alignment mechanism with which the inspection apparatus of the outer peripheral part of the silicon wafer was equipped.

1. As described above, the inspection apparatus of the present invention is, as described above, for a plurality of semiconductor wafers stacked apart from each other, for each semiconductor wafer, a camera for photographing an outer peripheral portion within 10 mm from the outer edge; A moving mechanism for moving at least one of the plurality of semiconductor wafers and the camera so that the camera moves relative to the plurality of semiconductor wafers along a stacking direction of the plurality of semiconductor wafers; It is a semiconductor wafer inspection apparatus characterized by the above.

FIG. 5 is a front view showing a configuration of an inspection apparatus for an outer peripheral portion of a semiconductor wafer according to an embodiment of the present invention. FIG. 6 is a plan view showing a part of the inspection apparatus shown in FIG.
The inspection apparatus 11 includes a cassette (basket) 12 that accommodates a plurality of SOI wafers 1 and a camera 13 that photographs each outer peripheral portion (region within 10 mm from the outer edge) of the plurality of SOI wafers 1 accommodated in the cassette 12. And a moving mechanism 14 for moving the camera 13 above the SOI wafer 1.

  The cassette 12 is for temporarily storing a silicon wafer in a manufacturing process of a silicon wafer or a semiconductor device, and is placed on a stage 19 in the inspection apparatus 11. FIG. 7 is a cross-sectional view showing the internal structure of the cassette 12. Inside the cassette 12, a plurality of partition plates 12s having the same thickness and arranged at equal intervals are provided. The plurality of partition plates 12s are arranged in the thickness direction of each partition plate 12s. The interval between the two adjacent partition plates 12 s is longer than the thickness of the SOI wafer 1. Each SOI wafer 1 is accommodated between two adjacent partition plates 12s in a state where its main surface is oriented substantially along the vertical direction (direction along the direction of gravity).

  Each SOI wafer 1 is inclined in the same direction with respect to the arrangement direction of the partition plates 12s. More specifically, all the SOI wafers 1 are in contact with the vicinity of the lower end of the partition plate 12s on one side with respect to the arrangement direction of the partition plates 12s and the bottom surface of the cassette 12, and on the other side with respect to the arrangement direction of the partition plates 12s. It arrange | positions so that the upper end part of a certain partition plate 12s may be touched. Thereby, each SOI wafer 1 is inclined so that the upper end portion is shifted to the other side as compared with the lower end portion, and the plurality of SOI wafers 1 accommodated in the cassette 12 are separated from each other at substantially equal intervals. It is in a laminated state. The stacking direction of the plurality of SOI wafers 1 is substantially perpendicular to the vertical direction.

  Since an opening for accommodating and taking out the wafer is formed in the upper part of the cassette 12, the outer peripheral portion of the SOI wafer 1 can be photographed by the camera 13 through this opening. The camera 13 can be a CCD camera, for example.

  The moving mechanism 14 includes a guide rail 15 extending in the horizontal direction, a first support bar 16 extending upward from the guide rail 15, and a second support bar 18 fixed in the vicinity of the upper end of the first support bar 16 and extending in the horizontal direction. including. The stage 19 is rectangular in plan view, and the guide rail 15 is arranged along one side of the stage 19 in plan view (see FIG. 6). A guide groove 15 a extending in the longitudinal direction of the guide rail 15 is formed on the upper surface of the guide rail 15. The lower end of the first support bar 16 is fitted in the guide groove 15a, and the first support bar 16 is slidable along the guide groove 15a. In FIG. 6, the direction in which the first support bar 16 is slidable is indicated by a white arrow.

  The second support bar 18 is fixed to the first support bar 16 by a fixing member 17 in the vicinity of one end thereof. A camera 13 is attached near the other end of the second support rod 18. Therefore, the camera 13 can be moved along the guide rail 15 by moving the first support rod 16 along the guide rail 15. The cassette 12 is fixed on the stage 19 in a predetermined posture by a guide member 20 provided on the stage 19. In a state where the cassette 12 is fixed by the guide member 20, the stacking direction of the plurality of SOI wafers 1 accommodated in the cassette 12 coincides with the longitudinal direction of the guide rail 15. Therefore, in this state, the camera 13 can move along the stacking direction of the plurality of SOI wafers 1.

FIG. 8 is a side view showing the vicinity of the upper ends of the plurality of SOI wafers 1 and the camera 13.
The terrace 4 of each SOI wafer 1 is substantially along the vertical direction. On the other hand, the camera 13 is fixed to the second support rod 18 in an attitude that forms an angle with respect to the vertical direction, and photographs the terrace 4 from an oblique direction with respect to the vertical direction. A stock sensor 25 is attached to the top surface of the camera 13 on the front end side of the camera 13. The presence sensor 25 can detect whether or not the upper end portion of the SOI wafer 1 exists before the presence sensor 25. When the upper end portion of the SOI wafer 1 is present in front of the in-stock sensor 25, the terrace 4 and its peripheral portion (hereinafter referred to as “terrace 4 etc.”) are reflected on the camera 25.

  With reference to FIG. 5, a light source 21 for irradiating illumination light to a plurality of SOI wafers 1 in the cassette 12 is disposed below the cassette 12. That is, the light source 21 irradiates the plurality of SOI wafers 1 with illumination light from the side opposite to the camera 13. The camera 13 can photograph the SOI wafer 1 (such as the terrace 4) irradiated with the illumination light. The light source 21 can be embedded in, for example, the stage 19. In this case, for example, an opening is formed in the lower portion of the cassette 12, and illumination light emitted from the light source 21 passes through this opening. Through this, a plurality of SOI wafers 1 in the cassette 12 can be irradiated.

  The camera 13 outputs a signal corresponding to an image obtained by shooting with the camera 13, and the signal is input to the computer 22. The computer 22 includes a storage device 23 (for example, a hard disk drive, a flash memory, or a write-once or rewritable optical disk and the disk drive), and image data (image data) obtained by photographing with the camera 13. Are stored in the storage device 23 in digital form. The computer 22 outputs a signal corresponding to an image obtained by photographing with the camera 13, and this signal is input to the monitor 24, and the image is displayed on the monitor 24.

  In the SOI wafer 1, when a notch or orientation flat is formed on the outer peripheral portion of the support wafer 2, the inspection apparatus 11 has a notch or orientation flat positioned at a specific angular position around the central axis of each SOI wafer 1. As described above, a mechanism for arranging a plurality of SOI wafers 1 (hereinafter referred to as “notch alignment mechanism”) may be further provided.

FIG. 9 is a front view showing a configuration of a notch alignment mechanism provided in the inspection device for the outer peripheral portion of the semiconductor wafer.
The notch alignment mechanism 30 includes a wafer rotating roller 31 that rotates the SOI wafer 1 in the cassette 12 about the central axis thereof, a notch guide 33 that can be inserted into the notch formed in the SOI wafer 1, and the cassette 12 as a camera. 13 and a cassette tilting jig 32 for tilting with respect to the SOI wafer 1 observation state.

  The wafer rotation roller 31 has a cylindrical shape, and the central axis of the wafer rotation roller 31 extends in the stacking direction of the plurality of SOI wafers 1 (direction perpendicular to the paper surface in FIG. 9). The wafer rotation roller 31 is located below the central axis of the plurality of SOI wafers 1. The wafer rotating roller 31 is in contact with the end surface of the SOI wafer 1 exposed from the opening formed in the lower portion of the cassette 12, and the plurality of SOI wafers 1 can be slightly lifted from the bottom of the cassette 12. . In this state, when the wafer rotation roller 31 rotates about its central axis, the SOI wafer rotates about its central axis.

  The notch guide 33 has a rod (column) shape and includes a guide portion that extends in the stacking direction of the SOI wafer 1 and a support portion that supports the guide portion and rotates the guide portion around an axis parallel to the guide portion. I have. The guide portion of the notch guide 33 can be pressed against the SOI wafer 1 from below independently of the wafer rotating roller 31. The wafer rotation roller 31 and the guide portion of the notch guide 33 are in contact with the SOI wafer 1 at positions shifted from each other in the circumferential direction of the SOI wafer 1.

  When the guide portions of the notch guides 33 are pressed against the plurality of SOI wafers 1 rotated by the wafer rotating roller 31 from below, the notches formed in the SOI wafers 1 are separated from the SOI wafers 1 and the guide portions. , The guide portion is inserted into the notch and stops the rotation of the SOI wafer 1. In this way, when the guide portion is inserted into the notch for all of the plurality of SOI wafers 1, the notch is positioned at a specific angular position around the central axis for all the SOI wafers 1.

  Thereafter, the guide portion is removed from the notch, and if necessary, all the SOI wafers 1 are rotated by the same angle by the wafer rotating roller 31, so that the regions having the same specific angular position with respect to the notch are obtained for all the SOI wafers 1. Can be observed.

  The cassette tilting jig 32 is disposed below the cassette 12 and is used to tilt the cassette 12 by lifting one side with respect to the wafer rotating roller 31 at the lower part of the cassette 12. By tilting the cassette 12 in this manner, the contact state of the wafer rotation roller 31 with respect to the SOI wafer 1 and the contact state of the guide portion of the notch guide 33 with respect to the SOI wafer 1 can be adjusted.

  In the above example, the notch alignment mechanism 30 is provided in the inspection device 11, but may be provided as a device different from the inspection device 11. In this case, after the plurality of SOI wafers 1 in the cassette 12 are positioned at specific angular positions around the central axis of the SOI wafer 1 by the notch alignment mechanism 30, the cassette 12 is Then, it is placed on the stage 19 of the inspection apparatus 11 and the SOI wafer 1 is observed.

2. Next, the bonded SOI wafer of the present invention (2) will be described. As described above, the inspection method is described as follows: “A step of laminating a plurality of semiconductor wafers apart from each other, and a camera relative to the plurality of semiconductor wafers along a laminating direction of the plurality of semiconductor wafers”. The step of moving at least one of the plurality of semiconductor wafers and the camera, the step of photographing an outer peripheral portion within 10 mm from the outer edge of each semiconductor wafer by the camera, and the photographing by the camera A method of inspecting the quality of each semiconductor wafer based on the obtained image ”.

  This inspection method will be described by taking as an example the case of using the inspection apparatus 11 shown in FIGS.

  First, a plurality of SOI wafers 1 are accommodated in the cassette 12 in the state shown in FIG. This state can be obtained as follows. That is, the SOI wafer 1 is inserted between two adjacent partition plates 12s, and the lower end of the SOI wafer 1 is brought into contact with the vicinity of the lower end portion of the one side partition plate 12s and the bottom surface of the cassette 12. Then, while maintaining this contact, the SOI wafer 1 is gradually tilted until the vicinity of the upper portion of the SOI wafer 1 contacts the upper end of the other partition plate 12s. By performing the same operation for a plurality of SOI wafers 1, these SOI wafers 1 are in the state shown in FIG.

  Then, the cassette 12 containing the plurality of SOI wafers 1 is fixed on the stage 19 by the guide member 20. Thereby, the stacking direction of the plurality of SOI wafers 1 and the moving direction of the camera 13 coincide with each other.

  Next, the light source 21 irradiates a plurality of SOI wafers 1 with illumination light. When the light source is arranged on the same side as the camera 13 with respect to the plurality of SOI wafers 1, the illumination light reflected by the SOI wafer 1 and captured by the camera 13 is substantially the same as that of the SOI wafer 1. Only the light reflected near the outer edge (the chamfered portion) is obtained. For this reason, the terrace 4 or the like cannot be clearly photographed due to halation due to reflection near the outer edge, or cannot be photographed with a sufficient amount of light.

  Since the light source 21 is disposed on the opposite side of the camera 13 with respect to the plurality of SOI wafers 1, the illumination light reflected by the terrace 4 or the like is captured by the camera 13. That is, it is possible to photograph the terrace 4 and the like with the camera 13 with a sufficient amount of light. Thereby, for example, the aperture diameter can be reduced, the depth of focus of the camera 13 can be increased, and the entire area of the terrace 4 can be focused.

  Next, the first support bar 16 is moved along the guide groove 15 a formed in the guide rail 15, thereby moving the camera 13 along the stacking direction of the plurality of SOI wafers 1. The terraces 4 are sequentially photographed. The movement of the first support rod 16 along the guide groove 15a may be performed manually or by a driving device (not shown). When the movement is performed by the driving device, the driving device may be controlled by the computer 22.

  When the upper end portion of the SOI wafer 1 is detected by the in-stock sensor 25, the camera 13 photographs the terrace 4 and the like (releases the shutter). As a result, the camera 4 can take an image of the terrace 4 or the like and obtain an image of the terrace 4 or the like. The photographing by the camera 13 may be performed based on the input from the stock sensor 25 under the control of the computer 22. When the terrace 4 is sequentially photographed, the SOI wafer 1 in the cassette 12 does not move. Therefore, only a partial image in the circumferential direction of the SOI wafer 1 is obtained for the outer peripheral portion of each SOI wafer 1. That is, an image of the entire circumference of the outer peripheral portion of the SOI wafer 1 cannot be obtained.

  Since the plurality of SOI wafers 1 are arranged at equal intervals, the terrace 4 and the like are photographed every time the camera 13 is moved by a certain distance. Since the plurality of SOI wafers 1 are arranged at equal intervals, the amount of light from the light source 21 can be made uniform, and the lightness and darkness of the image and the variation in color can be reduced. By using the in-stock sensor 25, it is possible to photograph the SOI wafer 1 at an appropriate timing even when the plurality of SOI wafers 1 are not arranged at equal intervals.

  As shown in FIG. 3 and FIG. 4, the camera 13 shoots the terrace 4 and the active layer wafer 3 (no oxide film is formed on the surface and silicon is exposed in one image (same field of view)). It is desirable to be able to enter. In this case, as will be described later, by using the color and brightness of the active layer wafer 3 as an index, it becomes easy to determine whether or not the terrace 4 has a portion where no oxide film exists.

  When taking an image with the camera 13, the camera 13 may be stationary. Alternatively, when the camera 13 is focused on the terrace 4 or the like while continuing to move the camera 13 along the stacking direction of the plurality of SOI wafers 1 without being stationary, the image of the terrace 4 or the like is obtained by the camera 13. May be taken.

  Image data obtained by photographing is stored in the storage device 23 in a digital format. When photographing of the terrace 4 and the like by the camera 13 and storage of the corresponding image data in the storage device 23 are completed for all the SOI wafers 1 to be inspected, the computer 22 causes the storage device 23 to store the respective SOI wafers 1. The image data obtained by the above photographing is read and the corresponding image is displayed on the monitor 24.

  Then, based on this image displayed on the monitor 24, the quality of each SOI wafer 1 is determined. The quality is determined, for example, by visually observing the image and determining whether an oxide film is present in the entire area of the terrace 4 within the field of view of the image. That is, if it is determined that an oxide film is present in the entire area of the terrace 4, the SOI wafer 1 is determined as a non-defective product. If it is determined that there is a region where no oxide film exists in the terrace 4, the SOI wafer 1 is determined. The wafer 1 is determined as a defective product.

  When the terrace 4 and the active layer wafer 3 (the surface of which the oxide film is not formed and the silicon is exposed) exist in one image (same field of view), the color of the terrace 4 and / or The brightness is compared with the color and / or brightness of the active layer wafer 3. If there is a portion of the terrace 4 that is determined to have the same color and / or lightness as the color and / or lightness of the active layer wafer 3 (see FIG. 4), that portion is exposed to silicon. It can be determined that no oxide film exists. On the other hand, if any part of the image on the terrace 4 has a uniform color and / or brightness that can be distinguished from the color and / or brightness of the active layer wafer 3 (see FIG. 3). It can be determined that an oxide film is present in any part of the terrace 4.

  When the terrace 4 of the SOI wafer 1 is directly visually inspected (hereinafter referred to as “direct visual inspection”), the terrace 4 is displayed on the monitor 24, and the displayed image is visually inspected (hereinafter, “ It was investigated how accurately the quality can be judged for “monitor display inspection”. As an inspection object, an SOI wafer 1 (hereinafter referred to as “non-defective wafer”) that has been confirmed to be a non-defective product by detailed inspection in advance and a part of the terrace 4 of the non-defective wafer are polished to remove a part of the oxide film. What was intentionally removed (hereinafter referred to as “defective wafer”) was prepared. The thickness of the oxide film of the non-defective wafer was 2 μm or more. In the defective product wafer, the portion from which the oxide film was removed was present at substantially the same radial position over the entire circumference of the SOI wafer 1.

  A total of 20 non-defective wafers and defective wafers were arranged in a random order, and direct visual inspection and monitor display inspection were performed on these wafers. By direct visual inspection and monitor display inspection, whether or not the inspection object is a non-defective wafer or a defective wafer can be determined. Table 1 shows the ratio of the correct number of wafers to the number of wafers to be inspected (accuracy rate). In direct visual inspection, there were 2 to 3 wafers that were misjudged for 20 wafers to be inspected, and the average accuracy rate was 87%. On the other hand, in the monitor display inspection, no wafer was erroneously determined, and the correct answer rate was 100%.

  The description of the embodiment of the present invention is as described above, but the present invention can be implemented in other forms. For example, a plurality of silicon wafers (SOI wafers 1) may be stacked apart from each other by means other than the cassette 12. For example, instead of the cassette 12, a plurality of silicon wafers may be stacked apart from each other by being housed in a transport pack for transporting the plurality of silicon wafers.

  The stacking direction of the plurality of silicon wafers (SOI wafers 1) is the horizontal direction (direction perpendicular to the direction of gravity) in the above embodiment, but may be the vertical direction (direction along the direction of gravity), The direction may be other than the horizontal direction and the vertical direction. In the embodiment, the moving mechanism 14 is configured to move the camera 13 with respect to a plurality of fixed SOI wafers 1. However, the moving mechanism may be configured to move a plurality of silicon wafers relative to a fixed camera, or may be configured to move both the camera and the plurality of silicon wafers. .

  The light source 21 that irradiates the plurality of SOI wafers 1 with illumination light may be disposed between the stage 19 and the cassette 12, or may be provided in the lower part of the cassette 12.

The quality of the SOI wafer 1 may be automatically determined by the computer 22. Also in this case, it can be based on the above-described method using the color and / or brightness of the active layer wafer 3 as an index.
The inspection apparatus 11 may not include the storage device 23. In this case, the image obtained by the camera 13 is directly copied to the monitor 24 (without passing through the storage device 23), and based on this image. Thus, the quality of each SOI wafer 1 can be determined by the operator or the computer 22.

1: SOI wafer, 4: Terrace, 11: Inspection device, 12: Cassette,
13: Camera, 14: Movement mechanism, 21: Light source, 22: Computer
23: Storage device, 24: Monitor notch alignment mechanism 30

Claims (15)

For a plurality of semiconductor wafers stacked apart from each other, for each semiconductor wafer, a camera for photographing an outer peripheral portion within 10 mm from the outer edge;
A moving mechanism for moving at least one of the plurality of semiconductor wafers and the camera so that the camera moves relative to the plurality of semiconductor wafers along a stacking direction of the plurality of semiconductor wafers; An inspection apparatus for semiconductor wafers.   The semiconductor wafer inspection apparatus according to claim 1, further comprising a storage device that stores image data obtained by photographing with the camera.   The semiconductor wafer inspection apparatus according to claim 1, further comprising a light source that irradiates illumination light from the opposite side of the camera to the plurality of semiconductor wafers.   The semiconductor wafer inspection apparatus according to claim 1, further comprising a holding member that holds the plurality of semiconductor wafers at equal intervals. An orientation flat or notch is formed in each of the plurality of semiconductor wafers,
5. A mechanism for arranging the plurality of semiconductor wafers so that the orientation flat or notch is positioned at a specific angular position around a central axis of each semiconductor wafer. The semiconductor wafer inspection apparatus according to any one of the above.   The semiconductor wafer inspection apparatus according to claim 1, wherein the semiconductor wafer is an SOI wafer.   The semiconductor wafer inspection apparatus according to claim 6, wherein the SOI wafer is a bonded SOI wafer in which a terrace is formed on the outer peripheral portion. Laminating a plurality of semiconductor wafers apart from each other;
Moving at least one of the plurality of semiconductor wafers and the camera so as to move the camera relative to the plurality of semiconductor wafers along a stacking direction of the plurality of semiconductor wafers;
A step of photographing an outer peripheral portion within 10 mm from an outer edge of each semiconductor wafer by the camera, and a step of judging pass / fail of each semiconductor wafer based on an image obtained by photographing by the camera. Semiconductor wafer inspection method. The method further includes a step of storing an image obtained by photographing with the camera in a storage device,
9. The semiconductor wafer inspection method according to claim 8, wherein the determining step includes a step of determining pass / fail of each semiconductor wafer based on the image stored in the storage device in the storing step. . Irradiating the plurality of semiconductor wafers with illumination light by a light source disposed on the opposite side of the camera;
The semiconductor wafer inspection according to claim 8, wherein the photographing step includes a step of photographing the outer peripheral portion with the camera for each semiconductor wafer irradiated with illumination light from the light source. Method.   The semiconductor wafer inspection method according to claim 8, wherein the stacking step includes a step of holding the plurality of semiconductor wafers at equal intervals. An orientation flat or notch is formed in each of the plurality of semiconductor wafers,
The step of laminating includes the step of arranging the plurality of semiconductor wafers such that the orientation flat or notch is positioned at a specific angular position around a central axis of each semiconductor wafer. The inspection method of the semiconductor wafer in any one of 8-11. The step of photographing includes a step of photographing the outer peripheral portion for a part of the circumferential direction of the semiconductor wafer,
The method for inspecting a semiconductor wafer according to any one of claims 8 to 12, wherein the step of determining pass / fail of each semiconductor wafer includes a step of determining pass / fail of the entire semiconductor wafer.   The semiconductor wafer inspection method according to claim 8, wherein the semiconductor wafer is an SOI wafer.   15. The semiconductor wafer inspection method according to claim 14, wherein the SOI wafer is a bonded SOI wafer in which a terrace is formed on the outer peripheral portion.

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