JP2015088198A5 - - Google Patents

Claims (9)

A first switch having one end electrically connected to the input section, a first capacitor element having a first capacitor first electrode and a first capacitor second electrode, a second capacitor first electrode and a second capacitor second A second capacitive element having an electrode, and a logic unit,
The other end of the first switch, the first capacitor first electrode, the second capacitor second electrode, and the input of the logic unit are electrically connected (referred to as a first node),
An output of the logic unit and the second capacitor first electrode are electrically connected (referred to as a second node).   The memory circuit according to claim 1, wherein the logic unit includes a buffer circuit. With a second switch,
One end of the second switch is electrically connected to the first node;
3. The memory circuit according to claim 1, wherein the other end of the second switch is electrically connected to the second node.   4. The memory circuit according to claim 3, wherein the first switch is turned on during a period in which the second switch is in an off state.   5. The memory circuit according to claim 3, wherein the second switch is turned on while the first switch is in an off state. 6. A signal line;
A storage circuit according to any one of claims 1 to 5 ,
The electro-optical device , wherein the storage circuit stores an image signal supplied to the signal line .   An electronic apparatus comprising the electro-optical device according to claim 6.   A semiconductor memory device comprising the memory circuit according to claim 1.   An electronic apparatus comprising the semiconductor memory device according to claim 8.