JP2015079852A - Semiconductor device and inspection method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of measuring the amount of overhang at a side of a second conductivity type region adjacent to a first conductivity type region located below a gate electrode.SOLUTION: A plurality of semiconductor devices include: a second conductivity type region 4a that is a region near a center in a lateral direction from one end side of each of a plurality of first conductivity type regions 3a and that is formed by introducing a second conductivity type impurity to a region having a different position of a side edge of the region near the center; and an electrode 6a that is formed, via an insulating film 5a, at a joint part of the first conductivity type region 3a and the second conductivity type region 4a and above a periphery thereof. A method includes the steps of: obtaining a relational expression that indicates a relation between capacitance values at inflection points of a plurality of voltage/capacitance characteristic lines, which are obtained by measuring a capacitance between the second conductivity type region 4a and the electrode 6a, and positions of the side edge in the second conductivity type impurity introduction region; and in addition obtaining the amount of overhang of the second conductivity type region from the side edge on the basis of the relational expression.

Description

  The present invention relates to a semiconductor device and an inspection method thereof.

  As a high / medium withstand voltage, high output transistor such as a high frequency power IC for mobile phone base stations, a switching power supply IC, an in-vehicle IC, etc., a MOS transistor having excellent withstand voltage near the drain end, such as lateral diffusion ( An LD (Laterally Diffused) MOS transistor is known.

  An LDMOS transistor has a drift region formed between a gate electrode and a drain region in a silicon substrate. The drift region is formed in the same conductivity type as the drain region, for example, n-type. Further, the n-type impurity concentration in the drift region is set lower than the n-type impurity concentration in the drain region. Thereby, the electric field strength between the drain region and the gate electrode can be relaxed and the breakdown voltage can be increased.

  Further, in the LDMOS transistor, a buried insulating film is buried above the drift region. In such a drift region, the drift length extends to a region below the buried insulating film or near the source, causing a voltage drop, and a high breakdown voltage can be secured. In addition, the LDMOS transistor employs a structure in which the end of the gate electrode near the drain region is disposed on the buried insulating film above the drift region, thereby reducing the electric field concentration at the end of the gate electrode.

  Further, under the gate electrode of the silicon substrate, a well having a conductivity type opposite to the drain region, for example, a p-type well is formed adjacent to the drift region. In the p-type well, an n-type source region is formed on the side of the gate electrode, and a channel region immediately below the gate electrode.

JP 2012-15388 A JP 2007-67436 A

  The p-type well is formed by a process of ion-implanting p-type impurities into a silicon substrate using a mask before forming the gate electrode and activating the p-type impurities by annealing. The boundary between the p-type well formed using the mask and the n-type drift region exists below the gate electrode. When forming a well, the well formation position is generally managed based on the position of the mask edge for impurity ion implantation and the annealing temperature.

  At the time of annealing for activation, the p-type impurity diffuses from the ion-implanted portion to the drift region around it, so that the well is overhanged, but it is difficult to examine the amount of overhang.

  An object of the present invention is to provide a semiconductor device for measuring a lateral extension amount of a second conductivity type well formed in a first conductivity type well located below a gate electrode, and an inspection method thereof. is there.

According to one aspect of the present embodiment, a plurality of first conductivity type regions formed in each of a plurality of element formation regions in a semiconductor substrate and a lateral side from one end side of each of the plurality of first conductivity type regions. In each of the plurality of element formation regions, a second conductivity type region formed by introducing a second conductivity type impurity by changing the position of the side edge near the center in a region near the center in the direction, The electrode formed on the boundary between the first conductivity type region and the second conductivity type region and the periphery thereof via an insulating film, and on the side of each of the plurality of element formation regions, the first And a contact region formed in the same conductivity type in any one of the second conductivity type regions and the first conductivity type region in each of the plurality of element formation regions. And the contour of the second conductivity type region The position of the edge near the one end of the depletion layer generated in the portion that is connected to the electrode and being connected to the electrode region is defined as the lateral reference position, and for each of the plurality of element formation regions, the electrode and Measure the relationship between the applied voltage applied between the contact regions and the capacitance between the electrode and the contact region, determine a plurality of voltage / capacitance characteristic lines, and in the plurality of voltage / capacitance characteristic lines The common capacitance value saturated at a low value is used as a reference capacitance, one first voltage in the inflection point region of the plurality of voltage / capacitance characteristic lines is selected, and the plurality of voltage / capacitance characteristic lines The capacitance at the first voltage is defined as a plurality of inflection point capacitance values, and the relationship between the position of the side edge and the inflection point capacitance value in the plurality of element formation regions where the inflection point capacitance value is obtained. The position of the side edge; A relational expression using a capacitance value as a variable is created, and in the relational expression, a protruding position of the side edge where the capacitance value becomes the reference capacity is obtained, and a distance between the protruding position and the reference position is determined as the second conductivity. A method for testing a semiconductor device is provided in which the amount of protrusion of the side edge of the mold region is set.
The objects and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims. It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention.

  According to the present embodiment, it is possible to measure the amount of lateral protrusion of the second conductivity type region formed in the first conductivity type region located below the gate electrode.

FIG. 1 is a plan view of the semiconductor device according to the first embodiment. FIG. 2 is a cross-sectional view of the semiconductor device according to the first embodiment viewed from the line II of FIG. 3A and 3B are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the first embodiment. 4A and 4B are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the first embodiment. 5A and 5B are cross-sectional views illustrating the manufacturing process of the semiconductor device according to the first embodiment. 6A and 6B are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the first embodiment. FIGS. 7A to 7C are cross-sectional views showing changes in voltage and carrier accumulation by the semiconductor device testing method according to the first embodiment. FIG. 8A is a diagram showing a voltage / capacitance characteristic line of the semiconductor device according to the first embodiment, and FIG. 8B is a diagram showing the capacitance value of the semiconductor device according to the first embodiment and the edge of the mask opening. It is an edge position / capacitance characteristic diagram showing the relationship between the position and the capacitance value. FIG. 9 is a cross-sectional view showing the well overhang of the semiconductor device according to the first embodiment. FIG. 10 is a plan view of the semiconductor device according to the second embodiment. 11A and 11B are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the second embodiment. 12A and 12B are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the second embodiment. 13A and 13B are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the second embodiment. FIG. 14 is a cross-sectional view of the semiconductor device according to the second embodiment viewed from the line II-II in FIG. FIG. 15A is a diagram illustrating a voltage / capacitance characteristic line of the semiconductor device according to the second embodiment, and FIG. 15B is a diagram illustrating the capacitance value of the semiconductor device according to the second embodiment and the edge of the mask opening. It is an edge position / capacitance characteristic diagram showing the relationship between the position and the capacitance value. FIG. 16 is a cross-sectional view showing the well overhang of the semiconductor device according to the second embodiment.

Embodiments will be described below with reference to the drawings. In the drawings, similar components are given the same reference numerals.
(First embodiment)
FIG. 1 is a plan view showing a semiconductor device according to this embodiment, and FIG. 2 is a cross-sectional view taken along the line II of FIG.

  1 and 2, a first transistor formation region A and a first monitor element formation region B surrounded by an element isolation insulating film 2 are disposed on the main surface of a silicon substrate 1 which is a semiconductor substrate. In the plan view of FIG. 1, the upper structure from the upper surface of the silicon substrate 1 is omitted. An n-type LDMOS transistor Tn used also as a monitor element is formed in the first transistor formation region A, and an n-type monitor element Mn is formed in the first monitor element formation region B. Hereinafter, the structures of the n-type LDMOS transistor Tn and the n-type monitor element Mn will be described together with the manufacturing steps shown in the cross-sectional views of FIGS.

  The n-type monitor element Mn formed in the first monitor element formation region B does not have a transistor function, but has the same structure as the n-type LDMOS transistor Tn except that it does not have a source region. For this reason, in the monitor elements Mn and Mp described below, the same structural portions as those of the LDMOS transistors Tn and Tp are indicated by the same names.

  Next, steps required until a structure shown in FIG.

  First, the element isolation insulating film 2 is formed in a region surrounding the first transistor formation region A and the first monitor element formation region B on the main surface of the silicon substrate 1. When the element isolation insulating film 2 is formed, the p-side contact regions 4c and 4d disposed near the first end portions (left side in the drawing) of the first transistor formation region A and the first monitor element formation region B, respectively. Partition insulating films 2 a and 2 b are formed on the main surface of the silicon substrate 1.

  Further, when the element isolation insulating film 2 is formed, a drift insulating film that partitions an after-mentioned n-type drain region 12b formed near the second end (right side in the drawing) in the first transistor formation region A from the inside. 2c is formed. At the same time, the drift insulating film 2d that partitions the n-type drain region 12c formed at the second end (right side in the drawing) of the first monitor element formation region B from the inside is formed. The drift insulating film 2c in the first transistor formation region A also has a function of deepening the movement path of carriers (electrons) flowing into the n-type drain region 12b.

  Shallow trench isolation (STI) is formed as the element isolation insulating film 2, the partition insulating films 2a and 2b, and the drift insulating films 2c and 2d. The STI is formed by forming a recess on the main surface of the silicon substrate 1 to a depth of about 400 nm, for example, and then filling the recess with an insulating film, for example, a silicon oxide film. The element isolation insulating film 2, the partition insulating films 2a and 2b, and the drift insulating films 2c and 2d may be formed by a LOCOS method.

After the element isolation insulating film 2 is formed, an n-type impurity such as phosphorus (P) is ion-implanted into each of the first transistor formation region A and the first monitor element formation region B in the main surface of the silicon substrate 1. N wells 3a and 3b are formed. Phosphorus ions are implanted, for example, in two portions under different conditions. For example, in the first time, the acceleration energy is set to about 2 MeV and the dose amount is set to about 2 × 10 ¹² cm ⁻² . In the second time, the acceleration energy is set to about 500 keV and the dose amount is set to about 2 × 10 ¹² cm ⁻² . N wells 3 a and 3 b are formed deeper than element isolation insulating film 2.

  Next, a resist is applied on the silicon substrate 1, the element isolation insulating film 2, etc., and subjected to exposure, development, and the like to form a resist pattern 51 as shown in FIG. The resist pattern 51 has a first opening 51a and a second opening 51b. The first opening 51a has a planar shape that exposes a region from the first end in the first transistor formation region A to the channel region CH1 of the transistor through the contact region 4c, the partition insulating film 2a, and the source formation region S. Have. The second opening 51b has a shape that exposes a region from the first end in the first monitor element formation region B to the contact region 4d and the partition insulating film 2b to the channel region CH2.

In the first opening 51a, the horizontal length of the exposed range extending from a first end of the first transistor forming region A on the edge x1 near the center and L _11. Further, the lateral distance between the first opening 51a and the drift insulating film 2c and Ln _1. Although the values of the distances L ₁₁ and Ln ₁ in the first transistor formation region A arranged as a plurality of monitor elements are different from each other, the total value of the distance L ₁₁ and the distance Ln ₁ is made substantially equal. .

In the second opening portion 51b, the horizontal length of the exposed range extending from a first end of the first monitor device forming region B on the edge x2 near the center and L _12. Further, the lateral distance between the second opening 51b and the drift insulating film 2d and Ln _2. Although the values of the distances L ₁₂ and Ln _{2 in} the plurality of first monitor element formation regions B are different from each other, the total value of L ₁₂ and Ln ₂ is made substantially equal.

The distances L ₁₁ , Ln ₁ , L ₁₂ , and Ln ₂ described above and the distances or lengths described below are cross sections along a linear II line from the first end to the second end in FIG. The horizontal distance or length at The horizontal direction described below is also a direction along the line II.

  Next, using the resist pattern 51 as a mask, boron (B) ions are implanted into the N wells 3a and 3b through the first and second openings 51a and 51b to form P wells 4a and 4b. The ion implantation angle is, for example, substantially perpendicular to the substrate surface. When a plurality of first transistor formation regions A are arranged on the silicon substrate 1 as monitor elements, the first transistor formation regions A are formed such that the positions of the edges x1 of the first openings 51a of the first transistor formation regions A are different. Similarly, when a plurality of first monitor element formation regions B are arranged in the silicon substrate 1, the positions of the edges x2 of the second openings 51b are different in each of the plurality of first monitor element formation regions B. It is formed.

  Thus, the lateral lengths from the first end to the second end of the P wells 4a in the plurality of first transistor formation regions A are different from each other from the beginning. Similarly, in the plurality of first monitor element formation regions B, the lengths of the P wells 4b in the horizontal direction are different from the beginning. In the first transistor formation region A and the first monitor element formation region B immediately after the ion implantation, the P wells 4a and 4b are formed at the same positions as the first and second openings 51a and 51b. The side edges of 4b substantially coincide with the edges x1 and x2 of the first and second openings 51a and 51b.

P wells 4a and 4b are formed deeper than element isolation insulating film 2 and shallower than N wells 3a and 3b. In this case, B ions are implanted, for example, in three times. For example, in the first time, the acceleration energy is about 400 keV and the dose amount is about 1 × 10 ¹³ cm ^−2, and in the second time, the acceleration energy is about 150 keV and the dose amount is about 5 × 10 ¹² cm ⁻² . Further, in the third time, the acceleration energy is about 15 keV and the dose is about 1 × 10 ¹³ cm ⁻² .

  The lateral junction between the P wells 4a, 4b and the N wells 3a, 3b formed under the above conditions is formed away from one end of the drift insulating films 2a, 2b toward the contact regions 4c, 4d. Thereafter, the resist pattern 51 is removed.

After introducing the p-type impurity and the n-type impurity as described above into the silicon substrate 1, the silicon substrate 1 is annealed at, for example, about 1000 ° C. to activate the p-type impurity and the n-type impurity. According to this annealing, the p-type impurities diffuse to the periphery in the N wells 3a and 3b, so that the P wells 4a and 4b project in the lateral direction. The amount of overhang varies depending on the substantial p-type impurity concentration of the P wells 4a and 4b. The amount of projection of the lateral direction of the case to the width Lx _0.

  Incidentally, the silicon substrate 1 also has a region where the p-type LDMOS transistor and the p-type monitor element are formed. When these P wells and N wells are formed, the upper surface of the silicon substrate 1 in the first transistor formation region A and the first monitor element formation region B is covered with a photoresist R as shown in FIG. The photoresist R is removed after the wells are formed.

  Next, a gate insulating film is formed on the surface of the silicon substrate 1 to a thickness of about 15 nm by, for example, thermal oxidation, and a polysilicon film is further formed thereon to a thickness of, for example, about 150 nm by a CVD method. Thereafter, the polysilicon film and the gate insulating film are patterned by a photolithography technique and an etching technique. As a result, in the first transistor formation region A and the first monitor element formation region B, the regions crossing over the N wells 3a and 3b and the P wells 4a and 4b are connected to the polysilicon first through the gate insulating films 5a and 5b. First, second gate electrodes 6a and 6b are formed.

  One side portion of the first gate electrode 6a in the first transistor formation region A is located above a part of the P well 4a, and the other side portion is located on the drift insulating film 2c. As a result, the surface layer of the P well 4 where the first gate electrode 6a overlaps becomes a channel region CH1 where a depletion layer can occur. Further, the lateral junction (boundary) between the P well 4a and the N well 3a is located below the first gate electrode 6a.

  An edge of one side of the second gate electrode 6b in the first monitor element formation region B is formed so as to overlap with or coincide with the edge of the adjacent partition insulating film 2a. The other side of the second gate electrode 6b is located on the drift insulating film 2d.

Next, steps required until a structure shown in FIG.
First, a photoresist is applied on the silicon substrate 1 and then subjected to exposure, development, and the like to form a resist pattern (not shown). In the first transistor formation region A and the first monitor element formation region B, the resist pattern covers the contact regions 4c and 4d at the first end portions of the P wells 4a and 4b and exposes other regions.

  Thereafter, the first and second gate electrodes 6a and 6b, the element isolation insulating film 2, the partition insulating films 2a and 2b, the drift insulating films 2c and 2d are used as a mask together with the resist pattern, and the N wells 3a and 3b are used. Then, an n-type impurity such as phosphorus is ion-implanted into the P wells 4a and 4b. Thus, the n-type extension region 7a is formed on one side of the first gate electrode 6a in the P well 4a in the first transistor formation region A. At the same time, n-type extension regions 7b and 7c are formed near the second ends of the N wells 3a and 3b in the first transistor formation region A and the first monitor element formation region B, respectively. The n-type extension regions 7 a, 7 b and 7 c are formed shallower than the element isolation insulating film 2. At this time, n-type impurities are also introduced into the first and second gate electrodes 6a and 6b. Thereafter, the resist pattern is removed.

  Further, a new photoresist is applied on the silicon substrate 1 and subjected to exposure, development and the like to form a resist pattern (not shown). This resist pattern exposes the contact regions 4c and 4d near the first ends of the P wells 4a and 4b and covers the other regions in the first transistor formation region A and the first monitor element formation region B, respectively. Has a shape. Thereafter, a p-type impurity such as boron is ion-implanted into the contact regions 4c and 4d of the P wells 4a and 4b using the resist pattern as a mask. As a result, p-type extension regions 9 a and 9 b shallower than the element isolation insulating film 2 are formed above the contact regions 4 c and 4 d surrounded by the element isolation insulating film 2.

Next, steps required until a structure shown in FIG.
First, an insulating film such as a silicon nitride film is formed on the silicon substrate 1, thereby covering the first and second gate electrodes 6a and 6b. Thereafter, the insulating film is etched back, and the insulating film is removed from the upper surface of the silicon substrate 1 and left as insulating side walls 11a and 11b on the side walls of the first and second gate electrodes 6a and 6b.

Next, steps required until a structure shown in FIG.
First, a photoresist is applied on the silicon substrate 1 and subjected to exposure, development and the like to form a new resist pattern (not shown). This resist pattern has a shape that covers the contact regions 4c and 4d of the P wells 4a and 4b and exposes other regions in the first transistor formation region A and the first monitor element formation region B. Thereafter, the first and second gate electrodes 6a and 6b, the element isolation insulating film 2, the partition insulating films 2a and 2b, and the drift insulating films 2c and 2d are used as a mask together with the resist pattern, and the n-type extension region 7a, N-type impurity high concentration regions 8a, 8b and 8c are formed on the upper portions of 7b and 7c. The n-type impurity high concentration regions 8a, 8b and 8c are formed with a higher n-type impurity concentration than the n-type extension regions 7a, 7b and 7c. Thereafter, the resist pattern is removed. The n-type impurity is also introduced into the first and second gate electrodes 6a and 6b.

  In the first transistor formation region A, the n-type extension region 7a formed on one side of the first gate electrode 6a in the P-well 4a and the n-type impurity high-concentration region 8a above the n-type source region 12a Become. Further, the n-type extension region 7c formed on the side of the drift insulating film 6c in the N well 4a and the n-type impurity high concentration region 8c thereabove become an n-type drain region 12b. In the first monitor element formation region B, the n-type extension region 7c formed beside the drift insulating film 6d in the N well 4b and the n-type impurity high concentration region 8c thereabove become an n-type drain region 12c. . The n-type drain regions 12b and 12c may be used as n-type contact regions for the N wells 3a and 3b. N wells 3a and 3b connected to drain regions 12b and 12c serve as drift regions.

  After removing the resist pattern, a new photoresist is applied on the silicon substrate 1 and subjected to exposure, development and the like to form a new resist pattern (not shown). This resist pattern has a shape that exposes the contact regions 4c and 4d of the P wells 4a and 4b and covers other regions in the first transistor formation region A and the first monitor element formation region B, respectively. Thereafter, using the resist pattern as a mask, p-type impurity ions are implanted into the contact regions 4c and 4d of the P wells 3a and 3b. Thereby, p-type impurity high concentration regions 10a and 10b having a higher p-type impurity concentration are formed above the p-type extension regions 9a and 9b. Thereafter, the resist pattern is removed. Thereafter, the ion-implanted n-type impurity and p-type impurity are activated by annealing.

Next, steps required until a structure shown in FIG.
First, a metal film, for example, a cobalt (Co) film is formed on the silicon substrate 1, the element isolation insulating film 2, the first and second gate electrodes 6a and 6b, and then the Co film, the first, first, The second gate electrodes 6a and 6b, the silicon substrate 1 and the like are annealed and the salicide technique is applied. Thereby, silicide layers 13a to 13g are formed on the first and second gate electrodes 6a and 6b, the n-type source region 12a, the n-type drain regions 12b and 12c, and the contact regions 4c and 4d. Thereafter, the Co film is removed. In the step of forming the silicide layers 13a to 13g, the first annealing may be performed after the Co film is formed, and the second annealing may be performed after the Co film is removed. In the second annealing, for example, the temperature is set higher than that in the first annealing.

  1 and 2, the n-type LDMOS transistor Tn is formed in the first transistor formation region A, and the n-type monitor element Mn is formed in the first monitor element formation region B. On these elements, the insulating film, conductive plug, wiring, etc. shown in FIG. 2 are formed by the following method.

  First, a silicon oxide film, for example, is formed as an interlayer insulating film 14 on the silicon substrate 1 by the CVD method, and the n-type LDMOS transistor Tn, the n-type monitor element Mn and the like are covered with the interlayer insulating film 14. Thereafter, the upper surface of the interlayer insulating film 14 is planarized by the CMP method. Further, a photoresist is applied on the interlayer insulating film 14, and a resist pattern (not shown) is formed by exposing and developing the photoresist. This resist pattern has an opening in a portion of the interlayer insulating film 14 where a contact hole is to be formed. Next, the interlayer insulating film 14 is etched through an opening of a resist pattern (not shown) to form contact holes 14a to 14g reaching the silicide layers 13a to 13g.

  Further, for example, titanium nitride (TiN) is formed as a barrier metal on the inner surfaces of the contact holes 14a to 14g, and the contact holes 14a to 14g are filled with a tungsten film. Subsequently, the tungsten film or the like on the interlayer insulating film 14 is removed by CMP to expose the upper surface. As a result, the tungsten film or the like remaining in the contact holes 14a to 14g is used as the conductive plugs 15a to 15g. Thereafter, wirings 16a to 16g connected to the conductive plugs 15a to 15g are formed on the interlayer insulating film 14, and further, another interlayer insulating film (not shown), vias (not shown), wirings (not shown). ) And the like are repeated to form a multilayer wiring structure, but details thereof are omitted.

In the process of forming the P well 4a in the n-type LDMOS transistor Tn as described above, as shown in FIG. 3B, the ion-implanted p-type impurity is diffused by annealing or the like and laterally extends from the implantation region. Overhang. In this case, the overhang amount Lx ₀ is detected by the following method.

A plurality of n-type LDMOS transistors Tn used as monitor elements are formed. These n-type LDMOS transistors Tn are formed under the same conditions except that the positions of the edges x1 of the openings 51a of the resist pattern 51 shown in FIG. 3B are different from each other. The monitor element thus formed is required to have an overhang Lx ₀ by the following electrical test.

First, as shown in FIG. 2, the voltage of the n-type source region 12a is Vs, the voltage Vd of the n-type drain region 12b, the substrate voltage of the silicon substrate 1 is Vb, and these voltages are set to 0 volt (0V). The p-type contact region 4c is set to 0V. In addition, the bias voltage connected between the first gate electrode 6a and the p-type contact region 4c, that is, the magnitude of the DC applied voltage Vg of the voltage source 41 is swept from, for example, -2V to + 2V and raised. At the same time, the capacitor capacitance measuring device 42 is used to measure the capacitance C _gb of the capacitor between the first gate electrode 6a and the p-type contact region 4c in the n-type LDMOS transistor Tn.

Under such conditions, since the P well 4a and the N well 3a have the same potential, the mutual influence due to the change in the DC voltage Vg can be ignored. The capacitance C _gb of the capacitor between the P well 4a and the first gate electrode 6a via the gate insulating film 5a is electrically connected to the first gate electrode 6a and the p-type contact region 4c via the wirings 16a and 16f. It is detected by the capacitor capacity measuring device 42 connected to the same.

When the DC voltage Vg is negative, a hole (h +) of majority carriers moves to the surface layer of the channel region CH1 of the P well 4a facing the first gate electrode 6a as illustrated in FIG. Density increases. Therefore, as the DC voltage Vg is increased in the negative direction, the capacitance C _gb between the first gate electrode 6a and the p-type contact region 4c increases. Further, as the DC voltage Vg is increased in the minus direction, a depletion layer is generated in the surface layer of the N well 3a, and holes that are minority carriers move to the surface layer to form an inversion layer.

When the DC voltage Vg is 0 V or a voltage in the vicinity thereof, majority carrier holes exist in the channel region of the surface layer of the P well 4a facing the first gate electrode 6a as illustrated in FIG. 7B. In the surface layer of the N well 3a, majority carrier electrons (e−) exist. Therefore, a value depending on the p-type impurity concentration of the P well 4a appears between the first gate electrode 6 and the p-type contact region 4c as the capacitance C _gb .

Furthermore, when the DC voltage Vg is positive, as illustrated in FIG. 7C, a depletion layer is generated in the surface layer of the P well 4a as the voltage is increased, and electrons that are minority carriers move to the surface layer. Thus, an inversion layer is formed. In this case, majority carrier electrons move to the surface layer of the N well 4a. As the DC voltage Vg increases to the positive side, the capacitance C _gb between the first gate electrode 6a and the p-type contact region 4c is further decreased and saturated.

At Vg = 0 V or voltages Vg ₁ and Vg ₂ in the vicinity thereof, the hole / electron carrier distribution on the surface of the silicon substrate 1 can be measured as it is, so the capacitance C _gb is the area where the P well 4a and the first gate electrode 6a overlap. That is, it has a certain correlation with the length of the region where the depletion layer occurs. Therefore, as shown in FIGS. 7A and 7C, when the strong inversion / strong accumulation is measured at + 2V / −2V, the P shown in FIG. 2B below the first gate electrode 6a is measured. The capacitance in the range of the length of the channel region CH1 of the well 4a and the N well 3a can be detected. Also, P and the length of the channel region CH1 of the well 4a and _{L CH1, L CH1} / Ln ₁ of precisely estimable bias voltage length Vg = 0V and _{L CH} dependent _{C gb} in the voltage conditions in the vicinity thereof Sex is shown.

When the DC voltage Vg is increased from −2V to + 2V, the measured capacitance C _gb changes, for example, as shown in the voltage / capacitance characteristic curve a, b or c in FIG. The point appears when Vg is about 0V. Three voltage / capacitance characteristic curves a, b and c are obtained by making the positions of the edges x1 of the openings 51a of the resist pattern 51 used for forming the P well 4a different from each other. It shows that the characteristics are different. The voltage-capacitance characteristic lines a, b, in c, the common capacitance value of saturation plus high voltage value and the reference capacitance C _0. Capacitance C _gb at the inflection points in the plurality of voltage / capacitance characteristic lines a, b, c is C _a , C _b , C _c, and the voltage at the inflection points is the inflection point voltage. Here, 10% of the highest inflection point capacitance _{C a,} the voltage + 10% of the capacity is obtained and _Vg 1, Vg _2. Further, a capacity in the range of −10% to + 10% with respect to the inflection point capacity C _a is defined as an inflection point area capacity, and a voltage range in this case is defined as an inflection point area voltage.

The three voltage / capacitance characteristic curves a, b, and c in FIG. 8A show the resist pattern 51 in the n-type LDMOS transistor Tn from the first end of the first transistor formation region A shown in FIG. It is shown from top to bottom in descending order of the distance L ₁₁ to the edge x1 openings 51a. Therefore, according to the characteristic curve a, b and c, the distance L ₁₁ is narrowed area of the P-well 4a below the first gate electrode 6a as shorter, between the P-well 4a and the first gate electrode 6a The capacity C _gb is reduced.

Further, the relationship between the position of the edge x1 of the opening 51a and the inflection point capacitance values C _a , C _b , and C _{c in} the plurality of first transistor formation regions A is plotted in two-dimensional coordinates, and the plots are connected. As shown in FIG. 8B, a linear characteristic line is obtained, and a relational expression of a linear function is obtained from the characteristic line.

In FIG. 8B, the vertical axis indicates the capacity C _gb , and the origin is the reference capacity C ₀ . The horizontal axis indicates the edge x1 of the opening 51, that is, the position of the end of the p-type impurity introduction region when the P well 4a is formed. In this case, the reference position L ₀ of the first end position of the edge of the (in the drawing left) side of the depletion layer generating region CH1 in P-well 4a, this is the origin of the horizontal axis. Figures horizontal axis of FIG. 8 (b) shows the distance to the position of the edge x1 from a reference position L _0. Here, the reference position L ₀ in FIG. 2 and one end of the first gate electrode 6a.

If it is assumed that the p-type impurity introduced into the formation of P-well 4a is not diffuse, capacitance C _gb of the capacitor assuming edges x1 coincides with the reference position L ₀ is a C _0. However, as shown in FIG. 9, since the p-type impurity in the P well 4a is diffused by annealing, the position of the edge z extends in the lateral direction. Therefore, even when the edges x1 of the opening 51a of the resist pattern 51 is aligned with the reference position L _0, becomes larger than the capacitance C _gb the reference capacitance C _0, as shown by a characteristic line of FIG. 8 (b), Intercepts occur on the vertical and horizontal axes. Sections of the vertical axis represents the increment C _alpha capacitance C _gb on the positive side. Further, the intercept on the horizontal axis, the projecting amount Lx ₀ of p-type impurity for the drift insulating film 6c minus side.

Therefore, the solid line in FIG. 8B can be obtained as a relational expression of C _gb = K · x1 + C _α (where K = C _α / Lx ₀ ) if L ₀ = 0 and C ₀ = 0. FIG. 9 is a cross-sectional view drawn based on a two-dimensional profile image of hole concentration calculated by technology CAD.

By the way, when the inflection point capacitance C _gb in the case of the voltage Vg ₁ on the minus side of the inflection point range in the characteristic lines a, b, c of FIG. It becomes like the one-dot chain line of 8 (b). Further, when the inflection point capacitance C _gb in the case of the voltage Vg ₂ on the plus side of the inflection point range is obtained on the characteristic lines a, b, and c in FIG. It becomes like the wavy line of 8 (b). In any case, it can be seen that the intercepts on the horizontal axis are almost the same, and the amount of overhang is the same. The slope of the capacitance / edge position characteristic line increases as the carrier concentration of the surface layer of the P well 4a increases.

  The above method for measuring the amount of protrusion of the P well 4a can also be applied to the measurement of the amount of protrusion of the P well 4b in the n-type monitor element Mn. That is, the relationship of the capacitance to the applied voltage Vg between the second gate electrode 6b and the contact region 4d is measured, a characteristic line as shown in FIG. 8A is obtained, and the opening 51b of the resist pattern 51 is further obtained. The overhang amount with respect to the edge x2 can be measured by the same method as described above. The position of the edge x2 of the opening 51b substantially coincides with the side edge of the region into which the p-type impurity is introduced.

In this case, the total lateral distance of the P well 4b and the N well 3b under the second gate electrode 6b is equal to the depletion layer generation region CH2 of the P well 4b between the partition insulating film 2b and the drift insulating film 2d. This is the total distance of the length L _CH2 and the length Ln ₂ of the N well 3b. The distance is not affected by the positional deviation of the second gate electrode 6b. As a result, the capacitance-voltage characteristic line as shown in FIG. 8A is obtained without being affected by the positional deviation of the second gate electrode 6b, and the capacitance C _gb and the opening shown in FIG. The positional relationship of the edge x2 of the part 51b can be detected with higher accuracy.

  Further, the n-type monitor element Mn does not have the n-type source region 12a as compared with the n-type LDMOS transistor Tn, and the interval between the second gate electrode 6b and the partition insulating film 2b is set to zero or is partially separated from each other. It has a structure that overlaps. For this reason, the overhang of the n-type impurity due to the annealing of the n-type source region 12a can be ignored during the inspection.

As described above, according to the test using the n-type monitor element Mn, the capacitance C _α and the positional shift amount Lx ₀ can be detected with higher accuracy than in the case of measuring using the n-type LDMOS transistor Tn. .

According to the above embodiment, the edges x1 of the openings 51a and 51b of the resist pattern 51 when forming the P wells 4a and 4b in the plurality of first transistor formation regions A or the plurality of first monitor element formation regions B, The horizontal positions of x2 are different from each other. Further, a voltage / capacitance characteristic line is obtained from the relationship between the voltage applied between the contact regions 4c and 4d of each P well 4a and 4b and the gate electrodes 6a and 6b and the capacitance measured therebetween. Further, the inflection point voltage and the inflection point capacity are obtained from the inflection point range of the voltage / capacitance characteristic line. Further, the relationship between the inflection point capacitance of each of the P wells 4a and 4b and the positions of the edges x1 and x2 of the openings 51a and 51b of the resist pattern 51 is plotted in two-dimensional coordinates to obtain a relational expression of characteristic lines. Furthermore, sections of the axis indicating the capacity of the characteristic line and changing capacitance C _alpha, and sections of the axis indicating a position of the edge x1, x2 and P-well 4a, 4b protruding amount Lx ₀ of. According to such a method, the amount of protrusion of the P wells 4a and 4b can be obtained with high accuracy without processing the completed semiconductor device, so that the inspection of the impurity diffusion region of the semiconductor device is facilitated, and the electrical Easy to understand characteristics. Further, P-well 4a was obtained in this way, associate the overhang amount Lx ₀ of 4b impurity ion implantation amount, such as annealing temperature, it is possible to improve the characteristics of the LDMOS transistor by storing the data.

  By the way, in the above description, a voltage is applied between the contact regions 4c and 4d of the P wells 4a and 4b and the gate electrodes 6a and 6b, and the capacitor capacitance between the P wells 4a and 4b and the gate electrodes 6a and 6b is measured. Thus, the amount of overhang of the P wells 4a and 4b was obtained. In contrast, the drain regions 12b and 12c of the N wells 3a and 3b are used as contact regions, a voltage is applied between the drain regions 12b and 12c and the gate electrodes 6a and 6b, and the N wells 3a and 3b and the gate electrode 6a are applied. , 6b may be measured to determine the amount of protrusion of the P wells 4a, 4b. When the N well is formed by n-type impurity ion implantation after the P well, the overhang amount for the N well is measured.

(Second Embodiment)
FIG. 10 is a plan view showing a semiconductor device according to the second embodiment, and FIGS. 11 to 13 are cross-sectional views showing manufacturing steps of the semiconductor device according to the second embodiment. In the plan view of FIG. 10, the upper structure from the upper surface of the silicon substrate 1 is omitted. Moreover, the cross section of FIGS. 11-13 is sectional drawing seen from the II-II line | wire of FIG.

  The semiconductor device inspection method according to the second embodiment is obtained by applying the inspection method shown in the first embodiment to the p-type LDMOS transistor Tp and the p-type monitor element Mp. Then, next, the structure of the p-type LDMOS transistor Tp and the p-type monitor element Mp will be described together with its formation method.

Next, steps required until a structure as shown in FIG.
First, the element isolation insulating film 2, partition insulating films 2e and 2f, and drift insulating films 2g and 2h are formed on the main surface of the silicon substrate 1 by the same method as in FIG. The element isolation insulating film 2 is formed in a region surrounding the second transistor formation region D and the second monitor element formation region E. The partition insulating films 2e and 2f partition the contact regions 23c and 23d disposed near the first ends (left in the drawing) of the second transistor formation region D and the second monitor element formation region E from the inside. Formed. Further, the drift insulating films 2g and 2h are disposed on the first end side of the drain regions 32b and 32c formed near the second ends (right side in the drawing) of the second transistor formation region D and the second monitor element formation region E, respectively. It is formed in a region closer to the center from the edge.

  Thereafter, an n-type impurity, for example, phosphorus is ion-implanted into each of the second transistor formation region D and the second monitor element formation region E in the main surface of the silicon substrate 1, and an N well 23a, 23b is formed. For example, phosphorus ions are implanted under the same conditions as those for forming the N wells 3a and 3b shown in FIG.

Next, steps required until a planar structure shown in FIG. 10 and a cross-sectional structure shown in FIG.
First, a resist is applied on the silicon substrate 1 and the element isolation insulating film 2, and this is subjected to exposure, development, and the like, thereby forming a resist pattern 52 having a first opening 52a and a second opening 52b. The first and second openings 52a and 52b are formed in a shape that exposes the drain regions 32b and 32c near the second end in the second transistor formation region D and the second monitor element formation region E and the drift region around them. Is done. The P wells 24a and 24b connected to the drain regions 32b and 32c serve as drift regions. The resist pattern 52 has a shape that covers other regions.

Here, the horizontal length of coverage extending from a first end of the second transistor forming region D on the first end side of the edge x3 of the first opening 52a and L _21. Further, the lateral distance between the first end side of the edge x3 and drift insulating film 2g of the first opening 52a and Lp _1. Although the values of the distances L ₂₁ and Lp ₁ in the second transistor formation region D arranged as a plurality of monitor elements are different from each other, the total value of the distance L ₂₁ and the distance Lp ₁ is made substantially equal. .

In the second opening portion 51b, the horizontal length of the first end side of the coverage leading to edge x4 of the first end from the second opening 52b of the second monitor element formation region E and L _22. Further, the lateral distance between the first end side of the edge x4 and drift insulating film 2h of the second opening 52b and Lp _2. Although each value of the distance L ₂₂ and Lp ₂ of the second monitor element formation region E which is more disposed different from each other as a monitor device, the sum of the values of the distance L ₂₁ and the distance Lp ₁ substantially equal To do.

The distances L ₂₁ , Lp ₁ , L ₂₂ , Lp ₂ described above and the distances or lengths described below are cross sections along a straight line II-II from the first end to the second end in FIG. The horizontal distance or length at Moreover, the horizontal direction demonstrated below is also a direction along the II-II line.

  Next, using the resist pattern 52 as a mask, boron (B) ions are implanted into the N wells 23a and 23b through the first and second openings 52a and 52b, and P wells 24a and 24b are formed in the regions. . The ion implantation angle is, for example, a direction perpendicular to the substrate surface. In this case, the first end edges x3 and x4 of the first and second openings 52a and 52b of the resist pattern 52 exist between the partition insulating films 2a and 2b and the drift insulating films 2c and 2d. Further, the edge x3 is formed at a position different in the lateral direction in the plurality of second transistor formation regions D, and the edge x4 is formed at a position different in the lateral direction in the plurality of second monitor element formation regions E. .

  Thus, the lateral lengths from the first end to the second end of the N wells 23a in the plurality of second transistor formation regions D are different from each other from the beginning. Similarly, the lateral length of the N well 23b is different from the beginning in the plurality of second monitor element formation regions E. The P wells 24a and 24b immediately after the ion implantation are formed in the same region as the first and second openings 52a and 52b, and the side edges of the P wells 24a and 24b are the edges of the first and second openings 52a and 52b. It substantially coincides with x3 and x4.

  The P wells 24a and 24b are formed deeper than the element isolation insulating film 2, the partition insulating films 2e and 2f, and the drift insulating films 2g and 2h, and shallower than the N wells 23a and 23b. In this case, B ions are implanted, for example, under the same conditions as the formation of the P wells 4a and 4b shown in FIG. Thereafter, the resist pattern 52 is removed, and the silicon substrate 1 is annealed at about 1000 ° C. to activate p-type impurities and n-type impurities.

According to this annealing, p-type impurity is ion-implanted so diffused around, P-well 24a, 24b are laterally protruding in an amount Lx _0. Accordingly, the lateral junctions (boundaries) between the P wells 24a and 24b and the N wells 23a and 23b project toward the partition insulating films 2e and 2f. Therefore, the distance between the junction and the drift insulating films 2g and 2h is Lp ₁ + Lx ₀ and Lp ₂ + Lx ₀ . In addition, the distance from the first end of the second transistor formation region D to the junction changes to L ₂₁ −Lx ₀ . Further, in the second monitor element formation region E, the distance between the first end and the junction changes to L ₂₂ -Lx ₀ .

When impurities are ion-implanted into the first transistor formation region A and the first monitor element formation region B, the second transistor formation region D and the second monitor element formation region are formed as shown in FIG. E is covered with a resist pattern _{R 21.}

Next, steps required until a structure shown in FIG.
First, the upper surfaces of the N wells 23a and 23b and the P wells 24a and 24b are thermally oxidized to form an insulating film on the upper surfaces, and a polysilicon film is further formed thereon by a CVD method. Thereafter, the polysilicon film is patterned by a photolithography technique and an etching technique, and third and fourth gate electrodes 6c and 6d are formed in areas passing over the second transistor formation area D and the second monitor element formation area E. Then, the insulating films under them are referred to as gate insulating films 5c and 5d.

  One end of the third gate electrode 6c is located on the N well 23a in the region between the partition insulating film 2e and the P well 24a, and the other end is located on the drift insulating film 2c. One end of the fourth gate electrode 6d is located on the edge of the second end side of the partition insulating film 2f or on the partition insulating film 2f, and the other end is located on the drift insulating film 2h. To do. Thus, junctions (boundaries) between the N wells 23a and 23b and the P wells 24a and 24b exist below the third and fourth gate electrodes 6c and 6d, respectively.

Next, steps required until a structure shown in FIG.
First, a resist pattern (not shown) that exposes the regions other than the contact regions 23c and 23d in the second transistor formation region D and the second monitor element formation region E is formed.

  Thereafter, in the second transistor formation region D, p-type impurity ions such as boron are formed in the N well 23a and the P well 24a using the resist pattern, the third gate electrode 6c, the drift insulating film 2g, and the partition insulating film 2e as a mask. Ions are implanted. Thus, a p-type extension region 27a is formed in the N well 23a on one side of the third gate electrode 6c. At the same time, a p-type extension region 27 b is formed on the other side of the third gate electrode 6 c and between the drift insulating film 2 g and the element isolation insulating film 2.

  In the second monitor element formation region E, boron ions, which are p-type impurities, are formed in the N well 23b and the P well 24b using the resist pattern, the fourth gate electrode 6d, the drift insulating film 2h, and the partition insulating film 2f as a mask. Inject. As a result, a p-type extension region 27 c is formed in a region between the drift insulating film 2 h and the element isolation insulating film 2. A p-type impurity is also ion-implanted into the third and fourth gate electrodes 6c and 6d. Thereafter, the resist pattern is removed.

  Next, in this case, a new resist pattern (not shown) that covers the region excluding the contact regions 23c and 23d is formed. N-type impurity ions such as phosphorus ions are implanted into the contact regions 23c and 23d of the N wells 23a and 23b. Thus, n-type extension regions 29a and 29b are formed in the contact regions 23c and 23d of the second transistor formation region D and the second monitor element formation region E, respectively.

  After removing the resist pattern, insulating sidewalls 31a and 31b are formed on the side surfaces of the third and fourth gate electrodes 6c and 6d. The sidewalls 31a and 31b are formed by the same method as the sidewalls 11a and 11b on the side surfaces of the first and second gate electrodes 6a and 6b.

  Thereafter, a resist pattern (not shown) that exposes the regions other than the contact regions 23c and 23d in the second transistor formation region D and the second monitor element formation region E is formed. Thereafter, the resist pattern (not shown), the third and fourth gate electrodes 6c and 6d, the partition insulating films 2e and 2f, and the drift insulating films 2g and 2h are used as masks, and the N wells 23a and 23b and the P well 24a are used. 24b, p-type impurity ions such as boron ions are implanted at a high concentration.

  Thus, p-type impurity diffusion regions 28a, 28b, and 28c having a p-type impurity concentration higher than that of the p-type extension are formed on the p-type extension regions 27a, 27b, and 27c, respectively. A p-type impurity is also ion-implanted into the third and fourth gate electrodes 6c and 6d. Thereafter, the resist pattern (not shown) is removed.

  Further, a resist pattern (not shown) is newly formed on the silicon substrate 1, and this resist pattern is used as a mask, and n-type impurity ions, for example, phosphorus ions are implanted into the contact regions 23c and 23d. Thereby, n-type impurity diffusion regions 30a and 30b having a higher n-type impurity concentration are formed on the n-type extension regions 29a and 29b. Further, after removing the resist pattern, the ion-implanted p-type impurity and n-type impurity are activated by annealing.

  Thus, the p-type extension region 27a and the p-type impurity diffusion region 28a formed on one side of the third gate electrode 6c are used as the p-type source region 32a. The p-type extension region 27b and the p-type impurity diffusion region 28b formed in the region adjacent to the drift insulating film 2g on the other side of the third gate electrode 6c are referred to as a p-type drain region 32b. Then, a p-type LDMOS transistor Tp is formed from the third gate electrode 6c, the p-type source region 32a, the p-type drain region 32b, and the like.

  The p-type extension region 27c and the p-type impurity diffusion region 28c adjacent to the drift insulating film 2h on the other side of the fourth gate electrode 6d are defined as a p-type drain region 32c. Then, a p-type monitor element M1 is formed from the fourth gate electrode 6d, the p-type drain region 32c, and the like. The p-type drain regions 32b and 32c may be used as p-type contact regions for the P wells 24a and 24b.

  Thereafter, as illustrated in FIG. 13B, on the third and fourth gate electrodes 6c and 6d, the p-type source region 32a, the p-type drain regions 32b and 32c, and the n-type contact regions 23c and 23d. Silicide layers 13h to 13n are formed. The silicide layers 13h to 13n are formed simultaneously with the silicide layers 13a to 13g formed in the n-type LDMOS transistor T and the n-type monitor element M.

  Next, as illustrated in FIG. 14, an interlayer insulating film 14 covering the n-type LDMOS transistor Tn and the n-type monitor element Mn is also formed on the p-type LDMOS transistor Tp and the p-type monitor element Mp. Further, similarly to the n-type LDMOS transistor Tn and the n-type monitor element Mn, the conductive plugs 35h to 35n are similarly connected to the p-type LDMOS transistor Tp and the p-type monitor element Mp, and the conductive plugs 35h to 35n are further connected. Wirings 36h to 36n are formed thereon.

When the P wells 24a in the plurality of p-type LDMOS transistors Tp are formed according to the semiconductor device manufacturing method as described above, the positions of the edges x3 of the openings 52a of the resist pattern 52 shown in FIG. Make a difference. A plurality of p-type LDMOS transistors Tp formed through such a process are used as monitor elements, and a test is performed by applying a voltage between each of the third gate electrode 6c and the n-type contact region 23c. In this case, the voltages Vd, Vb, and Vs of the n-type drain region 32b, the silicon substrate 1, and the n-type source region 32a are set to 0V. Thereby, the capacitance value C _{gb of the} capacitor formed by the third gate electrode 6c, the gate insulating film 5c, and the N well 23a is measured.

Under such conditions, since the P well 24a and the N well 23a have the same potential, the mutual influence due to the change in the DC voltage Vg applied to the third gate electrode 6c can be ignored. Further, the capacitance C _gb of the capacitor between the P well 24a and the gate electrode 6c via the third gate insulating film 5c is electrically connected to the third gate electrode 6c and the n-type contact region 23c via the wirings 36h and 36m. It is detected by the capacitor capacity measuring device 42 connected to the same.

Since the hole / electron carrier distribution on the surface of the silicon substrate 1 can be measured as it is in the range of voltages Vg ₁ and Vg _{2 in} the vicinity of Vg = 0 V or Vg ₂ , the capacitance C _gb is _{equal to} that of the N well 23a and the third gate electrode 6c. There is a certain correlation with the overlapping area, that is, the length of the region where the depletion layer occurs. Therefore, when the strong inversion / strong accumulation is measured at + 3V / −3V, the capacitance in the range of the channel region CH1 and the P well 24a of the N well 23a shown in FIG. 14 below the third gate electrode 6c can be detected. Further, N and the length of the channel region CH1 of the wells 23a and _{L CH1, L CH1} / Lp ₁ and Vg = 0V precisely estimable bias voltage length _{L CH1} dependent _{C gb} in the voltage conditions in the vicinity thereof Sex is shown.

When the DC voltage Vg is increased from −3 V to +3 V, the measured capacitance C _gb changes as shown in the voltage / capacitance characteristic curves d, e, f, g shown in FIG. The inflection point of appears at Vg = 0V. The four voltage / capacitance characteristic curves d, e, f, and g have different voltage / capacitance characteristics by changing the position of the edge x2 of the opening 52a of the resist pattern 52 used for forming the P well 24a. It is shown that.

Further, in the voltage-capacitance characteristic line D-G, and the reference capacitance C ₀ of the common capacitance value is saturated at a negative voltage value. Capacitance C _gb at the inflection point in the plurality of voltage / capacitance characteristic lines _{d to g} is defined as C _d , C _e , C _f , and C _g, and the voltage at the inflection point is defined as the inflection point voltage. Here, -10% of the highest inflection point capacitance _{C a,} the voltage + 10% of the capacity is obtained and _Vg 1, Vg _2. Moreover, the capacity in the range of -10% to +10% relative to the inflection point capacitance C _d is defined as an inflection point region capacity, defines the range of the voltage in this case the inflection point region voltage.

The four voltage / capacitance characteristic curves d to g in FIG. 15A indicate the opening of the resist pattern 52 from the first end of the second transistor formation region D shown in FIG. 11B in the p-type LDMOS transistor Tp. The distance L ₂₁ to the edge x3 of 52a is shown from top to bottom in the long order. Therefore, according to the characteristic curve D-G, the distance area under the N well 23a of the third gate electrode 6c as _{L 21} is shorter becomes narrow, the capacitance between the N-well 23a and the third gate electrode 6c C _gb becomes smaller.

Further, the relationship between the position of the edge x3 of the opening 52a and the inflection point capacitance values C _d , C _e , C _f , C _{g in} the plurality of second transistor formation regions D is plotted in two-dimensional coordinates, and these plots are plotted. When connected, a straight characteristic line is obtained as shown in FIG. 15B, and a relational expression of a linear function is obtained from the characteristic line. In FIG. 15B, the vertical axis indicates the capacity C _gb , and the origin is the reference capacity C ₀ . The horizontal axis indicates the edge x3 of the opening 52, that is, the position of the end of the p-type impurity introduction region when the P well 24a is formed. In this case, the first end position of the edge of the (in the drawing left) side of the depletion layer generated region CH1 of N-well 23a and the reference position L _0, which is the origin of the horizontal axis. Figures horizontal axis of FIG. 15 (b) shows the distance to the position of the edge x3 from the reference position L _0. Here, the reference position L ₀ in FIG. 14 and one end of the third gate electrode 6c.

If it is assumed that the p-type impurity to be introduced for forming the P-well 24a does not diffuse, even slightly away edge x3 openings 52 from the reference position L _0, the capacitance C _gb becomes C ₀ Sometimes. This is because, as indicated by the left-pointing arrow in FIG. 16, the p-type impurity in the P well 24a diffuses to the surroundings by annealing, so that the position of the edge z protrudes laterally. For this reason, in the characteristic line of FIG.15 (b), an intercept arises on a vertical axis | shaft and a horizontal axis. Sections on the horizontal axis, the projecting amount Lx ₀ of p-type impurity for the partition insulating layer 6e. Further, the intercept on the vertical axis, shows a decrease of the capacity minus side, not actually smaller than C _0.

Accordingly, the solid line in FIG. 15B can be obtained as a relational expression of C _gb = K · x 3 −C _α (where K = C _α / Lx ₀ ) if L ₀ = 0 and C ₀ = 0. . FIG. 16 is a cross-sectional view drawn based on a two-dimensional profile image of the hole concentration calculated by the technology CAD.

By the way, when the inflection point capacitance C _gb in the case of the voltage Vg ₁ on the minus side of the inflection point range in the characteristic lines d to g in FIG. b) Like a one-dot chain line. Further, when the inflection point capacitance C _gb in the case of the voltage Vg ₂ on the plus side of the inflection point range in the characteristic lines d to g in FIG. It becomes like the wavy line of b). In any case, the intercepts on the horizontal axis are almost the same, and it is understood that the amount of overhang is almost the same in the inflection point range. Note that the slope of the capacitance / edge position characteristic line increases as the carrier concentration of the surface layer of the N well 23a increases.

  The method for measuring the amount of protrusion of the P well 24a described above can also be applied to the measurement of the amount of protrusion of the P well 24b in the p-type monitor element Mp. That is, the relationship of the capacitance with respect to the applied voltage Vg between the fourth gate electrode 6d and the contact region 23d is measured, a characteristic line as shown in FIG. 15A is obtained, and the opening 52b of the resist pattern 51 is further obtained. The overhang amount with respect to the edge x4 can be measured by the same method as described above.

In this case, the total lateral distance of the P well 24b and the N well 23b under the fourth gate electrode 6d is the depletion layer generation region CH2 of the N well 23b between the partition insulating film 2f and the drift insulating film 2h. it is the distance of the sum of the length Lp ₂ of the length _{L CH2} and P-well 24b. The distance is not affected by the positional deviation of the fourth gate electrode 6d. Thus, the capacitance / voltage characteristic line as shown in FIG. 15A is obtained without being affected by the positional deviation of the fourth gate electrode 6d, and the capacitance C _gb and the opening shown in FIG. 15B are obtained. The positional relationship of the edge X4 of 25b can be detected with higher accuracy. The position of the edge X4 of the opening 52b substantially coincides with the side edge of the region into which the p-type impurity is introduced.

  Compared to the p-type LDMOS transistor Tp, the p-type monitor element Mp does not have the p-type source region 32a and has a structure in which the distance between the fourth gate electrode 6d and the partition insulating film 2f is zero, or a part of each other. It has a structure that overlaps. For this reason, at the time of inspection, the p-type impurity protrusion due to the annealing of the p-type source region 32a can be ignored.

As described above, according to the test using the p-type monitor element Mp, it is possible to detect the capacitance C _α and the positional shift amount Lx ₀ with higher accuracy than in the case of measuring using the p-type LDMOS transistor Tp. .

  In the above description, a voltage is applied between the contact regions 23c, 23d of the N wells 23a, 23b and the gate electrodes 6c, 6d, and the capacitor capacitance between the P wells 24a, 24b and the gate electrodes 6c, 6d is measured. Thus, the overhang amounts of the P wells 24a and 24b were obtained. In contrast, the drain regions 32b and 32c of the P wells 24a and 24b are used as contact regions, a voltage is applied between the drain regions 32b and 32c and the gate electrodes 6c and 6d, and the P wells 24a and 24b and the gate electrode 6c are applied. , 6d may be measured to determine the amount of protrusion of the P wells 24a and 24b. When the N well is formed after the P well, the overhang amount for the N well is measured.

According to the above embodiment, the edges x3 of the openings 52a and 52b of the resist pattern 52 when forming the P wells 24a and 24b in the plurality of second transistor formation regions D or the plurality of second monitor element formation regions E, The horizontal positions of x4 are different from each other. Further, a voltage / capacitance characteristic line is obtained from the relationship between the voltage applied between the contact regions 23c, 23d of the N wells 23a, 23b and the gate electrodes 6c, 6d and the capacitance measured therebetween. Further, the inflection point voltage and the inflection point capacity are obtained from the inflection point range of the voltage / capacitance characteristic line. Further, the relationship between the inflection point capacitance of each of the N wells 23a and 23b and the positions of the edges x3 and x4 of the openings 52a and 52b of the resist pattern 52 is plotted in two-dimensional coordinates to obtain a relational expression of characteristic lines. Furthermore, sections of the axis indicating the capacity of the characteristic line and changing capacitance C _alpha, and sections of the axis indicating a position of the edge x3, x4 and P-well 24a, 24b protruding amount Lx ₀ of. According to such a method, the amount of protrusion of the P wells 24a and 24b can be obtained with high accuracy without processing the completed semiconductor device, so that the inspection of the impurity diffusion region of the semiconductor device is facilitated, and the electrical It becomes easy to grasp the characteristics. Further, P-well 24a was obtained in this way, associate the overhang amount Lx ₀ of 24b impurity ion implantation amount, such as annealing temperature, it is possible to improve the characteristics of the LDMOS transistor by storing the data.

  By the way, when the n-type LDMOS transistor Tn and the p-type MOS transistor Tp are formed as monitor elements as described above, the formation of the source region may be omitted. In the test, the drain region may be used as a contact region, a voltage may be applied between the gate electrode and the drain region, and the capacitance may be measured. Note that the above-described monitoring elements may be formed on a plurality of substrates.

  Note that the p-type and the n-type have a relationship that when one is a first conductivity type, the other is a second conductivity type.

  All examples and conditional expressions given here are intended to help the reader understand the inventions and concepts that have contributed to the promotion of technology, such examples and It is interpreted without being limited to the conditions, and the organization of such examples in the specification is not related to showing the superiority or inferiority of the present invention. While embodiments of the present invention have been described in detail, it will be understood that various changes, substitutions and variations can be made thereto without departing from the spirit and scope of the invention.

Next, features of the embodiment of the present invention will be described.
(Supplementary Note 1) A plurality of first conductivity type regions formed in each of a plurality of element formation regions in a semiconductor substrate, and a region closer to the center in the horizontal direction from one end side of each of the plurality of first conductivity type regions. In each of the plurality of element formation regions, the second conductivity type region formed by introducing the second conductivity type impurity by changing the position of the side edge closer to the center, and the plurality of element formation regions, An electrode formed on the junction of the second conductivity type region and its periphery via an insulating film, and on the side of each of the electrodes in the plurality of element formation regions, the first conductivity type region, And a contact region formed in the same conductivity type in any one of the second conductivity type regions, and the first conductivity type region and the second conductivity type in each of the plurality of element formation regions. Connected to the contact region of the region The position of the edge near the one end of the depletion layer generated in the portion overlapping with the electrode is defined as the reference position in the lateral direction, and is applied between the electrode and the contact region for each of the plurality of element formation regions. Measuring the relationship between the applied voltage and the capacitance between the electrode and the contact region, obtaining a plurality of voltage / capacitance characteristic lines, and saturating at a low value in the plurality of voltage / capacitance characteristic lines. The value of the capacitance is used as a reference capacitance, one first voltage in an inflection point region of the plurality of voltage / capacitance characteristic lines is selected, and the first voltage is selected in the plurality of voltage / capacitance characteristic lines. The capacitance is a plurality of inflection point capacitance values, and the side edge position and the inflection point capacitance value are determined from the relationship between the side edge position and the inflection point capacitance value in the plurality of element formation regions from which the inflection point capacitance value is obtained. With the capacity value as a variable A relational expression is created, and in the relational expression, the protruding position of the side edge where the capacitance value becomes the reference capacity is obtained, and the distance between the protruding position and the reference position is determined as the distance of the side edge of the second conductivity type region. A method for testing a semiconductor device in which the amount of overhang is used.
(Supplementary Note 2) The inflection point region is a region that is within a range of ± 10% of the inflection point of the voltage / capacitance characteristic line with respect to the capacity, and the first voltage is the range of the voltage / capacitance characteristic line. The test method for a semiconductor device according to appendix 1, wherein the applied voltage is in a range obtained from an inflection point region.
(Supplementary note 3) The test method for a semiconductor device according to supplementary note 1 or 2, wherein the plurality of element formation regions are surrounded by a first insulating film formed on an upper portion of the semiconductor substrate.
(Supplementary note 4) The semiconductor device according to any one of supplementary notes 1 to 3, wherein the first conductivity type region is an n-type region and the second conductivity type region is a p-type region. Test method.
(Supplementary note 5) Any one of Supplementary notes 1 to 4, wherein a second insulating film is formed in a region between the contact region and the electrode above each of the plurality of element formation regions. A test method for a semiconductor device according to one of the above.
(Appendix 6) An impurity diffusion region having a conductivity type opposite to that of the contact region is formed in a region between the second insulating film and the electrode above each of the plurality of element formation regions. The test method of the semiconductor device according to appendix 5.
(Appendix 7) Whether the first conductivity type region and the second conductivity type region are formed adjacent to the electrode at the upper portion of the region to which the contact region is connected, with their edges aligned. The method for testing a semiconductor device according to any one of appendices 1 to 4, further comprising a fourth insulating film formed so as to partially overlap the electrode.
(Supplementary Note 8) A third insulating film that overlaps a side edge of the electrode is formed on the first conductive type region and the second conductive type region on a region that is not connected to the contact region. 8. The method for testing a semiconductor device according to any one of Supplementary Notes 1 to 7, wherein the semiconductor device is formed apart from a junction between the region and the second conductivity type region.
(Supplementary Note 9) A plurality of monitor elements formed in a plurality of element formation regions of a semiconductor substrate, wherein the plurality of monitor elements are formed in each of the plurality of element formation regions in the semiconductor substrate. The second conductivity type impurity is introduced by changing the position of the side edge near the center between the first conductivity type region and the region near the center in the lateral direction from one end side of each of the plurality of first conductivity type regions. In each of the second conductivity type region thus formed and the plurality of element formation regions, an insulating film is formed on a part of the first conductivity type region and the second conductivity type region. An electrode, a contact region formed in the same conductivity type in either the first conductivity type region or the second conductivity type region at a side of the electrode in the plurality of element formation regions, and the first conductivity type The contour of the region and the second conductivity type region And an insulating film formed on the upper portion of the semiconductor substrate, with one edge being adjacent to the electrode and having the edges aligned with each other. A semiconductor device comprising:
(Supplementary note 10) The semiconductor device according to supplementary note 9, wherein the monitor element is surrounded by a first insulating film formed on an upper portion of the semiconductor substrate.
(Supplementary note 11) The semiconductor device according to supplementary note 9 or 10, wherein the first conductivity type region is an n-type region and the second conductivity type region is a p-type region.
(Supplementary note 12) Any one of Supplementary notes 9 to 11, wherein a second insulating film is formed in a region between the contact region and the electrode above each of the plurality of element formation regions. The semiconductor device according to one.
(Supplementary Note 13) A third insulating film that overlaps a side end of the electrode is formed on the upper portion of the first conductivity type region and the second conductivity type region, which are away from the contact region, with the first conductivity type region. 13. The semiconductor device according to any one of appendices 9 to 12, wherein the semiconductor device is formed apart from a joint portion of the second conductivity type region.

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Element isolation insulating film 2a, 2b, 2e, 2f Partition insulating film 2c, 2d, 2g, 2h Drift insulating film 3a, 3b N well 4a, 4b P well 4c, 4d Contact region 5a, 5b, 5c, 5d Gate insulating film 6a, 6b, 6c, 6d Gate electrode 11a, 11b Side wall 12a Source region 12b, 12c Drain region 23a, 23b N well 23c, 23d Contact region 24a, 24b P well 31a, 32b Side wall 32a Source region 32b, 32c Drain region 41 Power supply 42 Capacity measuring device

Claims (5)

A plurality of first conductivity type regions formed in each of the plurality of element formation regions in the semiconductor substrate; and a region closer to the center in the lateral direction from one end side of each of the plurality of first conductivity type regions. In each of the plurality of element formation regions and the second conductivity type region formed by introducing the second conductivity type impurities at different positions of the side edges of the first conductivity type region and the second conductivity type An electrode formed on the bonding portion of the mold region and its periphery via an insulating film, and the first conductivity type region and the second conductivity type on a side of each of the plurality of element formation regions. A semiconductor device having a contact region formed in the same conductivity type in any of the regions,
In each of the plurality of element formation regions, a depletion layer generated near a portion of the first conductivity type region and the second conductivity type region that is connected to the contact region and overlaps with the electrode. The edge position is defined as the lateral reference position,
For each of the plurality of element formation regions, a relationship between an applied voltage applied between the electrode and the contact region and the capacitance between the electrode and the contact region is measured, and a plurality of voltage / capacitance characteristic lines are measured. Seeking
The common capacitance value saturated at a low value in the plurality of voltage / capacitance characteristic lines is used as a reference capacitance,
Selecting one first voltage in an inflection point region of the plurality of voltage-capacitance characteristic lines;
In the plurality of voltage-capacitance characteristic lines, the capacitance at the first voltage is a plurality of inflection point capacitance values,
Create a relational expression using the position of the side edge and the capacitance value as a variable from the relationship between the position of the side edge and the inflection point capacitance value in the plurality of element formation regions where the inflection point capacitance value is obtained,
In the relational expression, the protruding position of the side edge where the capacitance value becomes the reference capacity is obtained, and the distance between the protruding position and the reference position is the amount of protrusion of the side edge of the second conductivity type region.
Semiconductor device testing method.   The inflection point region is a region that is in a range of ± 10% of the inflection point of the voltage / capacitance characteristic line with respect to the capacitance, and the first voltage is the inflection point region of the voltage / capacitance characteristic line. The test method for a semiconductor device according to claim 1, wherein the applied voltage is in a range obtained from:   The impurity diffusion region having a conductivity type opposite to that of the contact region is formed in a region between the contact region and the electrode above each of the plurality of element formation regions. A test method for a semiconductor device according to claim 3.   The first conductivity type region and the second conductivity type region may be formed adjacent to the electrode with their edges aligned with each other at the upper portion of the region to which the contact region is connected. 5. The semiconductor device testing method according to claim 2, further comprising a fourth insulating film that is partially overlapped. 6. Having a plurality of monitor elements formed in a plurality of element formation regions of a semiconductor substrate;
The plurality of monitor elements are:
A plurality of first conductivity type regions formed in each of the plurality of element formation regions in the semiconductor substrate;
A second conductivity type region is formed by introducing a second conductivity type impurity in a region closer to the center in the lateral direction from one end side of each of the plurality of first conductivity type regions with the position of the side edge closer to the center being different. A conductive type region;
In each of the plurality of element formation regions, an electrode formed through an insulating film on a part of the first conductivity type region and the second conductivity type region;
A contact region formed in the same conductivity type in either the first conductivity type region or the second conductivity type region on a side of the electrode in the plurality of element formation regions;
One region of the first conductivity type region and the second conductivity type region to which the contact region is connected, and is formed adjacent to the electrode so that their edges coincide with each other. An insulating film formed on top of the semiconductor substrate with overlapping portions;
A semiconductor device comprising:

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