JP2015073760A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine capable of achieving a stable serial transmission without complicating a circuit configuration.SOLUTION: The game machine executes lottery processing on the basis of a prescribed switch signal and executes a game operation corresponding to the lottery result. The game machine comprises an upstream-side control part 21 that transmits a control command CMD for identifying the lottery result, and a downstream-side control part 22 for receiving the control command, where the control command CMD is transmitted as a form of an LVDS signal.

Description

  The present invention relates to a gaming machine that generates a big hit state by a lottery process resulting from a gaming operation, and more particularly to a gaming machine that can realize complicated and advanced performance control with a simple device configuration.

  A ball game machine such as a pachinko machine has a symbol start opening provided on the game board, a symbol display section for displaying a series of symbol variation patterns by a plurality of display symbols, and a big winning opening for opening and closing the opening and closing plate. Configured. When the detection switch provided at the symbol start port detects the passage of the game ball, the winning state is entered, and after the game ball is paid out as a prize ball, the display symbol is changed for a predetermined time in the symbol display section. Thereafter, when the symbol is stopped in a predetermined manner such as 7, 7, 7, etc., a big hit state is established, and the big winning opening is repeatedly opened to generate a gaming state advantageous to the player.

  Whether or not to generate such a game state is determined by a jackpot lottery executed on the condition that a game ball has won at the symbol start opening, and the above symbol variation operation is based on this lottery result. It has become a thing. For example, when the lottery result is in a winning state, an effect operation called reach action or the like is executed for about 20 seconds, and then the special symbols are aligned. On the other hand, a similar reach action may be executed even in the case of a lost state. In this case, the player pays close attention to the big hit state and pays close attention to the transition of the performance operation. When the predetermined symbols are aligned on the stop line at the end of the symbol variation operation, the player is guaranteed to be in the big hit state.

JP 2007-222690 A

  The above-mentioned performance operation is centered on the image production on the liquid crystal display device. In conjunction with this image production, a lamp production that blinks various lamps, an audio production that outputs a sound that excites the player, Movable effects such as moving animals are executed.

  In general, this type of gaming machine is divided into a main control board that centrally controls gaming operations and an effect control board that controls effect operations based on control commands received from the main control board. In addition, the effect control board may be divided into a plurality of parts, and in such a device configuration, there is an effect control board that receives a control command from the main control board or the upstream effect control board.

  In any case, this type of gaming machine requires a transmission path for control commands corresponding to the number of control boards, and the total transmission distance for routing the wiring becomes long. There is a problem that the design becomes complicated.

  Therefore, it is conceivable to serially transmit the control command (Patent Document 1). However, as the presentation control becomes more sophisticated, the bit length and command type of the control command increase, and the transmission frequency and per unit time correspond to this. Therefore, the generation of noise from the transmission path becomes a problem in simple serial transmission.

  In addition, noise is superimposed on the serial transmission path and the possibility that the control command will be garbled increases, and if an unreasonable presentation is executed, the player will be whitened. Although the circuit configuration can be complicated to cope with such a problem, this increases the manufacturing cost unnecessarily.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a gaming machine capable of realizing stable serial transmission without complicating the circuit configuration.

  In order to achieve the above object, the present invention is a gaming machine that executes a lottery process based on a predetermined switch signal and executes a gaming operation corresponding to a lottery result, and provides a control command for specifying the lottery result. An upstream control means for transmitting and a downstream control means for receiving the control command are configured, and the control command is configured to be transmitted in the form of an LVDS signal. The upstream control means is not limited to the main control unit in the embodiment, and includes an upstream production control unit that transmits a control command to the downstream production control unit.

  Since the present invention uses low voltage differential signaling, command transmission with small amplitude and low power consumption is realized, and necessary data is transmitted by differential signals, so that noise is generated even when high-speed transmission is performed. It doesn't matter. In addition, when transmitting the transmission clock CLK that specifies the break position of each bit of the control command CMD that is serial data in correspondence with the control command CMD, the transmission clock CLK is also preferably transmitted in the LVDS format.

  The circuit configuration in this case is the same as that in FIG. 6, for example, and two sets of serial transmission paths composed of the differential line driver Dri and the differential line receiver Rec are provided, while the control command CMD is transmitted. On the other hand, the transmission clock CLK is transmitted.

  In this case, the serial port Si of the upstream side control means outputs the control command CMD and the transmission clock CLK in synchronization (see FIG. 6), and the serial port (not shown) of the downstream side control means that receives this outputs the transmission. It is preferable to acquire each bit of serial data (control command) in order in synchronization with the clock CLK, and to convert it in parallel.

  For example, transmission is performed by embedding the transmission clock CLK in the control command CMD (see FIG. 13) or adding a start bit for specifying the transfer start timing of serial data (control command) (see FIG. 14). A transmission path for transmitting the clock CLK may be omitted.

  Regardless of which method is used, for example, the control command such as the strobe signal STB in FIG. 14 or 16A, the chip select signal CSi in FIG. 15, or the ready signal RDY in FIG. Corresponding to the transmission, it is preferable to transmit a notification signal for notifying the transmission of the LVDS signal from the upstream control means to the downstream control means.

  The notification signal is a signal for causing the control unit on the downstream side to start the reception operation, and the chip select signal CSi in FIG. 15 is sufficient. However, when the control command is transmitted with the configuration of FIG. 15, the serial transmission element 70R has a completion flag RDYF / F similar to the serial transmission element 71R (see FIG. 16C) or a circuit equivalent thereto. It is preferable to incorporate it.

  In any case, in the present invention, it is preferable that the serial transmission element for converting the parallel data control command into the LVDS signal format and outputting it is arranged in the upstream control means. When such a configuration is adopted, unlike the circuit configuration of FIG. 6, the upstream computer circuit only needs to output the control command as parallel data, and the circuit configuration of the computer circuit is not complicated.

  In the present invention, it is preferable that the serial transmission element that receives the LVDS signal, converts it into a parallel data control command and outputs it is arranged in the downstream control means. In this case, the downstream computer circuit can receive the control command as parallel data, and the circuit configuration is not complicated.

  Preferably, the control command has a length of a plurality of bytes, and is supplied to the serial transmission element of the upstream control unit for each byte, and is acquired from the serial transmission element of the downstream control unit for each byte, or It is preferable that the control command having a byte length is supplied to the serial transmission element of the upstream control unit in one process and acquired from the serial transmission element of the downstream control unit in one process.

  As described above, according to the gaming machine of the present invention, it is possible to realize a gaming machine that can realize stable serial transmission without complicating the circuit configuration.

It is a perspective view of the pachinko machine shown in an example. It is the front view which illustrated the game board of the pachinko machine of FIG. It is a block diagram which shows the whole structure of the pachinko machine of FIG. It is a block diagram illustrating a circuit configuration of an effect control unit. It is a block diagram which shows the internal structure of three lamp drive boards. It is drawing explaining with the connection relation of a production control board and a lamp drive board, an internal configuration of a serial port, etc. It is a time chart which shows the serial signal transmitted to a lamp drive board | substrate. It is a flowchart explaining operation | movement of an effect control part. It is a flowchart which shows a part of FIG. 8 in detail. It is a circuit diagram which shows the input part of a LED driver. It is a flowchart which shows the modification of FIG. It is a flowchart which shows another modification of FIG. It is a figure explaining LVDS transmission of a clock embedding system. It is a figure explaining LVDS transmission which adds a start bit. It is a circuit diagram which implement | achieves lamp control using a serial transmission element. It is a circuit diagram in the case of transmitting a control command and a switch signal using another serial transmission element.

  Hereinafter, the present invention will be described in detail based on examples. FIG. 1 is a perspective view showing a pachinko machine GM of the present embodiment. This pachinko machine GM includes a rectangular frame-shaped wooden outer frame 1 that is detachably mounted on an island structure, and a front frame 3 that is pivotably mounted via a hinge 2 fixed to the outer frame 1. It is configured. A game board 5 is detachably attached to the front frame 3 from the front side, not from the back side, and a glass door 6 and a front plate 7 are pivotally attached to the front side so as to be openable and closable.

  On the outer periphery of the glass door 6, an electric lamp such as an LED lamp is arranged in a substantially C shape. On the other hand, at the upper left and right positions and the lower side of the glass door 6, all three speakers are arranged. The two speakers arranged in the upper part are each configured to output sound of the left and right channels R and L, and the lower speaker is configured to output heavy bass.

  The front plate 7 is provided with an upper plate 8 for storing game balls for launching, and a lower plate 9 for storing game balls overflowing or extracted from the upper plate 8 and a launch handle at the lower part of the front frame 3. 10 are provided. The launch handle 10 is interlocked with the launch motor, and a game ball is launched by a striking rod that operates according to the rotation angle of the launch handle 10.

  A chance button 11 is provided on the outer peripheral surface of the upper plate 8. The chance button 11 is provided at a position where it can be operated with the left hand of the player, and the player can operate the chance button 11 without releasing the right hand from the firing handle 10. The chance button 11 does not function normally, but when the game state becomes the button chance state, the built-in lamp is turned on and can be operated. The button chance state is a game state provided as necessary.

  On the right side of the upper plate 8, an operation panel 12 for ball lending operation with respect to the card-type ball lending machine is provided, a frequency display unit for displaying the remaining amount of the card with a three-digit number, and a ball of game balls for a predetermined amount A ball lending switch for instructing lending and a return switch for instructing to return the card at the end of the game are provided.

  As shown in FIG. 2, a guide rail 13 made of a metal outer rail and an inner rail is provided on the surface of the game board 5 in an annular shape, and a central opening HO is provided at the approximate center thereof. A display device DS composed of a large liquid crystal color display (LCD) is disposed in the central opening HO.

  The display device DS is a device that variably displays a specific symbol related to the big hit state and displays a background image and various characters in an animated manner. This display device DS has special symbol display portions Da to Dc in the center portion and a normal symbol display portion 19 in the upper right portion. In the special symbol display portions Da to Dc, there is a case where a reach effect that expects a big hit state is invited, and in the special symbol display portions Da to Dc and the surroundings, an appropriate notice effect is executed.

  In the game area where the game ball falls and moves, a symbol start port 15, a big winning port 16, a normal winning port 17, and a gate 18 are arranged. Each of these winning openings 15 to 18 has a detection switch inside, and can detect the passage of a game ball.

  The symbol start port 15 is configured to be opened and closed by an electric tulip having a pair of left and right opening and closing claws 15a, and when the stop symbol after fluctuation of the normal symbol display unit 17 displays a winning symbol, a predetermined time is displayed. The opening / closing claw 15a is opened only until a predetermined number of game balls are detected.

  The normal symbol display unit 19 displays a normal symbol. When a game ball that has passed through the gate 18 is detected, the normal symbol fluctuates for a predetermined time and is extracted when the game ball passes through the gate 18. The stop symbol determined by the selected lottery random value is displayed and stopped.

  The special winning opening 16 includes an opening / closing plate 16a that advances and retreats in the front-rear direction. The operation of the special winning opening 16 is not particularly limited, but in a typical big hit state, a predetermined time elapses after the opening / closing plate 16a of the special winning opening 16 is opened, or a predetermined number (for example, ten) of games. When the ball wins, the opening / closing plate 16a is closed. Such an operation is continued up to 15 times, for example, and is controlled in a state advantageous to the player. In addition, when the stop symbol after the change of the special symbol display parts Da to Dc is a specific symbol among the special symbols, there is a privilege that the game after the end of the special game becomes a high probability state (probability variation state). Is granted.

  FIG. 3 is a block diagram showing an overall circuit configuration of the pachinko machine GM that realizes the above-described operations. As shown in the figure, this pachinko machine GM mainly receives a 24V AC and outputs various DC voltages, power supply abnormality signals ABN1, ABN2, a system reset signal (power reset signal) SYS, and the like, and a game control operation. Based on the main control board 21 that performs overall control, the effect control board 22 that executes the lamp effect and the sound effect based on the control command CMD received from the main control board 21, and the control command CMD ′ received from the effect control board 22 The image control board 23 for driving the display device DS, the payout control board 24 for controlling the payout motor M based on the control command CMD "received from the main control board 21, and paying out the game balls. It is mainly composed of a launch control board 25 that responds and launches a game ball.

  However, in this embodiment, the control command CMD output from the main control board 21 is transmitted to the effect control board 22 via the command relay board 26 and the effect interface board 27. The control command CMD ′ output from the effect control board 22 is transmitted to the image control board 23 via the effect interface board 27 and the image interface board 28, and is output from the main control board 21. Is transmitted to the payout control board 24 via the main board relay board 32. Although the control commands CMD, CMD ′, and CMD ″ are all 16 bits long, the main control board 21 and the payout control board 24 are used. The control commands related to are transmitted in parallel every two 8 bit lengths. On the other hand, the control command CMD 'transmitted from the effect control board 22 to the image control board 23 is 16 bits in length and transmitted in parallel. Therefore, even when the notification effects including the movable notification effect are diversified and a large number of control commands are continuously transmitted and received, the processing can be completed quickly, and other control operations are not hindered.

  By the way, in the present embodiment, the production interface board 27 and the production control board 22 are directly connected to each other by a male connector and a female connector without passing through a wiring cable, and two circuit boards are laminated. . Similarly, with respect to the image interface board 28 and the image control board 23, two circuit boards are laminated by directly connecting a male connector and a female connector without going through a wiring cable. Therefore, even if the circuit configuration of each electronic circuit is complicated and sophisticated, the storage space of the entire board can be minimized, and noise resistance can be improved by minimizing the connection lines.

  The main control board 21, the effect control board 22, the image control board 23, and the payout control board 24 are each equipped with a computer circuit including a one-chip microcomputer. Therefore, in this specification, the control board 21 to 24, the circuits mounted on the interface boards 27 to 28, and the operations realized by the circuits are generically named. May be referred to as a section 22 ′, an image control section 23 ′, and a payout control section 24. That is, in this embodiment, the effect control board 22 and the effect interface board 27 constitute an effect control part 22 ′, and the image control board 23 and the image interface board 28 constitute an image control part 23 ′. . Note that all or part of the effect control unit 22 ′, the image control unit 23 ′, and the payout control unit 24 are sub-control units.

  The pachinko machine GM is roughly divided into a frame side member GM1 surrounded by a broken line in FIG. 3 and a board side member GM2 fixed to the back of the game board 5. The frame side member GM1 includes a front frame 3 on which a glass door 6 and a front plate 7 are pivotally attached, and a wooden outer frame 1 on the outside thereof. Is fixedly installed. On the other hand, the board side member GM2 is replaced in response to the model change, and a new board side member GM2 is attached to the frame side member GM1 instead of the original board side member. All except the frame side member GM1 is the panel side member GM2.

  As shown in the broken line frame in FIG. 3, the frame side member GM1 includes a power supply board 20, a payout control board 24, a launch control board 25, a frame relay board 35, and a lamp drive board 36. These circuit boards are respectively fixed at appropriate positions of the front frame 3.

  A plurality of LEDs are connected to the lamp driving board 36, and the driving data SDATA for driving these LED groups is a clock signal CK, an operation permission signal ENABLE, and a lighting clear signal as serial signals of the clock synchronization method. Along with the CLR, the signal is transmitted to the plurality of drivers DRij mounted on the lamp driving board 36 via the effect control board 22 → the effect interface board 27 → the frame relay board 34 → the frame relay board 35.

  The driver DRij (driver IC) of the embodiment is an LED driver (for example, LV5236V) capable of driving up to 24 LED groups such as LEDs and illumination lamps. In this embodiment, the LED of the lamp driving board 36 is used. For convenience, the LEDs driven by the driver DRij are referred to as a 0th channel (CH0) LED group.

  The driver DRij of the embodiment can drive a motor group such as a stepping motor by cooperating with an appropriate motor driver. For example, the driver DRij is a stepping motor driven by four-phase driving pulses Φ1 to Φ4. If so, six motors can be driven by one driver DRij.

  In any case, the driver DRij of this embodiment receives the serial input terminal SDATA that receives the serial signal SDATA, the clock terminal SCLK that receives the clock signal CK, the enable terminal SDEN that receives the operation enable signal ENABLE, and the lighting clear signal CLR. It has a reset terminal RST for receiving it (see FIG. 5).

  By the way, on the back of the game board 5, the main control board 21, the effect control board 22, and the image control board 23 are fixed together with the display device DS and other circuit boards. And the frame side member GM1 and the board | substrate side member GM2 are electrically connected by the connection connectors C1-C4 concentratedly arranged in one place.

  The power supply board 20 is connected to the main board relay board 32 through the connection connector C2, and is connected to the power supply relay board 33 through the connection connector C3. The power supply board 20 is provided with a power supply monitoring unit MNT that monitors whether AC power is turned on or off. When power supply monitoring unit MNT detects that AC power is turned on, it maintains system reset signal SYS at L level for a predetermined time, and then transitions it to H level.

  Further, when power supply monitoring unit MNT detects the interruption of the AC power supply, power supply abnormality signals ABN1 and ABN2 are immediately shifted to the L level. The power supply abnormality signals ABN1 and ABN2 quickly become H level after the power is turned on.

  Incidentally, the system reset signal of this embodiment is generated by a DC power supply based on an AC power supply. For this reason, after detecting the turning-on of the AC power supply (usually turning on the power switch) and increasing it to the H level, the H level is maintained unless the DC power supply voltage drops to an abnormal level. Therefore, even if the AC power supply is in an instantaneous power interruption state while the DC power supply voltage is maintained, the system reset signal SYS does not reset the CPU. The power supply abnormality signals ABN1 and ABN2 are also output even when the AC power supply is instantaneously stopped.

  The main board relay board 32 outputs the power abnormality signal ABN1, the backup power supply BAK, and DC5V, DC12V, and DC32V output from the power board 20 to the main control unit 21 as they are. On the other hand, the power relay board 33 outputs the system reset signal SYS received from the power board 20 and the AC and DC power supply voltages to the effect interface board 27 as they are. The effect interface board 27 outputs the received system reset signal SYS to the effect control unit 22 'and the image control unit 23' as it is.

  On the other hand, the payout control board 24 is directly connected to the power supply board 20 without going through the relay board, and directly receives the same power abnormality signal ABN2 and backup power supply BAK as the main control unit 21 receives together with other power supply voltages. Is receiving.

  The system reset signal SYS output from the power supply board 20 is a power supply reset signal indicating that the AC power supply 24V has been applied to the power supply board 20, and one of the effect control unit 22 ′ and the image control unit 23 ′ is generated by the power supply reset signal. The chip microcomputer is reset together with other IC elements. The lighting clear signal CLR is a reset signal output from the effect control unit 22 'when necessary to reset the internal register of the driver DRij to an initial state, and is not directly related to the system reset signal SYS.

  Further, the system reset signal SYS is not supplied to the main control unit 21 and the payout control unit 24, and a power reset signal (CPU reset signal) is generated in the reset circuit RST of each of the circuit boards 21 and 24. ing. Therefore, for example, even if the connection connector C2 is rattled or noise is superimposed on the wiring cable, there is no possibility that the CPU of the main control unit 21 or the payout control unit 24 is abnormally reset. The production control unit 22 ′ and the image control unit 23 ′ execute production operations dependently on the basis of a control command from the main control unit 21, and therefore, in order to avoid complication of the circuit configuration, A system reset signal SYS output from the substrate 20 is used.

  By the way, the reset circuits RST provided in the main control unit 21 and the payout control unit 24 each have a built-in watchdog timer, and unless a regular clear pulse is received from the CPUs of the control units 21 and 24, Each CPU is forcibly reset.

  In this embodiment, the RAM clear signal CRAM is generated by the main control unit 21 and transmitted to the one-chip microcomputer of the main control unit 21 and the payout control unit 24. Here, the RAM clear signal CRAM is a signal for deciding whether or not to initialize all the areas of the built-in RAM of the one-chip microcomputer of each of the control units 21 and 24. The RAM clear signal CRAM is ON of the initialization switch SW operated by the staff. It has a value corresponding to the / OFF state.

  The main control unit 21 and the payout control unit 24 receive the power supply abnormality signals ABN1 and ABN2 from the power supply board 20 to start necessary end processing prior to a power failure or business end. The backup power supply BAK is a DC5V DC power source that retains data in the RAM of the one-chip microcomputer of the main control unit 21 and the payout control unit 24 even after the AC power supply 24V is shut off due to business termination or power failure. Therefore, the main control unit 21 and the payout control unit 24 can resume the game operation before power-off after power-on (power backup function). This pachinko machine is designed to retain the stored contents of the RAM of each one-chip microcomputer for at least several days.

  As shown in FIG. 3, the main control unit 21 transmits a control command CMD ″ to the payout control unit 24 via the main board relay board 32, while the payout control unit 24 indicates a game ball payout operation. A prize ball counting signal, a status signal CON relating to an abnormality in the payout operation, and an operation start signal BGN are received, and the status signal CON includes, for example, a replenishment signal, a payout shortage error signal, and a lower plate full signal. The operation start signal BGN is a signal for notifying the main control unit 21 that the initial operation of the payout control unit 24 has been completed after the power is turned on.

  The main control unit 21 is connected to each game component of the game board 5 directly or via the game board relay board 31. And while receiving the switch signal of the detection switch built in each winning opening 16-18 on a game board, solenoids, such as an electric tulip, are driven. The solenoids and the detection switch are configured to operate with the power supply voltage VB (12 V) distributed from the main control unit 21. Each switch signal indicating a winning state to the symbol start opening 15 is converted to a TTL level or CMOS level switch signal by an interface IC that operates with the power supply voltage VB (12 V) and the power supply voltage Vcc (5 V). And then transmitted to the main control unit 21.

  As described above, the effect control board 22 and the effect interface board 27 are integrated by connector connection, and the effect control unit 22 ′ is connected to each level from the power supply board 20 via the power relay board 33. A DC voltage (5V, 12V, 32V) and a system reset signal SYS are received (see FIGS. 3 and 4). The effect control unit 22 'receives the control command CMD and the strobe signal STB from the main control unit 21 via the command relay board 26 (see FIGS. 3 and 4).

  Then, the effect control unit 22 ′ permits the operation of lamp drive data SDATA (serial signal) to the driver DRij mounted on the lamp drive substrate 29 and the lamp drive substrate 30 via the effect interface board 27. It is supplied together with the signal ENABLE, the clock signal CK, and the lighting clear signal CLR. Although not particularly limited, the driver DRij mounted on the lamp driving boards 29 and 30 has the same configuration as the driver DRij mounted on the lamp driving board 36, and each of the lamp driving boards 29 and 30 includes Five drivers DRij are arranged.

  In such a configuration, each driver DRij can drive up to 24 lamps by receiving a serial signal (lamp drive data SDATA) in synchronization with the clock signal CK. Therefore, in the following description, a total of 24 × 5 lamps connected to the lamp driving substrate 29 will be referred to as a lamp group of the first channel CH1, and a total of 24 × 5 lamps connected to the lamp driving substrate 30 will be referred to. , Referred to as a lamp group of the second channel CH2.

  As described above, in this embodiment, a large number (3 × 24 × 5) of lamps are divided into three groups of lamps of channel CH0 to channel CH2, respectively, and the lamp driving board 36, the lamp driving board 29, and the lamp driving, respectively. It is connected to the substrate 30 (see FIG. 5). The three types of serial signals SDATA0 to SDATA2 of the channels CH0 to CH2 are transmitted in synchronization with the clock signals CK0 to CK2.

  Corresponding to this configuration, the operation enable signals ENABLE0 to ENABLE2 function as selection signals for activating a group of drivers DRij belonging to the channels CH0 to CH2. Further, the lighting clear signal CLR is used for simultaneously resetting all the drivers DRij to the initial state when necessary, such as at the start of the effect control operation.

  Then, the driver DRij belonging to the specific channel CHi receives only the corresponding part of the series of serial signals SDATAi output from the one-chip microcomputer 40 of the effect control unit 22 ′ in synchronization with the clock signal CKi, and receives the operation permission signal. The lamp group in charge is driven in synchronization with ENABLEi.

  FIG. 5 shows the circuit configuration of the lamp driving substrates 36, 29, and 30 in a confirmed manner. As shown in the figure, on the lamp driving board 36, five drivers DR00, DR01... DR04 are mounted to drive the LED group of the 0th channel (5 × 24 LEDs in total). Similarly, five drivers DR10, DR11... DR14 are mounted on the lamp driving board 29, and five drivers DR18, DR19... DR1C are mounted on the lamp driving board 30. Each of the LED groups of the first channel and the second channel (a total of 5 × 24 LEDs) is driven to light.

  Each driver DRij is provided with a 5-bit numbering terminal. By adopting a circuit configuration in which fixed digital data is supplied to this numbering terminal, each slave address SLV (port address) is serially provided. It is numbered. That is, in the case of the illustrated example, the slave address SLV of each driver (DR00, DR01... DR04, DR10, DR11... DR14, DR18, DR19... DR1C) is 00H, 01H in hexadecimal notation. ... 04H, 10H, 11H ... 14H, 18H, 19H ... 1CH.

  As described above, in this embodiment, a series of slave addresses SLV are assigned to the drivers DRij of the lamp control boards 36, 29, and 30, thereby speeding up the setting processing of luminance data and the like for each driver DRij. . However, the series of slave addresses SLV need not necessarily be arranged in a +1 relationship, and may be in a + N or -N relationship.

  In any case, each of the drivers DRij includes 24 gradation registers GR0 to GR23 that can respectively define analog levels of lighting drive signals for driving 24 LEDs. The driver DRij is provided with a large number of setting registers in addition to the gradation register GRn, but in this embodiment, only the gradation register GRn is used for the sake of explanation.

  Each of the gradation registers GRn can store 8-bit long luminance data, and the luminance level of the LED can be set in 256 steps from 00H to FFH. In other words, according to the driver DRij used in the embodiment, the brightness level of each LED is controlled to 256 gradations (PWM = Duty ratio = 0 to 255/256 = 0 to 99.6%). However, in this embodiment, the luminance level is suppressed to 16 gradations in consideration of human visual sensitivity, and the luminance data (00H to 0FH) of 4 bits and 16 gradations is multiplied by 16 to obtain 00H to F0H. Brightness data. The luminance data 00H means extinguishing (Duty ratio = 0%), and F0H means lighting with maximum luminance.

  The set values (luminance data LUi) for the 24 gradation registers GR0 to GR23, together with the slave address SLV (port address) that identifies the driver DRij, together with the register number REi that identifies the gradation register GRi. Is transmitted. Here, the luminance data LUi and the register number REi have a one-to-one correspondence. However, as in the present embodiment, the register numbers REi of the gradation registers GRi to which the luminance data LUi is to be set are in ascending order. In the case of being consecutive, after specifying the first minimum register number RE0, it is possible to omit specification of a series of register numbers that follow.

  Therefore, the drive data SDATA of this embodiment is a set of the slave address SLV, the head register number RE0, and the 24 luminance data LU0 to LU24, and a predetermined driver DRij is formed by this group of sets of serial data SDATA. Setting data for is defined. This point will be described again with reference to FIG.

  Although the driver DRij has been described above, as described above, the stepping motor can be driven using the same driver DRij. For example, as shown by the broken line in FIG. It is also preferable to drive the production motor groups M1 to Mn. In this case, the motor drive data is a serial signal to which the slave address SLV and register number REi similar to the lamp drive data are added, and the number of wiring cables increases even if the number of effect motors is increased to enrich the effect contents. The equipment configuration is simplified.

  As shown in FIGS. 3 and 4, the effect control unit 22 ′ has two types of control commands CMD ′ and strobe signal STB ′, and a system reset signal SYS received from the power supply board 20, with respect to the image control unit 23 ′. DC voltage (12V, 5V).

  Then, the image controller 23 'drives the display device DS based on the control command CMD' to execute various image effects. The display device DS emits light by an LED backlight, and is driven by receiving five pairs of LVDS (Low voltage differential signaling) signals and a backlight power supply voltage (12 V) from the image interface board 28. (See FIG. 4).

  Next, the configuration of the effect control unit 22 'described above will be described in more detail. As shown in FIG. 4, the production interface board 27 receives three types of DC voltages (5V, 12V, and 32V) from the power supply board 20 via the power supply relay board 33. Here, the DC voltage 5V is distributed as power supply voltage of the digital logic circuit to the rendering interface board 27, the lamp driving board 29, the lamp driving board 30, the image interface board 28, and the image control board 23, and is supplied to each digital circuit. Is operating.

  However, the direct current voltage 5V is not distributed on the effect control board 22, and the direct current voltage 3.3V stepped down from 12V by the DC / DC converter and the direct current stepped down from 3.3V by the DC / DC converter. Only the voltage 1.8V is distributed from the production interface board 27 to the production control board 22.

  As described above, the production control board 22 of the present embodiment is driven by the power supply voltage of 3.3V or lower because all the circuits are driven. The power can be reduced, and even if the effect interface board 27 is arranged and stacked immediately above the effect control board 22, no heat dissipation problem occurs.

  However, the DC voltage 12V received from the power supply board 20 is used as it is as the power supply voltage of the digital amplifier 46 and is distributed to the lamp drive board 30 and the lamp drive board 29 to become the power supply voltage of each lamp group. The direct current voltage 32V is stepped down to the direct current voltage 13V in the DC / DC converter of the production interface board and used as a drive power source for the production motors M1 to Mn as necessary.

  As shown in FIG. 4, the effect control unit 22 ′ includes a one-chip microcomputer 40 that executes processing such as a sound effect, a lamp effect, a notice effect by the effect movable body, and data transfer, and a control program for the one-chip microcomputer 40. A flash memory 41 to be stored, a voice synthesis circuit 42 that reproduces and outputs a voice signal based on an instruction from the one-chip microcomputer 40, and compressed voice data that is original data of the reproduced voice signal are stored. And an audio memory 43 that is configured.

  The one-chip microcomputer 40, the flash memory 41, and the voice memory 43 operate at a power supply voltage 3.3V, and the voice synthesis circuit 42 operates at a power supply voltage 3.3V and a power supply voltage 1.8V. As a result, significant power savings have been achieved. Here, 1.8V is the power supply voltage of the computer core part of the speech synthesis circuit, and 3.3V is the power supply voltage of the I / O part.

  The one-chip microcomputer 40 includes a plurality of parallel input / output ports PIO (Pi + Po + Po ′) and a plurality of serial output ports SI. Here, more specifically, the serial output port SI includes three-channel serial ports SI (S0 to S2) (see FIG. 6) and is mounted on the lamp driving boards 36, 29, and 30. Lamp drive data SDATA0 to SDATA2 are output to each of the five drivers DRij in synchronization with the clock signals CK0 to CK2.

  As described above, the lamp driving data SDATA0 to SDATA2 are mainly luminance data for adjusting the luminance of each LED by PWM control (pulse width modulation), and the driver DRij is specified prior to the luminance data. A slave address SLV to be registered and a register number RE0 for specifying the head address of the gradation register GRi are added.

  The lamp driving boards 36, 29, 30 are also connected to the parallel output port Po ′ of the parallel input / output port PIO. The driver DRij mounted on each of the lamp driving boards 36, 29, 30 is a parallel output port. The reset state is simultaneously performed based on the lighting clear signal CLR output by Po ′, and thereafter, the operation is started based on any of the 3-bit operation enable signals ENABLE0 to ENABLE2.

  On the other hand, the control command CMD and the strobe signal STB from the main control unit 21 are input to the input port Pi of the parallel input / output port PIO, and the control command CMD ′ and the strobe signal STB ′ are output from the command output port Po. It is comprised so that.

  Specifically, a control command CMD and a strobe signal (interrupt signal) STB output from the main control board 21 correspond to the power supply voltage 3.3 V in the buffer 44 of the effect interface board 27 at the input port Pi. Converted to a logic level to be supplied in units of 8 bits. The interrupt signal STB is supplied to the interrupt terminal of the one-chip microcomputer, and the effect control unit 22 'is configured to acquire the control command CMD by the reception interrupt process.

  The control command CMD acquired by the effect control unit 22 ′ includes (1) an abnormality notification and other notification control commands, and (2) control for specifying an outline of various effect operations resulting from winning at the symbol start opening. A command (variation pattern command) and a control command (symbol designation command) for designating a symbol type are included. Here, the outline of the production operation specified by the variation pattern command includes the production total time from the production start to the production end and the result of winning or failing in the jackpot lottery.

  In addition, the symbol designating command includes information for identifying information on the jackpot type (15R probability variation, 2R probability variation, 15R normal, 2R normal, etc.) in the case of a jackpot according to the result of the jackpot lottery. In some cases, information for identifying a loss is included. The outline of the production operation specified by the variation pattern command includes the production total time from the production start to the production end, and the result of success or failure in the big hit lottery. In addition to these, the change pattern command including the presence or absence of the reach effect or the notice effect may be specified, but even in this case, the specific content of the effect content is not specified.

  Therefore, when the change pattern command is acquired, the effect control unit 22 ′ performs an effect lottery subsequently to further specify the effect outline specified by the acquired change pattern command. For example, the specific contents of the reach effect and the notice effect are determined. Then, in accordance with the determined specific game content, a lamp effect by blinking LEDs and a sound effect preparation operation by a speaker are performed, and an effect operation by a lamp or speaker is performed on the image control unit 23 ′. A control command CMD ′ relating to the synchronized image effect is output.

  In order to realize such an image effect synchronized with the effect operation, the effect control unit 22 ′, along with the strobe signal (interrupt signal) STB ′ for the image control unit 23 ′, is sent to the image control unit 23 ′ through the command output port Po. CMD ′ is output toward the production interface board 27. When the production control unit 22 ′ receives a design designation command, a notification control command related to the display device DS, and other control commands, the control command is summarized in a 16-bit length. It is output toward the production interface board 27 together with the interrupt signal STB ′.

  Corresponding to the configuration of the production control board 22 described above, the production interface board 27 is provided with an output buffer 45, and a 16-bit control command CMD ′ and a 1-bit interrupt signal STB ′ are sent to the image interface. It is output to the substrate 28. These data CMD ′ and STB ′ are transmitted to the image control board 23 via the image interface board 28.

  The effect interface board 27 is provided with a digital amplifier 46 that receives the audio signal output from the audio synthesis circuit 42. As described above, the speech synthesis circuit 42 operates with power supply voltages of 3.3 V and 1.8 V, and the digital amplifier 46 performs class D amplification operation with a power supply voltage of 12 V, reducing power consumption. It is possible to produce a loud sound while suppressing it.

  The left and right speakers at the upper part of the gaming machine and the speakers at the lower part of the gaming machine are driven by the output of the digital amplifier 46. Therefore, the voice synthesis circuit 42 needs to generate a three-channel voice signal, and if this is transmitted in parallel, the wiring between the voice synthesis circuit 42 and the digital amplifier 46 becomes complicated.

  Therefore, in this embodiment, the voice synthesis circuit 42 and the digital amplifier 46 are connected by four signal lines in order to prevent deterioration of sound quality and avoid complicated wiring. In this case, the transfer clock signal SCLK, the channel control signal LRCLK, and the 2-bit serial signals SD1 and SD2 are suppressed to a total of 4 bit signal lines. Each signal is a normal single-ended signal, and its amplitude level is a theoretical value of 3.3V.

  Here, the serial signal SD1 is a serial signal for PCM data specifying the stereo signals R and L of the left and right speakers arranged at the upper part of the gaming machine, and the serial signal SD2 is a heavy bass speaker arranged at the lower part of the gaming machine. This is a serial signal for PCM data specifying a monaural signal. The voice synthesis circuit 42 transmits the left channel audio signal L while maintaining the channel control signal LRCLK at the L level, and maintains the channel control signal LRCLK at H level while maintaining the channel control signal LRCLK at the L level. Is transmitted (see FIG. 4B). Note that since there is only one heavy bass speaker in this embodiment, a monaural audio signal is transmitted, but it is of course possible to transmit it as a stereo audio signal.

  In any case, in this embodiment, four types of audio signals can be transmitted with four cables, and therefore, signal transmission without audio deterioration due to noise can be performed with the minimum number of cables. That is, since it is serial transmission, the number of cables is far smaller than that of parallel transmission. Note that when analog transmission is employed, the number of cables is the same, but noise is superimposed on an analog signal having an amplitude of 3.3 V, and the sound quality is greatly deteriorated. On the other hand, when the amplitude level is increased, the power supply wiring becomes complicated and the power consumption increases.

  Such serial signals SD1 and SD2 are acquired by the digital amplifier 46 in synchronization with the rising edge of the clock signal SCLK. In the digital amplifier 46, parallel conversion is performed for each predetermined bit length, and after D / A conversion, D-class amplification is performed and supplied to each speaker.

  The effect interface board 27 is provided with parallel output port Po 'of the one-chip microcomputer 40, serial buffer SI, and output buffer circuits 47, 48, and 49 for transmitting various signals to be output. Here, the output buffer 47 is related to the LED group of the 0th channel, and the frame relay board uses the operation enable signal ENABLE0 and the lighting clear signal CLR output from the one-chip microcomputer 40 as normal single end signals. 34 is output. The amplitude of this single end signal is 3.3 V in theory.

  On the other hand, the lamp driving data SDATA0 and the clock signal CK0 transmitted from the one-chip microcomputer 40 are respectively transmitted to the frame relay board 34 as differential signals through a differential line driver Dri (Differential Line Driver DS90C031B, etc.). Is output.

  As described above, in this embodiment, the transmission signals SDATAi and CKi whose levels change at high speed are suppressed to a few hundred mV (for example, ± 350 mV) by the differential line driver Dri. The energy of the harmonic components of the transmission signals SDATAi and CKi leaking from the antenna is effectively suppressed, and even if each transmission line functions as an antenna, the possibility of causing problems in the radio law is eliminated. . Further, since the transmission signals SDATAi and CKi are transmitted as differential signals, the influence of common mode noise is eliminated, so even if the transmission distance to the frame side member GM1 is long, the bit of the serial signal based on disturbance Garbage is prevented.

  The four types of signals (ENABLE0, CLR, SDATA0, CK0) output to the frame relay board 34 are lamp driven via the frame relay board 34 and the frame relay board 35 while maintaining the signal format. The single-ended signal is transmitted to the board 36 and supplied as it is to the driver DRij, and the differential signal is converted into a single-ended signal by a differential line receiver Rec (Differential Line Receiver DS90C402 or the like) and supplied to the driver DRij ( (See FIG. 5).

  The output buffer 48 outputs the lamp drive data SDATA1, the clock signal CK1, the operation enable signal ENABLE1, and the lighting clear signal CLR output from the one-chip microcomputer 40 directly or via the differential line driver Dri. The differential signal received and transmitted to the drive board 29 is converted to a single-ended signal by the differential line receiver Rec and supplied to the driver DRij.

  Similarly, the output buffer 49 transmits the lamp drive data SDATA2, the clock signal CK2, the operation enable signal ENABLE2, and the lighting clear signal CLR to the lamp drive substrate 30 directly or via the differential line driver Dri. In the lamp driving substrate 30, the received differential signal is converted into a single-ended signal by the differential line receiver Rec and then supplied to the driver DRij (see FIG. 5).

  The drivers DRij of the lamp driving board 36, the lamp driving board 29, and the lamp driving board 30 drive the LED groups of the 0th channel, the 1st channel, and the 2nd channel, respectively. Note that the lamp drive data SDATA and the clock signal CK to the lamp drive board 29 and the lamp drive board 30 are not necessarily limited to transmission by differential signals. For example, when the transmission distance is short, a single signal is used. Transmission using an end signal is also possible.

  Next, FIG. 6A shows the connection relationship between the effect control board 22 ′ and the driver DRij mounted on the lamp drive boards 29, 30, 36 inside the serial port SI built in the one-chip microcomputer 40. It is shown together with the configuration.

  As shown in the figure, in this embodiment, the lamp drive data SDATAi and the clock signal CKi are generated at the serial port SI of the effect control board 22 ′, and are respectively between the differential line driver Dri and the differential line receiver Rec. Is transmitted as an LVDS (Low voltage differential signaling) signal.

  As described above, the LVDS signal transmitted to the lamp driving substrates 29, 30, and 36 is converted into a voltage level of TTL level or CMOS level by the differential line receiver Rec and supplied to the driver DRij. As for the operation enable signal ENABLEi and the lighting clear signal CLR that do not change at high speed, the output of the parallel output port Po 'is transmitted as it is.

  As shown in FIGS. 5 and 6A, the lamp driving data SDATAi and the clock signal CKi are commonly supplied to the signal input terminals SDATA and the clock terminals SCLK of all the drivers DRij mounted on the lamp driving board of each channel CHi. Is done. Similarly, the operation permission signal ENABLEi and the lighting clear signal CLR are commonly supplied to the enable terminal SDEN and the reset terminal RST of all the drivers DRij mounted on the lamp driving board of each channel CHi.

  When the lighting clear signal CLR becomes L level, all the drivers DRij of all the channels CH0 to CH2 are simultaneously reset, and when the operation permission signal ENABLEi becomes the active level, all the drivers DRij of the channel CHi are operable. Thus, the reading operation of the lamp driving data SDATAi becomes possible.

  Next, the serial port SI built in the one-chip microcomputer 40 will be described (see FIG. 6A). The serial port S0 to serial port S2 all have the same configuration, and receive serial data as lamp drive data SDATAi upon receiving 1-byte data from the CPU core and 1-byte data transferred from the transmission data register DR. Transmission shift register SR, a number of control registers RG for managing the internal operation state of the serial port, and a baud rate for receiving the output pulse Φ of the counter circuit CT and outputting a clock signal CKi having a frequency division ratio designated by the control register RG And a generator BG.

  Here, the control register RG includes a READable control register including the empty bit EMP, and indicates whether or not the transmission data register DR can accept new data. That is, when transmission of 1-byte data in transmission shift register SR is completed, empty bit EMP changes to H level (empty level), indicating that new data can be written into transmission data register DR. Therefore, the CPU core (hereinafter referred to as CPU) writes new data into the transmission data register DR after confirming that the empty bit EMP is at the H level.

  The control register RG includes a WRITE control register including a transmission permission bit TXE. When the CPU sets the transmission permission bit TXE to the ON (H) level, the serial port transmission operation is permitted. When set to the OFF level, the transmission operation is prohibited. Therefore, in this embodiment, the CPU sets the transmission permission bit TXE to the ON state at the start of the transmission process, and resets the transmission permission bit TXE to the OFF level at the end of the transmission process.

  FIG. 6B is a time chart showing the operation at the start of transmission for the serial ports S0 to S2. As shown in the figure, when the serial ports S0 to S2 are in the transmission prohibited state (TXE = L), or after the data of the transmission data register DR is serially output, the clock signal CK is at the fixed H level. The transmission data register DR is empty, and the empty bit EMP is also at the H level (empty level).

  Then, after the CPU sets the transmission permission bit TXE to the ON state (transmission permission state) and then writes the first byte of transmission data to the transmission data register DR, the empty bit EMP transitions to the L level, and then After a predetermined time (τ) elapses, the first byte of transmission data is transferred to the transmission shift register SR, and the serial transmission operation is started.

  Further, since the transmission data is transferred to the transmission shift register SR, the empty bit EMP transitions to the H level (empty level) thereafter in response to the start of serial transmission of the first bit. Therefore, after confirming the H level empty bit EMP, the CPU writes the second byte of transmission data into the transmission data register DR.

  Then, in response to the data write operation to the transmission data register DR, the empty bit EMP transitions to the L level (full level). After that, when all the transmission data of the first byte is transmitted, the second byte of data is transferred from the transmission data register DR to the transmission shift register SR, and the data transmission of the second byte is started, and the empty bit EMP Transitions to the H level.

  The empty bit EMP changes to the L level in response to the data write operation of the third byte to the transmission data register DR. However, as shown in the figure, the empty bit EMP maintains the H level when no new data is written. . Further, after all the data is transmitted, the clock signal CK maintains the H level and does not change.

  Although not particularly limited, in this embodiment, in response to the internal operation of the driver DRij, transmission operation is performed in synchronization with the clock signal CK from the MSB (Most Significant Bit) of 1-byte data to the LSB (Least Significant Bit). Is set to be executed (MSB first). Specifically, an appropriate set value is set in the corresponding control register RG. Further, as shown in the figure, the transmission operation proceeds in synchronization with the falling edge of the clock signal CK.

  In this embodiment, the CPU writes the first byte data in the transmission data register DRi in the order of serial port S0 → serial port S1 → serial port S2, and then determines the H level of each empty bit EMPi. Thus, the second byte data is written in each transmission data register DRi in the same order.

  However, in the data writing process executed in series in the order of serial port S0 → serial port S1 → serial port S2, the write time difference of 1-byte data is practically zero. The transmission process is started almost simultaneously. Therefore, the end of the data transmission process to the driver DRij of the channels CH0 to CH2 is almost the same timing as long as the transmission data amount is the same, and the serial transmission process can be completed quickly.

  FIG. 7 is a time chart for explaining the operation of each driver DRij and the operation of the CPU. First, luminance data setting processing for the gradation registers GR0 to GR23 of each driver DRij will be described based on the lamp driving data SDATA0 to SDATA2 output from the one-chip microcomputer 40.

  In order to set the luminance data in the gradation registers GR0 to GR23, prior to this, transmission processing of the slave address SLV for specifying each driver DRij and the register number N (for example, N for the gradation registers GR0 to GR23) = 15H to 1CH) transmission processing needs to be executed. However, as described above, when the register numbers N (= 15H to 1CH) are continuous, after the first register number N (= 15H) is transmitted, it is set in the gradation registers GRn after the register number 15H. It is sufficient that the luminance data Dn to be output is output for each byte.

  The slave address is a 5-bit length port address that identifies the driver DRij, but is an 8-bit length with an appropriate addition of 3 bits. This 8-bit slave address is transmitted from the MSB to the LSB. As is apparent from the circuit configuration of FIG. 5, the 8-bit slave address is commonly transmitted to the five drivers DRij (for example, DR00 to DR04), but the identification corresponding to the transmitted slave address. Only the driver DRij will receive the subsequent transmission data.

  Specifically, in all drivers DRij (for example, DR00 to DR04), the first byte of data (slave address) is acquired at the rising edge of the 24th (= 8 × 3) clock signal CKi, Only the driver DRij that matches the slave address of the receiver continues the subsequent reception process.

  As described above, the register number N of the gradation register GRn is then transmitted to the driver DRij of this embodiment, and subsequently, the setting data Dn to the gradation register GRn is transmitted. It has become. Then, in the driver DRij corresponding to the designated slave address, the register number N is automatically incremented, and the setting data Dn + 1, Dn + 2,... Received thereafter are the gradation registers GRn + 1, GRn + 2, respectively. ... is set.

  As described above, in this embodiment, only the gradation register GRi is used. Therefore, the number of serial data transmitted from the one-chip microcomputer 40 to the driver DRij of each channel (0 to 2) is the slave address. (1 byte), the register number of the gradation register GR0 (1 byte of 15H), and the luminance data (24 bytes) to be set in the 24 gradation registers GR0 to GR23, total 26 bytes.

  As described with reference to FIG. 6B, the serial port S0 to S2 of the one-chip microcomputer 40 maintains the empty bit EMP of the control register RG at the H level after outputting the 23rd byte luminance data. The 24th byte of luminance data written in the transmission data register DR is output from the transmission shift register SR toward the LSB for each bit from the transmission shift register SR in a state where the empty bit EMP = H level is maintained. Then, after the serial ports S0 to S2 of the one-chip microcomputer 40 output the LSB of the luminance data of the 24th byte, the clock signal CK maintains the H level.

  Therefore, the CPU of the one-chip microcomputer 40 returns the operation permission signals ENABLE0 to ENABLE2 to the L level at the timing when the 24th byte luminance data is assumed to have been acquired by the corresponding driver DRij, and permits transmission of the control register RG. The bit TXE is returned to the transmission inhibition level (see FIG. 7). Then, in response to the operation enable signals ENABLE0 to 2 = L, each driver DRij then drives the LED based on the brightness data newly set or set in the gradation registers GR0 to GR23. Become.

  In this embodiment, every time serial data for one driver is transmitted, the transmission permission bit TXE is returned to the prohibited level. However, the transmission permission bit TXE is not limited at all, and is prohibited after the transmission processing for all the drivers is completed. You may return to the level. In particular, there is no need to return to the prohibited level.

  FIG. 8 is a flowchart for explaining the operation content of the effect control unit 22 ′, which is executed by the CPU of the one-chip microcomputer 40. The operation of the effect control unit 22 ′ includes a main process (FIG. 8A) executed in an infinite loop after the CPU reset, a timer interrupt process started every 1 mS (FIG. 8B), and a main control. And reception interrupt processing (not shown) for receiving a control command transmitted by the unit.

  First, the timer interrupt process will be described. In FIG. 8B, the process when the production motors M1 to Mn are provided is indicated by broken lines. In the embodiment in which the effect motors M1 to Mn are provided, the drive data is updated when necessary to advance the stepping motor by one step at every predetermined timing (ST20). And this drive data is output to each effect motor M1-Mn, and when there exists control command CMD 'which should be transmitted to image control part 23', this is output toward image control part 23 '. (ST22). Finally, the interrupt counter is incremented to finish the interrupt process (ST23).

  Next, the main process will be described. The CPU repeatedly checks the interrupt counter and waits until the value of the interrupt counter becomes 16 (ST10). As described above, since the interrupt counter is updated every 1 mS (ST23), in step ST10, an elapsed time until 16 mS elapses from the process of the previous step ST11 is waited. That is, in this embodiment, steps ST11 to ST17 are repeated every 16 ms.

  Therefore, when the standby time of 16 mS has elapsed, the interrupt counter is cleared to zero (ST11), the control command CMD transmitted from the main control unit 21 is analyzed, and the operation corresponding to the control command CMD is executed. Therefore, necessary start processing is executed. For example, when a variation pattern command CMD is received, start processing such as a lamp effect and a sound effect is executed based on the control command CMD.

  Next, a switch signal such as the chance button 11 is determined (ST13), and an effect scenario for the effect to be newly executed is constructed or an effect scenario for the effect being executed is updated (ST14). Then, the audio reproduction operation is advanced in response to the production scenario (ST15).

  Subsequently, for the LEDs connected to each of the lamp drive substrates 36, 29, and 30, the brightness data defining the brightness is updated and stored in the output buffer table TBL (ST16). In this embodiment, a total of 3 × 5 × 24 LEDs are arranged on the three lamp driving substrates 36, 29, and 30, and each LED is based on 16-gradation 4-bit long luminance data. Lighting control. Therefore, the output buffer table TBL is 3 × 5 × 24/2 bytes long.

  Next, the brightness data of the output buffer table TBL updated in the process of step ST16 is transmitted to each of the lamp drive boards 36, 29, 30 via the serial ports S0 to S2 (ST17). However, the CPU is not in charge of the transmission process itself, but the CPU only writes necessary data to the transmission data register DR of the serial ports S0 to S2 at an appropriate timing, and the control burden on the CPU is extremely small. It is. Further, as shown in FIG. 7, serial data is transmitted to the three lamp driving substrates 36, 29, and 30 all at once, so the processing time of step ST17 is not long regardless of the amount of transmission data.

  As shown in FIG. 7, the number of clock signals CK required to set the luminance data in the three drivers DR mounted on the three lamp driving boards 36, 29, and 30 is 8 × (2 + 24), and transmission starts. The timing and the transmission end timing are substantially the same for all three drivers DR.

  Therefore, the time required to update the lighting states of the three drivers DR mounted on the three lamp driving substrates 36, 29, and 30 is approximately 8 × (2 + 24) × T, and 8 × 26 × 5 × T. It is possible to update the lighting states of all 15 drivers in a certain processing time. The processing time for all the 15 drivers is substantially the same as the time required to update the lighting states of the five drivers.

  Here, T is the pulse period of the clock signal, and in this embodiment, T = 0.25 to 0... Corresponding to the clock signal having a frequency of about 4 to 5 MHz based on the set value to the baud rate generator BG. 2 μS. Therefore, the entire processing time is about 0.2 mS, and processing time for other processing is not consumed.

  Even when such high-speed processing is executed, the clock signal CKi and the lamp drive data SDATAi are transmitted as a low-level differential signal (LVDS signal). The problem does not occur. Further, as described above, since the influence of common mode noise is eliminated by being transmitted as a differential signal, bit corruption of the serial signal due to disturbance is prevented.

  FIG. 9 is a flowchart for explaining the LED output processing (ST17) in more detail. In the LED output process, first, initialization data is transmitted to all 15 drivers DRij, and the LED is set to be turned on in accordance with the luminance data (PWM value) written in the gradation register. .

  Note that the processing in step ST17 is the same as the procedure shown in FIG. 7, and the processing procedures in steps ST31 to ST45 shown below are adopted. That is, the slave address transmission → register number transmission → initialization data transmission processing is collectively executed for predetermined drivers (three) of the channels CH0 to CH2, and this processing is repeated five times to obtain 15 The initialization process for each driver DRij is completed. Therefore, the total processing time is about 8 × 3 × 5 × T [= data bit length 8 × data number 3 × repetition processing count 5 × clock cycle T].

  It is not always necessary to repeat such initialization processing every 16 ms, but in this embodiment, initialization data of all drivers DRij is transmitted every time the blinking state is updated. Even if the part is garbled, the abnormal operation due to garbled setting data is automatically resolved after 16 mS.

  When the initialization process is completed as described above (ST30), the process proceeds to the brightness data setting process (ST31 to ST45). At this start timing, as shown in FIG. 6B, the transmission permission bit TXE of each control register RG is at the OFF (L) level, the empty bit EMP is at the H level (empty level), and the clock The signal CK maintains the H level. Further, the operation enable signals ENABLE0 to ENABLE2 are at the L level.

  Continuing the description based on the above, in the brightness data setting process, first, the start slave address is specified for each of the five drivers DRij of the channels CH0 to CH2 (ST31). As shown in FIG. 5, in this embodiment, a series of slave addresses having an increment relationship are assigned to the five drivers DRij mounted on each lamp driving board, and the head address is 00H, 10H and 18H.

  Next, ON (H) level operation enable signals ENABLE0 to ENABLE2 are respectively output from the parallel output port Po '(ST32). As a result, all drivers DRij of all channels CH0 to CH2 can receive serial data.

  Therefore, for the serial ports S0 to S2, the transmission permission bit TXE of each control register RG is set to the ON level, and the transmission processing of the serial ports S0 to S2 is set to the permitted state (ST33). In addition, the three types of slave addresses that have been initially set in the process of step ST31 or are updated in the process of step ST44 are respectively written in the transmission data registers DR of the serial ports S0 to S2 (ST33).

  As shown in FIG. 7, the empty bit EMP of the control register RG of each of the serial ports S0 to S2 transitions to the L level by the process of step ST33, and after a predetermined time (τ), the empty bit EMP returns to the H level. At the same time, the slave address transmission operation is started.

  Therefore, when the empty bit EMP returns to the H level (ST34), for the gradation registers GR0 to GR23 of each driver DRij, the head address of the register number is written to the transmission data register DR of the serial ports S0 to S2. (ST35). In this embodiment, since the register numbers of the gradation registers GR0 to GR4 are N = 15H to 1CH, 15H is written in the transmission data registers DR of the serial ports S0 to S2 in the process of step ST35, respectively. . In addition, the empty bit EMP changes from the H level to the L level (full level) by the process of step ST35.

  Thereafter, when the transmission of the first slave address is completed, the empty bit EMP returns to the H level (empty level) (ST36), and thereafter, the process proceeds to a transmission process of 24 luminance data.

  Specifically, first, the variable n is initialized to zero (ST37). Here, the variable n specifies the gradation registers GR0 to GR23, and the variable n = 1 to 24 corresponds to the gradation registers GR0 to GR23.

  Therefore, next, after incrementing the variable n (ST38), the luminance data (PWM value) for the gradation register GRn-1 of each channel CH0 to CH2 is read from the output buffer table TBL, and the serial ports S0 to S2 are read. Each is written in the transmission data register DR (ST39). In step ST36, after the empty bit EMP transits to the H level, the empty bit EMP returns to the L level, and the register number transmission operation is repeated. When this transmission operation ends, the empty bit EMP Transitions to the H level.

  Therefore, next, the process waits for the empty bit EMP to transition to the H level (ST40). If the transition to the H level occurs, the process proceeds to step ST38 unless the variable n reaches 24 (ST41). Therefore, the luminance data to the gradation registers GR0 to GR23 are sequentially written in the transmission data register DR of the serial ports S0 to S2 by the processing of steps ST38 to ST41.

  Note that the timing at which the variable n reaches 24 is only that the 24th byte of luminance data is written in the transmission data register DR of the serial ports S0 to S2, and this is acquired by the driver DRij. After about eight clock signals CK are output.

  Therefore, after consuming about eight clock signals CK (ST42), the operation permission signal ENABLE is returned to the prohibited level, and the transmission permission bit TXE of the control register RG is returned to the prohibited level (ST43). As a result, the lighting state of the LED driven by the driver DRij whose luminance data has been updated is updated.

  With the above processing, the luminance data setting processing and lighting update for the three drivers DRij for each channel 0 to 2 are completed. Next, the slave address is updated (ST44), and the next three drivers DRij are updated. The setting process is repeated (ST45).

  As described above, in the present embodiment, the setting process for each of the 24 gradation registers of the three drivers DRij is completed at once by the processes of steps ST32 to ST43, and this process is repeated five times. Processing can be completed.

  Then, the setting process for the three drivers starts almost simultaneously and ends almost simultaneously. Therefore, the total processing time is about 8 × 26 × NUM × T corresponding to the pulse period T of the clock signal and the total number TOTAL = NUM × 3 of the drivers DRij, and 24 × NUM × 3 LEDs. The setting process of luminance data can be finished very quickly.

  The first embodiment has been described in detail above, but appropriate modifications can be made. For example, in the above embodiment, for convenience of explanation, the number of drivers DRij and LEDs in the three-channel lamp driving boards 36, 29, and 30 is the same. is there. In such a case, when the setting process for the necessary driver DRij (ST32 to ST45 in FIG. 9) is completed, the subsequent setting process (ST32 to ST45) is skipped for that channel.

  Similarly, for the driver DRij in which the number of LEDs to be driven is less than 24, unnecessary setting processing (ST38 to ST41) is skipped by changing the processing in step ST41 in FIG.

  In the above embodiment, for convenience of explanation, the setting process for all the drivers is executed every 16 ms. However, it is also preferable to divide this appropriately. FIG. 8C illustrates such an operation. Instead of the LED output process in step ST17 of FIG. 8A, the LED output process (ST24) corresponding to the value CNT of the interrupt counter is executed. doing.

  Specifically, when CT = 10, initialization data is transmitted to all drivers, and when CT = 11, setting data is transmitted to three drivers in the first stage. Similarly, since the setting data is transmitted to the three drivers corresponding to the interrupt counter value CNT, no problem occurs even if the setting data is increased.

  As setting data, it is conceivable to transmit data defining the operation mode of fade-in and fade-out in addition to the luminance data defining the duty ratio (PWM). On the other hand, it is also conceivable to transmit switch data defining the ON / OFF state instead of the luminance data, and additionally transmitting data defining the operation mode of fade-in and fade-out.

  In the embodiment, the three-channel CH0 to CH2 lamp driving board has been described. However, the number of serial ports to be used may be increased in accordance with the number of lamp driving boards.

  Further, it is preferable to drive the stepping motor using the same driver DRij. In this case, a mode in which a motor drive board is separately provided and serial drive data (switch data) is transmitted every 1 mS, for example, is considered. (Refer to ST21 in FIG. 8B). On the other hand, a stepping motor may be connected to the lamp driving board. In this case, it is preferable that the driver DRij for driving the stepping motor repeats the serial driving data transmission process in a short cycle.

  Further, in the embodiment shown in FIG. 6, every time 1-byte serial data is transmitted, the CPU writes the next 1-byte parallel data in the transmission data register DR. . That is, a FIFO (First In First Out) buffer capable of temporarily storing parallel data of a predetermined unit length (multiple bytes) is secured, and each time 1-byte serial data is transmitted, the next data is automatically stored in the transmission data register DR. In this case, the CPU replenishes the FIFO buffer with the next 1-byte data when, for example, a 1-byte space (empty area) is generated in the FIFO buffer. It was enough.

  In each of the above embodiments, the CPU exclusively reads the control register repeatedly and checks the empty bit EMP of the control register. However, the timing when the transmission data register DR becomes empty is used. It is also preferable to adopt a configuration in which the CPU is interrupted at the timing when the FIFO buffer is empty (empty area). In this case, in response to the interrupt request, the CPU may write 1-byte data into the transmission data register DR or write data of a predetermined unit length into the FIFO buffer.

  Furthermore, in order to minimize the processing time, the driver of the embodiment is slave address → register address → 1 byte drive data → 1 byte drive data → 1 byte drive data →... → 1 byte drive. Although the procedure of data ... was taken, it is not limited at all. That is, it is possible to add 2 bytes to the number of data to be transmitted, first transmit a start command (start command), and finally transmit an end command (period command). However, in this case as well, the start bit and stop bit are not used, and each command has a unit length (1 byte length).

  Further, for example, drive data that defines the lighting state of each lamp may be transmitted to a driver capable of driving 24 lamps in a state where the lamps to be driven are individually specified. In this case, for example, a start command → a slave address that defines the driver → a subaddress that specifies a lamp → a driving data for the lamp → a subaddress that specifies a lamp → a driving data for the lamp → a period command Serial data is sent in the procedure. In this case, the total number of bytes of data to be transmitted is 24 × 2 + 3 bytes for one driver.

  6 to 9, the timing for updating the lighting state is defined by the operation permission signals ENABLE0 to ENABLE2, but this point is not limited at all. That is, if a configuration in which an end command (period command) is transmitted at the end of a series of serial data, the lighting state can be updated based on the internal processing of the driver DRij that recognizes that the period command has been received.

  In this case, for example, an internal counter that circulates in the range of 0 to 127 is provided in each driver DRij, and after receiving a period command, the lighting state is updated when the internal counter reaches a predetermined value (for example, 127). Is preferred. When such a configuration is adopted, after the lighting state is updated (that is, after the internal counter reaches a predetermined value), the same serial data transmission process can be started. In this sense, the operation permission signals ENABLE0 to ENABLE2 and other control signals are not necessary.

  In the embodiment shown in FIGS. 6 to 9, five drivers DRi0 to DRi04 are connected to the three-channel serial ports (S0 to S2) (total of 15 drivers). The number of DRij may be further increased. In the following description, the driver and the buffer are explicitly referred to as an LED driver DRij for convenience.

  When a large number of LED drivers DRij are connected to one serial port SI, the input part of the LED driver DRij is not a bipolar type current drive system in consideration of the maximum capacity of the output current of the serial port SI and the buffer. A unipolar voltage drive system is preferable. FIG. 10A and FIG. 10B show two preferable unipolar input circuits, and an LED driver DRij having such an input circuit is preferably used.

  Also, it is not always necessary to use a plurality of channel serial ports (S0 to S2), and a large number of LED drivers DRij may be connected to a single serial port. However, in this case, since it is necessary to repeat the serial data transmission process (see ST32 to ST43 in FIG. 9) for the number of LED drivers, it is preferable to speed up the clock signal CK to the limit.

  Further, the use of the operation permission signal ENABLEi can be omitted, and in this case, there is an advantage that the wiring can be simplified. However, a start command (start command) and a period command (end command) are added in response to the omission of the operation permission signal ENABLEi.

  That is, when updating the luminance data of 24 lamps, [start command] → [slave address that defines the LED driver] → [sub-address specifying the register corresponding to the first lamp] → [the register [Gradation data for] → [Subaddress specifying register corresponding to second lamp] → [Gradation data for that register] →... → [Subaddress specifying register corresponding to 24th lamp] → 24 × 2 + 3 bytes of serial data are transmitted to one driver in the procedure of [gradation data for the lamp] → [period command]. When the number of lamps whose luminance data is updated is N (<24), serial data of N × 2 + 3 bytes is transmitted.

  FIG. 11 is a flowchart showing a process of updating luminance data (serial data transmission process) in an embodiment that does not use the operation permission signal ENABLE. Although not particularly limited, as in the case of FIG. 9, the initial setting process is first executed for all the LED drivers in this transmission process (ST50). Specifically, for example, in accordance with the PWM value written in the gradation register (24 each) of each LED driver, initial setting is performed for each LED driver so that 24 LEDs are turned on.

  Next, a 1-byte start command (for example, FFH) is written in the transmission data register DR of the serial port S0 (ST51). Then, the start bit serial transmission of the start command is awaited by determining the empty bit EMP of the control register RG (ST52). When the empty bit EMP of the control register RG becomes EMP = 1, the slave address of the LED driver is written in the transmission data register DR (ST53). The slave address is nothing but the port number assigned to the LED driver.

  Next, it waits for the empty bit EMP to become EMP = 1 (ST54), and when serial transmission of the slave address (port number) is started, the variable n is initialized to zero (ST55). The variable n specifies the gradation registers GR0 to GR23, and the value (1 to 24) of the variable n corresponds to the gradation registers GR0 to GR23.

  Next, after incrementing the variable n (ST56), the subaddress is written to the transmission data register DR of the serial port S0 (ST57). Here, the sub-address is a register number that specifies the gradation registers GR0 to GR23, and is simply a value corresponding to the variable n. Next, it waits for the empty bit EMP to become EMP = 1 (ST58), and if EMP = 1, the luminance data to be transmitted to the gradation register specified by the previous subaddress (register number) is transmitted to the transmission data register. Write to DR (ST59). The luminance data (PWM value) is read from an appropriately configured output buffer table TBL (see FIG. 8).

  The same applies to the following, and when serial transmission of luminance data is started (ST60), unless it is the 24th luminance data (ST61 is No), the next subaddress (register number) is used as the transmission data register of the serial port S0. Writing to DR (ST56 to ST57), the same serial data transmission processing is repeated.

  On the other hand, when serial transmission of the 24th luminance data is started (Yes in ST61), a period command indicating that serial transmission to the LED driver is completed is subsequently written in the transmission data register DR ( ST62). When serial transmission of a period command is started (ST63), the transmission time is secured (ST64), the slave address (port number) is updated, and the same serial data transmission processing (ST51 to ST65) is performed. repeat. In this embodiment, serial data transmission processing (ST51 to ST65) is repeated a total of 16 times corresponding to the number of LED drivers. However, transmission processing (luminance data) is performed by using a high-speed clock signal CK. Update processing) can be completed quickly.

  Incidentally, in the case where a total of N LED drivers DRij are used and each LED driver DRij drives M LEDs, and all luminance data is updated, the total number of data is (M × 2 + 3) × If N = 16 and M = 24, 816 bytes = 6528 bits, which is a considerable value. However, for example, when a clock signal of about 10 Mz is used, the entire processing can be completed in a processing time of about 0.653 mS, and the processing time of other control processing is not short.

  Moreover, even if the clock signal CK is increased in speed, in this embodiment, the input part of the element directly connected to the CK line or the SDATA line is a unipolar type, and the number of such elements is limited. There is no risk of malfunction due to waveform numeration. Here, for convenience of explanation, it is assumed that each LED driver DRij drives 24 LEDs, and all luminance data is updated every time. However, a gradation register that is updated by one update process. By thinning out to 1 / X, the update processing time for each time can be reduced to about 1 / X. In this case, each update processing time is (M × 2 / X + 3) × N × τ corresponding to the cycle τ of the clock signal CK.

  Further, when a serial port provided with a FIFO buffer is used, the serial data transmission process shown in FIG. 11 can be simplified. As shown in FIG. 12B, the FIFO buffer is configured to be accessible from the CPU core, and is automatically transferred to the transmission data register DR for each byte sequentially from the data stored in the FIFO buffer first (First In First Out), the data is output as serial data SDATA via the transmission shift register SR.

  The processing in this case is, for example, as shown in FIG. 12A. Using the FIFO buffer and setting the byte length to be used in the control register RG of the serial port S0, steps ST50 to ST66 are performed. Processing is executed.

  Specifically, after the initialization data is output to the LED driver (ST50), a group of data is written to the FIFO buffer (ST53), and a wait is made for an empty area to be generated in the FIFO buffer (ST54). As described above, the data having a plurality of bytes written in the FIFO buffer is automatically transferred to the transmission data register DR for each byte, and is output as serial data SDATA via the transmission shift register SR. When the output of 1-byte serial data is completed, the fact is indicated in the corresponding flag of the control register RG. Therefore, the variable n is appropriately updated (ST55 to ST56), and the next 1-byte data is stored in the FIFO buffer. (ST57).

  The subsequent process is the same, and whenever a 1-byte length free area is generated in the FIFO buffer (ST58), the process of replenishing the next 1-byte data to the FIFO buffer (ST59) is repeated. When serial transmission of all data is completed, a period command may be written into the FIFO buffer (ST62).

  In the embodiment of FIG. 12, the group of data (M × 2 + 3) to be transmitted is larger than the storage capacity of the FIFO buffer. However, a FIFO buffer having a storage capacity of M × 2 + 3 bytes is illustrated. If secured, the processing of steps ST53 to ST63 can be integrated, and the processing load on the CPU is reduced to a limit. For example, if M = 24, a 51-byte FIFO buffer is required. For example, the gradation data is divided into four gradation registers by dividing the 24 gradation registers into four equal parts and time-divided four times of LED output processing. If the configuration is used, the storage capacity of the FIFO buffer is 15 bytes long, which is very reasonable.

  If the configuration does not use the start command and the period command, the serial data required to update the M gradation registers is M + 2 bytes. Therefore, even when M = 24, the gradation register is divided into two. The storage capacity of a 14-byte FIFO buffer is sufficient by dividing the output processing into two.

  Furthermore, when N effect motors are driven by one driver, the PWM setting value (= drive data: corresponding to the brightness data defining the brightness of the LED) to the gradation register supplied to the N effect motors. ) Becomes N bytes as a whole.

  Therefore, if the start command and the period command are not used, it is sufficient to transmit N + 2 byte data to update the operation state of N effect motors, and if a 16 byte FIFO buffer is used, the FIFO buffer The set values for the 14 effect motors can be rewritten with a single write process. For example, when the production motor is stepped at an interrupt interval of 1 mS, the CPU only has to write 16 bytes of drive data to the FIFO buffer at a time in each interrupt process, so the processing burden on the CPU is extremely reduced. The

<Transmission by clock-embedded composite differential signal DIF>
In the above description, separate transmission lines are provided for the clock signal CKi and the serial signal (lamp drive data) SDATAi. However, it is also preferable to integrate them in order to simplify the circuit configuration.

  In FIG. 13, the clock signal CK and the serial signal SDATA are integrated by the coupling circuit 50 and then supplied to the differential line driver Dri. The output of the differential line receiver Rec is output by the separation circuit 56 to the original two signals. A circuit configuration for returning to CK and SDATA is shown.

  The combining circuit 50 converts the serial signal SDATA (FIG. 13A), which is an NRZ (Non-Return-to-Zero) signal, into an RZ (Return-to-Zero) signal shown in FIG. 13B. , A circuit that superimposes a logically inverted clock signal CK (= PL1).

  The circuit configuration of the coupling circuit 50 is as shown in FIG. 13H. The one-shot multivibrator 51 that operates at the falling edge of the clock signal CK and the one-shot multivibrator 52 that operates at the rising edge of the clock signal CK. And a delay circuit 53 including three NOT gates, an AND gate 54, and an OR gate 55.

  Here, the one-shot multivibrator 51 operates in synchronization with the falling edge of the clock signal CK having the pulse width τ (for example, duty ratio 50%), so that the logically inverted pulse width = τ / 2 (for example, duty) The clock signal PL1 of about 25%) is generated. On the other hand, the one-shot multivibrator 52 operates in synchronization with the rising edge of the clock signal CK, thereby generating a clock signal PL2 that has been transformed to a pulse width = τ × 4/5 (for example, a duty ratio of 40%). (See FIG. 13 (g)).

  Then, the clock signal PL2 passes through the delay circuit 53 including three NOT gates and is time-delayed, and logically inverted and supplied to the AND gate 54 as an inverted clock signal PL2 ″ (FIG. 13 (g)). Since the serial signal SDATA, which is an NRZ signal, is also supplied to the AND gate 54, the output of the AND gate 54 becomes an RZ signal, and this is ORed with the clock signal PL1, so that FIG. The composite differential signal DIF shown in FIG.

  Note that the output of the AND gate 54 is not exactly coincident with the RZ signal shown in FIG. 13B because the L period is slightly extended by the inverted clock signal PL2 ″, but is superimposed on the clock signal PL1. Thus, the RZ waveform is substantially the same as that in Fig. 13 (b), and the coupling circuit 50 is not necessarily required, for example, the RZ signal shown in Fig. 13 (b) or the RZ signal shown in Fig. 13 (c). It is also preferable to output the clock signal shown from the serial port SI, or the composite differential signal DIF shown in FIG.

  Such a composite differential signal DIF (clock signal PL1 + RZ signal) is supplied to the differential line driver Dri and transmitted to the differential line receiver Rec as a low-level composite differential signal DIF. Return to the original signals CK and SDATA. Note that, at the timing when the serial signal SDATA is not transmitted, the composite differential signal DIF is configured to be maintained at the L level.

  The separation circuit 56 is as shown in FIG. 13 (i), and is synchronized with the one-shot multivibrator 57 operating at the rising edge of the composite differential signal DIF and the falling edge of the output signal of the one-shot multivibrator 57. The D latch 58 stores the level of the composite differential signal DIF at that timing.

  The operation content of the separation circuit 56 is as shown in FIGS. 13D to 13F, and the clock signal CK and the serial signal SDATA are restored in a state in which the phase is delayed by a half cycle of the clock signal CK. Is done. Then, the restored clock signal CK and the serial signal SDATA are supplied to the driver DRij, so that a predetermined lamp is lit with the luminance specified by the serial signal SDATA.

<When not using the clock embedding method>
As described above, the clock-embedded composite differential signal DIF obtained by superimposing the clock signal PL1 on the RZ signal has been described as the LVDS signal, but is not particularly limited. For example, the transmission of the clock signal can be omitted by adding the start bit ST prior to the series of serial signals SDATA.

  Further, the transmission by the LVDS signal is not limited to the drive data SDATAi for driving the LED lamp and the motor, and for example, it is also preferable to transmit the control commands CMD, CMD ′, and CMD ″ by the LVDS signal.

  FIG. 14 exemplifies such a circuit configuration, and shows a case where a 16-bit control command CMD is transmitted from the upstream control unit to the downstream control unit by LVDS transmission. Note that the logical value of the start bit ST is appropriately set. For example, when the serial signal SDATA during non-transmission is maintained at the H level, the logical value of the start bit ST becomes L (FIG. 14). (A)). Also, the start bit is automatically added, for example, at the serial port.

  In this case, in the LVDS signal (serial transmission signal SGN), the start bit ST that falls from the steady level (H) to the L level has a bit pattern preceding the 16-bit control command CMD (FIG. 14A). . In this case, for example, a strobe signal STB instructing that the control command CMD should be acquired is transmitted from the upstream control unit to the downstream control unit (see FIG. 14B).

  Corresponding to the configuration of the upstream control unit, the downstream control unit includes a reproduction clock generation unit 80 that generates a reproduction clock RCK for a 16-bit section of the serial transmission signal SGN, a serial transmission signal SGN, and a reproduction clock RCK. And a signal reproduction unit 81 for reproducing the control command CMD. The signal reproducing unit 81 includes a shift register RG that receives a 16-bit control command CMD as serial data, and an output buffer BUF that stores the 16-bit control command CMD as parallel data. .

  As shown in FIG. 14 (d), the recovered clock generation unit 80 generates a set pulse corresponding to the falling edge of the start bit ST, and a 16 × N-ary counter 82 that receives the reference clock CK for a predetermined time interval. A one-shot multivibrator 83, an RS flip-flop 84 that receives a set pulse from the one-shot multivibrator 83 and a reset pulse from the 16 × N-ary counter 82 are configured.

  The one-shot multivibrator 83 is supplied with an output signal of an AND gate 85 that receives the inverted signal of the serial transmission signal SGN and the Q-bar output of the RS flip-flop 84. An output signal of the AND gate 86 that receives the reference clock CK and the Q output of the RS flip-flop 84 is supplied to the count terminal of the 16 × N-ary counter 82. In this embodiment, for example, since N = 2, the 16 × N-ary counter 82 is hereinafter expressed as a 32-ary counter 82.

  In the recovered clock generation unit 80 having such a circuit configuration, the RS flip-flop 84 is in the reset state in the initial state, the Q output thereof is L level, and the Q bar output is H level. Therefore, the AND gate 85 waits in an open state, and the AND gate 86 waits for an operation start in a closed state.

  In such a standby state, when the serial transmission signal SGN is transmitted, the start bit ST is inverted and supplied to the one-shot multivibrator 83, and a set pulse that maintains the H level for a predetermined time is generated. The At this time, since the reset terminal of the RS flip-flop 84 is at the L level, the RS flip-flop 84 is set and the Q output transitions to the H level, while the Q bar output transitions to the L level.

  As a result, the AND gate 86 that receives the Q output at the H level changes from the closed state to the open state. Further, since the L level Q-bar output is supplied to the AND gate 85 after some time delay, the AND gate 85 is closed thereafter. Since the operation state of the RS flip-flop 84 is maintained even after the set pulse disappears, the serial transmission signal SGN after the start bit ST does not affect the one-shot multivibrator 83. Therefore, the open state of the AND gate 86 and the closed state of the AND gate 85 are maintained thereafter.

  In such an operating state, the 32-bit counter 82 repeats the counting operation, but its N-divided output is supplied to the signal reproduction unit 81 as the reproduction clock RCK. FIGS. 14B and 14C illustrate the relationship between the reference clock CK and the recovered clock RCK. In this embodiment in which N = 2, the divide-by-2 output of the reference clock CK is It shows that it becomes the reproduction clock RCK.

  By the way, the 32nd counter 82 outputs a carry signal CY when receiving the 32nd reference clock CK. Since the carry signal CY is supplied to the reset terminal of the RS flip-flop 84, the RS flip-flop 84 is reset at this timing, and as a result, the AND gate 86 changes to the open state, while the AND gate 85 is Transition to the open state.

  Since the reset state of the RS flip-flop 84 is maintained even after the carry signal CY disappears, the open state of the AND gate 86 and the open state of the AND gate 85 are maintained thereafter, and serial transmission thereafter. The standby state waiting for the start bit ST of the signal SGN is maintained. The carry signal CY undergoes a time delay, is logically inverted, and is supplied to the clear terminal of the binary counter 82, so that the counter value returns to the initial state, and the reproduction clock generation unit 80 receives the next serial transmission signal. After receiving the start bit ST of SGN, the same operation as described above is executed.

  As described above, in this embodiment, the reproduction clock generator 80 outputs the reproduction clock RCK only in the 16-bit section of the serial transmission signal SGN, whereby the control command CMD is extracted from the serial transmission signal SGN. The extracted control command CMD is converted from a serial signal to a parallel signal and stored in the output buffer BUF of the signal reproducing unit 81. Therefore, the downstream control unit that has been notified that the control command has been transmitted by the strobe signal STB has only to acquire the control command from the output buffer BUF of the signal reproduction unit 81.

  According to the circuit configuration of FIG. 14D described above, LVDS transmission can be easily performed without embedding a clock signal. In addition, since the control commands CMD, CMD ′, CMD ”and the like are transmitted as low-level differential signals (LVDS signals), there is no problem in the radio law due to the harmonics of the transmission signal. Since the command is transmitted as a differential signal and the influence of common mode noise is eliminated, the bit corruption of the control command is effectively prevented.

<When using a serial transmission element instead of a serial port>
In the above description, the serial signal is generated using the serial port SI. However, the configuration is not necessarily limited to such a configuration, and a configuration that does not use the serial port SI is also very suitable in terms of simplicity. .

  FIG. 15 shows a configuration example in which the operation of the serial port SI is substituted for a dedicated serial transmission element (IC) 70. As illustrated, the serial transmission element 70 includes an oscillation circuit OSC that generates an operation clock, a 16-bit input / output buffer 60 (60T / 60R), a serializer / deserializer 61 (61T / 61R), and a clock extraction. The circuit 62, the differential line driver Dri, and the differential line receiver Rec are built in. In addition, an operation control terminal DIR, a reset terminal RSTN for controlling the operation availability state, and a chip selection terminal CS for element selection are provided.

  The operation control terminal DIR is a control terminal that defines whether the serial transmission element 70 is operated in the transmission mode (DIR = L) or the reception mode (DIR = H). The input buffer 60T of the serial transmission element 70 in the transmission mode is supplied with 16-bit parallel data from, for example, the parallel port P0 'of the one-chip microcomputer 40 of the effect control unit 22'. On the other hand, the serial transmission element 70 in the reception mode is connected to, for example, an LED driver, and the output buffer 60R controls lighting of 16 LEDs.

  As shown in the figure, in the circuit configuration of FIG. 15, since the operation control terminal DIR of the serial transmission elements 70R... 70R is fixed at the H level, the serial signal receiving operation is repeated, Output to the LED driver. Although not particularly limited, in the case of this embodiment, the serial signal to be transmitted is simple lighting data having a 16-bit length that defines the ON / OFF level of 16 LEDs.

  On the other hand, the operation control terminal DIR of the serial transmission element 70T in FIG. 15 is configured to maintain the L level for a predetermined time by the one-chip microcomputer 40 of the effect control unit 22 'when necessary. The operation control terminal DIR is kept at the L level until the 16-bit serial transmission processing is completed. The transmission operation of the serializer 61T of the serial transmission element 70 is started when the reset terminal RSTN is synchronized with the H level at the timing when the operation control terminal DIR transitions to the L level.

  The serializer 61T that has started the transmission operation receives the 16-bit data of the input buffer 60T bit by bit in synchronization with the operation clock of the oscillation circuit OSC, and supplies the LVDS signal to the differential line driver Dri.

  Although not particularly limited, the LVDS signal is a clock-embedded serial signal, and is a composite difference in which a clock signal (an operation clock output from the oscillation circuit OSC) is superimposed on the RZ signal shown in FIG. This is a motion signal DIF. The clock extraction circuit 62 operates in the same manner as the separation circuit 56 in FIG. 13 and extracts the clock signal embedded in the composite differential signal DIF.

  The deserializer 61R functions in synchronization with the clock signal extracted by the extraction circuit 62, extracts a 16-bit long serial signal (RZ signal) from the composite differential signal DIF, and outputs the 16-bit parallel signal to the output buffer 60R. Output as data. As described above, in this embodiment, the serial signal to be transmitted is 16-bit lighting data that defines the ON / OFF level of 16 LEDs, and the parallel data of the output buffer 60R is the LED driver. To control the lighting of 16 LEDs.

  Based on the above description, the one-chip microcomputer 40 of the production control unit 22 ′ performs the lighting control operation of N × 16 LED lamps via the N serial transmission elements 70R... 70R every predetermined time. The scheduled operation (lighting update process) that repeats the above will be described.

  The one-chip microcomputer 40 outputs the first address value (chip number) of the N serial transmission elements 70R to the address decoder 63, thereby activating the chip select signal CS0, and then the parallel port Po of the one-chip microcomputer 40. The lighting data is set to 'and the transmission command signal CTL is maintained at the L level for a predetermined time.

  Then, when the transmission command signal CTL becomes L level, the serial transmission element 70T automatically starts the transmission process described above and outputs the composite differential signal DIF from the differential line driver Dri. Corresponding to this operation, the differential line receiver Rec of the serial transmission element 70R that is chip-selected receives the composite differential signal DIF, and the received composite differential signal DIF is restored to lighting data in the deserializer 61R. Then, the restored lighting data is output to the LED driver.

  Next, the one-chip microcomputer 40 outputs the second address value to the address decoder 63, sets the corresponding lighting data to the parallel port Po ', and maintains the transmission command signal CTL at the L level for a predetermined time. The same is true for the following, and the same transmission operation is repeated for the N serial transmission elements 70R, thereby completing the scheduled processing for updating the N × 16 lamp lighting states.

  As confirmed from the above operation, the embodiment of FIG. 15 has an advantage that the control burden of the one-chip microcomputer 40 is greatly reduced. Moreover, the number of signal lines to the serial transmission element 70R is three (DIF + CSi), and the device configuration can be greatly simplified. Furthermore, since the LVDS signal is used, it is strong against common mode noise, and troubles in the radio law are prevented.

<When using another serial transmission element>
Incidentally, the serial transmission element shown in FIG. 15 inputs / outputs 16-bit parallel data, but it is also preferable to use a serial transmission element 71 that processes 2-byte parallel data in units of 1 byte. .

  FIG. 16A shows a circuit example in this case. The serial transmission element 71 includes an oscillation circuit OSC that generates an operation clock, an 8-bit input / output buffer 65 (65T / 65R), and a 16-bit circuit. It includes a serializer / deserializer 66 (66T / 66R) that handles data, a clock extraction circuit 67, a differential line driver Dri, a differential line receiver Rec, and the like. In addition, operation control terminals TXEN and RXEN, and upper and lower enable terminals LEN_U and LEN_L for defining whether the input / output data is an upper byte or a lower byte of 16-bit data are provided.

  Here, the serial transmission element 71 on the left side of FIG. 16A whose operation control terminal TXEN is at the L level performs a transmission operation, and the serial transmission element 71 on the right side of FIG. 16A where the operation control terminal RXEN is at the L level. Performs the receiving operation.

  Note that the serializer / deserializer 66 (66T / 66R) and the clock extraction circuit 67 function in the same manner as in the case of the serial transmission element 70 of FIG. 15, for example, a control command having a 2-byte length is embedded in the clock shown in FIG. Is transmitted as a serial signal. Here, since the control command CMD is transmitted from the upstream control board to the downstream control board, the strobe signal STB indicating that the control command CMD has been transmitted is also transmitted to the downstream control board.

  When the upstream control unit transmits a control command, the upstream computer element outputs the first byte of the 2-byte control command and then activates one of the upper and lower enable terminals LEN_U and LEN_L. To do. Then, in the serial transmission element 70, the control command for the first byte is acquired in the input buffer 65T, and the transfer operation of the control command for the first byte to the serializer 66T is started.

  Therefore, after waiting until the transfer operation for the first byte is completed, the upstream computer element outputs the second byte of the control command and activates the other side of the upper and lower enable terminals LEN_U and LEN_L. Then, in the serial transmission element 70, the control command for the second byte is acquired in the input buffer 65T, and the transfer operation of the control command for the second byte to the serializer 66T is started. Further, serial transmission is started for a control command having a length of 2 bytes, and LVDS signals are output in time sequence from the differential line driver Dri.

  The output LVDS signal is received by the differential line receiver Rec of the serial transmission element 71, and the clock extraction circuit 67 and the deserializer 66R function, so that a 2-byte control command is converted into parallel data, and the output buffer Stored in 65R.

  On the other hand, the computer element of the downstream control board that has received the strobe signal STB acquires a control command from the output buffer 65R for each byte. In this case, the downstream computer element activates the upper enable terminal LEN_U to acquire the upper 1 byte, and activates the lower enable terminal LEN_L to acquire the lower 1 byte.

  In the above description, the clock embedding method is adopted. However, the LVDS signal is not particularly required to be a clock embedded serial signal. For example, the clock extraction circuit 67 is shown in FIG. If a circuit configuration similar to that of the reproduction clock generation unit 80 and the signal reproduction unit 81 shown in FIG.

  In addition, in FIG. 16A, transmission of the control command has been described. However, it is also preferable that the chance button 11 as the frame side member GM1 and other switch signals are collectively transmitted using the serial transmission element 71. is there.

  FIG. 16B shows a serial transmission element 71T in transmission mode that receives the chance button 11 and other switch signals, and a serial transmission element 71R in reception mode that is arranged in the effect control unit 22 '. Although not particularly limited, the switch signal has a maximum of 16 bits and is acquired by the one-chip microcomputer 40 of the effect control unit 22 'every 8 bits.

  In the circuit configuration of FIG. 16B, an oscillation circuit OSC, an octal counter 90, and a 3-8 decoder 91 are provided in the vicinity of the serial transmission element 71T. Here, the oscillation period T of the oscillation circuit OSC is set to about 1 mS to 10 mS, for example, corresponding to the sampling period of the switch signal.

In this case, from 3-8 decoder 91, respectively, for each 8 × T, the decoded output _{OT 0, OT 1, ··· OT} 7 is outputted, the decoded output OT ₀ is the upper enable terminal LEN_U is supplied, the decoded output OT ₁ is supplied to the lower enable terminal LEN_L. The decode output OT ₇ is transmitted to the effect control unit 22 ′ as a notification signal RDY indicating the start of transmission.

  In this circuit configuration, the upper enable terminal LEN_U and the lower enable terminal LEN_L are activated in this order every 8 × T (about 1 mS to 10 mS) corresponding to the oscillation period T of the oscillation circuit OSC. Therefore, a 2-byte long switch signal is acquired in the input buffer 65T of the serial transmission element 71T in the order of the upper byte → the lower byte, and is embedded in the clock or other format via the serializer 66T and the differential line driver Dri. The LVDS signal is transmitted toward the effect control unit 22 ′. On the other hand, the serial transmission element 71R that receives the LVDS signal restores the received LVDS signal into a 2-byte switch signal via the differential line receiver Rec and the deserializer 66R.

Then, after 6 × T after the lower enable terminal LEN_L becomes the active level, the decode output OT ₇ (notification signal RDY) becomes the active level. This switch signal is acquired for each byte.

  In the circuit configuration of FIG. 16B, it is necessary to transmit the notification signal RDY from the terminal device side to the effect control unit. However, if the serial transmission element 71 includes the flag register 93 indicating the completion of the operation of the deserializer 66R, the one-chip microcomputer of the effect control unit 22 ′ refers to the flag register 93 to know the completion of reception of the LVDS signal. And transmission of the notification signal RDY can be made unnecessary.

  As described above, in FIGS. 15 to 16, the circuit configuration for realizing the differential transmission using the serial transmission element 71 has been described. However, (1) When there is no concern about noise, (2) When the transmission distance is short (3) When it is desired to emphasize simplicity, a single-ended signal may be transmitted instead of the differential signal. In this case, there is a great merit that the control command and the switch signal can be transmitted through one signal line.

  Although various embodiments have been described above, it goes without saying that the circuit configuration and circuit operation method for transmitting the switch signal and the lighting signal can also be used for transmitting the control command CMD. In addition, although various embodiments have been described here by taking a bullet feeding game machine as an example, the application of the present invention is not limited to a bullet ball game machine.

GM gaming machine CK clock signal CMD control command 21 upstream control means 22 downstream control means

Claims (10)

A gaming machine that executes a lottery process based on a predetermined switch signal and executes a gaming operation corresponding to the lottery result,
An upstream control means for transmitting a control command for specifying the lottery result, and a downstream control means for receiving the control command,
A gaming machine, wherein the control command is configured to be transmitted in the form of an LVDS signal.   The gaming machine according to claim 1, wherein a transmission clock that specifies a break position of each bit of the control command is transmitted in the form of an LVDS signal corresponding to the control command.   The gaming machine according to claim 1, wherein a transmission path of a transmission clock that specifies a break position of each bit of the control command is not provided.   The game according to any one of claims 1 to 3, wherein a notification signal for notifying transmission of an LVDS signal is transmitted from the upstream control means to the downstream control means in response to the transmission of the control command. Machine.   The gaming machine according to any one of claims 1 to 4, wherein a serial transmission element that converts a parallel data control command into an LVDS signal format and outputs the same is arranged in the upstream control means.   The gaming machine according to any one of claims 1 to 5, wherein a serial transmission element that receives an LVDS signal, converts it into a parallel data control command, and outputs the parallel data control command is arranged in the downstream control means.   7. The gaming machine according to claim 1, wherein the LVDS signal is a composite signal obtained by superimposing a transmission clock on a serial control command.   The gaming machine according to claim 1, wherein the LVDS signal is a composite signal in which a start bit is added to a serial control command.   The control command has a length of a plurality of bytes, and is configured to be supplied to the serial transmission element of the upstream control unit for each byte and to be acquired from the serial transmission element of the downstream control unit for each byte. The gaming machine according to any one of 1 to 8. The control command having a length of a plurality of bytes is configured to be supplied to the serial transmission element of the upstream side control means in one process and acquired from the serial transmission element of the downstream side control means in one process. 8. The gaming machine according to any one of 8.

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