JP2015073135A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method which allows simple continuity inspection.SOLUTION: A manufacturing method of a semiconductor device 1 comprises: a process of providing a semiconductor chip 3 on a first surface of a wiring board 2 which has first wiring and second wiring electrically isolated from the first wiring; a process of forming an encapsulation resin layer 5 on the first surface so as to encapsulate the semiconductor chip 3; a process of forming a conductive layer which is electrically connected to the first wiring and the second wiring and covers at least a part of the wiring board 2 and the encapsulation resin layer 5; and a process of forming on a second surface of the wiring board 2, an external connection terminal 6 including a first terminal electrically connected to the first wiring and a second terminal electrically connected to the second wiring. In the manufacturing method of the semiconductor device 1, the conductive layer is formed in a manner such that the second wiring is electrically isolated with the first wiring except between the conductive layers.

Description

  Embodiments described herein relate generally to a method for manufacturing a semiconductor device.

  In a semiconductor device used for communication equipment or the like, a structure in which a surface is covered with a conductive shield layer is used in order to suppress electromagnetic interference such as EMI (Electro Magnetic Interference). In order to obtain a sufficient magnetic field shielding effect with the above structure, it is preferable to electrically connect the conductive shield layer to the ground wiring and to release electromagnetic noise to the outside via the ground wiring.

  At this time, the magnetic field shielding effect may not be obtained if the electrical connection between the conductive shield layer and the ground wiring is insufficient. For this reason, it is effective to perform a test (conductivity test) on whether or not the electrical connection between the conductive shield layer and the ground wiring is sufficient, and to select a semiconductor device that can obtain a sufficient magnetic field shielding effect. The continuity test is performed by bringing the tester terminal into contact with the external connection terminal electrically connected to the ground wiring and the conductive shield layer, and measuring the resistance value between the external connection terminal and the conductive shield layer. Done. Such an inspection method is inconvenient because a dedicated measuring instrument must be used, and a part of the surface of the conductive shield layer may be damaged. Therefore, a simpler and less damaged inspection method is required.

US Patent Application Publication No. 2012/015687

  The problem to be solved by the present invention is to provide a method of manufacturing a semiconductor device capable of simply conducting a continuity test.

  A method of manufacturing a semiconductor device according to an embodiment includes a step of providing a semiconductor chip on a first surface of a wiring board having a first wiring and a second wiring electrically isolated from the first wiring, Forming a sealing resin layer on the first surface so as to seal the chip; electrically connected to each of the first wiring and the second wiring; and sealing at least a part of the wiring substrate. A step of forming a conductive layer covering the stop resin layer; and a first terminal electrically connected to the first wiring and the second wiring electrically connected to the second surface of the wiring board; Forming an external connection terminal including the second terminal. In the method for manufacturing a semiconductor device, the conductive layer is formed so that the second wiring is electrically separated from the first wiring except between the conductive layer.

It is a perspective view which shows a semiconductor device. It is sectional drawing which shows a semiconductor device. It is an upper surface schematic diagram of a wiring board. It is an upper surface schematic diagram of a wiring board. It is sectional drawing which shows the other example of a semiconductor device. It is sectional drawing which shows the other example of a semiconductor device. It is sectional drawing which shows the other example of a semiconductor device. It is sectional drawing which shows the other example of a semiconductor device. It is a figure which shows the measurement result of resistance value.

  The semiconductor device of the embodiment will be described below with reference to the drawings. FIG. 1 is a perspective view showing a semiconductor device, and FIG. 2 is a cross-sectional view of the semiconductor device shown in FIG.

  A semiconductor device 1 shown in FIGS. 1 and 2 includes a wiring substrate 2 having a first surface and a second surface, and a semiconductor chip 3 having electrode pads and provided on the first surface of the wiring substrate 2. A sealing resin layer 5 provided on the first surface of the wiring substrate 2 so as to seal the semiconductor chip 3, an external connection terminal 6 provided on the second surface, and the wiring substrate 2. A conductive shield layer 7 covering at least a part of the side surface and the sealing resin layer 5 is provided, and a bonding wire 8A and a bonding wire 8B are provided. The first surface of the wiring board 2 corresponds to the upper surface of the wiring board 2 in FIG. 2, and the second surface corresponds to the lower surface of the wiring board 2 in FIG. The surface and the second surface face each other.

  The wiring board 2 includes an insulating layer 21 provided between the first surface and the second surface, a wiring layer 22 provided on the first surface, and a wiring layer 23 provided on the second surface. A via 24 provided through the insulating layer 21, a solder resist layer 28 provided on the wiring layer 22, and a solder resist layer 29 provided on the wiring layer 23.

  As the insulating layer 21, for example, a silicon substrate, a glass substrate, a ceramic substrate, a resin substrate such as epoxy, or the like can be used. Moreover, as the sealing resin layer 5, an insulating organic resin material etc. can be used, for example.

  The wiring layer 22 and the wiring layer 23 are provided with signal wiring, power supply wiring, ground wiring, and the like, for example. Each of the wiring layer 22 and the wiring layer 23 is not limited to a single layer structure, and may have a stacked structure in which a plurality of conductive layers are stacked with an insulating layer interposed therebetween. For the wiring layer 22 and the wiring layer 23, for example, a copper foil, a conductive paste containing silver or copper is used, and nickel plating, gold plating, or the like is applied to the surface as necessary.

  The wiring layer 22 includes a wiring 22A and a wiring 22B. The wiring 22A has a function as a first ground wiring, and the wiring 22B has a function as a second ground wiring. Note that the value of the ground potential supplied to the wiring 22A may be different from the value of the ground potential supplied to the wiring 22B. Further, the wiring 22A and the wiring 22B have connection pads. The wiring layer 23 includes a wiring 23A and a wiring 23B. The wiring 23A and the wiring 23B have connection pads. Note that the wiring 23A may have a function as a first ground wiring, and the wiring 23B may have a function as a second ground wiring.

  A plurality of vias 24 are provided through the insulating layer 21. The via 24 has, for example, a conductor layer provided on the inner surface of an opening that penetrates the insulating layer 21 and a hole filling material filled inside the conductor layer. For the conductor layer, for example, a copper foil or a conductive paste containing silver or copper is used, and the surface is subjected to nickel plating, gold plating, or the like as necessary. The hole filling material is formed using, for example, an insulating material or a conductive material. Note that the via 24 may be formed by filling the through hole with a metal material (copper or the like) by plating or the like.

  Furthermore, as the external connection terminal 6, for example, a signal terminal, a power supply terminal, a ground terminal, and the like are provided. For example, the external connection terminal 6 includes a ground terminal 6A and a ground terminal 6B. The ground terminal 6A is electrically connected to the wiring 22A, and the ground terminal 6B is electrically connected to the wiring 22B. In other words, the ground terminal 6A is electrically connected to the first ground wiring, and the ground terminal 6B is electrically connected to the second ground wiring. The external connection terminal 6 has a solder ball 4. The solder ball 4 is provided on the connection pad of the wiring layer 23. A land may be provided instead of the solder ball 4.

  The conductive shield layer 7 has a function of shielding unnecessary electromagnetic waves radiated from the semiconductor chip 3 and the like and preventing leakage to the outside. As the conductive shield layer 7, for example, a metal layer having a low resistivity is preferably used. For example, a metal layer containing copper, silver, nickel, or the like is preferably used. By using a metal layer having a low resistivity for the conductive shield layer 7, it is possible to suppress leakage of unnecessary electromagnetic waves radiated through the semiconductor chip 3 and the wiring substrate 2.

  The conductive shield layer 7 is formed by applying a conductive paste by, for example, a transfer method, a screen printing method, a spray coating method, a jet dispensing method, an ink jet method, an aerosol method, or the like. The conductive paste preferably contains, for example, silver or copper and a resin as main components and has a low resistivity. Alternatively, the conductive shield layer 7 may be formed by applying a method of forming a film of copper, nickel, or the like by an electroless plating method or an electrolytic plating method, or a method of forming a film of copper, etc. by a sputtering method.

  The thickness of the conductive shield layer 7 is preferably set based on its resistivity. For example, it is preferable to set the thickness of the conductive shield layer 7 so that the sheet resistance value obtained by dividing the resistivity of the conductive shield layer 7 by the thickness is 0.5Ω or less. By setting the sheet resistance value of the conductive shield layer 7 to 0.5Ω or less, leakage of unnecessary electromagnetic waves from the sealing resin layer 5 can be suppressed with good reproducibility. If necessary, the conductive shield layer 7 may be covered with a protective layer having excellent corrosion resistance and migration resistance. As the protective layer, polyimide resin or the like can be used.

  The bonding wire 8A is electrically connected to the wiring 22A and the semiconductor chip 3, and the bonding wire 8B is electrically connected to the wiring 22B and the semiconductor chip 3. Note that the present invention is not limited to this, and at least the connection pads or the semiconductor chip 3 of the wiring board 2 and the first ground wiring or the second ground wiring may be electrically connected by the bonding wire 8A.

  Furthermore, in the semiconductor device of this embodiment, each of the first ground wiring and the second ground wiring is electrically connected to the conductive shield layer 7, and the first ground wiring and the second ground wiring are mutually connected. Electrically separated.

  For example, FIG. 3 is a schematic top view of the wiring board 2. In FIG. 3, for convenience, the wiring 22A and the wiring 22B are shown, and other components are omitted. The region 30 is a region where the semiconductor chip 3 and various wirings are provided.

  In FIG. 3, the wiring 22 </ b> A and the wiring 22 </ b> B are arranged along the periphery of the wiring board 2 so as to be electrically separated from each other. The wiring 22A is electrically connected to the ground terminal 6A via the via 24A in the contact portion 20A, and the wiring 22B is electrically connected to the ground terminal 6B via the via 24B in the contact portion 20B. Note that a plurality of each of the contact part 20A and the contact part 20B may be provided.

  Furthermore, the side surface of the wiring 22 </ b> A and the side surface of the wiring 22 </ b> B are exposed on the side surface of the wiring board 2. Thereby, the side surface of the wiring 22 </ b> A and the side surface of the wiring 22 </ b> B are in contact with the conductive shield layer 7. In this way, unnecessary electromagnetic waves are released to the outside through the first ground wiring and the second ground wiring by electrically connecting the first ground wiring and the second ground wiring to the conductive shield layer 7. Can do. The structure is not limited to this, and the side surface of the wiring 23 </ b> A and the side surface of the wiring 23 </ b> B may be in contact with the conductive shield layer 7.

  Further, the wiring 22 </ b> A has a plurality of exposed portions 10 </ b> A exposed on the side surface of the wiring substrate 2, and the wiring 22 </ b> B has a plurality of exposed portions 10 </ b> B exposed on the side surface of the wiring substrate 2 along the periphery of the wiring substrate 2. By increasing the area of the wiring 22A and the area of the wiring 22B exposed on the side surface of the wiring board 2, the contact resistance between the wiring 22A and the wiring 22B and the conductive shield layer 7 can be lowered, and the magnetic field shielding effect is enhanced. be able to.

  In a semiconductor device provided with a conductive shield layer, for example, in order to inspect the presence or absence of a shielding effect by the conductive shield layer, there is a case where a continuity test between the conductive shield layer and the ground terminal is performed. A general inspection method is to test the continuity between the conductive shield layer and the ground terminal by bringing a tester into contact with the conductive shield layer and the ground terminal and measuring the resistance value between the conductive shield layer and the ground terminal. I do. In this case, it is necessary to use a dedicated device, and the conductive shield layer may be damaged by inspection.

  In the semiconductor device of the present embodiment, the ground wiring is divided into two systems (first ground wiring and second ground wiring), the first ground wiring is electrically connected to the ground terminal 6A, and the second ground wiring is used. Are electrically connected to the ground terminal 6B, and the first ground wiring and the second ground wiring are electrically connected to the conductive shield layer 7. Therefore, for example, the resistance value between the ground terminal 6A and the ground terminal 6B is measured by bringing a tester into contact with the ground terminal 6A and the ground terminal 6B, and the first ground wiring and the second ground are measured based on the measurement result. The connection state between the wiring and the conductive shield layer 7 can be inspected. Therefore, the inspection can be performed without using a dedicated device. Further, since the tester is not brought into contact with the conductive shield layer 7, damage to the conductive shield layer 7 due to inspection can be suppressed.

  In the present embodiment, the example in which the ground wiring is divided into two systems has been described. However, the present invention is not limited to this, and the wiring may be divided into three or more systems (for example, four systems). The semiconductor device of the present embodiment is preferably applied to, for example, a portable information communication terminal such as a smartphone or a tablet information communication terminal.

  Further, in the semiconductor device of the present embodiment, the first ground wiring and the second ground wiring are arranged in a conductive shield by arranging the first ground wiring or the second ground wiring along the periphery of the wiring board 2. It functions as a layer and can suppress leakage of unnecessary electromagnetic waves radiated through the semiconductor chip 3 and the wiring substrate 2.

  FIG. 9 shows a measurement result of the resistance value between the ground terminal 6A and the ground terminal 6B when a tester is brought into contact with the ground terminal 6A and the ground terminal 6B in a plurality of semiconductor device samples. As shown in FIG. 9, the measured sample of the semiconductor device is a sample in which the resistance value can be measured (here, a sample having a resistance value of 0.1Ω to 0.3Ω (Sample 1)) and an open state in which the resistance value cannot be measured. It is divided into a sample (Sample 2).

Further, Table 1 shows the magnetic field shielding effect of the sample belonging to Sample 1 and the sample belonging to Sample 2. Note that the magnetic field strength is a measured value obtained by scanning the measuring instrument with reference to the magnetic field strength 1 mm above the center of the semiconductor device. The magnetic field shielding effect is a value obtained from the difference between when the conductive shield layer is present and when it is absent.

  In Table 1, the magnetic field shielding effect of the sample belonging to Sample 1 is 19.9 dB, whereas the magnetic field shielding effect of the sample belonging to Sample 2 is extremely small, 7.6 dB, and the value of the magnetic field shielding effect of the sample belonging to Sample 1 is It can be seen that the value of the sample magnetic field shielding effect belonging to Sample 2 is clearly different. From this, it can be seen that by measuring the resistance value, it is possible to select a semiconductor device which is not electrically connected, that is, the magnetic field shielding effect is insufficient.

  Furthermore, in the semiconductor device of this embodiment, the magnetic field shielding effect can be further enhanced by devising the top surface layout of the wirings 22A and 22B. For example, the wiring 22 </ b> A and the wiring 22 </ b> B may be extended to a region other than the periphery of the wiring board, for example, where no other wiring is provided. At this time, the wiring 22A and the wiring 22B may have a mesh shape. As the wiring 22A and the wiring 22B are extended, leakage of unnecessary electromagnetic waves radiated through the semiconductor chip 3 and the wiring substrate 2 in the thickness direction of the semiconductor device 1 can be suppressed. Further, as shown in FIG. 4, the wiring 22B may be used as a wiring for continuity inspection. As a result, the influence on other elements connected to the ground wiring can be suppressed during the continuity test.

  Furthermore, the structure of the semiconductor device in the present embodiment is not limited to the above structure. Another structural example of the semiconductor device will be described with reference to FIGS. 5 to 8 are cross-sectional views showing other examples of the semiconductor device. 5 to 8, the same portions as those of the semiconductor device illustrated in FIG. 2 are denoted by the same reference numerals, and the description of the semiconductor device illustrated in FIG. 2 is incorporated as appropriate.

  5 includes an insulating layer 21A and an insulating layer 21B instead of the insulating layer 21 of the semiconductor device 1 shown in FIG. 2, and a conductive layer provided between the insulating layer 21A and the insulating layer 21B. 15. In addition, about the structure of the semiconductor chip 3, the sealing resin layer 5, the external connection terminal 6, the electroconductive shield layer 7, the bonding wire 8A, and the bonding wire 8B, description of the semiconductor device 1 shown in FIG. 2 is used.

  As the insulating layer 21A and the insulating layer 21B, for example, a substrate applicable to the insulating layer 21 can be used.

  The conductive layer 15 includes a conductive layer 15A and a conductive layer 15B. The conductive layer 15 </ b> A and the conductive layer 15 </ b> B are preferably overlapped with at least a part of the semiconductor chip 3. The conductive layer 15A has a function as a first ground wiring, and the conductive layer 15B has a function as a second ground wiring. The conductive layer 15A and the conductive layer 15B are preferably, for example, a solid film or a mesh film. In other words, at least one of the first ground wiring and the second ground wiring preferably has a solid film or a mesh film.

  The conductive layer 15A and the conductive layer 15B are formed, for example, by forming a resist on the same conductive film using a photolithography technique and removing a part of the conductive film using the resist as a mask. As the conductive film, for example, a material applicable to the conductive shield layer 7 is preferably used.

  The via 24A is provided through the insulating layer 21A, the conductive layer 15A, and the insulating layer 21B, and the via 24B is provided through the insulating layer 21A, the conductive layer 15B, and the insulating layer 21B. Note that the via 24 electrically connected to the signal wiring or the like is electrically separated from the conductive layer 15A and the conductive layer 15B. For example, by providing an opening in the conductive layer 15B in advance, the via 24 electrically connected to the signal wiring and the like can be electrically separated from the conductive layer 15A and the conductive layer 15B. Note that the description of the semiconductor device 1 shown in FIG. 2 is used for the configuration of the wiring 22A, the wiring 22B, the wiring 23A, the wiring 23B, the via 24A, the via 24B, the solder resist layer 28, and the solder resist layer 29.

  By providing the conductive layer 15 </ b> A and the conductive layer 15 </ b> B, the effect of suppressing leakage of unnecessary electromagnetic waves through the wiring substrate 2 can be enhanced. Furthermore, the side surface of the conductive layer 15 </ b> A and the side surface of the conductive layer 15 </ b> B are preferably in contact with the conductive shield layer 7. Thereby, since the number of connection points with the conductive shield layer 7 can be increased, connection failure between the ground terminal 6A and the ground terminal 6B and the conductive shield layer 7 can be suppressed, and the contact resistance can be lowered. Therefore, the magnetic field shielding effect can be enhanced.

  In the semiconductor device 1 shown in FIG. 6, the surface of the bonding wire 8 </ b> B of the semiconductor device 1 shown in FIG. 5 is exposed from the sealing resin layer 5 and is in contact with the conductive shield layer 7. At this time, a dummy electrode pad may be provided on the semiconductor chip 3 and the bonding wire 8B may be connected to the electrode pad. The via 24B is electrically separated from the conductive layer 15B, and the side surface of the wiring 22B is not in contact with the conductive shield layer 7. For example, by providing an opening in the conductive layer 15B in advance, the via 24B and the conductive layer 15B can be electrically separated. At this time, the side surface of the wiring 23 </ b> B or the conductive layer 15 </ b> B may not be in contact with the conductive shield layer 7. With the above structure, the ground terminal 6B becomes a continuity test terminal, and the influence on other elements connected to the ground wiring can be suppressed during the continuity test.

  Further, in the semiconductor device 1 shown in FIG. 7, the bonding wires 8 </ b> B of the semiconductor device 1 shown in FIG. 6 are electrically connected to the connection pads 22 </ b> C provided on the wiring layer 22 instead of the semiconductor chip 3. The connection pad 22C has a function as a dummy pad. With the above structure, the ground terminal 6B becomes a continuity test terminal, and the influence on other elements connected to the ground wiring can be suppressed during the continuity test.

  Further, the semiconductor device 1 shown in FIG. 8 has a shape in which the via 24A and the via 24B of the semiconductor device 1 shown in FIG. 2 are arranged on the peripheral edge of the wiring board 2 and are cut in the thickness direction (via penetration direction). It is the structure which has. The cut surface of the via 24 </ b> A is exposed at the side surface of the wiring substrate 2 and is in contact with the conductive shield layer 7, and the cut surface of the via 24 </ b> B is exposed at the side surface of the wiring substrate 2 and is in contact with the conductive shield layer 7. In the semiconductor device 1 shown in FIG. 8, the shape of the via 24A and the via 24B is cut to the middle in the thickness direction. However, the shape is not limited to this, and the shape of the via 24A and the via 24B is the thickness. You may make it the shape cut | disconnected to the last of the direction (penetration direction of the via | veer 24). Further, the cut surfaces of the via 24A and the via 24B do not necessarily pass through the center, and it is sufficient that a part of the via is included in the cut surface.

  By making the cut surfaces of the via 24A and the via 24B in contact with the conductive shield layer 7, the contact area between the via 24A and the via 24B and the conductive shield layer 7, in other words, the first ground wiring and the second ground Since the contact area between the wiring and the conductive shield layer 7 can be increased, the contact resistance can be reduced and the magnetic field shielding effect can be enhanced. Instead of the insulating layer 21 of the semiconductor device 1 shown in FIG. 8, the insulating layer 21A and the insulating layer 21B of the semiconductor device 1 shown in FIG. 5 may be provided, and the conductive layer 15A and the conductive layer 15B may be provided.

  In addition, the said embodiment is an example and does not intend limiting the range of invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

1 semiconductor device, 2 wiring board, 3 semiconductor chip, 4A solder ball, 4B solder ball, 5 sealing resin layer, 6 external connection terminal, 6A ground terminal, 6B ground terminal, 7 conductive shield layer, 8A bonding wire, 8B Bonding wire, 10A exposed portion, 10B exposed portion, 15A conductive layer, 15B conductive layer, 20A contact portion, 20B contact portion, 21 insulating layer, 21A insulating layer, 21B insulating layer, 22 wiring layer, 22A wiring, 22B wiring, 22C Connection pad, 23 wiring layer, 23A wiring, 23B wiring, 24 via, 24A via, 24B via, 30 regions

Claims (4)

Providing a semiconductor chip on a first surface of a wiring board having a first wiring and a second wiring electrically isolated from the first wiring;
Forming a sealing resin layer on the first surface so as to seal the semiconductor chip;
Forming a conductive layer electrically connected to each of the first wiring and the second wiring and covering at least a part of the wiring substrate and the sealing resin layer;
An external connection terminal comprising a first terminal electrically connected to the first wiring and a second terminal electrically connected to the second wiring on the second surface of the wiring board. A method of manufacturing a semiconductor device comprising:
A manufacturing method of a semiconductor device, wherein the conductive layer is formed so that the second wiring is electrically separated from the first wiring except between the conductive layer and the conductive layer. The wiring board is
An insulating layer provided between the first surface and the second surface;
A via provided through the insulating layer and electrically connected to the first wiring or the second wiring;
Exposing at least one of the first wiring or the second wiring and the via to a side surface of the wiring board;
2. The method of manufacturing a semiconductor device according to claim 1, wherein the conductive layer is formed so as to be in contact with at least one of the first wiring or the second wiring exposed on a side surface of the wiring substrate and the via. . Further comprising the step of forming a bonding wire for electrically connecting the connection pad or the semiconductor chip of the wiring board and the first wiring or the second wiring;
Forming the sealing resin layer such that the bonding wire is exposed on the surface of the sealing resin layer;
The method for manufacturing a semiconductor device according to claim 1, wherein the conductive layer is formed so as to be in contact with the bonding wire exposed on the surface of the sealing resin layer.   4. The device according to claim 1, wherein at least one of the first wiring and the second wiring has a solid film or a mesh film overlapping with at least a part of the semiconductor chip. 5. A method for manufacturing a semiconductor device.

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