JP2015073047A - Variable capacity device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve a variable capacity device having a structure capable of easily coping with a plurality of initial capacities.SOLUTION: A variable capacity device includes: a first conductor layer; a dielectric layer formed on the first conductor layer; and a second conductor layer formed on the dielectric layer. The variable capacity device includes one or more variable capacity elements each varying its capacity by applying a voltage between the first conductor layer and the second conductor layer. Then, the dielectric layer is divided into two or more areas in the same layer, and the conductor layer is formed on at least one predetermined area of the dielectric layer.

Description

  The present invention relates to a variable capacitance device.

  A variable capacitance device including one or more variable capacitance elements using a thin film has been proposed. Since the initial capacity of the variable capacity device, that is, the capacity in a state where no voltage for capacity control is applied, differs depending on the application, typically, a plurality of types of variable capacity devices are designed and manufactured. However, it takes time and effort to design each initial capacity and determine the manufacturing conditions.

Japanese Patent Laying-Open No. 2005-064437 JP 2010-055570 A JP 2011-119482 A JP 2008-066682 A

  Accordingly, it is an object of the present invention to provide a variable capacitance device having a structure that can easily cope with a plurality of initial capacitances.

  A variable capacitance device according to the present invention includes a first conductor layer, a dielectric layer formed on the first conductor layer, and a second conductor layer formed on the dielectric layer. One or more variable capacitance elements that change the capacitance by applying a voltage between the first conductor layer and the second conductor layer are provided. The dielectric layer is divided into two or more regions in the same layer, and the second conductor layer is formed on at least one predetermined region of the dielectric layer.

  In this way, if the dielectric layer is divided into a plurality of regions, the design is changed so that the region used to realize the desired capacitance is selected and the second conductor layer is formed on the selected region. Therefore, it is possible to easily cope with the change of the initial capacity.

  In this variable capacitance device, 2n (n is an integer of 1 or more) variable capacitance elements are connected in series, and the second conductive layer is connected to the variable capacitance elements forming a pair, The first conductor layer may be connected between the pair of variable capacitance elements. In this way, an efficient structure can be obtained when variable capacitance elements are connected in series.

  Further, in the present variable capacitance device, the initial capacitance of the first variable capacitance element and the initial capacitance of the 2nth variable capacitance element coincide, and the initial capacitance of the nth variable capacitance element and the (n + 1) th variable capacitance element. In some cases, the initial capacitances of the first and 2nth variable capacitance elements are equal to or less than the initial capacitances of the nth and n + 1th variable capacitance elements. In this way, even if a signal having a large amplitude is input, it can be dealt with.

  Further, in the variable capacitance device, the first conductor layer is connected to the first external terminal for applying the first voltage via the first resistance layer, and the second conductor layer includes the second conductor layer. It may be connected to a second external terminal for applying the second voltage via the resistance layer. If it does in this way, a capacity | capacitance can be specifically changed with an applied voltage.

  Further, in the variable capacitance device, the areas of the two or more regions described above may be different from each other. In this way, variations in initial capacity can be increased. It is also possible to lower the equivalent series resistance.

  The configuration described above will be specifically described in the following embodiment, but is not limited to the embodiment.

  According to one aspect, a variable capacitance device having a structure that can easily cope with a plurality of initial capacitances can be obtained.

FIG. 1 is a plan view of the variable capacitance device according to the first embodiment. FIG. 2 is a diagram illustrating an equivalent circuit of the variable capacitance device according to the first embodiment. FIG. 3 is a diagram showing an AA ′ cross section of the variable capacitance device in FIG. 1. FIG. 4 is a diagram showing a BB ′ cross section of the variable capacitance device in FIG. 1. FIG. 5 is a diagram schematically illustrating an example of a current route between regions. FIG. 6 is a diagram for explaining variations such as gaps between regions. FIG. 7 is a diagram illustrating an equivalent series resistance ESR for each variation such as a gap between regions. FIG. 8 is a diagram illustrating a second variation of the variable capacitance device according to the first embodiment. FIG. 9 is a diagram showing a BB ′ cross section of the variable capacitance device in FIG. 8. FIG. 10 is a diagram illustrating a third variation of the variable capacitance device according to the first embodiment. FIG. 11 is a diagram illustrating a fourth variation of the variable capacitance device according to the first embodiment. FIG. 12 is a diagram illustrating a fifth variation of the variable capacitance device according to the first embodiment. FIG. 13 is a diagram illustrating a sixth variation of the variable capacitance device according to the first embodiment. FIG. 14 is a diagram illustrating a table summarizing variations according to the first embodiment. FIG. 15 is a diagram showing a basic variation of the variable capacitance device according to the second embodiment. 16 is a diagram showing an equivalent circuit of the variable capacitance device in FIG. FIG. 17 is a diagram illustrating a second variation of the variable capacitance device according to the second embodiment. FIG. 18 is a diagram illustrating a third variation of the variable capacitance device according to the second embodiment. FIG. 19 is a diagram illustrating a fourth variation of the variable capacitance device according to the second embodiment. FIG. 20 is a diagram illustrating a fifth variation of the variable capacitance device according to the second embodiment. FIG. 21 is a diagram illustrating a sixth variation of the variable capacitance device according to the second embodiment. FIG. 22 is a diagram illustrating a seventh variation of the variable capacitance device according to the second embodiment. FIG. 23 is a diagram illustrating an eighth variation of the variable capacitance device according to the second embodiment. FIG. 24 is a diagram illustrating a ninth variation of the variable capacitance device according to the second embodiment. FIG. 25 is a diagram illustrating a tenth variation of the variable capacitance device according to the second embodiment. FIG. 26 is a diagram illustrating an eleventh variation of the variable capacitance device according to the second embodiment. FIG. 27 is a diagram illustrating a twelfth variation of the variable capacitance device according to the second embodiment. FIG. 28 is a diagram showing a thirteenth variation of the variable capacitance device according to the second embodiment. FIG. 29 is a diagram illustrating a fourteenth variation of the variable capacitance device according to the second embodiment. FIG. 30 is a diagram illustrating a fifteenth variation of the variable capacitance device according to the second embodiment. FIG. 31 is a diagram illustrating a sixteenth variation of the variable capacitance device according to the second embodiment. FIG. 32 is a diagram illustrating a seventeenth variation of the variable capacitance device according to the second embodiment. FIG. 33 is a diagram illustrating an eighteenth variation of the variable capacitance device according to the second embodiment. FIG. 34 is a diagram showing a nineteenth variation of the variable capacitance device according to the second embodiment. FIG. 35 is a diagram illustrating a twentieth variation of the variable capacitance device according to the second embodiment. FIG. 36 is a diagram illustrating a twenty-first variation of the variable capacitance device according to the second embodiment. FIG. 37 is a diagram showing a table summarizing variations according to the second embodiment.

[Embodiment 1]
FIG. 1 is a plan view showing an outline of the variable capacitance device according to the present embodiment. The variable capacitance device is formed on the substrate, but is not shown in FIG. Lower conductors 14a to 14c for four variable capacitance elements are formed on the substrate. The lower conductor 14c functions as a connection portion to the first electrode and other portions of the first variable capacitance element. The lower conductor 14b functions as a connection portion to the first electrode and other portions of the second and third variable capacitance elements. The lower conductor 14a functions as a connection portion to the first electrode and other portions of the fourth variable capacitance element.

  On the lower conductor 14c, regions 20a and 20b of a dielectric layer for the first variable capacitance element are formed. As shown in FIG. 1, the dielectric layer is separated into regions 20a and 20b having two different areas. Similarly, regions 21a and 21b of a dielectric layer for the second variable capacitance element are formed on the lower conductor 14b. As shown in FIG. 1, the dielectric layer is divided into two regions 21a and 21b having different areas. In the example of FIG. 1, the first variable capacitance element and the second variable capacitance element are paired, and the area of the dielectric layer region 20a and the area of the dielectric layer region 21b are the same. Thus, the area of the dielectric layer region 20b and the area of the dielectric layer region 21a are the same.

  Furthermore, dielectric layer regions 22a and 22b for the third variable capacitance element are formed on the lower conductor 14b. As shown in FIG. 1, the dielectric layer is separated into regions 22a and 22b having two different areas. Thus, the second variable capacitance element and the third variable capacitance element share the lower conductor 14b. Similarly, regions 23a and 23b of a dielectric layer for the fourth variable capacitance element are formed on the lower conductor 14a. As shown in FIG. 1, the dielectric layer is separated into regions 23a and 23b having two different areas.

  In the example of FIG. 1, the third variable capacitor and the fourth variable capacitor are paired, and the area of the dielectric layer region 22a and the area of the dielectric layer region 23b are the same. Thus, the area of the dielectric layer region 22b and the area of the dielectric layer region 23a are the same.

  Although not shown in FIG. 1, a conductor layer functioning as a second electrode is also formed on each region of the dielectric layer.

  Also, upper conductors 10a and 10c functioning as wiring layers are formed on the upper side of the dielectric layer. Specifically, the upper conductor 10a is formed above the regions 20a and 20b of the dielectric layer of the first variable capacitor and the regions 21a and 21b of the dielectric layer of the second variable capacitor. Yes. An upper conductor 10c is formed above the dielectric layer regions 22a and 22b of the third variable capacitance element and the dielectric layer regions 23a and 23b of the fourth variable capacitance element. Thus, the first and second variable capacitors share the upper conductor 10a, and the third and fourth variable capacitors share the upper conductor 10c.

  The upper conductor 10e is connected to the lower conductor 14c via vias 18d and 18c, and is further connected to a signal input pad 12d. The upper conductor 10d is connected to the lower conductor 14a via vias 18a and 18b, and is further connected to a signal output pad 12b.

  As described above, the first to fourth variable capacitance elements are formed in series between the pad 12d and the pad 12b, and a high-frequency signal flows.

  The lower conductor 14c is also connected to the resistance film 16e, the resistance film 16e is connected to the upper conductor 10f, and the upper conductor 10f is connected to the ground pad 12c. The lower conductor 14b is connected to the resistive film 16d, and the resistive film 16d is connected to the pad 12c via the upper conductor 10f. Further, the lower conductor 14a is connected to the resistance film 16c, the resistance film 16c is connected to the upper conductor 10f, and the upper conductor 10f is connected to the pad 12c. As described above, the lower conductors 14a to 14c are grounded via the resistance films 16c to 16e in a direct current manner.

  Further, the upper conductor 10a is connected to the resistance film 16a, the resistance film 16a is connected to the upper conductor 10b, and the upper conductor 10b is connected to the pad 12a for applying control voltage. The upper conductor 10c is connected to the resistance film 16b, and the resistance film 16b is connected to the pad 12a via the upper conductor 10b. As described above, the control voltage is applied to the upper electrodes 10a and 10c through the resistance films 16a and 16b in a direct current manner.

  The variable capacitance device shown in FIG. 1 is represented by an equivalent circuit as shown in FIG. The variable capacitance element groups C1 to C4 are connected in series between the high frequency signal input terminal and the high frequency signal output terminal, and each of the variable capacitance element groups C1 to C4 has a small initial capacitance. A capacitive element and a variable capacitive element having a large initial capacitance. One end of each of the variable capacitance element groups C1 to C4 is connected to a ground terminal via a resistor R, and the other end is connected to a control voltage application terminal via a resistor R. The capacitance of each of the variable capacitance element groups C1 to C4 changes according to the voltage applied between these terminals.

FIG. 3 is a view showing the AA ′ cross section in FIG. The substrate 30 is a Si substrate with a SiO ₂ thermal oxide film. For example, the Si substrate has a thickness of 200 μm, and the SiO ₂ thermal oxide film has a thickness of 1 μm. Instead of the Si substrate, an insulating substrate such as quartz, alumina, sapphire, or glass, or a conductive substrate such as Si (preferably a high resistance substrate) and an insulating film formed thereon are formed.

A second insulating layer 31 is formed on the substrate 30. The second insulating layer 31 is, for example, Al ₂ O ₃ . However, the second insulating layer 31 may be a single layer or a combination of Al ₂ O ₃ , SiN, Ta ₂ O ₅ , SrTiO ₃ or the like. The thickness of the second insulating layer 31 is about 100 nm.

On the second insulating layer 31, lower conductors 14a to 14c of Pt are formed. Ti or TiO ₂ may be deposited as an adhesion layer under the Pt layer. Further, in place of Pt, a noble metal such as Ir or Ru, or a conductive oxide such as SrRuO ₃ , RuO ₂ , or IrO ₂ may be used. The thickness of the lower conductors 14a to 14c is about 250 nm.

As shown in FIG. 1, the dielectric layer of the first variable capacitance element is formed on the lower conductor 14c. In FIG. 3, the region 20b of the dielectric layer is shown. The dielectric layer is, for example, BST (BaSrTiO ₃ ) to which a small amount of Mn is added. However, PZT (PbZrTiO ₃ ) or other perovskite structure oxide may be used instead of BST.

  Similarly, a dielectric layer of the second variable capacitance element is formed on the lower conductor 14b. In FIG. 3, a region 21b of the dielectric layer is shown. Further, the dielectric layer of the third variable capacitance element is formed on the lower conductor 14b. In FIG. 3, a region 22b of the dielectric layer is shown. Further, a dielectric layer of the fourth variable capacitance element is formed on the lower conductor 14a. In FIG. 3, a region 23b of the dielectric layer is shown. The thickness of the dielectric layer is about 100 nm.

An upper electrode 32b made of Pt, for example, is formed on the dielectric layer region 20b. Further, an upper electrode 33b made of Pt, for example, is formed on the region 21b of the dielectric layer. Further, an upper electrode 34b made of Pt, for example, is formed on the region 22b of the dielectric layer. An upper electrode 35b made of Pt, for example, is formed on the region 23b of the dielectric layer. Similar to the lower conductors 14a to 14c, the upper electrodes 32b to 35b may be made of a noble metal such as Ir or Ru, or a conductive oxide such as SrRuO ₃ , RuO ₂ , or IrO ₂ . The thickness of the upper electrodes 32b to 35b is about 250 nm.

  Further, an upper conductor 10a made of Cu, for example, is formed on the upper electrodes 32b and 33b. As shown in FIG. 1, the upper conductor 10a connects the first variable capacitance element and the second variable capacitance element. An upper conductor 10c made of, for example, Cu is formed on the upper electrodes 34b and 35b. As shown in FIG. 1, the upper conductor 10c connects the third variable capacitance element and the fourth variable capacitance element. The thickness of the upper conductors 10a and 10c is about 3 μm. The upper conductors 10a and 10c may be various conductive materials such as Al.

  The lower conductor 14c is connected to the upper conductor 10e via the via 18c, and the lower conductor 14a is connected to the upper conductor 10d via the via 18a. The vias 18a and 18c are filled with, for example, Cu.

  Pads 12b and 12d are formed on the upper conductors 10e and 10d. The pads 12b and 12d are, for example, SnAg, and may be an Al—Cu alloy, Au, or a solder material. The thickness of the pads 12b and 12d is about 5 μm.

In other portions, third and fourth insulating layers 41 and 42 are formed, and the thicknesses thereof are about 3 μm, respectively. The insulating layers 41 and 42 are made of polyimide, for example, and may be various inorganic insulating films (for example, SiO ₂ and SiN) and various organic insulating films (for example, polyimide resin and BCB resin).

Note that TaN and Ta are used for the seed layer and the barrier layer formed when the variable capacitance element is formed. TiN, TaN, TiSiN, TaSiN and other nitrides, SrRuO ₃ , IrO _{2 and} other oxides may be used.

  FIG. 4 is a view showing a BB ′ cross section in FIG. 1. As shown in FIG. 4, the resistance film 16 b is formed on the second insulating layer 31. The resistance film 16b is, for example, Ta—SiN and has a thickness of about 80 nm. A high resistance film such as a Ni—Cr alloy or a Fe—Cr—Al alloy may be used. The resistance film 16b is connected to the upper conductor 10c and the upper conductor 10b. The upper conductor 10b is formed on the pad 12a.

  In addition to the dielectric layer region 23b, a dielectric layer region 23a is formed on the lower conductor 14a. An upper electrode 35a is also formed on the region 23a of the dielectric layer. An upper conductor 10c is formed on the upper electrode 35a.

  By dividing the dielectric layer into two regions in this manner, two elements are formed in parallel in each variable capacitance element group as shown in FIG. Thereby, the Q value is improved.

  Further, by dividing the dielectric layer in this way, the equivalent series resistance ESR is also lowered. For example, FIG. 5 shows the second variable capacitance element and the third variable capacitance element. For example, the current flowing through the lower conductor 14b by the gap between the regions of the dielectric layer, for example, the portion X in FIG. The ESR is reduced by increasing the number of routes (arrows).

  For example, as shown in FIG. 6, the distance h between the second variable capacitor and the third variable capacitor is not changed, and the gap g between the regions of the dielectric layer is changed, or the region of the dielectric layer is changed. FIG. 7 shows how the ESR changes when the area ratio is changed or when the gap is inserted in the horizontal direction instead of the gap in the vertical direction. Note that the total area is the same in all cases.

  The first row shows a case where the region is not divided and is a reference case. The second row shows a case where the gap is g = 5 μm and the area ratio is 1: 3, and the ESR is smaller than that in the case of the first row. Further, the third row shows a case where the gap is g = 10 μm and the area ratio is 1: 3, and the ESR is smaller than the case of the second row. Further, the fourth row shows a case where the gap is g = 20 μm and the area ratio is 1: 3, and the ESR is reduced as compared with the case of the third row. Thus, the ESR decreases as the gap g increases. However, as the gap g is increased, the size of the element increases accordingly.

  On the other hand, the fifth row shows a case where the gap g is 10 μm and the area ratio is 1: 1, and the ESR is decreased from the first row, but the gap g is increased from the same third row. doing. Thus, it is preferable that the areas of the regions are different.

  Further, the sixth row shows a case where the division direction is changed from vertical to horizontal, the gap g = 10 μm, and the area ratio is 1: 1, and the effect similar to that of the third row is obtained. . However, the size of the element also increases in this case.

  As described above, even when all the formed dielectric layers are effectively used, a preferable variable capacitance device can be obtained from the viewpoint of Q value and ESR.

  However, the region division of the dielectric layer in the present embodiment has a main point in that the initial capacitance of the variable capacitance element can be changed only by changing the shape of the upper conductors 10a and 10c.

  As shown in FIG. 8, an upper conductor 110a is formed instead of the upper conductor 10a, and an upper conductor 110c is formed instead of the upper conductor 10c. The upper conductor 110a is formed on the dielectric layer region 20b and the regions 21a and 21b, but is not formed on the region 20a. That is, in the second variable capacitance element, two elements remain configured in parallel, but the first variable capacitance element is configured by only one element. For example, when a capacitance of 100 pF is realized by the smaller region and a capacitance of 300 pF is realized by the larger region, the initial capacitance of the first variable capacitance element is 100 pF. The initial capacitance of the second variable capacitance element is 400 pF.

  Similarly, the upper conductor 110c is formed on the regions 22a and 22b and the region 23b of the dielectric layer, but is not formed on the region 23a. That is, in the third variable capacitance element, two elements remain configured in parallel, but the fourth variable capacitance element is configured by only one element. Given the premise described above, the initial capacitance of the third variable capacitance element is 400 pF, and the initial capacitance of the fourth variable capacitance element is 100 pF. In the case of FIG. 8, the initial combined capacitance is 40 pF.

  FIG. 9 shows the variable capacitance device shown in FIG. 8 with the same cross section as the BB ′ cross section shown in FIG. As can be seen from FIG. 8, the difference from FIG. 4 is that the upper conductor 110c is not formed above the region 23a of the dielectric layer and the upper electrode 35a.

  The initial capacitance of the first variable capacitance element and the initial capacitance of the fourth variable capacitance element are the same, the initial capacitance of the second variable capacitance element and the initial capacitance of the third variable capacitance element are the same, And the initial capacitance of the fourth variable capacitance element is set to be equal to or less than the initial capacitance of the second and third variable capacitance elements. Then, even if a signal with a large amplitude is input, it can be handled.

  Therefore, according to such constraint conditions, variations of the upper conductor shape as shown in FIGS. 10 to 13 can be obtained in addition to the configuration examples of FIGS. In the subsequent drawings, the upper conductors 10b and 10f, the resistor portion 16, and the pad portion 12 that do not affect the variation are omitted.

  In the configuration example of FIG. 10, the upper conductor 120a is formed instead of the upper conductor 10a, and the upper conductor 120c is formed instead of the upper conductor 10c. The upper conductor 120a is formed on the dielectric layer region 20a and the regions 21a and 21b, but is not formed on the region 20b. That is, in the second variable capacitance element, two elements remain configured in parallel, but the first variable capacitance element is configured by only one element. Given the premise described above, the initial capacitance of the first variable capacitance element is 300 pF, and the initial capacitance of the second variable capacitance element is 400 pF.

  Similarly, the upper conductor 120c is formed on the regions 22a and 22b and the region 23a of the dielectric layer, but is not formed on the region 23b. That is, in the third variable capacitance element, two elements remain configured in parallel, but the fourth variable capacitance element is configured by only one element. Given the premise described above, the initial capacitance of the third variable capacitance element is 400 pF, and the initial capacitance of the fourth variable capacitance element is 300 pF. In the case of FIG. 10, the initial combined capacitance is 85.7 pF.

  In the configuration example of FIG. 11, the upper conductor 130a is formed instead of the upper conductor 10a, and the upper conductor 130c is formed instead of the upper conductor 10c. The upper conductor 130a is formed on the regions 20a and 21b of the dielectric layer, but is not formed on the regions 20b and 21a. That is, both the first variable capacitance element and the second variable capacitance element are configured by only one element. Given the premise described above, the initial capacitance of the first variable capacitance element is 300 pF, and the initial capacitance of the second variable capacitance element is 300 pF.

  Similarly, the upper conductor 130c is formed on the regions 22b and 23a of the dielectric layer, but is not formed on the regions 22a and 23b. That is, the third variable capacitance element and the fourth variable capacitance element are configured by only one element. Given the premise described above, the initial capacitance of the third variable capacitance element is 300 pF, and the initial capacitance of the fourth variable capacitance element is 300 pF. In the case of FIG. 11, the initial combined capacitance is 75 pF.

  In the configuration example of FIG. 12, the upper conductor 140a is formed instead of the upper conductor 10a, and the upper conductor 140c is formed instead of the upper conductor 10c. The upper conductor 140a is formed on the regions 20b and 21b of the dielectric layer, but is not formed on the regions 20a and 21a. That is, both the first variable capacitance element and the second variable capacitance element are configured by only one element. Given the premise described above, the initial capacitance of the first variable capacitance element is 100 pF, and the initial capacitance of the second variable capacitance element is 300 pF.

  Similarly, the upper conductor 140c is formed on the regions 22b and 23b of the dielectric layer, but is not formed on the regions 22a and 23a. That is, the third variable capacitance element and the fourth variable capacitance element are configured by only one element. Given the premise described above, the initial capacitance of the third variable capacitance element is 300 pF, and the initial capacitance of the fourth variable capacitance element is 100 pF. In the case of FIG. 12, the initial combined capacitance is 37.5 pF.

  In the configuration example of FIG. 13, the upper conductor 150a is formed instead of the upper conductor 10a, and the upper conductor 150c is formed instead of the upper conductor 10c. The upper conductor 150a is formed on the regions 20b and 21a of the dielectric layer, but is not formed on the regions 20a and 21b. That is, both the first variable capacitance element and the second variable capacitance element are configured by only one element. Given the premise described above, the initial capacitance of the first variable capacitance element is 100 pF, and the initial capacitance of the second variable capacitance element is 100 pF.

  Similarly, the upper conductor 150c is formed on the regions 22a and 23b of the dielectric layer, but is not formed on the regions 22b and 23a. That is, the third variable capacitance element and the fourth variable capacitance element are configured by only one element. Given the premise described above, the initial capacitance of the third variable capacitance element is 100 pF, and the initial capacitance of the fourth variable capacitance element is 100 pF. In the case of FIG. 13, the initial combined capacitance is 25 pF.

  1, 8, and FIGS. 10 to 13 are summarized as shown in FIG. 14. Of these eight variations, a desired initial capacity configuration may be employed.

[Embodiment 2]
In the first embodiment, an example in which the dielectric layer for one variable capacitance element is divided into two regions has been described, but the number of divisions of the dielectric layer may be three or more. In the present embodiment, an example of the division number 3 is shown.

  For example, it is assumed that the initial capacitance of one variable capacitance element is 600 pF, and is divided into an initial capacitance of 100 pF, an initial capacitance of 200 pF, and an initial capacitance of 300 pF.

  Note that the dielectric layer in the first variable capacitor is divided into regions 201a to 201c, and the ratio of the area of the region 201a, the area of the region 201b, and the area of the region 201c is 3: 2: 1. Shall.

  Further, the dielectric layer in the second variable capacitor is divided into regions 202a to 202c, and the ratio of the area of the region 202a, the area of the region 202b, and the area of the region 202c is 1: 2: 3. Shall.

  Further, the dielectric layer in the third variable capacitance element is divided into regions 203a to 203c, and the ratio of the area of the region 203a, the area of the region 203b, and the area of the region 203c is 1: 2: 3. Shall.

  The dielectric layer in the fourth variable capacitor is divided into regions 204a to 204c, and the ratio of the area of the region 204a, the area of the region 204b, and the area of the region 204c is 3: 2: 1. Shall.

  Then, the same constraint conditions as in the first embodiment are assumed.

  As shown in FIG. 15, the first variation in the present embodiment is that the dielectric layer regions 201a to 201c for the first variable capacitance element and the dielectric layer region for the second variable capacitance element. An upper conductor 210a is formed on 202a to 202c. Similarly, the upper conductor 210c is formed on the dielectric layer regions 203a to 203c for the third variable capacitance element and the dielectric layer regions 204a to 204c for the fourth variable capacitance element. As a result, the initial capacitance of each variable capacitance element is 600 pF, and the combined capacitance is 150 pF. In the subsequent drawings, variations are not affected, and therefore the upper conductors 10b and 10f, the resistor portion 16, and the pad portion 12 shown in FIG. 1 are omitted.

  With the configuration of FIG. 15, an equivalent circuit as shown in FIG. 16 is realized. FIG. 16 differs from FIG. 2 in that for each of the variable capacitance element groups C11 to C14, a small capacitance variable capacitance device, a medium capacitance variable capacitance device, and a large capacitance variable capacitance device are connected in parallel. It becomes the composition which was done.

  Further, as shown in FIG. 17, the second variation is that the dielectric layer regions 201a and 201b for the first variable capacitance element and the dielectric layer regions 202a to 202c for the second variable capacitance element. On top of this, an upper conductor 220a is formed. Similarly, the upper conductor 220c is formed on the dielectric layer regions 203a to 203c for the third variable capacitance element and the dielectric layer regions 204a and 204b for the fourth variable capacitance element. As a result, the initial capacitance of the first and fourth variable capacitance elements is 500 pF, the initial capacitance of the second and third variable capacitance elements is 600 pF, and the combined capacitance is 136.4 pF.

  Further, as shown in FIG. 18, the third variation is that the dielectric layer regions 201a and 201b for the first variable capacitance element and the dielectric layer regions 202b and 202c for the second variable capacitance element. On top of this, an upper conductor 230a is formed. Similarly, the upper conductor 230c is formed on the dielectric layer regions 203b and 203c for the third variable capacitor and the dielectric layer regions 204a and 204b for the fourth variable capacitor. As a result, the initial capacitance of the first to fourth variable capacitance elements is 500 pF, and the combined capacitance is 125 pF.

  Further, as shown in FIG. 19, the fourth variation is that the dielectric layer regions 201a and 201c for the first variable capacitance element and the dielectric layer regions 202a to 202c for the second variable capacitance element. On top of this, an upper conductor 240a is formed. Similarly, the upper conductor 240c is formed on the dielectric layer regions 203a to 203c for the third variable capacitance element and the dielectric layer regions 204a and 204c for the fourth variable capacitance element. As a result, the initial capacitance of the first and fourth variable capacitance elements is 400 pF, the initial capacitance of the second and third variable capacitance elements is 600 pF, and the combined capacitance is 120 pF.

  Further, as shown in FIG. 20, the fifth variation is that the dielectric layer regions 201a and 201c for the first variable capacitance element and the dielectric layer regions 202b and 202c for the second variable capacitance element. On top of this, an upper conductor 250a is formed. Similarly, the upper conductor 250c is formed on the dielectric layer regions 203b and 203c for the third variable capacitor and the dielectric layer regions 204a and 204c for the fourth variable capacitor. As a result, the initial capacitance of the first and fourth variable capacitance elements is 400 pF, the initial capacitance of the second and third variable capacitance elements is 500 pF, and the combined capacitance is 111.1 pF.

  Further, as shown in FIG. 21, the sixth variation is that the dielectric layer region 201a for the first variable capacitance element and the dielectric layer regions 202a to 202c for the second variable capacitance element are overlaid. In addition, the upper conductor 260a is formed. Similarly, the upper conductor 260c is formed on the dielectric layer regions 203a to 203c for the third variable capacitance element and the dielectric layer region 204a for the fourth variable capacitance element. As a result, the initial capacitance of the first and fourth variable capacitance elements is 300 pF, the initial capacitance of the second and third variable capacitance elements is 600 pF, and the combined capacitance is 100 pF.

  Further, as shown in FIG. 22, the seventh variation is that the dielectric layer regions 201a and 201c for the first variable capacitance element and the dielectric layer regions 202a and 202c for the second variable capacitance element. On top of this, an upper conductor 270a is formed. Similarly, the upper conductor 270c is formed on the dielectric layer regions 203a and 203c for the third variable capacitor and the dielectric layer regions 204a and 204c for the fourth variable capacitor. As a result, the initial capacitance of the first to fourth variable capacitance elements is 400 pF, and the combined capacitance is 100 pF.

  Further, as shown in FIG. 23, the eighth variation is that the dielectric layer region 201a for the first variable capacitance element and the dielectric layer regions 202b and 202c for the second variable capacitance element are overlaid. Then, the upper conductor 280a is formed. Similarly, the upper conductor 280c is formed on the dielectric layer regions 203b and 203c for the third variable capacitor and the dielectric layer region 204a for the fourth variable capacitor. As a result, the initial capacitances of the first and fourth variable capacitance elements are 300 pF, the initial capacitances of the second and third variable capacitance elements are 500 pF, and the combined capacitance is 93.8 pF.

  Further, as shown in FIG. 24, the ninth variation is that the dielectric layer region 201a for the first variable capacitance element and the dielectric layer regions 202a and 202c for the second variable capacitance element are overlaid. Then, the upper conductor 290a is formed. Similarly, the upper conductor 290c is formed on the dielectric layer regions 203a and 203c for the third variable capacitor and the dielectric layer region 204a for the fourth variable capacitor. As a result, the initial capacitance of the first and fourth variable capacitance elements is 300 pF, the initial capacitance of the second and third variable capacitance elements is 400 pF, and the combined capacitance is 85.7 pF.

  In addition, as shown in FIG. 25, the tenth variation is that the dielectric layer region 201b for the first variable capacitance element and the dielectric layer regions 202a to 202c for the second variable capacitance element are overlaid. In addition, the upper conductor 300a is formed. Similarly, the upper conductor 300c is formed on the dielectric layer regions 203a to 203c for the third variable capacitance element and the dielectric layer region 204b for the fourth variable capacitance element. As a result, the initial capacitance of the first and fourth variable capacitance elements is 200 pF, the initial capacitance of the second and third variable capacitance elements is 600 pF, and the combined capacitance is 75 pF.

  In addition, as shown in FIG. 26, the eleventh variation is formed on the dielectric layer region 201a for the first variable capacitance element and the dielectric layer region 202c for the second variable capacitance element. An upper conductor 310a is formed. Similarly, the upper conductor 310c is formed on the dielectric layer region 203c for the third variable capacitor and the dielectric layer region 204a for the fourth variable capacitor. Thus, the initial capacitance of the first to fourth variable capacitance elements is 300 pF, and the combined capacitance is 75 pF.

  Further, as shown in FIG. 27, the twelfth variation is that the dielectric layer region 201b for the first variable capacitance element and the dielectric layer regions 202b and 202c for the second variable capacitance element are overlaid. In addition, the upper conductor 320a is formed. Similarly, the upper conductor 320c is formed on the dielectric layer regions 203b and 203c for the third variable capacitance element and the dielectric layer region 204b for the fourth variable capacitance element. As a result, the initial capacitance of the first and fourth variable capacitance elements is 200 pF, the initial capacitance of the second and third variable capacitance elements is 500 pF, and the combined capacitance is 71.4 pF.

  Further, as shown in FIG. 28, the thirteenth variation is that the dielectric layer region 201b for the first variable capacitance element and the dielectric layer regions 202a and 202c for the second variable capacitance element are overlaid. Further, the upper conductor 330a is formed. Similarly, the upper conductor 330c is formed on the dielectric layer regions 203a and 203c for the third variable capacitance element and the dielectric layer region 204b for the fourth variable capacitance element. As a result, the initial capacitance of the first and fourth variable capacitance elements is 200 pF, the initial capacitance of the second and third variable capacitance elements is 400 pF, and the combined capacitance is 66.7 pF.

  In addition, as shown in FIG. 29, the fourteenth variation is formed on the dielectric layer region 201b for the first variable capacitance element and the dielectric layer region 202c for the second variable capacitance element. An upper conductor 340a is formed. Similarly, the upper conductor 340c is formed on the dielectric layer region 203c for the third variable capacitor and the dielectric layer region 204b for the fourth variable capacitor. As a result, the initial capacitance of the first and fourth variable capacitance elements is 200 pF, the initial capacitance of the second and third variable capacitance elements is 300 pF, and the combined capacitance is 60 pF.

  In addition, as shown in FIG. 30, the fifteenth variation is that the dielectric layer region 201b for the first variable capacitance element and the dielectric layer region 202b for the second variable capacitance element are An upper conductor 350a is formed. Similarly, the upper conductor 350c is formed on the dielectric layer region 203b for the third variable capacitance element and the dielectric layer region 204b for the fourth variable capacitance element. Thus, the initial capacitance of the first to fourth variable capacitance elements is 200 pF, and the combined capacitance is 50 pF.

  In addition, as shown in FIG. 31, the sixteenth variation is that the dielectric layer region 201c for the first variable capacitor and the dielectric layer regions 202a to 202c for the second variable capacitor are provided. Then, the upper conductor 360a is formed. Similarly, the upper conductor 360c is formed on the dielectric layer regions 203a to 203c for the third variable capacitance element and the dielectric layer region 204c for the fourth variable capacitance element. As a result, the initial capacitance of the first and fourth variable capacitance elements is 100 pF, the initial capacitance of the second and third variable capacitance elements is 600 pF, and the combined capacitance is 42.9 pF.

  Further, as shown in FIG. 32, the seventeenth variation is that the dielectric layer region 201c for the first variable capacitance element and the dielectric layer regions 202b and 202c for the second variable capacitance element are overlaid. In addition, an upper conductor 370a is formed. Similarly, the upper conductor 370c is formed on the dielectric layer regions 203b and 203c for the third variable capacitor and the dielectric layer region 204c for the fourth variable capacitor. As a result, the initial capacitance of the first and fourth variable capacitance elements is 100 pF, the initial capacitance of the second and third variable capacitance elements is 500 pF, and the combined capacitance is 41.7 pF.

  Further, as shown in FIG. 33, the eighteenth variation is that the dielectric layer region 201c for the first variable capacitor and the dielectric layer regions 202a and 202c for the second variable capacitor are provided. In addition, an upper conductor 380a is formed. Similarly, the upper conductor 380c is formed on the dielectric layer regions 203a and 203c for the third variable capacitance element and the dielectric layer region 204c for the fourth variable capacitance element. As a result, the initial capacitance of the first and fourth variable capacitance elements is 100 pF, the initial capacitance of the second and third variable capacitance elements is 400 pF, and the combined capacitance is 40 pF.

  In addition, as shown in FIG. 34, the nineteenth variation is provided on the dielectric layer region 201c for the first variable capacitance element and the dielectric layer region 202c for the second variable capacitance element. An upper conductor 390a is formed. Similarly, the upper conductor 390c is formed on the dielectric layer region 203c for the third variable capacitor and the dielectric layer region 204c for the fourth variable capacitor. As a result, the initial capacitance of the first and fourth variable capacitance elements is 100 pF, the initial capacitance of the second and third variable capacitance elements is 300 pF, and the combined capacitance is 37.5 pF.

  In addition, as shown in FIG. 35, the twentieth variation is formed on the dielectric layer region 201c for the first variable capacitance element and the dielectric layer region 202b for the second variable capacitance element. An upper conductor 400a is formed. Similarly, the upper conductor 400c is formed on the dielectric layer region 203b for the third variable capacitor and the dielectric layer region 204c for the fourth variable capacitor. As a result, the initial capacitance of the first and fourth variable capacitance elements is 100 pF, the initial capacitance of the second and third variable capacitance elements is 200 pF, and the combined capacitance is 33.3 pF.

  In addition, as shown in FIG. 36, the twenty-first variation includes a dielectric layer region 201c for the first variable capacitance element and a dielectric layer region 202a for the second variable capacitance element. An upper conductor 410a is formed. Similarly, the upper conductor 410c is formed on the dielectric layer region 203a for the third variable capacitor and the dielectric layer region 204c for the fourth variable capacitor. Accordingly, the initial capacitance of the first to fourth variable capacitance elements is 100 pF, and the combined capacitance is 25 pF.

  The relationship between the above configuration, the initial capacity, and the combined capacity is summarized as shown in FIG.

  In this way, various capacitance variations can be realized simply by selecting the region of the dielectric layer according to the intended initial capacitance and changing the shape of the upper conductor accordingly. Therefore, it is possible to reduce the time and effort of designing and determining manufacturing conditions.

  Although the embodiment of the present invention has been described above, the present invention is not limited to this. For example, more variations can be realized if the above-described constraints are not adopted.

  Furthermore, the number of variable capacitance elements is not limited to four. 1 or a larger number of variable capacitance elements may be included in the variable capacitance device. In addition, an even number of variable capacitance elements are preferable as long as the constraint conditions are obeyed, but an odd number of variable capacitance elements may be used in the case where they are not obeyed.

  Further, portions other than the variable capacitance element may be changed according to the terminal and other conditions. Furthermore, the vertical direction of the layers may be interchanged.

10 Upper conductor 12 Pad 14 Lower conductor 16 Resistive film 18 Via

Claims (5)

A first conductor layer;
A dielectric layer formed on the first conductor layer;
A second conductor layer formed on the dielectric layer;
And having one or more variable capacitance elements that change capacitance by applying a voltage between the first conductor layer and the second conductor layer,
The dielectric layer is divided into two or more regions in the same layer,
The second conductor layer is formed on at least one predetermined region of the dielectric layer. 2n (n is an integer of 1 or more) pieces of the variable capacitance elements are connected in series,
For the variable capacitance element that forms a pair, the second conductor layer is connected,
The variable capacitance device according to claim 1, wherein the first conductor layer is connected between the pair of variable capacitance elements. The initial capacitance of the first variable capacitance element and the initial capacitance of the 2n-th variable capacitance element match,
The initial capacitance of the nth variable capacitive element matches the initial capacitance of the (n + 1) th variable capacitive element,
The variable capacitance device according to claim 2, wherein initial capacitances of the first and 2nth variable capacitance elements are equal to or less than an initial capacitance of the nth and n + 1th variable capacitance elements. The first conductor layer is connected to a first external terminal for applying a first voltage via a first resistance layer,
The variable capacitance device according to claim 1, wherein the second conductor layer is connected to a second external terminal for applying a second voltage via the second resistance layer.   The variable capacitance device according to claim 1, wherein areas of the two or more regions are different from each other.

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