JP2015065301A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide means of practically inhibit non-elastic strain of a lead-free solder layer in a semiconductor device such as a power module using a lead-free solder to improve reliability of the semiconductor device.SOLUTION: A semiconductor device comprises a substrate 11, a semiconductor element 12 arranged on the substrate, and an Sn solder layer 13 arranged so as to bond the semiconductor element with the substrate. The Sn solder layer 13 is arranged in a manner such that a C-axis of an Sn crystal in the Sn solder layer is substantially orthogonal to the maximum principal stress direction of the Sn solder layer.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  In hybrid vehicles, electric vehicles, and the like, a power module that is a semiconductor device in which a power semiconductor is mounted is used as an inverter that controls a high-power motor. The power module as described above is usually mounted in an engine room. Since the engine room has a high temperature environment exceeding 125 ° C., the members constituting the power module are required to have heat resistance that can be used even under such a high temperature environment. Therefore, Pb—Sn solder having excellent heat resistance has been used as a joining member used for joining semiconductor elements in power modules.

  In recent years, it has become clear that lead contained in Pb-Sn solder is harmful to living organisms including humans. For this reason, since 2000, environmental regulations by the RoHS (Restriction of the use of the certain Hazardous Substances in Electrical and Electronic Equipment) directive and ELV (End of Life Vehicles directive) directive have been strengthened, and the use of lead is restricted. It became a thing.

  In power modules as well, lead-free solders such as Sn-3Ag-0.5Cu alloy and other lead-free solders were promoted as an alternative material for Pb-Sn solders. However, lead-free solder generally has low heat resistance because it has a lower melting temperature than Pb—Sn solder (melting temperature: about 300 ° C.). For this reason, attempts have been made to improve the heat resistance or thermal stability of lead-free solder.

  For example, Patent Document 1 is a semiconductor device having a configuration in which a semiconductor element is mounted on a ceramic substrate fixed to a metal conductor and a heat sink for heat dissipation is attached to the metal conductor, and the semiconductor element is the ceramic substrate An Ni metallized layer is formed on the surface to be attached to the surface of the semiconductor element, and the surface of the semiconductor element on which the Ni metallized layer is formed and the ceramic substrate are made of Sn-based solder having an average crystal grain size of the mother phase of 20 μm or more. A semiconductor device which is bonded is described.

  Non-Patent Document 1 describes that the Sn-3Ag-0.5Cu alloy, which is a lead-free solder, has greatly different deformation characteristics of BGA (Ball grid array) solder due to the difference in crystal orientation.

JP 2013-33891 A

Katsuhiko Sasaki et al., M & M 2009 Conference, Japan Society of Mechanical Engineers, 2009, OS0320, p. 1-3

  In Sn-based solder used as lead-free solder, Sn crystals have strong anisotropy. For this reason, in a semiconductor device using Sn-based solder, the reliability of the semiconductor device may be reduced due to non-uniformity in the thermal characteristics of the Sn-based solder layer caused by Sn crystal anisotropy, for example, inelastic strain There is sex.

  Therefore, the present invention provides means for improving the reliability of a semiconductor device by substantially suppressing inelastic strain of the lead-free solder layer in a semiconductor device such as a power module using lead-free solder. With the goal.

  As a result of various studies on means for solving the above problems, the present inventor, as a result, in a semiconductor device using Sn-based solder as lead-free solder, the C axis of the Sn crystal in the Sn-based solder layer, the Sn-based solder layer of the Sn-based solder layer It has been found that the inelastic strain of the Sn-based solder layer can be substantially suppressed by disposing it so as to be substantially orthogonal to the maximum principal stress direction, and the present invention has been completed.

  That is, the gist of the present invention is as follows.

  (1) A substrate, a semiconductor element disposed on the substrate, and an Sn-based solder layer disposed so as to join the substrate and the semiconductor element, and a Sn crystal C-axis in the Sn-based solder layer Is disposed so as to be substantially orthogonal to the maximum principal stress direction of the Sn-based solder layer.

(2) A method of manufacturing the semiconductor device according to (1),
A molten Sn-based solder layer forming step of forming a molten Sn-based solder layer between the substrate and the semiconductor element;
The molten Sn-based solder is cooled so that the heat flow from the molten Sn-based solder layer moves in a direction substantially parallel to the substrate surface, and the substrate and the semiconductor element are joined with the Sn-based solder layer. Joining process;
Said method.

  (3) The molten Sn-based solder is cooled so that the heat flow from the molten Sn-based solder layer moves in a direction that forms an angle of 30 to 50 ° with the maximum principal stress direction of the molten Sn-based solder layer. ) Method.

  According to the present invention, in a semiconductor device such as a power module using lead-free solder, it is possible to provide a means for substantially suppressing inelastic strain of the lead-free solder layer and improving the reliability of the semiconductor device. Become.

FIG. 1 is a schematic view showing a form of a semiconductor device of the present invention. FIG. 2 is a schematic diagram showing the crystal structure of the Sn crystal. FIG. 3 is a schematic diagram showing the relationship between the maximum principal stress direction of the Sn-based solder layer and the crystal orientation of the Sn crystal in the semiconductor device of the present invention and the conventional semiconductor device. A: Semiconductor device of the present invention; B: Semiconductor device of the prior art. FIG. 4 is a process diagram showing an embodiment of a method for producing a semiconductor device of the present invention. FIG. 5 is a schematic diagram showing the relationship between the direction of heat flow from the molten Sn-based solder layer and the crystal orientation of the Sn crystal in the resulting Sn-based solder layer in the bonding step of the method for manufacturing a semiconductor device of the present invention. It is. FIG. 6 is a diagram showing the relationship between the number of thermal cycles and the rate of increase in thermal resistance in the semiconductor device of Comparative Example 1. FIG. 7 is a view showing a scanning electron microscope (SEM) image of a sample of a cross section of the Sn-based solder structure in the semiconductor device of Comparative Example 2. FIG. 8 is a diagram showing a backscattering diffraction (EBSD) image of a part of the sample in the cross section of the Sn-based solder structure in the semiconductor device of Comparative Example 2. A: EBSD image of the area indicated by A in the SEM image of FIG. 7; B: EBSD image of the area indicated by B in the SEM image of FIG. FIG. 9 is a diagram illustrating a result of calculating the inelastic strain of the Sn-based solder layer in the semiconductor devices of Example and Comparative Example 2 by computer simulation (CAE). A: Result of the semiconductor device of Example; B: Result of the semiconductor device of Comparative Example 2.

  Hereinafter, preferred embodiments of the present invention will be described in detail.

  In the present specification, features of the present invention will be described with reference to the drawings as appropriate. In the drawings, the size and shape of each part are exaggerated for clarity, and the actual size and shape are not accurately depicted. Therefore, the technical scope of the present invention is not limited to the size and shape of each part shown in these drawings.

<I: Semiconductor device>
The present invention relates to a semiconductor device.

  FIG. 1 is a schematic diagram showing the form of the semiconductor device of the present invention. As shown in FIG. 1, the semiconductor device 1 of the present invention includes a substrate 11, a semiconductor element 12 disposed on the substrate 11, and an Sn disposed so as to join the substrate 11 and the semiconductor element 12. It is necessary to provide the system solder layer 13. The semiconductor device of the present invention is usually a power module on which a power semiconductor is mounted, and is typically a power module used as an inverter for controlling a high-output motor such as a hybrid vehicle and an electric vehicle.

  As a substrate and a semiconductor element constituting the semiconductor device of the present invention, a substrate and a semiconductor usually used in the technical field for use in an inverter for controlling a high output motor of a power module, particularly a hybrid vehicle and an electric vehicle. Any element can be used without particular limitation.

  The Sn-based solder constituting the semiconductor device of the present invention is not particularly limited as long as it is a material normally used in the technical field as lead-free solder, and can be used. Examples of the Sn-based solder include Sn-3Ag-0.5Cu alloy and Sn-0.7Cu alloy.

  The Sn-based solder layer is usually formed entirely from a single dendrite. Sn crystals constituting the Sn-based solder layer have strong anisotropy. A schematic diagram showing the crystal structure of the Sn crystal is shown in FIG. Of the initial orientations of the Sn crystal, the (001) orientation, that is, the C-axis direction has the highest linear expansion coefficient and elastic modulus, and the (100) orientation has the lowest linear expansion coefficient and elastic modulus. For this reason, when the C axis of the Sn crystal in the lead-free solder layer is oriented parallel to the maximum principal stress direction of the solder layer, there is a high possibility that the inelastic strain becomes large.

  In the manufacture of a semiconductor device using lead-free solder, the initial crystal orientation is generally not controlled. The present inventor may reduce the reliability of the semiconductor device due to the inelastic strain of the solder layer depending on the relationship between the initial orientation of the Sn crystal in the lead-free solder layer and the maximum principal stress direction of the solder layer. Found that there is. The present inventor also arranges the C axis of the Sn crystal in the Sn-based solder layer so as to be substantially perpendicular to the maximum principal stress direction of the Sn-based solder layer in a semiconductor device using Sn-based solder as lead-free solder. Thus, it was found that the inelastic strain of the Sn-based solder layer can be substantially suppressed.

  In view of the above knowledge, the semiconductor device of the present invention needs to be arranged so that the C axis of the Sn crystal in the Sn-based solder layer is substantially orthogonal to the maximum principal stress direction of the Sn-based solder layer. It is preferable that the C axis of the Sn crystal in the Sn-based solder layer is arranged so as to be substantially orthogonal to the substrate surface. Further, it is preferable that the (100) orientation of the Sn crystal in the Sn-based solder layer is arranged substantially parallel to the maximum principal stress direction of the Sn-based solder layer. Particularly preferably, the Sn-based solder layer is arranged so that the C-axis of the Sn crystal is substantially perpendicular to the substrate surface, and the (100) orientation of the Sn crystal is substantially the same as the maximum principal stress direction of the Sn-based solder layer. Arranged in parallel. The maximum principal stress direction is preferably oriented substantially parallel to the substrate surface. The C axis of the Sn crystal in the Sn based solder layer is arranged so as to be substantially perpendicular to the maximum principal stress direction of the Sn based solder layer, and / or the (100) orientation of the Sn crystal in the Sn based solder layer is By disposing the Sn-based solder layer substantially parallel to the maximum principal stress direction, inelastic strain of the Sn-based solder layer can be substantially suppressed.

  In the present invention, “the C axis of the Sn crystal in the Sn-based solder layer is substantially orthogonal to the maximum principal stress direction of the Sn-based solder layer” means that the C axis of the Sn crystal and the maximum principal stress direction of the Sn-based solder layer Means that the angle between is in the range of 45-135 °. The angle is preferably in the range of 60 to 120 °, more preferably in the range of 75 to 105 °, and particularly preferably 90 °.

  In the present invention, “the (100) orientation of the Sn crystal in the Sn-based solder layer is disposed substantially parallel to the maximum principal stress direction of the Sn-based solder layer” means that the (100) orientation of the Sn crystal and the Sn-based solder It means that the angle between the maximum principal stress direction of the layer is in the range of -45 to 45 °. The angle is preferably in the range of −30 to 30 °, more preferably in the range of −15 to 15 °, and particularly preferably 0 °.

  FIG. 3 shows the relationship between the maximum principal stress direction of the Sn-based solder layer and the crystal orientation of the Sn crystal in the semiconductor device of the present invention and the conventional semiconductor device. By arranging the Sn crystal in the Sn-based solder layer under the above conditions, the inelastic strain of the Sn-based solder layer can be substantially suppressed and the reliability of the semiconductor device can be improved.

  The direction of the C axis of the Sn crystal in the Sn-based solder layer is not limited, but can be determined by the following method, for example. A sample having an arbitrary cross section in the Sn-based solder layer is prepared, and a back scatterer diffraction (EBSD) pattern of an arbitrary portion of the sample is obtained. Based on the obtained EBSD pattern, by analyzing the crystal orientation of the Sn crystal, the direction of the C axis of the Sn crystal in the Sn-based solder layer is determined.

  The maximum principal stress direction of the Sn-based solder layer is not limited. For example, the inelastic strain of the Sn-based solder layer is calculated by computer simulation using the Abaqus program (Computer Aided Engineering, CAE). Can be determined.

<II: Method for Manufacturing a Semiconductor Device>
The present invention also relates to a method of manufacturing the semiconductor device described above.

  FIG. 4 is a process diagram showing an embodiment of a method for producing a semiconductor device of the present invention. Hereinafter, a preferred embodiment of the method of the present invention will be described in detail with reference to FIG.

[II-1. Molten Sn solder layer formation process]
The method of the present invention needs to include a molten Sn-based solder layer forming step (step S1) in which a molten Sn-based solder layer is formed between the substrate and the semiconductor element.

  What was demonstrated above can be used for a board | substrate, a semiconductor element, and Sn type solder used in this process.

  In this step, as a means for forming a molten Sn-based solder layer between the substrate and the semiconductor element, a soldering method usually used in this technical field can be applied.

[II-2. Joining process]
The method of the present invention cools the molten Sn-based solder so that the heat flow from the molten Sn-based solder layer moves in a direction substantially parallel to the substrate surface, and the Sn-based gap is formed between the substrate and the semiconductor element. It is necessary to include a bonding step (step S2) in which bonding is performed with a solder layer.

  In the present invention, “the heat flow from the molten Sn-based solder layer moves in a direction substantially parallel to the substrate surface” means that the angle between the heat flow direction and the substrate surface is −45 to 45 °. It means that it is in the range. The angle is preferably in the range of −30 to 30 °, more preferably in the range of −15 to 15 °, and particularly preferably 0 °.

  In this step, it is preferable to cool the molten Sn solder so that the heat flow from the molten Sn solder layer moves in a direction that forms an angle of 30 to 50 ° with the maximum principal stress direction of the molten Sn solder layer. . The angle is preferably in the range of 35 to 50 °, more preferably in the range of 40 to 50 °, and particularly preferably 45 °.

  FIG. 5 shows the relationship between the direction of heat flow from the molten Sn-based solder layer in this step and the crystal orientation of the Sn crystal in the resulting Sn-based solder layer. As shown in FIG. 5, by moving the heat flow from the molten Sn-based solder layer under the above-described conditions, the C axis of the Sn crystal in the Sn-based solder layer is approximately perpendicular to the maximum principal stress direction of the Sn-based solder layer. And / or the (100) orientation of the Sn crystal in the Sn-based solder layer is disposed substantially parallel to the maximum principal stress direction of the Sn-based solder layer. Thereby, the inelastic strain of the Sn-based solder layer that has been cooled and solidified can be substantially suppressed, and the reliability of the resulting semiconductor device can be improved.

  In this step, means for moving the heat flow from the molten Sn-based solder layer is not particularly limited as long as it satisfies the above requirements, and can be used. Examples of the means include a method in which a cooling member such as a cooling plate or a Cu heat sink is disposed in a direction in which the heat flow from the molten Sn-based solder layer is moved, and the heat flow is moved to the cooling member.

  As described above, the semiconductor device of the present invention can substantially improve the inelastic strain of the lead-free solder layer and improve the reliability of the semiconductor device. Therefore, by using the semiconductor device of the present invention for an inverter that controls a high output motor such as a hybrid vehicle and an electric vehicle, it is possible to obtain a highly reliable and long-life electronic device even in a high temperature environment. Become.

  Hereinafter, the present invention will be described more specifically with reference to examples. However, the technical scope of the present invention is not limited to these examples.

<I: Comparative Example 1>
[Fabrication of semiconductor devices]
An Sn-based solder foil (Sn-3Ag-0.5Cu, 10 × 10 mm, thickness 150 μm) is placed on a Cu-based substrate (20 × 30 mm), and then a power semiconductor element (10 × 10 mm) Placed. The apparatus was heated at 330 ° C. for 1 minute in a reducing atmosphere to melt the Sn-based solder foil. Thereafter, the entire semiconductor device was cooled to 25 ° C. in 2 minutes. As a result, the molten Sn-based solder was solidified, and the substrate and the semiconductor element were joined by the Sn-based solder layer.

[Thermal cycle test]
The semiconductor device manufactured by the above-described method is turned on / off by supplying power to the element, thereby causing a temperature cycle test by element heat generation (temperature difference of about 80 ° C. at on / off, 1 cycle (cyc): about 10 sec. ). Thereafter, the thermal resistance of the semiconductor device was measured. The increase rate (%) of the thermal resistance relative to the thermal resistance of the untreated semiconductor device was calculated. FIG. 6 shows the relationship between the number of thermal cycles and the rate of increase in thermal resistance.

  As shown in FIG. 6, the thermal resistance increase rate of the semiconductor device after the thermal cycle treatment has a large difference in measured values even when the number of thermal cycles is the same.

<II: Comparative example 2>
[Fabrication of semiconductor devices]
An Sn-based solder foil (Sn-3Ag-0.5Cu, 10 × 10 mm, thickness 150 μm) is placed on a Cu-based substrate (20 × 30 mm), and then a power semiconductor element (10 × 10 mm) Placed. The apparatus was heated at 330 ° C. for 1 minute in a reducing atmosphere to melt the Sn-based solder foil. Thereafter, a cooling plate (25 ° C., 500 × 500 mm) is brought into close contact with the lower surface of the substrate, so that the heat flow from the molten Sn-based solder layer moves in a direction perpendicular to the substrate surface and toward the lower surface of the substrate. The system solder was cooled. As a result, the molten Sn-based solder was solidified, and the substrate and the semiconductor element were joined by the Sn-based solder layer.

[Crystal structure analysis of solder structure]
The power semiconductor element was removed from the semiconductor device manufactured by the above method to expose the Sn-based solder layer. A Sn-based solder layer was excavated from the upper surface of the semiconductor device, and a cross-sectional sample of the Sn-based solder structure was produced. FIG. 7 shows a scanning electron microscope (SEM) image of the cross-sectional sample of the obtained Sn-based solder structure. FIG. 8 shows a backscatter diffraction (EBSD) image of a part of the sample. 8A corresponds to the EBSD image of the region indicated by A in the SEM image of FIG. 7, and FIG. 8B corresponds to the EBSD image of the region indicated by B in the SEM image of FIG.

  As shown in FIG. 7, the entire Sn-based solder layer was formed of one dendrite, and one dendrite axis was observed. Further, as shown in FIGS. 8A and 8B, the (110) orientation of the Sn crystal in the Sn-based solder layer was oriented so as to be substantially parallel to the axis orthogonal to the substrate surface.

<III: Examples>
[Fabrication of semiconductor devices]
An Sn-based solder foil (Sn-3Ag-0.5Cu, 10 × 10 mm, thickness 150 μm) is placed on a Cu-based substrate (20 × 30 mm), and then a power semiconductor element (10 × 10 mm) Placed. The apparatus was heated to 25 ° C. in a reducing atmosphere for 2 minutes to melt the Sn-based solder foil. Thereafter, a cooling gas was jetted from the side surface of the substrate, and the molten Sn-based solder was cooled so that the heat flow from the molten Sn-based solder layer moved in a direction parallel to the substrate surface. As a result, the molten Sn-based solder was solidified, and the substrate and the semiconductor element were joined by the Sn-based solder layer.

[Analysis of solder structure]
An EBSD image was obtained in the same manner as in Comparative Example 2. From the obtained EBSD image, the (001) orientation (C axis) of the Sn crystal in the Sn-based solder layer of the semiconductor device of the example was oriented so as to be substantially orthogonal to the substrate surface.

[Inelastic strain analysis of solder structure]
The inelastic strain of the Sn-based solder layer in the semiconductor device of Example and Comparative Example 2 manufactured by the above method was calculated by computer simulation (Computer Aided Engineering, CAE). Abuqus program was used for the calculation. The result of the semiconductor device of the example is shown in FIG. 9A, and the result of the semiconductor device of the comparative example 2 is shown in FIG. 9B.

  In both cases of the semiconductor device of the example and the semiconductor device of Comparative Example 2, the maximum principal stress direction was oriented substantially parallel to the substrate surface. Considering the results of EBSD analysis, it was found that in the semiconductor device of the example, the maximum principal stress direction was oriented substantially parallel to the (100) orientation of the Sn crystal in the Sn-based solder layer (FIG. 9A). ). In contrast, in the semiconductor device of Comparative Example 2, it was found that the maximum principal stress direction was oriented substantially parallel to the (001) orientation (C axis) of the Sn crystal in the Sn-based solder layer (Fig. 9B). When comparing the inelastic strain of the Sn-based solder layer in the semiconductor device of the example and the comparative example 2, it was 0.067 in the example, and 0.0835 in the comparative example 2. The difference in inelastic strain corresponded to the application of stress of about 100,000 cycles in a fatigue test with repeated stress.

1 ... Semiconductor device of the present invention
11, 21… Board
12, 22… Semiconductor element
13, 23… Sn solder layer
A, B ... Backscattering diffraction (EBSD) measurement area
C ... Dendrite axis

Claims (3)

  A substrate, a semiconductor element disposed on the substrate, and a Sn-based solder layer disposed so as to join the substrate and the semiconductor element, and the C axis of the Sn crystal in the Sn-based solder layer is Sn A semiconductor device arranged so as to be substantially orthogonal to the maximum principal stress direction of the solder layer. A method of manufacturing the semiconductor device according to claim 1,
A molten Sn-based solder layer forming step of forming a molten Sn-based solder layer between the substrate and the semiconductor element;
The molten Sn-based solder is cooled so that the heat flow from the molten Sn-based solder layer moves in a direction substantially parallel to the substrate surface, and the substrate and the semiconductor element are joined with the Sn-based solder layer. Joining process;
Said method.   3. The molten Sn-based solder is cooled so that the heat flow from the molten Sn-based solder layer moves in a direction that forms an angle of 30 to 50 ° with the maximum principal stress direction of the molten Sn-based solder layer. Method.

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