JP2015060401A - Information processor and control method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce power consumption for transmission of configuration information.SOLUTION: A dynamic reconfiguration circuit 101 includes a plurality of PEs 106 for performing arithmetic processing, a plurality of routers 107 for connecting the plurality of PEs 106, and a plurality of switches 108 for forming a transmission route of configuration information indicative of at least partial operation settings of the plurality of PEs 106 and the plurality of routers 107. A determination unit 103 determines a PE 106 and a router 107 of which the operation settings are to be changed by the configuration information. A route setting unit 104 transmits a route switching signal for forming a transmission route through which the configuration information is to be transmitted to the PE 106 and the router 107 of which the operation settings are to be changed, to the plurality of switches 108.

Description

  The present invention relates to an information processing apparatus having a plurality of arithmetic elements and capable of dynamic reconfiguration.

  With the miniaturization of devices due to advances in semiconductor manufacturing technology, a huge number of transistors have been integrated on large-scale integrated circuits (LSIs). Static power increases due to the miniaturization and the increase in the number of transistors. Furthermore, the operating power increases as the frequency of the processor increases. As a result, a trade-off between performance and low power consumption occurs, and a limit to performance improvement is beginning to appear.

  Therefore, as a means to realize further performance improvement, an array type in which a plurality of processor elements (PE) such as a central processing unit (CPU), a digital signal processor (DSP), a single arithmetic unit, or an arithmetic unit are mounted on an LSI. Arithmetic devices are attracting attention. By performing parallel processing using a plurality of PEs, the array-type arithmetic unit can obtain high arithmetic performance even in a situation where improvement in operating frequency due to process miniaturization cannot be expected as in the past.

  Configuration information defining the operation of the apparatus is input to the array type arithmetic apparatus from the outside. Each PE in the array type arithmetic unit is connected via a router, and the data transfer path between the PEs is switched by changing the setting of the router according to the configuration information. The operation of the arithmetic unit in the array type arithmetic device is also set according to the configuration information.

  There may be several hundred arithmetic units in the array type arithmetic unit. For this reason, if a method of transmitting configuration information to a plurality of arithmetic units simultaneously by addressing is used, the number of wirings connected to each arithmetic unit increases, which is not suitable for mounting. For this reason, in the array type arithmetic unit, the circuit for transmitting the configuration information is composed of one or a plurality of shift registers.

  A method has been proposed in which configuration information supplied from outside an FPGA (field-programmable gate array) is shifted bit by bit, transmitted to a shift register in the FPGA, and stored in memory. (Patent Document 1).

  Note that there is a demand for a system realized by an array type arithmetic unit to change its operation without stopping the entire system or stopping the data flow. For this reason, there are cases where operation settings of some arithmetic units and routers are changed during system operation.

  However, if the configuration information transmission circuit is configured with a shift register, it is necessary to transmit the configuration information to all the arithmetic units and routers connected to the shift register even when the operation settings of some arithmetic units and routers are changed. . Therefore, even the shift register that does not need to transmit configuration information operates and wasteful power is consumed. Furthermore, since transmission of configuration information is not completed until all shift operations are completed, the time required for transmission of configuration information becomes longer.

JP 2003-198361 A

  An object of the present invention is to reduce power consumption when transmitting configuration information.

  Another object is to reduce the time required for transmitting the configuration information.

  The present invention has the following configuration as one means for achieving the above object.

  An information processing apparatus according to the present invention includes a plurality of calculation elements that perform calculation processing, a plurality of connection elements that connect the plurality of calculation elements, and at least a part of the plurality of calculation elements and the plurality of connection elements. An arithmetic circuit including a plurality of switches that form a transmission path of configuration information indicating the operation setting, determination means for determining an operation element and a connection element whose operation setting is changed according to the configuration information, and the operation setting is changed And a path setting means for transmitting a path switching signal for forming a transmission path for transmitting the configuration information to the connection element to the plurality of switches.

  According to the present invention, it is possible to reduce power consumption when transmitting configuration information.

  Furthermore, the time required for transmitting the configuration information can be shortened.

The block diagram which shows the structural example of the information processing apparatus of an Example. The figure explaining the structural example of structural information. The figure which shows the internal structural example of a dynamic reconfiguration circuit. The figure which shows the detailed example of a circuit block. The block diagram which shows the internal structural example of PE. The block diagram which shows the internal structural example of a router. The figure which shows the example of ID setting of PE and a router in a dynamic reconfiguration circuit. The figure explaining the determination table with which a determination signal and a determination part are provided. The flowchart explaining the production | generation process of a determination signal. The figure which shows the example of an address of a crossbar switch. The figure explaining the route switching table with which a route switching signal and a route determination part are provided. The flowchart explaining the production | generation process of a path | route switching signal and a path | route setting completion signal. The figure which shows an example of the transmission path | route of structure information. The figure explaining the process which changes some operation settings of PE and a router while a dynamic reconfiguration circuit is operate | moving. The flowchart explaining a series of operation | movement including a change process of operation | movement setting. FIG. 3 is a block diagram illustrating a configuration example of a configuration information generation device that generates configuration information and a semiconductor device that uses the configuration information. The figure which shows the example of arrangement | positioning of the structure information hold | maintained at an external memory. FIG. 3 is a block diagram illustrating a configuration example of an information processing apparatus according to a second embodiment. The figure explaining the table with which the structural example of a circuit block and a gate setting part are provided. FIG. 9 is a block diagram illustrating a configuration example of an information processing apparatus according to a third embodiment. FIG. 10 is a diagram illustrating a configuration example of a dynamic reconfiguration circuit according to the third embodiment. The figure explaining the power supply control table with which a power supply control part is provided.

  Hereinafter, an information processing apparatus according to an embodiment of the present invention will be described in detail with reference to the drawings. In the following, an example in which the present invention is applied to an array type arithmetic device that is one of information processing devices will be described.

  An information processing device inputs configuration information generated by a configuration information generation device, and assigns processing to arithmetic elements (processor elements (PE)) and connection elements (routers) such as arithmetic units and arithmetic units according to the configuration information. Next, the operation of the calculation element and the connection element is set. Note that the process assignment means associating a process with a computation element or a connection element that executes the process. In the embodiment, the setting value of the configuration information is written in the calculation element and the connection element, thereby assigning the processing to the calculation element and the connection element.

  In addition, the transmission / reception means and transmission method of various signals demonstrated in an Example are examples, and this invention is not limited to these transmission / reception means and transmission methods.

[Device configuration]
A block diagram of FIG. 1 shows a configuration example of the information processing apparatus 100 according to the embodiment.

  When the control unit 102 receives the configuration information 105 from the outside of the information processing apparatus 100 and receives a path setting completion signal from the path setting unit 104, the control unit 102 transmits the configuration information 105 to the dynamic reconfiguration circuit 101 that is an arithmetic circuit, Thereafter, a processing start signal is transmitted to the dynamic reconfiguration circuit 101.

  The control unit 102 receives the configuration information 105 from the outside after the transmission of the configuration information 105 to the computing unit (PE) 106 and the router 107 is completed. Further, the control unit 102 receives the processing completion signal from the PE 106 after transmitting the processing start signal.

  Although details will be described later, the determination unit 103 receives the configuration information 105 input from the outside, determines the PE 106 and the router 107 whose operation settings are changed by the configuration information 105, and generates a determination signal generated based on the determination result. Transmit to the route setting unit 104. The path setting unit 104 generates a path switching signal based on the determination signal, and transmits the path switching signal to the dynamic reconfiguration circuit 101.

  A configuration example of the configuration information 105 will be described with reference to FIG. The configuration information 105 is information obtained by combining the PE setting data 201 and the router setting data 202. In the example shown in FIG. 2A, the PE setting data 201 is X pieces and the router setting data 202 is Y pieces. It is. In other words, the configuration information 105 includes setting information for X PEs and setting information for Y routers. FIG. 2A shows an example of binary data in which each setting information is N + 1 bits.

  FIG. 2B shows a format example of each setting information. Each setting information includes an ID 301, an address 302, and a setting value 303. ID 301 is an identification number, and a unique identification number (ID) is preset in each PE 106 and each router 107. The address 302 designates an area for writing the setting value 303 in each PE 106 or router 107. The setting value 303 is a value for setting the operation of each PE 106 and each router 107.

[Calculation circuit]
FIG. 3 shows an internal configuration example of the dynamic reconfiguration circuit 101 which is an arithmetic circuit. The dynamic reconfiguration circuit 101 shown in FIG. 3 includes a plurality of PEs 106, a plurality of routers 107 indicated by ◯ marks, and a plurality of crossbar switches (hereinafter referred to as switches) 108 indicated by □ marks.

  The switch 108 receives the path switching signal from the path setting unit 104 and switches the input / output path according to the path switching signal. By switching the path by the switch 108, various transmission paths for the configuration information 105 in the dynamic reconfiguration circuit 101 can be formed.

  In addition, in order to transmit / receive the path switching signal by the number of the switches 108, transmission wiring of the path switching signal is provided by the number of the switches 108. Further, there are a maximum of four types of input / output switching patterns of the switch 108, and a 2-bit width is sufficient for the path switching signal input to each switch 108.

  In FIG. 3, a circuit block 401 surrounded by a broken line is one arithmetic unit. A detailed example of the circuit block 401 is shown in FIG. FIG. 4 shows the input / output relationship of signals and data of the PE 106, the router 107, and the switch 108, but this relationship is an example, and the present invention is not limited to the input / output relationship shown in FIG.

  Upon receiving the processing start signal 503 from the control unit 102, the PE 106 processes the data 501 transmitted from the router 107, transmits the processing result to another router 107, and then transmits a processing completion signal 504 to the control unit 102. . The router 107 transmits / receives data 501 to / from the PE 106, and transmits / receives data 501 to / from other routers 107.

Calculation element (PE)
An example of the internal configuration of the PE 106 is shown in the block diagram of FIG.

  The configuration information setting unit 601 receives the configuration information 502 and determines whether or not the ID 301 included in the received configuration information 502 matches the ID set in the PE 106. That is, it is determined whether or not the configuration information 502 includes an ID 301 that matches its own ID.

  When the IDs match, the configuration information setting unit 601 stores the setting value 303 of the corresponding configuration information in the memory in the configuration information setting unit 601 according to the address 302 of the configuration information (hereinafter, the corresponding configuration information) that matches the ID of itself. The written and received configuration information 502 is output. The configuration information setting unit 601 then sets the input switching setting 606 in the data input unit 604, the operation setting 607 for determining the processing contents in the arithmetic processing unit 603, and the output switching setting 602 in the data output unit 605 according to the setting value 303. Set. Hereinafter, the input switching setting 606, the operation setting 607, and the output switching setting 602 may be collectively referred to as “setting information”, and the operation for setting the setting information and the set operation may be referred to as “operation setting”.

  The operation setting determines the input path through which the data input unit 604 inputs the data 501, the arithmetic processing performed by the arithmetic processing unit 603, and the output path through which the data output unit 605 outputs the processing result data 501. That is, the contents of the calculation process of the PE 106 are determined.

  If the IDs do not match, the configuration information setting unit 601 outputs the received configuration information 502 to the back of the transmission path without performing operation setting. According to the transmission path setting according to the present embodiment, the possibility that the PE 106 whose operation setting is not changed by the configuration information is arranged in the transmission path is extremely low. For example, when an exceptional situation occurs in which a transmission route cannot be formed between adjacent routers 107, there is a possibility that PEs 106 whose operation settings adjacent to those routers 107 are not changed are placed in the transmission route. .

  When receiving the processing start signal 503, the arithmetic processing unit 603 starts arithmetic processing of the data 501 input by the data input unit 604. When the arithmetic processing is completed, the processing result data 501 is output to the data output unit 605, and the processing completion signal 504 is transmitted to the control unit 102.

  Note that the configuration of the PE 106 is not limited to that shown in FIG. 5 and may be any configuration as long as the operation setting according to the configuration information 502 is possible.

Router An example of the internal configuration of the router 107 is shown in the block diagram of FIG.

  The configuration information setting unit 701 receives the configuration information 502 and determines whether the ID 301 included in the received configuration information 502 matches the ID set in the router 107. That is, it is determined whether or not the configuration information 502 includes an ID 301 that matches its own ID.

  When the IDs match, the configuration information setting unit 701 writes the setting value 303 of the corresponding configuration information in the memory in the configuration information setting unit 701 according to the address 302 of the corresponding configuration information, and sends the received configuration information 502 to the rear of the transmission path Output to. Then, the configuration information setting unit 701 transmits the setting value 303 to the input / output switching unit 702.

  If the IDs do not match, the configuration information setting unit 701 outputs the received configuration information 502 to the back of the transmission path without setting the input / output switching unit 702. According to the setting of the transmission path according to the present embodiment, the router 107 whose operation setting is not changed by the configuration information may be arranged in the transmission path, but compared with the case where all the routers 107 are arranged in the transmission path. The number of routers 107 arranged on the route can be reduced.

  The input / output switching unit 702 is connected to a plurality of input signal lines and a plurality of output signal lines, and selects one of the input signal lines and one of the output signal lines according to the set value 303. Then, the selected signal lines are electrically connected, and the unselected signal lines are electrically disconnected. Hereinafter, the operation for causing the input / output switching unit 702 to select an input / output signal line and the set operation may be referred to as “operation setting”.

  That is, the router 107 inputs the data 501 from the selected input signal line (input path), and outputs the data 501 to the selected output signal line (output path). In other words, the set value 303 includes information indicating from which input path the data 501 is input and to which output path the data 501 is output.

Determination Unit The determination unit 103 generates a determination signal indicating the PE 106 and the router 107 whose operation settings are changed by the configuration information 105.

  FIG. 7 shows an ID setting example of the PE 106 and the router 107 in the dynamic reconfiguration circuit 101. FIG. 7 shows an example in which there are 12 PEs 106 and 30 routers 107 (42 in total). IDs “01” to “42” are assigned to the PEs 106 and the routers 107, respectively. Note that the ID may be able to identify the PE 102 or the router 107, and need not be a consecutive number as shown in FIG.

  The determination table provided in the determination signal and determination unit 103 will be described with reference to FIG. As shown in FIG. 8 (A), the determination signal has at least as many bits as the PE 106 and the router 107 (at least 42 bits in the example of FIG. 7). As shown in FIG. 8B, the determination table shows the correspondence between the ID and the bit of the determination signal. For example, the bit of the determination signal corresponding to ID = N is indicated by D [N].

  The determination signal generation process will be described with reference to the flowchart of FIG.

  Upon receiving the configuration information 105, the determination unit 103 resets all bits of the determination signal to '0' (S801), acquires all ID information from the received configuration information 105, and generates an ID list (S802). .

  Next, the determination unit 103 selects one arbitrary ID from the generated ID list (S803), searches the determination table shown in FIG. 8B for a record that matches the selected ID, '1' is set to bit D [N] of the recorded determination signal (S804). The example of the determination signal shown in FIG. 8A shows a state in which ID = 02 is selected from the ID list and “1” is set in the bit D [2] corresponding to ID = 02.

  Next, the determination unit 103 deletes the selected ID from the ID list (S805), and determines whether the ID list is empty (S806). If there is an unselected ID and the ID list is not empty, the process returns to step S803. If there is no unselected ID and the ID list is empty, a determination signal generation process for the received configuration information 105 is performed. Exit.

Route Setting Unit The route setting unit 104 generates a route switching signal based on the determination signal received from the determination unit 103.

  FIG. 10 shows an example of the address of the switch 108. In FIG. 10, the numbers of switches 108, PEs 106, and routers 107 are the same as those in FIG. 7, and there are 32 switches 108. As shown in FIG. 10, addresses “01” to “32” are assigned to each switch 108. Note that the address may specify the switch 108 and need not be a consecutive number as shown in FIG.

  A route switching table provided in the route switching signal and route determination unit 104 will be described with reference to FIG. As shown in FIG. 11A, the path switching signal has 2-bit information for each switch. For example, the first bit S [0] and the second bit S [1] of the path switching signal are signals indicating switching of the switch 108 at address = 01. For example, S [0] indicates the setting of the connection destination on the input side of the switch 108, and S [1] indicates the setting of the connection destination on the output side of the switch 108. That is, the input / output of each switch 108 can be switched between a maximum of four patterns by a 2-bit path switching signal. The example of the path switching table shown in FIG. 11B shows an example of the relationship between the determination signal and the path switching signal.

  The generation process of the path switching signal and the path setting completion signal will be described with reference to the flowchart of FIG.

  When receiving the determination signal, the path determination unit 104 searches the path switching table shown in FIG. 11B for a record corresponding to the received determination signal, and outputs the path switching signal recorded in the detected record (S901). ). Note that the configuration for outputting the path switching signal corresponding to the determination signal with reference to the path switching table is merely an example, and any configuration may be used as long as the path switching signal corresponding to the determination signal can be output.

  Next, the route determination unit 104 counts time (S902), and outputs a route setting completion signal to the control unit 102 when a predetermined time has passed (S903), and a route switching signal and a route setting completion signal for the received determination signal. This completes the generation process. Note that the predetermined time is a time required for transmission of the path switching signal, and is, for example, the maximum value of the time required for transmission of the path switching signal from the path determination unit 104 to the switch 108.

[Operation of information processing device]
Hereinafter, a series of operations for acquiring the configuration information 105, switching the route for transmitting the configuration information 105, and transmitting the configuration information 105 to the PE 106 and the router 107 will be described.

  An example of the transmission path of the configuration information 105 is shown in FIG. FIG. 13 shows an initial transmission path of the configuration information 105 when the information processing apparatus 100 is activated and the dynamic reconfiguration circuit 101 starts operation. In FIG. 13, the configuration information 105 is transmitted in the arrow direction via the switch 108, the router 107, and the PE 106. That is, all PEs 106 and routers 107 included in the dynamic reconfiguration circuit 101 are incorporated in the initial transmission path.

  Assume that the ID shown in FIG. 7 is assigned to the PE 106 and the router 107. In this embodiment, when the operation of the dynamic reconfiguration circuit 101 is started, the operation settings of all the PEs 106 and the routers 107 are performed. Therefore, it is necessary to transmit the configuration information 105 to all the PEs 106 and routers 107, and the configuration information 105 is sequentially transmitted to each PE 106 and each router 107 along the initial transmission path shown in FIG. The dynamic reconfiguration circuit 101 starts data processing in accordance with the operation set by the configuration information 105.

  A process of changing some operation settings of the PE 106 and the router 107 while the dynamic reconfiguration circuit 101 is operating will be described with reference to FIG. Further, a series of operations including operation setting change processing will be described with reference to the flowchart of FIG. The operation shown in FIG. 15 corresponds to one piece of configuration information 105, and the operation shown in FIG. 15 is repeated every time the configuration information 105 is received.

  When the information processing apparatus 100 receives the configuration information 105 from the outside, the determination unit 103 inputs the configuration information 105 (S101), and determines the PE 106 and the router 107 whose operation settings are to be changed from the ID included in the configuration information 105. Then, a determination signal is output (S102). For example, when the configuration information 105 includes ID = 01, 02, 04, 07, 08, 10, 11, 13, PEs corresponding to these IDs are PEs 106a to 106d, and the corresponding routers are routers 107a to 107f. .

  Next, the path determination unit 104 generates a path switching signal based on the determination signal and the path switching table shown in FIG. 11B, and transmits the path switching signal to the dynamic reconfiguration circuit 101 (S103). When a predetermined time elapses (S104), a route setting completion signal is output (S105). At this time, the transmission path of the configuration information 105 is as shown in FIG. In FIG. 14, routers 107g to 107n are routers 107 that are not the target of changing the operation setting but are necessary for forming a transmission path, and are incorporated in the transmission path.

  When the route setting completion signal is output, the control unit 102 transmits the configuration information 105 to the dynamic reconfiguration circuit 101 (S106). Then, it is determined whether or not the configuration information 105 has been received from the dynamic reconfiguration circuit 101 (S107). When the transmitted configuration information 105 is received again, the control unit 102 determines that all the PEs 106 and the router 107 that should receive the configuration information 105 have received the configuration information 105, in other words, transmission of the configuration information 105 has been completed. To do. Then, the control unit 102 transmits a processing start signal to the dynamic reconfiguration circuit 101 (S108).

  The PE 106 that has received the processing start signal receives data to be processed from the router 107, and executes arithmetic processing (S109). When the arithmetic processing is completed, a processing completion signal is transmitted to the control unit 102 (S110).

  As described above, the determination unit 103 determines the PE 106 and the router 107 whose operation settings are changed. According to the determination result, the route setting unit 104 sets a transmission route for transmitting the configuration information 105 to the PE 106 and the router 107 whose operation settings are changed. As a result, the minimum transmission path necessary for transmitting the configuration information 105 to the PE 106 and the router 107 whose operation settings are changed is formed as the transmission path. Therefore, it is possible to reduce the dynamic power consumed when changing some operation settings of the calculation element and the connection element. Furthermore, the time required for transmitting the configuration information can be shortened by shortening the transmission path.

Configuration Description of Configuration Information Generation Device and Semiconductor Device A configuration example of a configuration information generation device that generates configuration information 105 and a semiconductor device that uses the configuration information 105 is shown in the block diagram of FIG.

  In FIG. 16A, the CPU 1901 controls the entire apparatus. The ROM 1902 stores a boot program and the like. The RAM 1903 is used as a work area for the CPU 1901 and is loaded with an operating system (OS), application programs, and the like.

  A hard disk drive (HDD) 1904 stores the OS, an application program for creating the configuration information 105, and various data. A keyboard 1905 and a mouse 1906 function as an input unit for the user interface.

  The display control unit 1907 includes a video memory and a video controller. The display device 1908 receives the video signal from the display control unit 1907 and displays an image represented by the video signal. An image displayed on the display device 1908 includes a user interface.

  An interface (I / F) 1909 is an interface for communicating with various external devices. For example, when the external memory 1910 is connected to the I / F 1909, the CPU 101 can write the created configuration information 105 into the external memory 1910.

  In the above configuration, when the configuration information generating apparatus is powered on, the CPU 1901 executes the boot program stored in the ROM 1902 and loads the OS stored in the HDD 1904 into the RAM 1903. Thereafter, when an application program for creating the configuration information 105 is activated, the configuration information generation device functions as a circuit configuration information creation device. Then, the created configuration information 105 is input to the information processing apparatus 100 via, for example, the external memory 1910 and used for the processing of the present invention.

  In FIG. 16B, the semiconductor device 200 includes a reconstruction device 201 and an external memory 1910. The reconfiguration device 201 includes the information processing apparatus 100 according to the embodiment, the CPU 202, an interface (I / F) 204, an input / output port (I / O) 205, and a bus 203 that connects these configurations. Note that the structure of the semiconductor device is not limited to FIG.

  The CPU 202 controls the entire reconfigurable device 201. An external memory 1910 connected to the I / F 204 is a memory such as an EEPROM or a RAM that stores configuration information 105, a boot program, an OS, and applications. The I / O 205 is a port for the reconstruction device 201 to input / output processing target data such as image data or processing result data 206. Of course, the configuration information 105 can also be input via the I / O 205.

  FIG. 17 shows an arrangement example of the configuration information 105 held in the external memory 1910. Each piece of configuration information 105 is stored in order from the upper address of the external memory 1910 in the order in which the configuration information is used. That is, the first configuration information 1601 for realizing the first data processing, the second configuration information 1602 for realizing the second data processing, and so on are stored in this order. The first configuration information 1601 is held in the address area 1603, and the second configuration information 1602 is held in the address area 1604. Note that the configuration information 105 is not limited to the arrangement of the configuration information 105 illustrated in FIG.

  When power is turned on to the semiconductor device 200, the CPU 202 executes a boot program stored in the external memory 1910 to start the system. When the system is activated, for example, the CPU 202 reads the configuration information 105 via the I / O 205, stores the configuration information 105 in the external memory 1910, and then reads the configuration information 105 from the external memory 1910 to the information processing apparatus 100. Instruct. In accordance with the instruction, the information processing apparatus 100 reads the configuration information 105 from the external memory 1910, and the configuration information 105 is read into the information processing apparatus 100 in the order of the first configuration information 1601, the second configuration information 1602,.

  Thereafter, the information processing apparatus 100 performs operation setting and data processing according to the configuration information 105. That is, operation setting of the dynamic reconfiguration circuit 101 in the information processing apparatus 100 is performed, and when the operation setting is completed, the processing target data 206 is input to the information processing apparatus 100 via the I / O 205. Then, data processing is performed by the PE 106 in the dynamic reconfiguration circuit 101, and when the data processing is completed, the processing result data 206 is output via the I / O 205.

  In the above description, the configuration information 105 is read via the I / O 205 and the configuration information 105 is stored in the external memory 1910. However, the external memory 1910 in which the configuration information 105 is stored in advance is incorporated in the semiconductor device 200. But you can.

  The information processing apparatus according to the second embodiment of the present invention will be described below. Note that the same reference numerals in the second embodiment denote the same parts as in the first embodiment, and a detailed description thereof will be omitted.

  Although the clock signal is supplied to the dynamic reconfiguration circuit 101, the clock supply to the circuit block unnecessary for the transmission operation of the configuration information 105 can be stopped after the transmission path is set.

  An example of the configuration of the information processing apparatus 100 according to the second embodiment is shown in the block diagram of FIG. The information processing apparatus 100 according to the second embodiment has a clock gating function that stops clock supply to a circuit block that is unnecessary for the transmission operation of the configuration information 105.

  The determination unit 103 generates a determination signal as in the first embodiment, and transmits the generated determination signal to the path determination unit 104 and the gate setting unit 110. Further, the path setting unit 104 generates a path setting completion signal as in the first embodiment, and transmits the generated path setting completion signal to the control unit 102 and the gate setting unit 110.

  The gate setting unit 110 starts generating a clock gating signal when receiving the determination signal, and transmits the clock gating signal to the dynamic reconfiguration circuit 101 when receiving the path setting completion signal.

  A configuration example of the circuit block and a table provided in the gate setting unit 110 will be described with reference to FIG. The clock gate circuit 111 illustrated in FIG. 19A switches between clock supply and supply stop. The clock gate circuit 111 is prepared for each of the PE 106, the router 107, and the switch 108, and a clock signal is input to one input and a clock gating signal is input to the other input. The clock gate circuit 111 can be constituted by, for example, a two-input logical product (AND) circuit. That is, the clock gate circuit 111 supplies the clock signal to the PE 106, the router 107, or the switch 108 when the input clock gating signal is '1', and the clock signal of the clock signal when the clock gating signal is '0'. Stop supplying.

  The table shown in FIG. 19B shows a correspondence relationship between the determination signal and transmission path signals representing the PE 106, the router 107, and the switch 108 that form the transmission path. Each bit of the transmission path signal corresponds to each address of the PE 106, the router 107, and the switch 108. For example, when the transmission path shown in FIG. 14 is formed, the bit corresponding to PEs 106a to 106d, the bit corresponding to routers 107a to 107n, and the bit corresponding to the switch 108 indicated by the arrow in FIG. A transmission path signal is generated.

  When receiving the determination signal, the gate setting unit 110 refers to the table shown in FIG. 19B and generates a transmission path signal corresponding to the determination signal. Then, a signal (clock gating signal) obtained by logically inverting the transmission path signal is transmitted to the clock gate circuit 111.

  As a result, a clock gating signal having a signal value of “0” is input to the clock gate circuit 111 connected to the PE 106, the router 107, and the switch 108 that are not arranged in the transmission path of the configuration information 105. That is, the supply of the clock signal to the PE 106, the router 107, and the switch 108 that are unnecessary for the transmission operation of the configuration information 105 is stopped.

  In order to transmit the clock gating signal to the PE 106, the router 107, and the switch 108 in parallel, transmission wiring for the clock gating signal is provided by the number of the PE 106, the router 107, and the switch 108.

  In this way, by providing a function for clock gating circuit blocks that are unnecessary for the transmission operation of the configuration information 105 in the dynamic reconfiguration circuit 101, the clock consumed by the components that are unnecessary for the transmission operation of the configuration information 105 The power related to can be reduced.

  The information processing apparatus according to the third embodiment of the present invention will be described below. Note that the same reference numerals in the third embodiment denote the same parts as in the first and second embodiments, and a detailed description thereof will be omitted.

  The dynamic reconfiguration circuit 101 may have a plurality of circuit blocks that can switch the power source between an on state and an off state. In this case, the power of circuit blocks (hereinafter referred to as necessary blocks) necessary for the operation of the dynamic reconfiguration circuit 101 may be turned on, and the power of circuit blocks other than the necessary blocks (hereinafter unnecessary blocks) may be turned off. it can.

  A block diagram of FIG. 20 shows a configuration example of the information processing apparatus 100 according to the third embodiment. The information processing apparatus 100 according to the third embodiment includes a plurality of circuit blocks that can be controlled by the dynamic reconfiguration circuit 101, and includes a power control unit 120 that controls on / off of the power of each circuit block.

  FIG. 21 shows a configuration example of the dynamic reconfiguration circuit 101 of the third embodiment. The dynamic reconfiguration circuit 101 includes a plurality of circuit blocks 401a to 401d capable of power supply control. Each circuit block 401a to 401d is supplied with power from a power circuit block (not shown) via power switches 402a to 402d. By switching opening and closing of the power switches 402a to 402d, it is possible to switch between power supply (power on) and power shutdown (power off) to the circuit blocks 401a to 401d.

  The power control table provided in the power control unit 120 will be described with reference to FIG. The power control table indicates the correspondence relationship between the power switching signal and the path switching signal corresponding to the determination signal. Each bit of the power switch signal indicates opening / closing of each power switch 402a to 402d. For example, when the power switch signal is "0001", the power switches 402a to 402c are opened and the power switch 402d is closed. Further, the route switching signal is the same as in FIG. 11B, and the detailed description thereof is omitted.

  When receiving the determination signal, the power supply control unit 120 refers to the power supply control table, and outputs a power supply switching signal for turning on a circuit block that requires power supply to the dynamic reconfiguration circuit 101, and a path switching signal. Is output to the route setting unit 104. The path setting unit 104 outputs the received path switching signal to the dynamic reconfiguration circuit 101. The power supply control unit 120 holds the power supply switching signal until a new determination signal is received.

  Although an example in which the power control unit 120 outputs the power switch signal and the path switch signal corresponding to the determination signal has been described, the power control unit 120 may only output the power switch signal corresponding to the determination signal. In that case, the path setting unit 104 obtains a power switch signal, determines a circuit block in the power-on state, and uses a circuit switch in the power-on state to generate a path switch signal for setting the transmission path of the configuration information 105. Output. That is, the path setting unit 104 includes a table in which a path switching signal corresponding to the determination signal is registered for each combination of circuit blocks in the power-on state, and outputs the path switching signal with reference to the table.

  Alternatively, the transmission route of the configuration information 105 may be set by a configuration in which the transmission route provided in the route setting unit 104 is autonomously searched without referring to the table provided in the power control unit 120 or the route setting unit 104. . For example, a CPU may be mounted on the route setting unit 104 and the route search may be executed by the CPU.

  In addition, in order to transmit the power switching signal for the number of circuit blocks, transmission wiring for the power switching signal is prepared for the number of circuit blocks.

  In this way, the function of turning off the power of the unnecessary block is provided, and the transmission path of the configuration information 105 is set according to the power state of the circuit block. As a result, power consumption of unnecessary blocks can be reduced, and the configuration information 105 can be transmitted via the circuit block in the power-on state.

  Note that the information processing apparatus 100 that combines the clock gating function of the second embodiment and the power supply control function of the third embodiment can be easily realized by those skilled in the art referring to the above description, and such an information processing apparatus. 100 is also included in the scope of the present invention.

  In addition, the configuration other than the dynamic reconfiguration circuit 101 of the information processing apparatus 100 can be configured by a computer such as a microprocessor. In this case, the computer is supplied with a program that realizes a configuration other than the dynamic reconfiguration circuit 101 via a recording medium such as a ROM.

[Other Examples]
The present invention can also be realized by executing the following processing. That is, software (program) that realizes the functions of the above-described embodiments is supplied to a system or apparatus via a network or various recording media, and a computer (or CPU, MPU, etc.) of the system or apparatus reads the program. It is a process to be executed.

Claims (18)

Transmission of configuration information indicating a plurality of calculation elements that perform calculation processing, a plurality of connection elements that connect the plurality of calculation elements, and operation settings of at least some of the plurality of calculation elements and the plurality of connection elements An arithmetic circuit including a plurality of switches forming a path;
A determination means for determining a calculation element and a connection element whose operation settings are changed by configuration information;
An information processing apparatus comprising: an arithmetic element whose operation setting is changed; and a path setting unit which transmits a path switching signal for forming a transmission path for transmitting the configuration information to a connection element to the plurality of switches.   2. The information processing apparatus according to claim 1, further comprising a control unit that transmits the configuration information to the transmission path. The route setting means outputs a route setting completion signal when a predetermined time has elapsed after transmitting the route switching signal,
3. The information processing apparatus according to claim 2, wherein the control unit transmits the configuration information when the route setting completion signal is output.   4. The information processing apparatus according to claim 2, wherein the control unit transmits a processing start signal to the arithmetic circuit when the transmitted configuration information is received from the arithmetic circuit.   5. The information processing apparatus according to claim 1, wherein the transmission path is formed by at least a part of the plurality of arithmetic elements, the plurality of connection elements, and the plurality of switches. Furthermore, it has a gate setting means for generating a clock gating signal based on the result of the determination,
6. The information processing apparatus according to claim 5, wherein the clock gating signal is transmitted to a plurality of gates included in the arithmetic circuit that switches between supply and stop of a clock for each of the arithmetic element, the connection element, and the switch. .   7. The information processing apparatus according to claim 6, wherein the clock gating signal is a signal for stopping supply of the clock to the arithmetic element, the connection element, and the switch that do not form the transmission path. Furthermore, based on the result of the determination, it has a power supply control means for generating a power supply switching signal,
The power supply switching signal is transmitted to a plurality of power switches included in the arithmetic circuit that switches between power supply and cutoff for each of the circuit blocks including the arithmetic element, the connection element, and the switch. The information processing apparatus described in any one of the above.   9. The information processing apparatus according to claim 8, wherein the power control unit supplies a path switching signal generated based on the determination result to the path setting unit.   9. The information processing apparatus according to claim 8, wherein the path setting unit generates the path switching signal based on the determination result and the power switching signal.   When the received configuration information includes an identification number that matches its own identification number, the calculation element and the connection element perform the operation setting according to the setting value of the configuration information corresponding to the identification number, and the configuration information 11. The information processing apparatus according to any one of claims 1 to 10, wherein the information is output to the rear of the transmission path.   The calculation element and the connection element, when the received configuration information does not include an identification number that matches its own identification number, outputs the configuration information to the rear of the transmission path without performing the operation setting. The information processing apparatus according to any one of claims 1 to 10.   The operation setting of the arithmetic element includes setting of an input path for inputting data to be processed, setting of arithmetic processing to be performed on the processing target data, and setting of an output path for outputting processing result data. An information processing apparatus according to claim 12.   14. The information processing apparatus according to claim 11, wherein the operation setting of the connection element includes setting of an input path for inputting data and setting of an output path for outputting the data.   15. The information processing apparatus according to claim 1, wherein the determination unit determines a calculation element and a connection element whose operation setting is changed based on an identification number included in the configuration information. Transmission of configuration information indicating a plurality of calculation elements that perform calculation processing, a plurality of connection elements that connect the plurality of calculation elements, and operation settings of at least some of the plurality of calculation elements and the plurality of connection elements A method for controlling an information processing apparatus having an arithmetic circuit including a plurality of switches forming a path,
Determine the calculation element and connection element whose operation settings are changed according to the configuration information,
A control method for transmitting, to the plurality of switches, a path switching signal for forming a transmission path for transmitting the configuration information to the arithmetic element and the connection element whose operation settings are changed.   16. A program for causing a computer to function as each unit of the information processing apparatus according to any one of claims 1 to 15.   A computer-readable recording medium on which the program according to claim 17 is recorded.

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