JP2015060025A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display device that secures capacity for transferring a pixel signal capable of satisfactorily driving a liquid crystal, and allows for downsizing.SOLUTION: A first holding capacity part C1 holds a pixel signal selectively inputted via a first transistor Tr1, includes a holding capacity part C11, a holding capacity part C12 and a holding capacity part C13, and is formed on a first capacity formation layer and a second capacity formation layer which are located above a semiconductor substrate 400 on which the first transistor Tr1 and a second transistor Tr2 are formed. A second holding capacity part C2 holds a pixel signal selectively transferred via the second transistor Tr2, and is formed on a second capacity formation layer which is located above the semiconductor substrate 400 on which the first transistor Tr1 and the second transistor Tr2 are formed.

Description

  The present invention relates to a reflective liquid crystal display device that employs a structure in which liquid crystal is sandwiched between an opposing semiconductor substrate and a light-transmitting substrate.

  Conventionally, as this type of technology, for example, one described in Patent Document 1 shown below is known. Patent Document 1 describes a reflective liquid crystal display device including a plurality of pixel circuits 7 arranged in a matrix on a silicon substrate 21. In the pixel circuit 7, the pixel signal is written and held in the capacitor Cs2 via the transistor Tr2, and the held pixel signal is transferred to the capacitor Cs1 and held via the transistor Tr1. The pixel signal held in the capacitor Cs1 is applied to the reflective electrode 9a of the liquid crystal display element 8, and the liquid crystal display element 8 is driven.

  The capacitor Cs2 is formed on the silicon substrate 21 on which the transistor Tr2 is formed. That is, the capacitor Cs2 has a MIS structure in which an oxide film on a silicon substrate is sandwiched between the polysilicon 205 and the high diffusion region 209.

JP 2004-133147 A

  In the above conventional liquid crystal display device, in order to sufficiently drive the liquid crystal, the capacitor Cs2 needs to secure a capacitance value that can sufficiently transfer the held pixel signal to the capacitor Cs1 with respect to the capacitance value of the capacitor Cs1. is there.

  On the other hand, when the pixel pitch is miniaturized in order to reduce the size of the liquid crystal display device or increase the number of pixels for higher resolution, the area of the unit pixel circuit is reduced. Accordingly, the area of the capacitor Cs2 formed on the silicon substrate 21 is also reduced, and the capacitance value of the capacitor Cs2 is reduced. For this reason, when trying to reduce the pixel pitch, the capacitance value of the capacitor Cs2 cannot be sufficiently secured, and the liquid crystal may not be sufficiently driven.

  In other words, if it is attempted to drive the liquid crystal while sufficiently securing the capacitance value of the capacitor Cs2, it has been difficult to reduce the pixel pitch and reduce the size of the liquid crystal display device or to increase the resolution.

  An object of the present invention is to provide a liquid crystal display device capable of reducing the size and increasing the resolution while ensuring a capacity capable of sufficiently driving a liquid crystal.

  The present invention includes a plurality of pixel circuits (11) sandwiched between a semiconductor substrate (400) and a translucent substrate (412) and arranged in a matrix, and the pixel circuits are formed on the semiconductor substrate. A liquid crystal (LC) sandwiched between the pixel electrode (16a) formed and the common electrode (16b) formed on the translucent substrate, and the liquid crystal has a voltage applied to the pixel electrode and a voltage applied to the common electrode. And a first transistor (Tr1) which is formed on a semiconductor substrate and selectively receives a pixel signal. The pixel portion is driven in accordance with the potential difference between the light-transmitting substrate and the light incident from the translucent substrate. ), A first storage capacitor portion (C1) that holds a pixel signal selectively input via the first transistor, and a pixel signal formed in the semiconductor substrate and held in the first storage capacitor portion is transferred. The second transistor (Tr2) and the second A second storage capacitor section (C2) that holds the pixel signal transferred through the transistor, and drives the liquid crystal by applying the voltage of the pixel signal stored in the second storage capacitor section to the pixel electrode. The first storage capacitor unit has a dielectric (410) sandwiched between electrodes (L21, L31, M11, M12, M21), and the first storage capacitor unit is more than the semiconductor substrate on which the first transistor and the second transistor are formed. It is formed in the upper first capacitor forming layer and the second capacitor forming layer, and the second storage capacitor portion is formed in the second capacitor forming layer with the dielectric sandwiched between the electrodes (L33, M22). A liquid crystal display device is provided.

  According to the liquid crystal display device of the present invention, it is possible to provide a liquid crystal display device capable of reducing the size and increasing the resolution while ensuring a capacity capable of sufficiently driving the liquid crystal.

It is a figure which shows the structure of the liquid crystal display device which concerns on embodiment of this invention. It is a figure which shows an example of the characteristic of the drive voltage of a liquid crystal, and the transmittance | permeability. It is a figure which shows typically the voltage applied to a liquid crystal, and the drive mode of a liquid crystal. It is a figure which shows the typical cross-section of the pixel circuit in the liquid crystal display device which concerns on embodiment of this invention. It is a figure which shows the planar structure of one electrode of the 1st capacity | capacitance holding part and the 2nd capacity | capacitance holding part of a pixel circuit. It is a figure for demonstrating the relationship between the capacitance value of the 1st capacity | capacitance holding part in a pixel circuit, and the 2nd capacity | capacitance holding part, and transfer of a pixel signal.

  Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.

(Embodiment)
A circuit configuration of a liquid crystal display device according to an embodiment of the present invention will be described with reference to FIG. In FIG. 1, the liquid crystal display device includes a pixel circuit 11, a horizontal scanning circuit 12, and a vertical scanning circuit 13.

  A plurality (m × n) of pixel circuits 11 are arranged in a matrix at each intersection of m column data lines D (D1 to Dm) and n row scanning lines G (G1 to Gn). . The plurality of pixel circuits 11 are all configured identically. Therefore, here, the configuration of the pixel circuit 11 will be described on behalf of the pixel circuit 11 arranged at the intersection of the column data line D1 and the row scanning line G1.

  The pixel circuit 11 includes a first transistor Tr1, a second transistor Tr2, a first storage capacitor unit C1, a second storage capacitor unit C2, and a liquid crystal LC.

  The first transistor Tr1 is a switching transistor, and is composed of, for example, an N-channel MOS field effect transistor. The first transistor Tr1 has a gate terminal connected to the row scanning line G1, and a drain terminal connected to the column data line D1. The first transistor Tr1 is conductively controlled according to a row selection signal applied to the row scanning line G1, and selectively inputs a pixel signal applied to the column data line D1 to the pixel circuit 11.

  The second transistor Tr2 is a transfer transistor, and is composed of, for example, an N-channel MOS type field effect transistor die. The second transistor Tr2 has a gate terminal connected to the trigger signal line TS and a drain terminal connected to the source terminal of the first transistor Tr1. The second transistor Tr2 is conduction-controlled according to a trigger signal (Trg) given to the trigger signal line TS. The second transistor Tr2 transfers the pixel signal held in the first holding capacitor unit C1 to the second holding capacitor unit C2.

  The first storage capacitor C1 has a so-called MIM (Metal-Insulator-Metal) structure in which a dielectric (not shown) is sandwiched between a first electrode 14a and a second electrode 14b made of metal. In the first storage capacitor C1, the first electrode 14a is connected to the source terminal of the first transistor Tr1 and the drain terminal of the second transistor Tr2, and the second electrode 14b is connected to the reference potential common terminal Com. A preset reference voltage Vcom, for example, a ground potential is applied to the reference potential common terminal Com. The first holding capacitor unit C1 holds a pixel signal selectively input via the first transistor Tr1.

  The second storage capacitor C2 has a so-called MIM (Metal-Insulator-Metal) structure in which a dielectric (not shown) is sandwiched between a first electrode 15a and a second electrode 15b made of metal. In the second storage capacitor unit C2, the first electrode 15a is connected to the source terminal of the second transistor Tr2, and the second electrode 15b is connected to the reference potential common terminal Com. The second storage capacitor unit C2 stores the pixel signal transferred from the first storage capacitor unit C1 via the second transistor Tr2.

  The liquid crystal LC is configured so as to be filled and sealed between a pixel electrode 16a having light reflectivity and a common electrode 16b disposed opposite to the pixel electrode 16a. The pixel electrode 16a is connected to the source terminal of the second transistor Tr2 and the first electrode 15a of the second storage capacitor unit C2. The common electrode 16b is connected to the common electrode terminal CE. The common electrode terminal CE is supplied with a common electrode voltage Vce set in advance according to the voltage of the pixel signal applied to the pixel electrode 16a.

  The liquid crystal LC is driven according to the potential difference between the voltage of the pixel signal applied to the pixel electrode 16a and the common electrode voltage Vce applied to the common electrode 16b.

  Column data lines D (D1 to Dm) are connected to the horizontal scanning circuit 12. The horizontal scanning circuit 12 inputs a horizontal synchronization signal (Hst), a horizontal scanning clock signal (Hck), and a pixel signal. The horizontal scanning circuit 12 sequentially outputs pixel signals to the column data lines D1 to Dm in units of one horizontal scanning period based on the horizontal synchronization signal and the horizontal scanning clock signal.

  Row scanning lines G 1 to Gn are connected to the vertical scanning circuit 13. The vertical scanning circuit 13 receives a vertical synchronization signal (Vst) and a vertical scanning clock signal (Vck). The vertical scanning circuit 13 sequentially supplies row selection signals, for example, to the row scanning lines G1 to Gn in units of one horizontal scanning period based on the vertical synchronization signal and the clock signal for vertical scanning.

  As described above, the pixel circuit 11 includes the pixel unit including the liquid crystal LC sandwiched between the pixel electrode 16a and the common electrode 16b, the first transistor Tr1, the second transistor Tr2, the first storage capacitor unit C1, and the second transistor. And a drive unit including a storage capacitor unit.

  Next, the operation of the liquid crystal display device having the above configuration will be described.

  The pixel signals corresponding to the column data lines D1 to Dm are output from the horizontal scanning circuit 12 to the column data lines D1 to Dm during one horizontal scanning period. On the other hand, a selection signal for turning on the first transistor Tr1 is output from the vertical scanning circuit 13 to the row scanning line G, for example, the row scanning line G1, for one horizontal scanning period. As a result, the m first transistors Tr1 whose gate terminals are connected to the row scanning line G1 are turned on.

  Each pixel signal output to each column data line D1 to Dm is given to and written to the first storage capacitor C1 via the first transistor Tr1 connected corresponding to each column data line D1 to Dm. Thereafter, a selection signal for turning off the first transistor Tr1 is output from the vertical scanning circuit 13 to the row scanning line G1. As a result, the m first transistors Tr1 whose gate terminals are connected to the row scanning line G1 are turned off.

  The pixel signal written in the first storage capacitor unit C1 is stored in the first storage capacitor unit C1 during a non-selection period until a new pixel signal is given in the next vertical scanning period. Note that the second transistor Tr2 is in a non-conductive state until the operation in which the pixel signal is written and held in the first holding capacitor portion C1 of all the pixel circuits 11 is completed.

  Such pixel signal writing operation is executed for all the row scanning lines G, and one frame of pixel signals is sequentially written in the first storage capacitor C1 of all the m × n pixel circuits 11. Held.

  When the pixel signal writing operation for one frame is completed, a trigger signal for turning on the second transistor Tr2 is commonly applied to the gate terminals of the second transistors Tr2 of all the pixel circuits 11. As a result, the second transistors Tr2 of all the pixel circuits 11 are simultaneously turned on. In all the pixel circuits 11, the pixel signal held in the first holding capacitor unit C1 is transferred all at once to the second holding capacitor unit C2 via the second transistor Tr2, and the pixel electrode is used as a voltage corresponding to the pixel signal. 16a. The pixel signal transferred to the second storage capacitor unit C2 is stored in the second storage capacitor unit C2.

  After a voltage corresponding to the pixel signal is applied to each pixel electrode 16a of all the pixel circuits 11, a trigger signal for turning off the second transistor Tr2 is applied to the gate terminal of the second transistor Tr2, and the second transistor Tr2 is turned off. Thereafter, the pixel signal writing operation for the next frame is started as described above.

  While the pixel signal writing operation for the next frame is being performed, the second transistor Tr2 is maintained in a non-conductive state. As a result, the pixel signal transferred to the second storage capacitor unit C2 is stored in the second storage capacitor unit C2 and also holds the state of being applied to the pixel electrode 16a as a voltage corresponding to the pixel signal.

  A signal voltage of the pixel signal held in the second holding capacitor unit C2 is applied to the pixel electrode 16a. The liquid crystal LC is driven according to the potential difference between the voltage of the pixel signal applied to the pixel electrode 16a and the common electrode voltage Vce applied to the common electrode 16b, and the display corresponding to the pixel signal written to each pixel circuit 11 is displayed. Is done.

  A liquid crystal display mode suitable for a reflective liquid crystal display device includes a field effect birefringence mode. In the field effect birefringence mode, normally black type or normally white type characteristics can be obtained depending on the dielectric anisotropy and initial orientation of the liquid crystal. In the present embodiment, a normally black type will be described with reference to FIG.

  FIG. 2 is a diagram showing an example of the liquid crystal driving voltage-transmittance characteristics of the liquid crystal LC used in this embodiment. In FIG. 2, the horizontal axis represents the voltage applied to the pixel electrode 16a of the liquid crystal LC, the vertical axis represents the monochrome (black and white) display color of the display image, and the voltage V1 represents the black (output light) of the display image. Corresponding to the intensity Pb), the voltage V2 corresponds to the white color of the display image (output light intensity Pw).

  In a liquid crystal display device, it is preferable to drive a normal liquid crystal with an alternating voltage in which a positive voltage application and a negative voltage application are alternately set from the viewpoint of preventing burn-in of a display image and deterioration of a liquid crystal material. Here, positive polarity is when the voltage applied to the pixel electrode 16a is higher than the common electrode voltage Vce, and negative polarity is when the voltage applied to the pixel electrode 16a is lower than the common electrode voltage Vce. .

  In a pixel circuit having a configuration in which a pixel signal is captured and held in one holding capacitor portion via one transistor, the pixel signal cannot be simultaneously supplied to the liquid crystals of all the pixel circuits. As a result, the common electrode voltage Vce applied to the common electrode 16b of the liquid crystal LC is not changed, and when displaying black, the voltage that becomes the common electrode voltage Vce + voltage V1 and the voltage that becomes the common electrode voltage Vce−voltage V1 alternate. Is applied to the pixel electrode 16a. On the other hand, when displaying white, a voltage that becomes the common electrode voltage Vce + voltage V2 and a voltage that becomes the common electrode voltage Vce−voltage V2 are alternately applied to the pixel electrode 16a. Here, the voltages V1 and V2 are the voltages shown in FIG. In such a driving mode, the amplitude of the voltage applied to the pixel electrode 16a of the liquid crystal LC is 2 × V2 at the maximum.

  In contrast, in the present embodiment, the liquid crystal LC is driven by applying a voltage as shown in FIG. FIG. 3 schematically shows the voltage applied to the liquid crystal LC used in this embodiment and the driving mode of the liquid crystal LC.

  As shown in FIG. 3, the voltage Va applied to the pixel electrode 16a when displaying black with a positive polarity is substantially equal to the voltage Va applied to the pixel electrode 16a when displaying white with a negative polarity. In addition, the voltage Vb applied to the pixel electrode 16a when displaying a positive white color and the voltage Vb applied to the pixel electrode 16a when displaying black negative polarity are substantially equal. As described above, the pixel electrode 16a is supplied with a voltage in a form in which the voltage ranges and levels of the positive and negative polarities overlap in the amplitude direction.

  When black display is performed in the positive polarity, the common electrode voltage Vce that is lower than the voltage Va applied to the pixel electrode 16a by a voltage V1 is applied to the common electrode 16b. Further, when black display is performed in the negative polarity, a common electrode voltage Vce that is higher than the voltage Vb applied to the pixel electrode 16a by a voltage V1 is applied to the common electrode 16b. That is, the common electrode voltage Vce is voltage Va−voltage V1 in the positive polarity and is voltage Vb + voltage V1 in the negative polarity.

  On the other hand, when white display is performed in the positive polarity, the common electrode voltage Vce that is lower than the voltage Vb applied to the pixel electrode 16a by the voltage V2 is applied to the common electrode 16b. Further, when white display is performed in the negative polarity, the common electrode voltage Vce that is lower than the voltage Va applied to the pixel electrode 16a by a voltage V2 is applied to the common electrode 16b. That is, the common electrode voltage Vce is voltage Vb−voltage V2 in the positive polarity, and is voltage Va + voltage V2 in the negative polarity.

  As described above, when black or white display is performed with positive and negative polarities, as shown in FIG. 3, the amplitude of the voltage applied to the pixel electrode 16a is voltage Va−voltage Vb, that is, voltage V2−voltage V1. Become. As a result, the applied voltage to be applied to the pixel electrode 16a can be reduced in amplitude compared to the case where the common electrode voltage Vce is not changed. As a result, the required breakdown voltage of the first transistor Tr1, the second transistor Tr2, the first storage capacitor unit C1, and the second storage capacitor unit C2 can be reduced, and the device can be densified.

  FIG. 4 is a diagram showing a schematic cross-sectional structure of a pixel circuit in the liquid crystal display device of the present embodiment. FIG. 4 shows a cross-sectional structure of two pixel circuits in the horizontal direction of the drawing. Since all the pixel circuits have the same structure, the pixel circuit shown on the left side of FIG. The structure of the pixel circuit will be described.

  In FIG. 4, a well region 401 is formed on a semiconductor substrate 400 made of, for example, a silicon substrate. In the well region 401, the first transistor Tr1 and the second transistor Tr2 shown in FIG. 1 are formed. When the first transistor Tr1 and the second transistor Tr2 are N-channel field effect transistors, the well region 401 is a P-type well region.

  In the well region 401, diffusion layers 402 and 403 in which impurities are diffused are formed with a predetermined distance therebetween. When the first transistor Tr1 is composed of an N-channel field effect transistor, N-type impurities such as boron are implanted and diffused into the diffusion layers 402 and 403, for example.

  Polysilicon 405 is formed on the well region 401 between the diffusion layer 402 and the diffusion layer 403 via a silicon oxide film 404 serving as a gate oxide film. Thus, the first transistor Tr1 is formed using the diffusion layer 402 as the drain region, the diffusion layer 403 as the source region, and the polysilicon 405 as the gate electrode.

  In the well region 401, a diffusion layer 406 in which impurities are diffused is formed at a predetermined distance from the diffusion layer 403. When the second transistor Tr2 is composed of an N-channel field effect transistor, an N-type impurity such as boron is implanted and diffused into the diffusion layer 406, for example.

  A polysilicon 408 is formed on the well region 401 between the diffusion layer 403 and the diffusion layer 406 via a silicon oxide film 407 serving as a gate oxide film. Thus, the second transistor Tr2 is formed using the diffusion layer 403 as the drain region, the diffusion layer 406 as the source region, and the polysilicon 408 as the gate electrode.

  The diffusion layer 403 that becomes the source region of the first transistor Tr1 and the drain region of the second transistor Tr2 is shared by both transistors. Thereby, the source of the first transistor Tr1 and the drain of the second transistor Tr2 are electrically connected.

  An element isolation region 409 is formed adjacent to the diffusion layer 402 and the diffusion layer 406 so as to surround the first transistor Tr1 and the second transistor Tr2. That is, the inside of the element isolation region 409 is a formation region of the first transistor Tr1 and the second transistor Tr2. By this element isolation region 409, the first transistor Tr1 and the second transistor Tr2 are electrically isolated from the first transistor Tr1 and the second transistor Tr2 of other adjacent pixel circuits.

  Multi-layer wiring at a position where the region in which the first transistor Tr1 and the second transistor Tr2 are formed is substantially translated upward and within an area substantially equal to the formation area in which the first transistor Tr1 and the second transistor Tr2 are formed. The structure is built. With this multilayer wiring structure, the first storage capacitor C1 and the second storage capacitor C2 of one pixel circuit 11 are formed. That is, the first storage capacitor unit C1 and the second storage capacitor unit C2 of one pixel circuit are within an area substantially equal to the formation area where both transistors are formed above the region where both transistors are formed. Is formed.

  In this multilayer wiring structure, a first wiring layer L1, a second wiring layer L2, a third wiring layer L3, and a fourth wiring layer L4 are formed in order from the semiconductor substrate 400 upward. The first wiring layer L1 to the fourth wiring layer L4 are made of a metal such as aluminum or copper, for example. The wiring layers of the first wiring layer L1 to the fourth wiring layer L4 are insulated from each other by an interlayer insulating film 410 such as a silicon oxide film.

  The first wiring layer L1 includes a first wiring portion L11, a second wiring portion L12, and a third wiring portion L13. The first wiring portion L11, the second wiring portion L12, and the third wiring portion L13 are electrically separated from each other.

  The first wiring portion L11 of the first wiring layer L1 is joined to the diffusion layer 402 serving as the drain region of the first transistor Tr1 through the through hole T11. The second wiring portion L12 of the first wiring layer L1 is joined to the diffusion layer 403 serving as the source region of the first transistor Tr1 and the drain region of the second transistor Tr2 through the through hole T12. The third wiring portion L13 of the first wiring layer L1 is joined to the diffusion layer 406 serving as the source region of the second transistor Tr2 through the through hole T13.

  In the structure shown in FIG. 4, the first storage capacitor unit C1 is divided into three storage capacitor units C11, C12, and C13. That is, the three storage capacitor units C11, C12, and C13 are electrically connected in parallel to form the first storage capacitor unit C1.

  The second wiring layer L2 includes a first wiring portion L21 and a second wiring portion L22. The first wiring portion L21 and the second wiring portion L22 are electrically separated from each other.

  The first wiring portion L21 of the second wiring layer L2 constitutes one electrode of the storage capacitor portions C11 and C12. The first wiring portion L21 of the second wiring layer L2 is joined to the second wiring portion L12 of the first wiring layer L1 through the through hole T21. The second wiring portion L22 of the second wiring layer L2 is joined to the third wiring portion L13 of the first wiring layer L1 through the through hole T22.

  A first metal layer M1 is formed between the second wiring layer L2 and the third wiring layer L3. The first metal layer M1 is formed to face the first wiring portion L21 of the second wiring layer L2 with a predetermined spacing. An interlayer insulating film 410 is formed between the first metal layer M1 and the first wiring portion L21 of the second wiring layer L2.

  The first metal layer M1 is made of a metal such as titanium nitride (TiN) or titanium (Ti). The first metal layer M1 forms a first electrode part M11 and a second electrode part M12. The first electrode part M11 and the second electrode part M12 are electrically separated from each other.

  The first electrode part M11 constitutes the other electrode of the storage capacitor part C11. Therefore, the storage capacitor portion C11 is formed with an MIM structure in which the interlayer insulating film 410 serving as a dielectric is sandwiched between the first wiring portion L21 of the second wiring layer L2 and the first electrode portion M11 of the first metal layer M1. ing.

  The second electrode part M12 constitutes the other electrode of the storage capacitor part C12. Accordingly, the storage capacitor portion C12 is formed with an MIM structure in which an interlayer insulating film 410 serving as a dielectric is sandwiched between the first wiring portion L21 of the second wiring layer L2 and the second electrode portion M12 of the first metal layer M1. ing.

  A third wiring layer L3 is formed on the first metal layer M1. The third wiring layer L3 includes a first wiring portion L31, a second wiring portion L32, a third wiring portion L33, and a fourth wiring portion L34. The first wiring portion L31, the second wiring portion L32, the third wiring portion L33, and the fourth wiring portion L34 are electrically separated from each other.

  The first wiring portion L31 of the third wiring layer L3 is connected to the reference potential common terminal Com shown in FIG. 1, and a ground potential is applied as the reference potential Vcom. The first wiring portion L31 of the third wiring layer L3 is joined to the first electrode portion M11 of the first metal layer M1 through the through hole T31. The second wiring portion L32 of the third wiring layer L3 is joined to the first wiring portion L21 of the second wiring layer L2 through the through hole T32.

  The third wiring portion L33 of the third wiring layer L3 is connected to the reference potential common terminal Com shown in FIG. 1, and a ground potential is applied as the reference potential Vcom. The third wiring portion L33 of the third wiring layer L3 is joined to the second electrode portion M12 of the first metal layer M1 through the through hole T33. The fourth wiring portion L34 of the third wiring layer L3 is joined to the second wiring portion L22 of the second wiring layer L2 through the through hole T34.

  A second metal layer M2 is formed between the third wiring layer L3 and the fourth wiring layer L4. The second metal layer M2 is made of a metal such as titanium nitride (TiN) or titanium (Ti). The second metal layer M2 forms a first electrode part M21 and a second electrode part M22. The first electrode part M21 and the second electrode part M22 are electrically separated from each other.

  The first electrode part M21 of the second metal layer M2 is formed to face the first wiring part L31 of the third wiring layer L3 with a predetermined spacing. An interlayer insulating film 410 is formed between the first electrode part M21 of the second metal layer M2 and the first wiring part L31 of the third wiring layer L3.

  The first electrode part M21 of the second metal layer M2 constitutes the other electrode of the storage capacitor part C13. Accordingly, the storage capacitor portion C13 has an MIM structure in which the interlayer insulating film 410 serving as a dielectric is sandwiched between the first wiring portion L31 and the first electrode portion M21 of the third wiring layer L3.

  The second electrode portion M22 of the second metal layer M2 is formed to face the third wiring portion L33 of the third wiring layer L3 with a predetermined spacing. An interlayer insulating film 410 is formed between the second electrode part M22 of the second metal layer M2 and the third wiring part L33 of the third wiring layer L3.

  The second electrode part M22 of the second metal layer M2 constitutes the other electrode of the second storage capacitor part C2. Therefore, the second storage capacitor portion C2 has an MIM structure in which the interlayer insulating film 410 serving as a dielectric is sandwiched between the third wiring portion L33 of the third wiring layer L3 and the second electrode portion M22 of the second metal layer M2. It is configured.

  A fourth wiring layer L4 is formed on the second metal layer M2. The fourth wiring layer L4 includes a first wiring portion L41 and a second wiring portion L42. The first wiring portion L41 and the second wiring portion L42 are electrically separated from each other.

  The first wiring portion L41 of the fourth wiring layer L4 is joined to the first electrode portion M21 of the second metal layer M2 through the through hole T41. The first wiring portion L41 of the fourth wiring layer L4 is joined to the second wiring portion L32 of the third wiring layer L3 through the through hole T42. The second wiring portion L42 of the fourth wiring layer L4 is joined to the second electrode portion M22 of the second metal layer M2 through the through hole T43. The second wiring portion L42 of the fourth wiring layer L4 is joined to the fourth wiring portion L34 of the third wiring layer L3 through the through hole T44.

  In the stacked structure, the first wiring portion L21 of the second wiring layer L2 constituting one electrode of the holding capacitor portion C11 and the holding capacitor portion C12, and the second metal layer constituting one electrode of the holding capacitor portion C13. The first electrode portion M21 of M2 is electrically connected. Further, the first electrode portion M11 of the first metal layer M1 serving as the other electrode of the storage capacitor portion C11 and the first wiring portion L31 of the third wiring layer L3 serving as the other electrode of the storage capacitor portion C13 are electrically connected. And is connected to ground potential. Further, the second electrode portion M12 of the first metal layer M1 which is the other electrode of the storage capacitor portion C12 is electrically connected to the third wiring portion L33 of the third wiring layer L3 and given a ground potential. .

  Accordingly, the storage capacitor unit C11, the storage capacitor unit C12, and the storage capacitor unit C13 are connected in parallel. The electrodes of the storage capacitor unit C11, the storage capacitor unit C12, and the storage capacitor unit C13 that are connected in parallel to which no ground potential is applied are the diffusion layer 403 that becomes the source region of the first transistor Tr1 and the drain region of the second transistor Tr2. Is electrically connected. Therefore, the parallel-connected electrodes of the storage capacitor unit C11, the storage capacitor unit C12, and the storage capacitor unit C13 constitute the first electrode 14a of the first storage capacitor unit C1.

  In the storage capacitor C11, the storage capacitor C12, and the storage capacitor C13, a common ground potential is applied to the other electrode. That is, the respective electrodes to which the ground potential of the storage capacitor unit C11, the storage capacitor unit C12, and the storage capacitor unit C13 are applied constitute the second electrode 14b of the first storage capacitor unit C1.

  In the above stacked structure, the second electrode portion M22 of the second metal layer M2 serving as one electrode of the second storage capacitor portion C2 is electrically connected to the diffusion layer 406 serving as the source region of the second transistor Tr2. . A ground potential is applied to the third wiring portion L33 of the third wiring layer L3 which is the other electrode of the second storage capacitor portion C2. As a result, the second electrode portion M22 of the second metal layer M2 serving as one electrode of the second storage capacitor portion C2 constitutes the first electrode 15a of the second storage capacitor portion C2 shown in FIG. The third wiring portion L33 of the third wiring layer L3 serving as the other electrode of the second storage capacitor portion C2 constitutes the second electrode 15b of the second storage capacitor portion C2 shown in FIG.

  The storage capacitor unit C11, the storage capacitor unit C12, and the storage capacitor unit C13 and the second storage capacitor unit C2 constituting the first storage capacitor unit C1 are each a dielectric sandwiched between both electrodes and the distance between the two electrodes. Are formed equally. Therefore, the capacitance values of the storage capacitor unit C11, the storage capacitor unit C12, and the storage capacitor unit C13 and the second storage capacitor unit C2 constituting the first storage capacitor unit C1 are the areas of the electrodes of the respective storage capacitor units. Determined.

  FIG. 5A is a diagram showing a planar structure of the first metal layer M1, and FIG. 5B is a diagram showing a planar structure of the second metal layer M2.

  As shown in FIG. 5B, the area of the second electrode part M21 of the second metal layer M2 that becomes one electrode of the storage capacitor part C13 is the second metal that becomes one electrode of the second storage capacitor part C2. It is formed larger than the area of the second electrode portion M22 of the layer M2. This is because the capacitance value of the first storage capacitor unit C1 is made larger than the capacitance value of the second storage capacitor unit C2, as will be described in detail later.

  As shown in FIG. 5A, the first electrode part M11 of the first metal layer M1 that is one electrode of the storage capacitor part C11 and the second electrode part M12 that is one electrode of the storage capacitor part C12 are: It is formed electrically separated. The area of the first electrode part M11 of the first metal layer M1 is formed to be equal to the area of the first electrode part M21 of the second metal layer M2 shown in FIG. The area of the second electrode part M12 of the first metal layer M1 is formed to be equal to the area of the second electrode part M22 of the second metal layer M2 shown in FIG.

  This is because the first metal layer M1 and the second metal layer M2 are formed using the same mask pattern. By doing in this way, compared with the case where the 1st metal layer M1 and the 2nd metal layer M2 are formed using a different mask pattern, a mask process can be reduced and a manufacturing process can be facilitated. In addition, it is possible to reduce an area when forming a through hole to be joined to the first metal layer M1 or the second metal layer M2.

  The first electrode part M11 and the second electrode part M12 of the first metal layer M1 can be integrated without being separated, and the storage capacitor part C11 and the storage capacitor part C12 can be formed as one storage capacitor part. . In this case, the capacity value of the first storage capacitor unit C1 can be increased as compared with the case where the storage capacitor unit is divided.

  Returning to FIG. 4, the pixel electrode 16 a is formed on the fourth wiring layer L <b> 4 via the interlayer insulating film 410. The pixel electrode 16a is joined to the second wiring portion L42 of the fourth wiring layer L4 through the through hole T51. Thus, the pixel electrode 16a is electrically connected to the diffusion layer 406 that forms the source region of the second transistor Tr2 through the first wiring layer L1 to the fourth wiring layer L4 and the through-holes that join them. Yes.

  On the upper layer of the pixel electrode 16a, a liquid crystal LC is formed by being sandwiched between alignment layers 411a and 411b that align the initial molecular arrangement of the liquid crystal LC in a predetermined direction.

  A common electrode 16b is formed on the upper layer of the liquid crystal LC. Thereby, the liquid crystal LC is formed to be filled and sealed between the pixel electrode 16a and the common electrode 16b.

  A translucent substrate 412 is formed on the upper layer of the common electrode 16b. Thus, the pixel circuit 11 is formed between the semiconductor substrate 400 and the translucent substrate 412.

  Incident light incident from the translucent substrate 412 passes through the liquid crystal LC and reaches the pixel electrode 16a, and incident light reaching the pixel electrode 16a is reflected by the pixel electrode 16a and passes through the liquid crystal LC again to transmit the light. The light is emitted from the substrate 412. In this process, the incident light is modulated by the liquid crystal LC according to the voltage of the pixel signal applied to the pixel electrode 16a, and a display according to the pixel signal is made.

  FIG. 6 is a diagram for explaining the relationship between the capacitance values of the first storage capacitor unit C1 and the second storage capacitor unit C2 of the pixel circuit 11 and the transfer of the pixel signal to the pixel electrode 16a. 6, the same components as those in FIG. 1 are denoted by the same reference numerals, and the description thereof is omitted. With reference to FIG. 6, the capacitance values of the first storage capacitor C1 and the second storage capacitor C2 constituting the pixel circuit 11 of the liquid crystal display device according to the present invention will be described.

  Here, consider an operation in which the voltage of the pixel signal held in the first holding capacitor C1 is transferred to the second holding capacitor C2. First, it is assumed that the voltage Va is held as the voltage of the pixel signal in the first holding capacitor C1 when the first transistor Tr1 and the second transistor Tr2 are in a non-conductive state. It is assumed that the voltage Vp (n−1) applied to the pixel electrode 16a in the previous frame is held in the second storage capacitor unit C2. That is, the connection point a where one electrode of the first storage capacitor C1 is connected to the first transistor Tr1 and the second transistor Tr2 becomes the voltage Va. Further, the connection point b where one electrode of the second storage capacitor C2 is connected to the second transistor Tr2 and the pixel electrode 16a becomes the voltage Vp (n−1).

  In such a state, when the second transistor Tr2 is turned on by the trigger signal (Trg), the connection point a and the connection point b are electrically connected via the second transistor Tr2. As a result, the voltage at the connection point a and the voltage at the connection point b become the same voltage. When the voltage at the connection point b at this time is Vp (n), the voltage Vp (n) is expressed by the following equation (1).

Vp (n) = K * Vs + (1-K) * Vp (n-1) (1)
In the above equation (1), if the capacitance value of the first storage capacitor unit C1 is C1c and the capacitance value of the second storage capacitor unit C2 is C2c, K = C1c / (C1c + C2c).

  Here, when the relationship of C1c >> C2c is established between the capacitance value C1c of the first storage capacitor unit C1 and the capacitance value C2c of the second storage capacitor unit C2, in the equation (1), K≈1 and Vp (N) ≈Vs. That is, the voltage Vp (n) is substantially equal to the voltage Vs regardless of the value of the voltage Vp (n−1).

  Therefore, in order to efficiently transfer the pixel signal from the connection point a to the connection point b, the ratio C1c / C2c between the capacitance value C1c of the first storage capacitor unit C1 and the capacitance value C2c of the second storage capacitor unit C2 is made as large as possible. It is necessary to set. For example, at least about C1c / C2c = 5 is required, and it is desirable to set C1c / C2c = 10.

  Thereby, the pixel signal written in the pixel circuit 11 and held in the first storage capacitor C1 can be efficiently transferred to the second storage capacitor C2. As a result, the liquid crystal LC can be sufficiently driven with a voltage substantially equal to the voltage of the written pixel signal, and a good liquid crystal display can be realized.

  In order to set the ratio C1c / C2c between the capacitance value C1c of the first storage capacitor unit C1 and the capacitance value C2c of the second storage capacitor unit C2 as large as possible, the capacitance value C1c is increased or the capacitance value C2c is decreased. It is possible.

  However, if the capacitance value C2c is reduced, the function of holding the pixel signal in the second storage capacitor unit C2 may be degraded. Therefore, in order not to cause such a problem, it is desirable to increase the capacitance value C1c.

  In this embodiment, as shown in FIGS. 4 and 5, the first storage capacitor portion C1 includes a first capacitance forming layer including a second wiring layer L2 and a first metal layer M1, and a third wiring layer. It is formed in a second capacitance forming layer composed of L3 and the second metal layer M2. The second storage capacitor portion C2 is formed in a second capacitor formation layer including the third wiring layer L3 and the second metal layer M2. That is, the first storage capacitor unit C1 and the second storage capacitor unit C2 are formed of two different capacitor formation layers.

  As a result, it is possible to increase the degree of freedom in determining the area of the electrodes of both of the storage capacitor units as compared with the case where the first storage capacitor unit C1 and the second storage capacitor unit C2 are formed in one capacitor formation layer. It becomes. That is, the degree of freedom in determining the capacitance value C1c of the first storage capacitor unit C1 and the capacitance value C2c of the second storage capacitor unit C2 can be increased.

  The first storage capacitor unit C1 is formed in two different capacitor formation layers, the first capacitor formation layer and the second capacitor formation layer, whereas the second storage capacitor unit C2 is the second storage capacitor unit C2. It is formed only on the capacitor forming layer. Further, the electrode of the first storage capacitor C1 formed in the second capacitor formation layer is formed larger than the electrode of the second storage capacitor C2. That is, the capacitance value of the storage capacitor unit C13 that bears a partial capacity of the first storage capacitor unit C1 formed in the second capacitor formation layer is set larger than the capacitance value of the second storage capacitor unit C2.

  Accordingly, as described above, in the structure shown in FIG. 4 employed in this embodiment, the ratio C1c / C2c between the capacitance value C1c of the first storage capacitor unit C1 and the capacitance value C2c of the second storage capacitor unit C2 is increased. It becomes possible to set.

  As described above, in this embodiment, the first storage capacitor unit C1 and the second storage capacitor unit C2 are formed in the MIM structure on the upper layer of the semiconductor substrate 400 on which the first transistor Tr1 and the second transistor Tr2 are formed. ing. As a result, it is possible to form the first storage capacitor unit C1 and the second storage capacitor unit C2 in an area substantially equal to the area of the formation region in which the first transistor Tr1 and the second transistor Tr2 are formed.

  As a result, the pixel circuit can be reduced in size as compared with the conventional configuration in which the storage capacitor portion is formed on the semiconductor substrate. For example, the pixel pitch of the conventional one-pixel circuit is about 4.0 μm, whereas the configuration adopted in this embodiment can be reduced to about 3.5 μm. Therefore, a liquid crystal display device having a large number of pixel circuits can be reduced in size.

  The first storage capacitor unit C1 and the second storage capacitor unit C2 are formed in a plurality of layers. Thereby, the freedom degree of design at the time of forming the 1st storage capacitor | condenser part C1 and the 2nd storage capacitor | condenser part C2 can be raised compared with the case where it forms in a single layer. As a result, the capacitance value of the first storage capacitor unit C1 can be made larger than the capacitance value of the second storage capacitor unit C2, and the pixel circuit can be secured while ensuring the capacitance value that can sufficiently drive the liquid crystal as described above. Can be miniaturized.

  The electrodes to which the ground potential is applied as the reference potential of the first storage capacitor unit C1 and the second storage capacitor unit C2 are formed in common by the same third wiring layer L3. This makes it possible to form an electrode to which a ground potential is applied as a reference potential for the first storage capacitor unit C1 and the second storage capacitor unit C2 with a single wiring layer. As a result, it is possible to reduce the number of wiring layers used when forming the first storage capacitor unit C1 and the second storage capacitor unit C2, thereby contributing to simplification of the manufacturing process and downsizing of the device. .

  In FIG. 4 and the description thereof described above, in order to make the description easy to understand, the interlayer insulating film between the second wiring layer L2 and the first metal layer M1 is also formed of the first metal layer M1 and the third wiring layer L3. The interlayer insulating film between the two is also integrally represented as an interlayer insulating film 410, and a specific description thereof is omitted. Actually, after forming the second wiring layer L2, a first interlayer insulating film is formed, a first metal layer M1 is formed on the first interlayer insulating film, and further on the first metal layer M1. A second interlayer insulating film is formed. That is, the interlayer insulating film 410 between the second wiring layer L2 and the third wiring layer L3 is composed of these first and second interlayer insulating films.

  Further, the interlayer insulating film 410 between the third wiring layer L3 and the fourth wiring layer L4 also has two layers, similar to the interlayer insulating film 410 between the second wiring layer L2 and the third wiring layer L3. It is comprised by the interlayer insulation film of this.

DESCRIPTION OF SYMBOLS 11 ... Pixel circuit 16a ... Pixel electrode 16b ... Common electrode 400 ... Semiconductor substrate 410 ... Interlayer insulating film 412 ... Translucent substrate C1 ... 1st holding capacity part C2 ... 2nd holding capacity part C11, C12, C13 ... Holding capacity part L1 ... 1st wiring layer L2 ... 2nd wiring layer L3 ... 3rd wiring layer L4 ... 4th wiring layer LC ... Liquid crystal M1 ... 1st metal layer M2 ... 2nd metal layer

Claims (4)

Having a plurality of pixel circuits arranged in a matrix sandwiched between a semiconductor substrate and a translucent substrate;
The pixel circuit includes a liquid crystal sandwiched between a pixel electrode formed on the semiconductor substrate and a common electrode formed on the translucent substrate, and the liquid crystal is applied to a voltage applied to the pixel electrode and the common electrode. A pixel unit that is driven according to a potential difference with an applied voltage, and light incident from the translucent substrate is modulated with the liquid crystal according to the potential difference;
A first transistor that is formed on the semiconductor substrate and that selectively receives a pixel signal, a first storage capacitor that holds a pixel signal that is selectively input via the first transistor, and a first transistor that is formed on the semiconductor substrate. A second transistor that transfers the pixel signal held in the first holding capacitor unit, and a second holding capacitor unit that holds the pixel signal transferred through the second transistor. A driving unit that drives the liquid crystal by applying a voltage of a pixel signal held in a capacitor to the pixel electrode;
The first storage capacitor portion is formed in a first capacitor formation layer and a second capacitor formation layer above the semiconductor substrate on which the first transistor and the second transistor are formed, with a dielectric sandwiched between electrodes. In the liquid crystal display device, the second storage capacitor portion is formed in the second capacitor formation layer with a dielectric sandwiched between electrodes. 2. The liquid crystal display device according to claim 1, wherein one electrode of the first storage capacitor unit and one electrode of the second storage capacitor unit are formed in common by the same wiring layer. The capacitance value of the first storage capacitor unit and the capacitance value of the second storage capacitor unit are set by an area ratio between one electrode of the first storage capacitor unit and one electrode of the second storage capacitor unit. The liquid crystal display device according to claim 1, wherein the liquid crystal display device is a liquid crystal display device. The first storage capacitor portion formed in the first capacitor formation layer is located at a position substantially translated upward in a formation region of the semiconductor substrate on which the first transistor and the second transistor are formed, and The first storage capacitor unit and the second storage capacitor unit formed in the second capacitor formation layer and formed in an area substantially equal to the area of the formation region in which the first transistor and the second transistor are formed. Is a position that is substantially translated upward in the formation region of the semiconductor substrate on which the first transistor and the second transistor are formed, and the area of the formation region on which the first transistor and the second transistor are formed. The liquid crystal display device according to claim 1, wherein the liquid crystal display device is formed within a substantially equivalent area.

Images