CN114518674B - Array substrate, control method thereof and display device - Google Patents
Array substrate, control method thereof and display device Download PDFInfo
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- CN114518674B CN114518674B CN202210288778.1A CN202210288778A CN114518674B CN 114518674 B CN114518674 B CN 114518674B CN 202210288778 A CN202210288778 A CN 202210288778A CN 114518674 B CN114518674 B CN 114518674B
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- 239000000758 substrate Substances 0.000 title claims abstract description 38
- 238000000034 method Methods 0.000 title claims abstract description 16
- 230000004044 response Effects 0.000 claims description 6
- 239000004973 liquid crystal related substance Substances 0.000 abstract description 14
- 230000005684 electric field Effects 0.000 abstract description 9
- 230000008859 change Effects 0.000 description 5
- 230000009471 action Effects 0.000 description 4
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000001795 light effect Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 238000002834 transmittance Methods 0.000 description 2
- 230000002146 bilateral effect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000012466 permeate Substances 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0421—Structural details of the set of electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0233—Improving the luminance or brightness uniformity across the screen
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- Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Physics (AREA)
- Optics & Photonics (AREA)
- Liquid Crystal Display Device Control (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The application provides an array substrate, a control method thereof and a display device, wherein the array substrate comprises: a plurality of gate lines and data lines intersecting to define a pixel unit including: the pixel electrode comprises a first sub-pixel electrode and a second sub-pixel electrode which are mutually and electrically insulated, and the polarities of voltages applied to the first sub-pixel electrode and the second sub-pixel electrode are opposite, so that the directions of an electric field formed by the first sub-pixel electrode and the common electrode and an electric field formed by the second sub-pixel electrode and the common electrode are opposite, and the positive polarity and the negative polarity of liquid crystal in each frame of picture are mixed, so that each frame of picture has no brightness difference, and the flicker problem caused by the brightness difference when each frame of picture is alternated can be weakened or even eliminated.
Description
Technical Field
The disclosure relates to the technical field of display, and in particular relates to an array substrate, a control method thereof and a display device.
Background
Under the action of an electric field, the liquid crystal molecules of the liquid crystal display device can change in arrangement, so that the incident light beam can be influenced to permeate the liquid crystal to generate intensity change, and the light intensity change is further represented as brightness change through the action of the polaroid. Therefore, the brightness change of the light can be realized by controlling the liquid crystal electric field, thereby achieving the purpose of information display. However, the current liquid crystal display has a difference between positive and negative frame brightness, thereby causing a flicker problem of the display.
Disclosure of Invention
In view of the above, the present application provides an array substrate, a control method thereof, and a display device.
Based on the above object, the present application provides an array substrate comprising: a plurality of gate lines and data lines intersecting to define a pixel unit including: and a pixel electrode including a first subpixel electrode and a second subpixel electrode electrically insulated from each other, the first subpixel electrode and the second subpixel electrode being opposite in polarity to a voltage applied thereto.
In some embodiments, the first subpixel electrode and the second subpixel electrode are equal in area.
In some embodiments, the first subpixel electrode is disposed symmetrically with the second subpixel electrode.
In some embodiments, the plurality of data lines includes a first data line and a second data line; the pixel unit further includes: a first transistor and a second transistor;
The first electrode of the first transistor is connected with the first sub-pixel electrode, the second electrode of the first transistor is connected with the first data line, the first electrode of the second transistor is connected with the second sub-pixel electrode, the second electrode of the second transistor is connected with the second data line, the first data line is used for providing a first voltage signal for the first transistor, the second data line is used for providing a second voltage signal for the second transistor, and the polarities of the voltages of the first voltage signal and the second voltage signal are opposite.
In some embodiments, the plurality of gate lines includes: a first gate line and a second gate line; the pixel unit further includes: a first transistor and a second transistor;
The first electrode of the first transistor is connected with the first sub-pixel electrode, the second electrode of the first transistor is connected with the data line, the control electrode of the first transistor is connected with the first grid line, the first electrode of the second transistor is connected with the second sub-pixel electrode, the second electrode of the second transistor is connected with the data line, the control electrode of the second transistor is connected with the second grid line, the data line provides voltage signals for the first transistor and the second transistor, the first grid line is used for providing an opening signal for the first transistor when the polarity of the voltage signals is a first polarity, the second grid line is used for providing an opening signal for the second transistor when the polarity of the voltage signals is a second polarity, and the polarities of the first polarity and the second polarity are opposite.
In some embodiments, two adjacent pixel units share one data line.
In some embodiments, two adjacent pixel units share one gate line.
Based on the same inventive concept, the embodiment of the application also provides a display device, which comprises the array substrate.
Based on the same inventive concept, the embodiment of the application also provides a control method of an array substrate, wherein the array substrate comprises: a plurality of gate lines and data lines intersecting to define a pixel unit including: the pixel electrode comprises a first sub-pixel electrode and a second sub-pixel electrode which are insulated from each other;
The method comprises the following steps: the polarity of the voltage applied to the first sub-pixel electrode and the second sub-pixel electrode is controlled to be opposite.
In some embodiments, the plurality of data lines includes a first data line and a second data line; the pixel unit further includes: a first transistor and a second transistor; the first electrode of the first transistor is connected with the first sub-pixel electrode, the second electrode of the first transistor is connected with the first data line, the first electrode of the second transistor is connected with the second sub-pixel electrode, and the second electrode of the second transistor is connected with the second data line;
The controlling the voltage polarity of the first sub-pixel electrode and the second sub-pixel electrode to be opposite includes:
Controlling the first data line to provide a first voltage signal for the first transistor and controlling the second data line to provide a second voltage signal for the second transistor; wherein the polarities of the voltages of the first voltage signal and the second voltage signal are opposite.
In some embodiments, the plurality of gate lines includes: a first gate line and a second gate line; the pixel unit further includes: a first transistor and a second transistor; the first electrode of the first transistor is connected with the first sub-pixel electrode, the second electrode of the first transistor is connected with the data line, the control electrode of the first transistor is connected with the first grid line, the first electrode of the second transistor is connected with the second sub-pixel electrode, the second electrode of the second transistor is connected with the data line, the control electrode of the second transistor is connected with the second grid line, and the data line provides voltage signals for the first transistor and the second transistor;
The controlling the voltage polarity of the first sub-pixel electrode and the second sub-pixel electrode to be opposite includes:
controlling the first gate line to provide an on signal for the first transistor in response to determining that the polarity of the voltage signal is a first polarity;
controlling the second gate line to provide an on signal for the second transistor in response to determining that the polarity of the voltage signal is a second polarity; wherein the first polarity is opposite to the second polarity.
As can be seen from the above, the array substrate provided by the present application includes: a plurality of gate lines and data lines intersecting to define a pixel unit including: the pixel electrode comprises a first sub-pixel electrode and a second sub-pixel electrode which are mutually and electrically insulated, and the polarities of voltages applied to the first sub-pixel electrode and the second sub-pixel electrode are opposite, so that the electric field formed by the first sub-pixel electrode and the common electrode is opposite to the electric field formed by the second sub-pixel electrode and the common electrode, and the positive polarity and the negative polarity of liquid crystal in each frame of picture are mixed, so that each frame of picture has no brightness difference, and the flicker problem caused by the brightness difference when each frame of picture is alternated can be reduced or even eliminated.
Drawings
In order to more clearly illustrate the technical solutions of the present disclosure or related art, the drawings required for the embodiments or related art description will be briefly described below, and it is apparent that the drawings in the following description are only embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort to those of ordinary skill in the art.
Fig. 1 is a schematic structural cross-sectional view of an array substrate according to the related art;
FIG. 2 is a schematic cross-sectional view of a first array substrate according to an embodiment of the present application;
FIG. 3 is a schematic cross-sectional view illustrating a second embodiment of an array substrate according to the present application;
FIG. 4 is a schematic cross-sectional view illustrating a third embodiment of an array substrate according to the present application;
FIG. 5 is a schematic cross-sectional view of a fourth array substrate according to an embodiment of the present application;
FIG. 6 is a schematic structural cross-sectional view of a fifth array substrate according to an embodiment of the present application;
FIG. 7 is a schematic cross-sectional view of a sixth embodiment of an array substrate;
FIG. 8 is a schematic cross-sectional view of a seventh array substrate according to an embodiment of the present application;
FIG. 9 is a schematic cross-sectional view of an eighth array substrate according to an embodiment of the present application;
Fig. 10 is a flowchart illustrating a control method of a pixel unit according to an embodiment of the application.
Detailed Description
For the purposes of promoting an understanding of the principles and advantages of the disclosure, reference will now be made to the embodiments illustrated in the drawings and specific language will be used to describe the same.
It should be noted that unless otherwise defined, technical or scientific terms used in the embodiments of the present disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which the present disclosure pertains. The terms "first," "second," and the like, as used in embodiments of the present disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", etc. are used merely to indicate relative positional relationships, which may also be changed when the absolute position of the object to be described is changed.
As described in the background art, the inventor of the present application found that the difference of brightness of positive and negative frames exists in the current liquid crystal display, and that the difference of brightness of positive and negative frames is caused by the deflection difference of the liquid crystal under the voltage driving of different directions of positive and negative frames due to the flexoelectric effect of the liquid crystal under the action of an electric field, and the difference of transmittance of positive and negative polarities is increased due to the difference of rotation components of the liquid crystal above and between the electrodes. At this time, the brightness difference of the positive and negative frames is reduced by changing the voltage values of the positive and negative frames, so that the partial transmittance is sacrificed. Therefore, the present application provides a new array substrate, which mixes the positive polarity light effect and the negative polarity light effect of the liquid crystal so that each frame of picture has no brightness difference. So that the flicker problem caused by the brightness difference when each frame of picture is alternated can be reduced or even eliminated.
Referring to fig. 1, a schematic cross-sectional view of an array substrate according to the related art is shown, wherein G1 represents a gate line, D1, D2, D3 represent data lines, T represents a transistor, S represents a pixel electrode, and R represents a pixel unit. In fig. 1, each pixel unit R includes a pixel electrode S, the voltage applied to each pixel electrode S is controlled by a voltage signal sent from a data line to a transistor T, and in normal circumstances, when the pixel unit is in operation, the voltage signal of its corresponding data line is sent alternately from positive to negative, which results in that if the pixel unit is applied with a positive voltage in a first frame, the pixel unit is applied with a negative voltage in a second frame, and due to the flexoelectric effect, the liquid crystal is deflected under the driving of voltages in different directions of the positive and negative frames, so that the brightness of the pixel unit is different between the first frame and the second frame, and a flicker problem occurs.
In order to solve the above-mentioned problems, an embodiment of the present application provides an array substrate, referring to fig. 2, the array substrate includes: a plurality of gate lines and data lines intersecting to define a pixel unit including:
The pixel electrode comprises a first sub-pixel electrode S1 and a second sub-pixel electrode S2 which are mutually electrically insulated, and the polarities of voltages applied to the first sub-pixel electrode S1 and the second sub-pixel electrode S2 are opposite, so that the pixel unit is driven to rotate by voltages in positive and negative directions in each frame, the pixel unit is further ensured to maintain the same brightness in the positive and negative frames, and the flicker problem caused by brightness difference is avoided.
In this embodiment, the pixel unit generally refers to a single sub-pixel unit, and optionally, the pixel unit may be any sub-pixel unit of red, green and blue, or may be a pixel unit of another color, which is not limited herein.
In some embodiments, the first subpixel electrode and the second subpixel electrode may be disposed in the same layer in the pixel unit, i.e., in a direction perpendicular to the common electrode, and the two subpixel electrodes are equidistant from the common electrode. Alternatively, the first subpixel electrode and the second subpixel electrode may be disposed on different layers of the pixel unit. Optionally, when the first subpixel electrode and the second subpixel electrode are disposed in the same layer in the pixel unit, the polarities of the voltages applied to the first subpixel electrode and the second subpixel electrode are opposite, and the values are equal.
In some embodiments, the first subpixel electrode and the second subpixel electrode are equal in area.
In this embodiment, in order to ensure that the pixel units can maintain the same brightness as much as possible during the positive and negative frames, the areas of the first subpixel electrode and the second subpixel electrode should be as equal as possible. It should be noted that, in the present application, the areas of the first subpixel electrode and the second subpixel electrode are equal, which may be completely equal, or equal in a certain process error, and all fall within the protection scope of the present application.
In some embodiments, the first subpixel electrode is disposed symmetrically with the second subpixel electrode.
In this embodiment, the first subpixel electrode and the second subpixel electrode may be symmetrically disposed, and the specific symmetrical manner may be disposed according to needs, which is not limited herein, and referring to fig. 2, the first subpixel electrode and the second subpixel electrode may be disposed vertically symmetrically. Referring to fig. 3, the first subpixel electrode and the second subpixel electrode may be disposed in bilateral symmetry.
In some embodiments, referring to fig. 2, the plurality of data lines includes a first data line D1 and a second data line D2; the pixel unit further includes: a first transistor T1 and a second transistor T2;
The first electrode of the first transistor T1 is connected to the first subpixel electrode S1, the second electrode of the first transistor T1 is connected to the first data line D1, the first electrode of the second transistor T2 is connected to the second subpixel electrode S2, the second electrode of the second transistor T2 is connected to the second data line D2, the first data line D1 is configured to provide a first voltage signal to the first transistor T1, the second data line D2 is configured to provide a second voltage signal to the second transistor T2, and polarities of voltages of the first voltage signal and the second voltage signal are opposite.
In this embodiment, the first transistor T1 and the second transistor T2 may be Thin Film Transistors (TFTs), or may be other transistors, which are not limited herein. The first data line D1 and the second data line D2 respectively supply voltages with different polarities to the first transistor T1 and the second transistor T2, so that the voltages applied to the first subpixel electrode S1 and the second subpixel electrode S2 are different, and optionally, when the first subpixel electrode and the second subpixel electrode are disposed on the same layer in the pixel unit, the values of the voltages applied to the first subpixel electrode and the second subpixel electrode are equal.
When the two sub-pixel electrodes are controlled by the first data line and the second data line, the first sub-pixel electrode and the second sub-pixel electrode may share one gate line, for example, in fig. 4, the first sub-pixel electrode S1 and the second sub-pixel electrode S2 are connected to the first gate line G1 through respective transistors. Alternatively, the first subpixel electrode and the second subpixel electrode may be connected to one gate line, for example, 2 or fig. 3, and the first subpixel electrode S1 is connected to the first gate line G1 through the first transistor T1, and the second subpixel electrode S2 is connected to the second gate line G2 through the second transistor T2.
In some embodiments, referring to fig. 5, the plurality of gate lines includes: a first gate line G1 and a second gate line G2; the pixel unit further includes: a first transistor T1 and a second transistor T2;
the first electrode of the first transistor T1 is connected to the first sub-pixel electrode S1, the second electrode of the first transistor T1 is connected to the data line D1, the control electrode of the first transistor T1 is connected to the first gate line G1, the first electrode of the second transistor T2 is connected to the second sub-pixel electrode S2, the second electrode of the second transistor T2 is connected to the data line D1, the control electrode of the second transistor T2 is connected to the second gate line G2, the data line D1 provides a voltage signal for the first transistor T1 and the second transistor T2, the first gate line G1 is configured to provide an on signal for the first transistor T1 when the polarity of the voltage signal is a first polarity, and the second gate line G2 is configured to provide an on signal for the second transistor T2 when the polarity of the voltage signal is a second polarity, the polarity of the voltage signal is opposite to the first polarity.
In this embodiment, the polarities of the voltages applied to the first sub-pixel electrode and the second sub-pixel electrode are opposite by one data line and two gate lines, and since the voltage signal of the data line is sent alternately by positive and negative electrodes, when the polarity of the voltage signal is the first polarity, the first gate line is used for providing the turn-on signal for the first transistor, and at this time, the second transistor connected to the second sub-electrode does not receive the turn-on signal, so that the second sub-electrode is not applied with the voltage of the first polarity; when the polarity of the voltage signal is the second polarity, the second gate line is configured to provide an on signal for the second transistor, and at this time, the first transistor connected to the first sub-electrode does not receive the on signal, so that the first sub-electrode is not applied with the voltage of the second polarity, so that it can be ensured that the polarities of the voltages applied to the first sub-electrode and the second sub-electrode are different, alternatively, the first polarity may be a positive polarity or a negative polarity, and the second polarity is opposite to the first polarity.
In some embodiments, two adjacent pixel units share one gate line.
In this embodiment, two adjacent pixel units share one gate line, so that one gate line is saved, and the distance between two adjacent pixels is reduced. Referring to fig. 6, wherein D1, D2, D3, D4 are four data lines, and G1, G2, G3 are three gate lines. It can be seen that two adjacent pixel cells in fig. 6 share one gate line.
In some embodiments, two adjacent pixel units share one data line.
In this embodiment, two adjacent pixel units share one data line, so that one data line is saved, and the distance between two adjacent pixels is reduced. Referring to fig. 7, D1, D2, D3 are three data lines, and G1, G2, G3, G4 are four gate lines. It can be seen that two adjacent pixel cells in fig. 7 share one data line.
In some embodiments, two adjacent pixel units share one data line, and two adjacent pixel units share one gate line.
In this embodiment, two adjacent pixel units share one data line, and two adjacent pixel units share one gate line. Referring to fig. 8, D1, D2, D3 are three data lines, and G1, G2, G3 are three gate lines. Fig. 8 uses one less gate line in the case where the number of pixel cells is the same as fig. 7, and fig. 8 uses one less data line in the case where the number of pixel cells is the same as fig. 6.
In some embodiments, referring to fig. 9, the pixel electrode has a pseudo-dual domain structure, that is, the first sub-pixel electrode S1 and the second sub-pixel electrode S2 have a "V" structure, the data line of the array substrate is bent, and the shape of the bent data line is matched with that of the pixel electrode; the pixel electrode is a comb-shaped electrode, that is, each sub-pixel electrode comprises a plurality of branch electrodes as shown in fig. 9, and gaps exist between the branch electrodes.
The array substrate provided by the application comprises: a plurality of gate lines and data lines intersecting to define a pixel unit including: the pixel electrode comprises a first sub-pixel electrode and a second sub-pixel electrode which are mutually and electrically insulated, and the polarities of voltages applied to the first sub-pixel electrode and the second sub-pixel electrode are opposite, so that the electric field formed by the first sub-pixel electrode and the common electrode is opposite to the electric field formed by the second sub-pixel electrode and the common electrode, and the positive polarity and the negative polarity of liquid crystal in each frame of picture are mixed, so that each frame of picture has no brightness difference, and the flicker problem caused by the brightness difference when each frame of picture is alternated can be reduced or even eliminated.
The application also provides a display device comprising the array substrate of any embodiment. The display device can be a mobile phone, a television, a tablet personal computer, a display and other devices with display functions.
Based on the same inventive concept, the application also provides a control method of the pixel unit, corresponding to the pixel unit of any embodiment, wherein the pixel unit comprises: the pixel electrode comprises a first sub-pixel electrode and a second sub-pixel electrode which are insulated from each other;
referring to fig. 10, the control method includes:
s101, controlling the polarity of the voltage applied to the first sub-pixel electrode and the second sub-pixel electrode to be opposite.
In some embodiments, the pixel cell further comprises:
a first data line, a second data line, a first transistor, and a second transistor; the first electrode of the first transistor is connected with the first sub-pixel electrode, the second electrode of the first transistor is connected with the first data line, the first electrode of the second transistor is connected with the second sub-pixel electrode, and the second electrode of the second transistor is connected with the second data line;
The controlling the voltage polarity of the first sub-pixel electrode and the second sub-pixel electrode to be opposite includes:
Controlling the first data line to provide a first voltage signal for the first transistor and controlling the second data line to provide a second voltage signal for the second transistor; wherein the polarities of the voltages of the first voltage signal and the second voltage signal are opposite.
In some embodiments, the pixel cell further comprises:
A data line, a first gate line, a second gate line, a first transistor, and a second transistor;
the first electrode of the first transistor is connected with the first sub-pixel electrode, the second electrode of the first transistor is connected with the data line, the control electrode of the first transistor is connected with the first grid line, the first electrode of the second transistor is connected with the second sub-pixel electrode, the second electrode of the second transistor is connected with the data line, the control electrode of the second transistor is connected with the second grid line, and the data line provides voltage signals for the first transistor and the second transistor;
The controlling the voltage polarity of the first sub-pixel electrode and the second sub-pixel electrode to be opposite includes:
controlling the first gate line to provide an on signal for the first transistor in response to determining that the polarity of the voltage signal is a first polarity;
controlling the second gate line to provide an on signal for the second transistor in response to determining that the polarity of the voltage signal is a second polarity; wherein the first polarity is opposite to the second polarity.
It should be noted that the foregoing describes some embodiments of the present application. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims may be performed in a different order than in the embodiments described above and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.
Those of ordinary skill in the art will appreciate that: the discussion of any of the embodiments above is merely exemplary and is not intended to suggest that the scope of the application (including the claims) is limited to these examples; the technical features of the above embodiments or in the different embodiments may also be combined within the idea of the application, the steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the application as described above, which are not provided in detail for the sake of brevity.
Additionally, well-known power/ground connections to Integrated Circuit (IC) chips and other components may or may not be shown within the provided figures, in order to simplify the illustration and discussion, and so as not to obscure the embodiments of the present application. Furthermore, the devices may be shown in block diagram form in order to avoid obscuring the embodiments of the present application, and also in view of the fact that specifics with respect to implementation of such block diagram devices are highly dependent upon the platform within which the embodiments of the present application are to be implemented (i.e., such specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the application, it should be apparent to one skilled in the art that embodiments of the application can be practiced without, or with variation of, these specific details. Accordingly, the description is to be regarded as illustrative in nature and not as restrictive.
While the application has been described in conjunction with specific embodiments thereof, many alternatives, modifications, and variations of those embodiments will be apparent to those skilled in the art in light of the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may use the embodiments discussed.
The present embodiments are intended to embrace all such alternatives, modifications and variances which fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, and the like, which are within the spirit and principles of the embodiments of the application, are intended to be included within the scope of the application.
Claims (10)
1. An array substrate, characterized by comprising: a plurality of gate lines and data lines intersecting each other to define a pixel unit including a pixel electrode including first and second sub-pixel electrodes electrically insulated from each other, the first and second sub-pixel electrodes being opposite in polarity to a voltage applied thereto; wherein two adjacent pixel units share one gate line; the first sub-pixel electrode and the second sub-pixel electrode are of V-shaped structures, the data line of the array substrate is bent, and the bent shape is matched with the pixel electrode.
2. The array substrate of claim 1, wherein the first subpixel electrode and the second subpixel electrode have an equal area.
3. The array substrate of claim 1, wherein the first subpixel electrode and the second subpixel electrode are symmetrically disposed.
4. The array substrate of claim 1, wherein the plurality of data lines includes a first data line and a second data line; the pixel unit further includes: a first transistor and a second transistor;
The first electrode of the first transistor is connected with the first sub-pixel electrode, the second electrode of the first transistor is connected with the first data line, the first electrode of the second transistor is connected with the second sub-pixel electrode, the second electrode of the second transistor is connected with the second data line, the first data line is used for providing a first voltage signal for the first transistor, the second data line is used for providing a second voltage signal for the second transistor, and the polarities of the voltages of the first voltage signal and the second voltage signal are opposite.
5. The array substrate of claim 1, wherein the plurality of gate lines comprises: a first gate line and a second gate line; the pixel unit further includes: a first transistor and a second transistor;
The first electrode of the first transistor is connected with the first sub-pixel electrode, the second electrode of the first transistor is connected with the data line, the control electrode of the first transistor is connected with the first grid line, the first electrode of the second transistor is connected with the second sub-pixel electrode, the second electrode of the second transistor is connected with the data line, the control electrode of the second transistor is connected with the second grid line, the data line provides voltage signals for the first transistor and the second transistor, the first grid line is used for providing an opening signal for the first transistor when the polarity of the voltage signals is a first polarity, the second grid line is used for providing an opening signal for the second transistor when the polarity of the voltage signals is a second polarity, and the polarities of the first polarity and the second polarity are opposite.
6. The array substrate of claim 1, wherein two adjacent pixel units share one data line.
7. A display device comprising the array substrate according to any one of claims 1 to 6.
8. The control method of the array substrate is characterized in that the array substrate comprises the following steps: a plurality of gate lines and data lines intersecting to define a pixel unit including: the pixel electrode comprises a first sub-pixel electrode and a second sub-pixel electrode which are insulated from each other; wherein two adjacent pixel units share one gate line; the first sub-pixel electrode and the second sub-pixel electrode are of V-shaped structures, the data line of the array substrate is bent, and the bent shape is matched with the pixel electrode;
The method comprises the following steps: the polarity of the voltage applied to the first sub-pixel electrode and the second sub-pixel electrode is controlled to be opposite.
9. The method of claim 8, wherein the plurality of data lines comprises a first data line and a second data line; the pixel unit further includes: a first transistor and a second transistor; the first electrode of the first transistor is connected with the first sub-pixel electrode, the second electrode of the first transistor is connected with the first data line, the first electrode of the second transistor is connected with the second sub-pixel electrode, and the second electrode of the second transistor is connected with the second data line;
The controlling the voltage polarity of the first sub-pixel electrode and the second sub-pixel electrode to be opposite includes:
Controlling the first data line to provide a first voltage signal for the first transistor and controlling the second data line to provide a second voltage signal for the second transistor; wherein the polarities of the voltages of the first voltage signal and the second voltage signal are opposite.
10. The method of claim 8, wherein the plurality of gate lines comprises: a first gate line and a second gate line; the pixel unit further includes: a first transistor and a second transistor; the first electrode of the first transistor is connected with the first sub-pixel electrode, the second electrode of the first transistor is connected with the data line, the control electrode of the first transistor is connected with the first grid line, the first electrode of the second transistor is connected with the second sub-pixel electrode, the second electrode of the second transistor is connected with the data line, the control electrode of the second transistor is connected with the second grid line, and the data line provides voltage signals for the first transistor and the second transistor;
The controlling the voltage polarity of the first sub-pixel electrode and the second sub-pixel electrode to be opposite includes:
controlling the first gate line to provide an on signal for the first transistor in response to determining that the polarity of the voltage signal is a first polarity;
controlling the second gate line to provide an on signal for the second transistor in response to determining that the polarity of the voltage signal is a second polarity; wherein the first polarity is opposite to the second polarity.
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