JP2015056465A - Multilayer substrate, printed circuit board, semiconductor package substrate, semiconductor package, semiconductor chip, semiconductor device, information processing device, and communication device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multilayer substrate capable of suppressing rising of a cost by making a conductor loss for a differential component smaller than a conductor loss for a common component, so that the differential loss is reduced to attenuate common noise.SOLUTION: A multilayer substrate includes a plurality of signal wirings for transferring a differential signal. The plurality of signal wirings include a wiring layer for constituting a pair wiring, a GND layer which faces the wiring layer and contains a GND plane of entire surface or partial one, and a dielectric layer provided between the wiring layer and the GND layer. A wiring width between the plurality of signal wirings is narrower than a wiring width in a case where a characteristic impedance for a single signal wiring is a half of the differential impedance of the pair wiring, and a resistance increase generated by a skin effect on a surface of the plurality of signal wirings is smaller than a resistance increase generated by skin effect on a surface of the GND layer.

Description

  The present invention relates to a multilayer substrate, a printed circuit board and a semiconductor package substrate using the multilayer substrate, a semiconductor package using the semiconductor package substrate, a semiconductor chip having a rewiring layer, a semiconductor device in which the semiconductor chip is sealed in a package, and a print The present invention relates to an information processing apparatus and a communication apparatus using at least one of a circuit board, a semiconductor chip, and a semiconductor device.

  In a multi-layer substrate constituting a resin printed circuit board, a package substrate, or the like, or a semiconductor chip rewiring layer, a GND (ground) layer or a GND plane in the layer is used as a reference potential, and a signal wiring (hereinafter, referred to as a signal wiring) The transmission line structure is simply provided with “wiring”.

  Here, when a high-speed signal or high noise resistance is required, a differential signal having a normal phase and a reverse phase is used, and the wiring is also two pair wirings. At this time, the driver outputs a differential signal, and the receiver identifies the logic signal based on whether the differential amplitude (positive phase-negative phase) is positive or negative.

  A differential signal is often used when transmitting a high-speed signal exceeding 1 Gbps, or when transmitting a long distance by a cable or the like. Therefore, it is necessary that the loss of frequency dependence in the transmission line is small in a frequency range from a low frequency to a signal frequency or several times thereof. In particular, when the frequency exceeds 1 GHz, a difference in amplitude due to the data pattern occurs due to frequency dependency, and problems such as a decrease in amplitude of the receiving waveform and an increase in jitter are likely to occur.

  The frequency-dependent loss includes a dielectric loss due to a dielectric surrounding the signal conductor of the transmission line and a conductor loss due to the skin effect of the conductor. Therefore, in order to reduce these losses, improvements have been made to materials and manufacturing methods for substrates and cables.

  That is, in order to reduce the dielectric loss of a substrate or a cable, a material having a small dielectric loss tangent (tan δ), which is a physical property value of the dielectric material, has been used.

  Also, in order to reduce the conductor loss of the substrate, a substrate manufacturing method that smoothes the surface by suppressing the height of the irregularities (anchors) on the conductor surface provided for the purpose of enhancing the adhesion with the dielectric material is adopted. As a result, the increase in resistance due to the skin effect in which high-frequency currents concentrate near the conductor surface can be suppressed to the same level as the theoretical value when the conductor surface is smooth.

  However, low loss for high-speed differential signals is not always an advantage. Hereinafter, this point will be described. First, a differential signal is a signal transmission method that inherently has low common noise and thus hardly emits radiation noise. Further, even if there is common noise in the GND plane that is the reference potential, the differential amplitude is not affected by the common amplitude, so that the differential signal is a signal transmission system that is highly resistant to common noise.

  Here, due to the asymmetry in the transmission circuit design of the printed circuit board and package board, or the semiconductor input / output buffer design, common noise is generated due to mode conversion in which a part of the differential amplitude changes to the common amplitude, and thus radiation. Noise may be generated. For the same reason, part of the common noise generated in the GND plane, which is the reference potential, may be converted into the differential amplitude of the differential signal and disturb the differential waveform at the receiver.

  Therefore, in order to make full use of the merit of using differential signal transmission, it is important to maintain symmetry throughout the entire signal transmission path such as a semiconductor, a package, a printed circuit board, a connector, and wiring within a semiconductor chip.

  However, in reality, it is difficult to realize a transmission line in which mode conversion does not occur at all. In addition, circuits are not necessarily composed of only differential signals, but some circuits are composed of single-ended signals, and common noise generated in these circuits is completely blocked from high-speed differential signals. It is difficult. Similarly, it is difficult to completely block common noise generated due to noise from the space.

  Therefore, in Serial-ATA, which is one of various standards for handling high-speed differential signals, there is a restriction value for mode conversion for each frequency on a transmission / reception LSI or a card board on which an LSI is mounted. Allows mode conversion.

  Here, as one solution to such a problem, in a high-speed differential signal transmission line, a transmission line that has a low loss for the differential component but a high loss for the common component is realized. It is possible.

  Therefore, in order to realize such a transmission path, a wiring layer including a signal wiring for transmitting a differential signal, a GND layer including a whole or partial GND plane, and a wiring layer and a GND layer are provided. A dielectric layer having a first dielectric layer on the side of the wiring layer and a second dielectric layer on the side of the GND layer, each having a dielectric tangent different from each other. A multilayer substrate has been proposed in which the tangent is smaller than the dielectric tangent of the second dielectric layer.

  According to this multilayer substrate, as for the differential component, a part of the electric lines of force pass only through the first dielectric layer having a small dielectric loss tangent, so the dielectric loss is low, and the common component is Since all electric lines of force always pass through the second dielectric layer, the dielectric loss is high.

  Regarding conductor loss, a linear first conductor disposed on the upper surface of the dielectric, and a planar second conductor formed so as to face the first conductor and cover the lower surface of the dielectric widely. A microstrip having a striped irregularity along the longitudinal direction of the first conductor on the lower surface or the upper surface of the first conductor or the surface of the second conductor facing the first conductor A track has been proposed (see, for example, Patent Document 1).

  In addition, a ground layer or a power supply layer formed on one surface of the insulating layer and a signal line formed on the other surface of the insulating layer, the ground layer or the power supply layer is a surface where the anchor layer of the signal line is not formed A microstrip line structure is proposed that is disposed so as to face each other (see, for example, Patent Document 2).

  Moreover, it has the high frequency transmission part which transmits a high frequency signal by the wiring conductor layer arrange | positioned facing each other across the insulating layer, and the surface of the wiring conductor layer facing each other in the high frequency transmission part has a skin effect on the high frequency signal There has been proposed a multilayer wiring board in which the surface resistance including the influence of the surface irregularities facing each other with respect to the surface resistance is 1.5 times or less (see, for example, Patent Document 3).

Japanese Patent Laid-Open No. 9-232820 JP 2004-87928 A JP 2006-66563 A

However, the prior art has the following problems.
The means described in Patent Documents 1 to 3 reduce the unevenness on the surface of the conductor of the substrate or reduce the unevenness in the current direction, and the conductor loss is equally equal for both the differential component and the common component. Low loss.

  For this reason, the common component generated by the mode conversion from the differential signal is not attenuated, and the radiation noise caused by the converted common component is not suppressed. In addition, when common noise generated in a circuit composed of single-ended signals or common noise generated by receiving noise from the space is transmitted to the differential signal transmission path, the common noise is not attenuated and the mode The differential noise generated when the conversion point is reached is not suppressed. Furthermore, manufacturing a substrate using a layer with little or no unevenness on the conductor surface causes an increase in the cost of the substrate material and substrate manufacturing.

  The present invention has been made to solve the above-described problems. The conductor loss for the differential component is made smaller than the conductor loss for the common component, and the differential loss is reduced to attenuate the common noise. Another object of the present invention is to obtain a multilayer substrate that can suppress an increase in cost.

  The multilayer substrate according to the present invention includes a plurality of signal wirings for transmitting a differential signal, and the plurality of signal wirings include a wiring layer constituting a pair wiring, a wiring layer facing the wiring layer, and a whole or partial GND plane. And a dielectric layer provided between the wiring layer and the GND layer. The wiring width between the plurality of signal wirings is such that the characteristic impedance of one signal wiring is the differential impedance of the pair wirings. Therefore, the increase in resistance caused by the skin effect on the surface of the plurality of signal wirings is smaller than the increase in resistance caused by the skin effect on the surface of the GND layer.

According to the multilayer substrate according to the present invention, the wiring width between the plurality of signal wirings is narrower than the wiring width when the characteristic impedance of one signal wiring is half of the differential impedance of the pair wiring. The increase in resistance caused by the skin effect on the surface of the signal wiring is smaller than the increase in resistance caused by the skin effect on the surface of the GND layer.
Therefore, the conductor loss for the differential component can be made smaller than the conductor loss for the common component, the differential loss can be reduced to attenuate the common noise, and the increase in cost can be suppressed.

(A), (b) is sectional drawing which shows the pair wiring of a general conventional multilayer substrate. (A), (b) is sectional drawing which shows the electric current distribution at the time of the differential in FIG. (A), (b) is sectional drawing which shows the electric current distribution at the time of the in-phase in FIG. (A), (b) is sectional drawing which shows the pair wiring of the multilayer board | substrate which concerns on Embodiment 1 of this invention. (A), (b) is sectional drawing which shows the electric current distribution at the time of the differential in FIG. (A), (b) is sectional drawing which shows the electric current distribution at the time of the in-phase in FIG. It is explanatory drawing which illustrates the board | substrate wiring in the multilayer substrate based on Embodiment 2 of this invention.

Hereinafter, preferred embodiments of a multilayer substrate according to the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts will be described with the same reference numerals.
This multilayer substrate includes, for example, a printed circuit board and a semiconductor package board that transmit a high-frequency signal, a semiconductor package using the semiconductor package board, a semiconductor chip and a semiconductor device having a redistribution layer, and a printed circuit board, a semiconductor chip, and a semiconductor device. It is used for an information processing apparatus and a communication apparatus using at least one.

Note that the following terms will be used in the future for the names related to the irregularities on the conductor surface of the substrate.
Anchor: Surface protrusion shape Surface roughness: Anchor length (average value)
Profile: Almost synonymous with surface roughness Profile-free: Surface is almost flat Low profile: Surface roughness is small

Embodiment 1 FIG.
FIG. 1 is a cross-sectional view showing a pair wiring often used for a high-speed signal in a general conventional multilayer substrate. FIG. 1A shows a stripline structure, and FIG. 1B shows a microstrip structure.

  In FIG. 1, this multilayer substrate is composed of a dielectric material 1 of the substrate, a wiring layer 20 and a GND layer 30 or a GND plane 31 (hereinafter referred to as “GND plane 31”) provided in the layer. Has been.

  The wiring layer 20 has wirings 21 and 22 (hereinafter also referred to as “normal phase signal wiring 21” and “reverse phase signal wiring 22”, respectively) that are respectively a positive phase signal wiring and a negative phase signal wiring for differential signals. ing. An anchor 25 is provided on the surface of the wirings 21 and 22, and an anchor 35 is provided on the surface of the GND plane 31.

  The anchors 25 and 35 are shown only on the surface facing the GND plane 31 for the wirings 21 and 22, and are shown only on the surface facing the wirings 21 and 22 for the GND plane 31. Further, unlike the above-mentioned Patent Document 1, the protrusions (anchors) on the conductor surface in the figure are not continuous with respect to the wiring direction (the depth direction on the paper).

  Here, the stripline structure means a structure in which layers having GND planes 31 are provided above and below the wiring layer 20 and the space between them is filled with the dielectric material 1 of the substrate. In addition, the microstrip structure includes a layer having the GND plane 31 only on either the upper or lower side of the wiring layer 20, and the space between the layers is filled with the dielectric material 1 of the substrate. On the opposite side, a structure without the GND plane 31 regardless of the presence or absence of the dielectric material 1 on the substrate is meant ((b) shows the case where the dielectric material 1 on the substrate is not on the wiring layer 20).

  In each structure, the pair wiring formed with the normal phase signal wiring 21 and the negative phase signal wiring 22 is referred to as a stripline pair wiring and a microstrip pair wiring. In a multilayer substrate having a microstrip structure, the upper surface of the wiring layer 20 on the surface or the upper portion of the dielectric material 1 on the substrate is often covered with a solder resist, but is omitted here. The above contents are common to other drawings.

  FIG. 2 is a cross-sectional view showing a current density distribution in a conductor when a differential alternating current flows through the pair wiring of FIG. FIG. 2A shows the case of the stripline structure, and FIG. 2B shows the case of the microstrip structure.

  In FIG. 2, Ip represents an alternating current (positive phase signal current) of a positive phase signal, In represents an alternating current (negative phase signal current) of a negative phase signal, and Igp represents a GND current opposed to the positive phase signal current Ip. Ign represents a GND current opposite to the negative phase signal current In. In FIG. 2, the symbol with a circle in the circle indicates the current flow from the front to the back of the paper, and the symbol with a circle in the circle indicates the current flow from the back of the paper to the front. Yes.

  These AC currents Ip, In, Igp, Ign are particularly in the case of AC currents exceeding GHz, and currents gather near the surface of the conductor due to the skin effect, and the GND currents Igp, Ign are in a range substantially equal to the conductor width. Concentrate on. Therefore, the thickness of the cross section through which the current flows is reduced by the skin effect, and the cross sectional area is reduced. As a result, the conductor resistance increases at high frequencies. Furthermore, if there are fine irregularities on the conductor surface, the resistance increases beyond the theoretical value of the skin effect.

  Further, the positive phase signal current Ip and the negative phase signal current In, the positive phase signal current Ip and its GND current Igp, and the negative phase signal current In and its GND current Ign are always opposite to each other. .

  Here, when the differential transmission line and the surrounding GND shape are symmetrical, the relationship of the following equation (1) is established.

    | Ip | = | In | (1)

  Further, when the coupling between the normal phase signal wiring 21 and the negative phase signal wiring 22 as shown in FIG. 2 is weak, the following expressions (2) and (3) are established.

| Ip | = | Igp | (2)
| In | = | Ign | (3)

  Further, from the equations (1) to (3), the relationship of the following equation (4) is established.

    | Igp | = | Ign | (4)

  As a result, the relationship of the following equation (5) is established from the equations (1) to (4). That is, all alternating currents are equal.

| Ip | = | In |
= | Igp |
= | Ign | (5)

  FIG. 3 is a cross-sectional view showing a current density distribution in the conductor when an in-phase (common) alternating current flows through the pair wiring of FIG. FIG. 3A shows the case of a stripline structure, and FIG. 3B shows the case of a microstrip structure.

  3 differs from FIG. 2 in that the direction of the negative phase signal current In is the same as the direction of the positive phase signal current Ip, and that the GND currents Igp and Ign that are opposite to the signal currents Ip and In are Are in the same direction. Also in this case, the relationship of the above formula (5) is established as in FIG.

  2 and 3, the four alternating currents Ip, In, Igp, and Ign are always equal to each other, whether they are differential alternating currents or in-phase alternating currents. Therefore, it can be seen that there is no difference in the current attenuation ratio between the differential and the in-phase even if means such as attenuating only the signal current or attenuating only the GND current is used.

  FIG. 4 is a cross-sectional view showing a pair wiring of the multilayer substrate according to the first embodiment of the present invention, and is for solving the above-described problem. 4A shows a stripline structure, and FIG. 4B shows a microstrip structure.

  In FIG. 4, the positive-phase signal wiring 21 and the negative-phase signal wiring 22 forming the pair wiring are close to each other, and even if they have the same differential impedance as compared with FIGS. The coupling between the wiring 21 and the reverse-phase signal wiring 22 is strong, and the coupling between the wirings 21 and 22 and the GND plane 31 at the time of differential is relatively weak.

  Specifically, the wiring width between the positive-phase signal wiring 21 and the negative-phase signal wiring 22 is narrower than the wiring width when the characteristic impedance of one signal wiring is half of the differential impedance of the pair wiring. In this structure, the resistance increase caused by the skin effect on the surfaces of the wirings 21 and 22 is smaller than the resistance increase caused by the skin effect on the surface of the GND plane 31.

  In addition, anchors 35 are provided on the surface of the GND plane 31 facing the wirings 21 and 22, but the surface of the wirings 21 and 22 has a structure with few or no anchors. . Therefore, the wirings 21 and 22 in FIG. 4 are thicker in thickness than the wirings 21 and 22 shown in FIGS.

  FIG. 5 is a cross-sectional view showing a current density distribution in the conductor when a differential alternating current flows through the pair wiring of FIG. 4, and FIG. 6 shows an in-phase (common) alternating current in the pair wiring of FIG. It is sectional drawing which shows the current density distribution in a conductor at the time of flowing. 5 (a) and 6 (a) show the case of a stripline structure, and FIGS. 5 (b) and 6 (b) show the case of a microstrip structure.

  Here, in FIG. 4, in the case of FIG. 5 in which the differential AC current flows through the pair wiring by the structure in which the coupling between the positive phase signal wiring 21 and the negative phase signal wiring 22 is strengthened, the above formula ( 1) and (4) are satisfied, but the above expressions (2) and (3) are not satisfied. Instead of the expressions (2) and (3), the following expressions (6) and (7) The relationship is established.

| Ip | >>>> Igp | (6)
| In | >>>> Ign | (7)

  On the other hand, in FIG. 4, in the case of FIG. 6 in which the common-mode alternating current flows through the pair wiring, the relationships of the above formulas (1) to (4) are established.

  Further, in FIG. 4, the surface of the normal phase signal wiring 21 and the reverse phase signal wiring 22 has a structure with little or no unevenness, and the wirings 21 and 22 have a depth at which an alternating current flows due to the skin effect. The GND plane 31 does not increase in resistance beyond the shallowness, but the GND plane 31 causes an increase in resistance beyond the shallowness of the flow of alternating current due to the skin effect due to surface irregularities.

  From the above phenomenon, the following differences occur in the high-frequency current and the resistance increase between when the differential alternating current flows through the pair wiring and when the in-phase alternating current flows. First, when the positive-phase signal current Ip and the negative-phase signal current In are equal to each other during differential and in-phase, the relationship of the following equation (8) is established.

    | Igp, Ign | at the time of differential | << | Igp, Ign | at the time of in-phase

  Therefore, there is a difference in the attenuation amount of the GND current between the differential time and the in-phase time. That is, although the rate of attenuation is the same, the GND currents Igp and Ign at the time of in-phase are larger than the GND currents Igp and Ign at the time of differential, so that the amount of attenuation is larger at the time of in-phase. Therefore, there is a difference between the differential current and the in-phase current with respect to the attenuation amount of the alternating current defined as the total of the signal currents Ip and In and the GND currents Igp and Ign.

  As described above, it is possible to obtain a signal wiring that has a higher loss in the same phase than in the differential mode. Further, by applying the above-described structure to a substrate having high-speed differential signal wiring, it is possible to realize a substrate in which the attenuation amount of the in-phase alternating current is larger than the attenuation amount of the differential alternating current. Furthermore, only the layer with high-speed differential signal wiring is made a layer with little unevenness (low profile) or a layer without unevenness (profile-free), thereby minimizing the increase in substrate cost. it can.

  Further, by using this substrate, the common-mode noise for the differential signal wiring can be attenuated by the substrate. In addition, even if noise that has entered from other parts of the board or noise that has propagated from space becomes in-phase noise for the differential signal wiring, this noise can be attenuated and the mode Differential noise caused by conversion can also be suppressed.

  On the other hand, even when the differential component of the mode conversion signal is converted to a common component (common noise), this common noise can be attenuated on the substrate, and the propagation of noise to other parts, And radiation noise can be suppressed.

  Further, by using such a substrate as a package substrate for a semiconductor IC, it is possible to realize a semiconductor device that hardly generates common noise and has high resistance to common noise.

  Further, by using such a substrate, high-frequency radiation noise can be suppressed, so that it is possible to prevent the noise from propagating through the space in the apparatus to another substrate and causing a malfunction. Moreover, in order to acquire such an effect, it is not necessary to use a noise suppression sheet etc., for example, Therefore Product cost and assembly cost can be suppressed.

  In addition, by applying such a substrate to a device that performs high-frequency wireless communication, the output power of the antenna can be reduced, and low power consumption can be realized. Furthermore, it is possible to prevent a decrease in reception sensitivity of the antenna.

As described above, according to the first embodiment, the wiring width between the plurality of signal wirings is larger than the wiring width when the characteristic impedance of one signal wiring is half of the differential impedance of the pair wiring. Narrow and the increase in resistance caused by the skin effect on the surface of the plurality of signal wirings is smaller than the increase in resistance caused by the skin effect on the surface of the GND layer.
Further, the unevenness of the surface of the pair wiring facing at least the GND plane is smaller than the unevenness of the surface of the GND plane facing the pair wiring at least.
Therefore, the loss of the positive phase signal current and the negative phase signal current of the differential signal is smaller than the loss of the GND current with respect to the positive phase signal current and the GND current with respect to the negative phase signal current.
Therefore, the stronger the positive-phase signal wiring and the negative-phase signal wiring of the differential signal are coupled, the smaller the GND current with respect to the positive phase and the negative phase is, so that the attenuation of the differential signal is suppressed.
On the other hand, in the case of common noise, amplitude fluctuations in the same phase occur in the positive-phase signal current and the negative-phase signal current, and the same GND current is generated. However, since the loss of the GND current increases, the common noise is attenuated. To do.
Moreover, since the conventional low-cost material and manufacturing method are applicable as a conductor layer with a large unevenness | corrugation of the surface (surface is rough), the raise of cost can be suppressed.
That is, the conductor loss with respect to the differential component can be made smaller than the conductor loss with respect to the common component, the differential loss can be reduced to attenuate the common noise, and the increase in cost can be suppressed.

  In the first embodiment, an example in which the difference in resistance increase at a high frequency with respect to the signal current and the GND current is realized by the degree of surface roughness or the presence or absence of surface roughness is shown, but the present invention is not limited to this. You may implement | achieve using the conductor material from which resistance value differs. Alternatively, the GND plane 31 may be provided with a large number of holes having a size and pitch smaller than the wiring width to substantially increase the resistance value of the GND plane. Moreover, you may implement | achieve by the combination of these means.

  Specifically, it can be considered that the DC resistance value of the conductor of the pair wiring is made smaller than the DC resistance value of the conductor of the GND plane 31. At this time, for example, the main material of the conductor of the pair wiring and the main material of the conductor of the GND plane 31 are any of gold, copper, aluminum, and tungsten, respectively, The resistivity may be made smaller than the resistivity of the conductor material of the GND plane 31.

  In addition, it is conceivable to provide a plurality of holes having a diameter and a distance smaller than the wiring width of the pair wiring in at least a range of the GND plane 31 facing the wirings 21 and 22.

Embodiment 2. FIG.
FIG. 7 is an explanatory view illustrating the substrate wiring in the multilayer substrate according to the second embodiment of the present invention. In FIG. 7, the substrate wiring includes a BGA (Ball Grid Array) package pad 60, a connector pin through hole 70 into which a connector pin (not shown) is inserted, a normal phase signal wiring 21 and a negative phase signal wiring 22. And a pair of pair wirings 81 including another normal phase signal wiring 21 and a reverse phase signal wiring 22. Each of the pair wirings 80 and 81 has a cross-sectional structure according to the first embodiment of the present invention shown in FIG.

  In the pair wiring 80, a signal is transmitted from another substrate to the BGA package pad 60 through the connector pin and the connector pin through hole 70. On the other hand, in the pair wiring 81, a signal is transmitted from the BGA package pad 60 to another substrate via the connector pin through hole 70 and the connector pin.

  Here, until the pair wirings 80 and 81 are formed from the BGA package pad 60 and the connector pin through hole 70, the pair wirings 80 and 81 are formed on the receiving side (upstream end in the signal transmission direction) in this board. ) Only isometric processing, not on the transmission side (downstream end in the signal transmission direction).

  In general, when the lengths of the normal phase signal and the reverse phase signal until the pair wirings 80 and 81 are formed are different, a mode conversion in which a part of the differential amplitude is changed to the common amplitude is generated. When common noise is induced and resonates on the substrate, large radiation noise is generated at the frequency of the common noise.

  For this reason, it is desirable to align the lengths of the wirings (leading lines) of the normal phase signal and the negative phase signal until the pair wirings 80 and 81 are formed. However, for this purpose, it is necessary to bother the individual lead lines and occupy an originally unnecessary wiring area. In addition, when there are a large number of differential signals, it may be difficult to draw out other signals. Furthermore, it takes time to design the substrate, leading to an increase in development cost.

  On the other hand, in the multilayer substrate shown in the first embodiment, common noise generated by mode conversion on the transmission side is attenuated during propagation, and resonance hardly occurs. This eliminates the need for equal length processing in the transmission line on the transmission side, eliminates the need for an extra wiring area, and further reduces the time required for board design.

  As described above, by using such a substrate as a package substrate for a semiconductor IC, it is possible to realize a semiconductor device that hardly generates common noise and has high resistance to common noise.

  Further, by using such a substrate, high-frequency radiation noise can be suppressed, so that it is possible to prevent the noise from propagating through the space in the apparatus to another substrate and causing a malfunction. Moreover, in order to acquire such an effect, it is not necessary to use a noise suppression sheet etc., for example, Therefore Product cost and assembly cost can be suppressed.

  In addition, by applying such a substrate to a device that performs high-frequency wireless communication, the output power of the antenna can be reduced, and low power consumption can be realized. Furthermore, it is possible to prevent a decrease in reception sensitivity of the antenna.

  If the receiving side package substrate or another substrate connected to the receiving side connector is also the cross-sectional structure shown in the first embodiment, it is not necessary to perform equal length processing on the receiving side lead line. Design time and development costs can be reduced. Further, this embodiment can obtain the same effect on the rewiring layer in the semiconductor chip.

  DESCRIPTION OF SYMBOLS 1 Dielectric material, 20 wiring layer, 21 normal phase signal wiring, 22 reverse phase signal wiring, 25 wiring surface anchor, 30 GND layer, 31 GND plane, 35 GND plane surface anchor, 60 BGA package pad, 70 connector Through hole for pins, 80, 81 pair wiring, Ip positive phase signal current, In reverse phase signal current, Igp GND current for positive phase signal current, and GND current for Ign negative phase signal current.

Claims (27)

A plurality of signal wirings for transmitting differential signals, wherein the plurality of signal wirings comprise a wiring layer constituting a pair wiring;
A GND layer facing the wiring layer and including the entire surface or a partial GND plane;
A dielectric layer provided between the wiring layer and the GND layer,
The wiring width between the plurality of signal wirings is narrower than the wiring width when the characteristic impedance of one signal wiring is half of the differential impedance of the pair wiring,
A multilayer substrate in which a resistance increase caused by a skin effect on a surface of the plurality of signal wirings is smaller than a resistance increase caused by a skin effect on the surface of the GND layer. The multilayer substrate according to claim 1, wherein the GND layer is disposed above and below the one or more wiring layers. The multilayer substrate according to claim 1, wherein the GND layer is arranged on one side with respect to one or more of the wiring layers. The multilayer substrate according to claim 3, wherein a protective film is formed on the surface of the substrate. The unevenness | corrugation of the surface which faces the said GND plane of the said pair wiring is at least smaller than the unevenness | corrugation of the surface which faces the said pair wiring of the said GND plane at least. Multilayer board. The multilayer substrate according to any one of claims 1 to 4, wherein a DC resistance value of the conductor of the pair wiring is smaller than a DC resistance value of the conductor of the GND plane. The main material of the conductor of the pair wiring and the main material of the conductor of the GND plane are each one of gold, copper, aluminum, and tungsten,
The multilayer substrate according to claim 6, wherein a resistivity of a material of a conductor of the pair wiring is smaller than a resistivity of a material of a conductor of the GND plane. 5. The plurality of holes having a diameter and a distance smaller than a wiring width between the plurality of signal wirings are provided at least in a range of the GND plane facing the signal wirings. 2. The multilayer substrate according to item 1.   A multilayer substrate comprising a combination of at least two of claims 5, 6, and 8.   A multilayer substrate obtained by combining at least two of claims 5, 7, and 8. The pair wirings have substantially the same lengths of the positive phase and the reverse phase from the pair wiring end on the signal reception side at both ends of the pair wiring, and the positive phase and the reverse phase from the pair wiring end on the signal transmission side. The multilayer substrate according to any one of claims 1 to 10, wherein the multilayer substrate has a wiring shape having a difference in wiring length. The pair wirings have substantially the same lengths of the positive phase and the reverse phase from the pair wiring end on the signal transmission side at both ends of the pair wiring, and the positive phase and the reverse phase from the pair wiring end on the signal reception side. The multilayer substrate according to any one of claims 1 to 10, wherein the multilayer substrate has a wiring shape having a difference in wiring length. The said pair wiring has wiring shape which has a difference in the wiring length of a normal phase and a reverse phase from the pair wiring end in each of the both ends of the said pair wiring. Multilayer board.   The printed circuit board which mounted components in the multilayer substrate in any one of Claim 1- Claim 13.   A semiconductor package substrate comprising the multilayer substrate according to any one of claims 1 to 13.   A semiconductor device using the semiconductor package substrate according to claim 15.   A semiconductor package using the semiconductor package substrate according to claim 15.   A semiconductor device in which a semiconductor chip is mounted on the semiconductor package according to claim 17.   A printed circuit board on which the semiconductor device according to claim 18 is mounted. A plurality of signal wirings for transmitting differential signals, wherein the plurality of signal wirings comprise a wiring layer constituting a pair wiring;
A GND layer facing the wiring layer and including the entire surface or a partial GND plane;
A dielectric layer provided between the wiring layer and the GND layer,
The wiring width between the plurality of signal wirings is narrower than the wiring width when the characteristic impedance of one signal wiring is half of the differential impedance of the pair wiring,
The increase in resistance caused by the skin effect on the surface of the plurality of signal wirings is smaller than the increase in resistance caused by the skin effect on the surface of the GND layer. The pair wirings have substantially the same lengths of the positive phase and the reverse phase from the pair wiring end on the signal reception side at both ends of the pair wiring, and the positive phase and the reverse phase from the pair wiring end on the signal transmission side. The semiconductor chip according to claim 20, having a wiring shape with a difference in wiring length. The pair wirings have substantially the same lengths of the positive phase and the reverse phase from the pair wiring end on the signal transmission side at both ends of the pair wiring, and the positive phase and the reverse phase from the pair wiring end on the signal reception side. The semiconductor chip according to claim 20, having a wiring shape with a difference in wiring length. The semiconductor chip according to claim 20, wherein the pair wiring has a wiring shape in which both ends of the pair wiring have a difference in wiring length between a normal phase and a reverse phase from the pair wiring end.   A semiconductor device in which the semiconductor chip according to any one of claims 21 to 23 is mounted on a package.   A printed circuit board on which the semiconductor device according to claim 24 is mounted.   An information processing apparatus using at least one of the printed circuit boards according to claim 14, claim 18 and claim 25.   A communication device using at least one of the printed circuit boards according to claim 14, claim 18 and claim 25.

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