JP2015041999A - Amplification circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an amplification circuit enabling high-speed response and high efficiency.SOLUTION: An amplification circuit includes: an amplification section into which an input signal is input; a signal generation section 35 that performs an AND process of a first pulse signal with a pulse width modulated on the basis of an envelope voltage of the input signal and a second pulse signal delayed from the first pulse signal to generate a first control signal, and performs an AND process of an inverted signal of the first pulse signal and an inverted signal of the second pulse signal to generate a second control signal; and a switching power supply 12 that has a first switch 22 operating on the basis of the first control signal and a second switch 23 operating on the basis of the second control signal, and supplies a power terminal of the amplification section with first power such that a voltage of the power terminal tracks the envelope voltage.

Description

  The present invention relates to an amplifier circuit, for example, an amplifier circuit that modulates the power supply of an amplifier based on an envelope of an input signal.

  In a high-output high-frequency amplifier circuit, there is an envelope tracking method as a method for improving efficiency. The envelope tracking method is a method of modulating the power supply voltage of the amplification stage based on the envelope of the input signal.

JP2013-9200A

  In the envelope tracking system amplifier circuit, high efficiency can be achieved by using a switching power supply for modulation of the power supply voltage. However, if a freewheeling diode is used for the switching power supply, a power loss corresponding to the forward voltage drop of the diode occurs. On the other hand, when a transistor is used instead of the free wheel diode, high-speed response becomes difficult.

  The present invention has been made in view of the above problems, and an object thereof is to enable high-speed response and high efficiency in an amplifier circuit.

  The present invention is an AND of an amplifying unit to which an input signal is input, a first pulse signal whose pulse width is modulated based on an envelope voltage of the input signal, and a second pulse signal delayed from the first pulse signal. A signal generation unit that generates a first control signal by performing processing, and generates a second control signal by performing AND processing on the inverted signal of the first pulse signal and the inverted signal of the second pulse signal; A first switch that operates based on the first control signal; and a second switch that operates based on the second control signal. The voltage of the power terminal is set to the envelope voltage at the power terminal of the amplifier. And a switching power supply that supplies the first power so as to follow the amplifier circuit.

  In the above configuration, the signal generation unit generates the first pulse signal based on a first envelope signal corresponding to an envelope voltage of the input signal, and based on the second envelope signal obtained by delaying the first envelope signal. It can be set as the structure which produces | generates a 2nd pulse signal.

  In the above configuration, a linear power source that outputs second power based on the second envelope signal, and a combining unit that supplies power obtained by combining the first power and the second power to a power supply terminal of the amplifying unit; It can be set as the structure which comprises.

  In the above configuration, the signal generation unit generates the first pulse signal based on a difference between the first envelope signal and the voltage of the output terminal of the switching power supply, and the second envelope signal and the output of the switching power supply. The second pulse signal can be generated based on the terminal voltage.

  In the above configuration, a delay circuit that delays the input signal, a first detection circuit that detects an envelope voltage of the input signal before being input to the delay circuit as the first envelope signal, and the delay circuit that is delayed by the delay circuit And a second detection circuit that detects the envelope voltage of the input signal as the second envelope signal.

  In the above configuration, a configuration is provided that includes a detection circuit that detects an envelope voltage of the input signal as the first envelope signal, and a delay circuit that generates a second envelope signal by delaying the first envelope signal. be able to.

  In the above configuration, the first switch is connected in series between a first power source and a second power source, and the second switch is connected to the first switch between the first power source and the second power source. It can be set as the structure connected in series.

  In the above configuration, the switching power supply may include a smoothing circuit that smoothes a voltage at a node between the first switch and the second switch and outputs the smoothed voltage to the power supply terminal of the amplifying unit.

  According to the present invention, high-speed response and high efficiency in an amplifier circuit can be achieved.

FIG. 1 is a block diagram of an amplifier circuit according to Comparative Example 1. FIG. 2 is a circuit diagram illustrating an example of the switching power supply in the first comparative example. FIG. 3 is a circuit diagram showing another example of the switching power supply in the first comparative example. FIG. 4 is a circuit diagram of a switching power supply showing an example of a dead time controller. FIG. 5 is a timing chart of the switching power supply of Comparative Example 1. FIG. 6 is a block diagram of an amplifier circuit according to the first embodiment. FIG. 7 is a circuit diagram illustrating the switching power supply and the signal generation unit in the amplifier circuit according to the first embodiment. FIG. 8 is a timing chart of the switching power supply and the signal generation unit according to the first embodiment. FIG. 9 is a block diagram of an amplifier circuit according to the second embodiment. FIG. 10 is a block diagram of an amplifier circuit according to the third embodiment.

  First, a comparative example will be described. FIG. 1 is a block diagram of an amplifier circuit according to Comparative Example 1. As shown in FIG. 1, the amplifier circuit 110 includes a high-power amplifier unit 10, a driver amplifier unit 11, a switching power source 12, a linear power source 14, an envelope detection circuit 16, a synthesis unit 18, and a delay circuit 20. A high frequency input signal is input from the input terminal. The envelope detection circuit 16 detects an envelope (envelope) voltage of the input signal and outputs an envelope signal. The linear power supply 14 and the switching power supply 12 generate a voltage that follows the envelope signal. The synthesizer 18 synthesizes the output power of the linear power supply 14 and the switching power supply 12 and supplies it to the power supply terminal of the high output amplifier 10.

  In the envelope tracking system amplifier circuit, it is possible to increase the efficiency by modulating the power supply voltage of the amplifier 10 using the envelope signal. The linear power supply 14 can modulate the output voltage at high speed in response to the modulation of the envelope signal. However, the linear power supply 14 is inefficient. Although the switching power supply 12 is highly efficient, it is difficult to follow the envelope signal at high speed. Therefore, when the envelope signal changes at high speed, power is supplied to the amplifier 10 mainly by the linear power supply 14. When the envelope signal changes to a low speed, the switching power supply 12 supplies power to the amplifier 10 mainly. As a result, a high-efficiency amplifier circuit that can respond to a high-speed envelope signal is obtained. For example, in a base station amplifier circuit for mobile phone communication, most of the envelope signal is low speed. Therefore, the amplifier circuit 110 becomes more efficient.

  FIG. 2 is a circuit diagram illustrating an example of the switching power supply in the first comparative example. As shown in FIG. 2, the switching power supply 12a is an asynchronous rectification step-down switching power supply. The switching power supply 12 a includes a field effect transistor (FET) 22, diodes D 1 and D 2, inductor L 1, capacitors C 1 and C 2, a gate driver 24, a level shifter 26, a PWM (Pulse Width Modulation) circuit 28, and a differential amplifier circuit 30. Yes.

  One end of the inductor L1 is connected to the output terminal Tout, and the other end is connected to the node N1. One end of the capacitor C1 is connected to the output terminal Tout, and the other end is connected to the ground. The source of the FET 22 is connected to the node N 1, the drain is connected to the power supply Vcc, and the gate is connected to the gate driver 24. The FET 22 is, for example, an n-type MOS (Metal Oxide Semiconductor) FET. The cathode of the diode D1 is connected to the node N1, and the anode is connected to the ground. The diode D1 suppresses a current from flowing from the power supply Vcc to the ground when the FET 22 is on, and connects the node N1 to the ground when the FET 22 is off. Thereby, the node N1 becomes almost the voltage of the power supply Vcc when the FET 22 is on, and becomes almost the ground voltage when the FET 22 is off. The inductor L1 and the capacitor C1 are a smoothing circuit that smoothes and outputs the voltage at the node N1.

  The negative power supply terminal of the gate driver 24 is connected to the node N1, and the positive power supply terminal is connected to the power supply Vcc through the diode D2 in the reverse direction. A capacitor C2 is connected between the positive power supply terminal and the node N1. The diode D2 and the capacitor C2 function as a bootstrap circuit that generates a voltage at the positive voltage terminal of the gate driver 24. When the FET 22 is a p-type FET, the bootstrap circuit may not be provided.

  The differential amplifier circuit 30 differentially amplifies the output voltage of the output terminal Tout and the envelope signal, and outputs an error signal. The PWM circuit 28 performs PWM processing on the error signal and converts it into a PWM signal. The PWM circuit 28 changes the duty ratio of the PWM signal according to the error signal. For example, when the error signal is high, the duty ratio is increased. The level shifter 26 converts the PWM signal into a voltage or amplitude suitable for driving the FET 22, and outputs the PWM signal to the gate of the FET 22.

  When the voltage at the output terminal Tout is lower than the envelope signal, the differential amplifier circuit 30 outputs a positive error signal. The PWM circuit 28 increases the duty ratio of the PWM circuit 28. Thereby, the time for which the FET 22 is turned on becomes longer. The time during which the node N1 is at the voltage of the power supply Vcc becomes longer. Therefore, the smoothed output voltage is increased. In this way, negative feedback can be performed on the output voltage and the envelope signal can be tracked.

  Like the switching power supply 12a, the asynchronous rectification method has one FET, is easy to control, and is low cost. However, when a forward current flows through the diode D1, the product of the forward voltage and the current is a power loss. Thus, the power loss is large and the efficiency is not high.

  FIG. 3 is a circuit diagram showing another example of the switching power supply in the first comparative example. As shown in FIG. 3, the switching power supply 12b is a synchronous rectification step-down switching power supply. An FET 23 is used instead of the diode D1. The FET 23 has a source connected to the ground and a drain connected to the node N1. The gate is connected to the gate driver 25. The dead time controller 27 adjusts the PWM signal and outputs the PWM signal to the gate drivers 24 and 25. Other configurations are the same as those in FIG.

  Since the FET 23 has the same function as the diode D1, it is turned off when the FET 22 is on and turned on when the FET 22 is off. When the switching timings of the FET 22 and the FET 23 are shifted and both the FETs 22 and 23 are turned on, a through current flows from the power supply Vcc to the ground. This results in large power consumption. Further, the FETs 22 and 23 may be burned out. Therefore, the dead time controller 27 intentionally delays the delay time when the FETs 22 and 23 are turned from off to on than the delay time when the FETs 22 and 23 are turned off. Thereby, it can suppress that FET22 and 23 turn ON simultaneously.

  FIG. 4 is a circuit diagram of a switching power supply showing an example of a dead time controller. As shown in FIG. 4, the dead time controller 27 includes delay circuits 38 and 39, AND circuits 32 and 36, and an inverter 34. The delay circuit 38 delays the PWM signal 51 and generates a delay signal 52. The AND circuit 32 AND-processes the PWM signal 51 and the delay signal 52 (delayed PWM signal) to generate a first AND signal 53. The inverter 34 inverts the PWM signal 51 and generates an inverted signal 54. The delay circuit 39 delays the inverted signal 54 and generates an inverted delay signal 55. The AND circuit 36 AND-processes the inverted signal 54 (inverted PWM signal) and the inverted delay signal 55 (inverted and delayed PWM signal) to generate a second AND signal 56. The first AND signal 53 is a signal corresponding to a signal input to the gate of the FET 22. The second AND signal 56 is a signal corresponding to a signal input to the gate of the FET 23.

  FIG. 5 is a timing chart of the switching power supply of Comparative Example 1. As shown in FIG. 5, at time t0, the PWM signal 51 and the delay signal 52 are at a low level. The first AND signal 53 is at a low level. Therefore, the FET 22 is in an off state. The inversion signal 54 and the inversion delay signal 55 are at a high level. The second AND signal 56 is at a high level. The FET 23 is on. The FET 22 is off and the FET 23 is on, and the voltage Vsw at the node N1 is almost the ground voltage.

  At time t1, the PWM signal 51 becomes high level. Since the delay signal 52 is delayed from the PWM signal 51, it maintains a low level. The first AND signal 53 maintains a low level, and the FET 22 maintains an off state. The inversion signal 54 becomes low level. The inverted delay signal 55 maintains a high level. The second AND signal 56 becomes a low level, and the FET 23 is turned off. Both FETs 22 and 23 are off, and the voltage Vsw at node N1 remains low.

  At time t2, the PWM signal 51 is maintained at a high level, and the delay signal 52 is delayed from the PWM signal 51 to become a high level. The first AND signal 53 becomes high level. The FET 22 is turned on. The inversion signal 54 maintains a low level, and the inversion delay signal 55 becomes a low level. The second AND signal 56 maintains a low level, and the FET 23 maintains an off state. The FET 22 is on, the FET 23 is off, and the voltage Vsw at the node N1 is substantially the voltage of the power supply Vcc.

  At time t3, the PWM signal 51 becomes low level, and the delay signal 52 maintains high level. The first AND signal 53 becomes a low level. The FET 22 is turned off. The inversion signal 54 becomes high level, and the inversion delay signal 55 maintains low level. The second AND signal 56 maintains a low level. The FET 23 remains off. Both FETs 22 and 23 are off, and the voltage Vsw at the node N1 is low.

  At time t4, the PWM signal 51 maintains the low level, and the delay signal 52 becomes the low level. The first AND signal 53 maintains a low level. The FET 22 remains off. The inversion signal 54 maintains a high level, and the inversion delay signal 55 becomes a high level. The second AND signal 56 becomes high level. The FET 23 is turned on. The FET 22 is off and the FET 23 is on, and the voltage Vsw at the node N1 maintains a low voltage.

  In this way, a period in which both FETs 22 and 23 are turned off can be set between a period in which FET 22 is turned on and FET 23 is turned off, and a period in which FET 22 is turned off and FET 23 is turned on. Therefore, a through current from the power supply Vcc to the ground can be suppressed.

  However, the dead time controller 27 intentionally delays the PWM signal 51 and the inverted signal 54 by the period T1. Since the dead time controller 27 is in the negative feedback loop, when the delay reaches 180 ° in phase, it becomes a positive feedback. For this reason, the switching frequency of the switching power supply 12b cannot be increased. Therefore, high-speed response becomes difficult in the switching power supply 12b.

  As described above, high speed response is difficult when the switching power supply 12b of FIG. 3 is used for high efficiency, and high efficiency is difficult when the switching power supply 12a is used for high speed response of FIG.

  FIG. 6 is a block diagram of an amplifier circuit according to the first embodiment. As illustrated in FIG. 6, the amplifier circuit 100 includes a high-power amplifier unit 10, a driver amplifier unit 11, a switching power source 12, a linear power source 14, envelope detection circuits 16a and 16b, a synthesis unit 18, and delay circuits 20 and 21. Yes. A high frequency input signal is input from the input terminal. The envelope detection circuit 16a detects the envelope of the input signal and outputs a first envelope signal. The envelope detection circuit 16b detects the envelope of the input signal delayed by the delay circuit 21, and outputs a second envelope signal. The delay circuit 20 delays the input signal in order to synchronize the timing of the input signal input to the high output amplifier 10 and the power supply voltage output from the combiner 18. The driver amplifier 11 amplifies the input signal. The high output amplifier 10 further amplifies the input signal amplified by the driver amplifier 11.

  The linear power supply 14 generates a voltage that follows the second envelope signal. The switching power supply 12 generates a voltage based on the first and second envelope signals. The combiner 18 combines the output power of the linear power supply 14 and the output power of the switching power supply 12 and outputs the combined power to the power supply terminal of the amplifier 10. The amplifying unit 10 includes an FET such as a HEMT (High Electron Mobility Transistor) using a nitride semiconductor, for example. A HEMT using a nitride semiconductor has, for example, a GaN channel layer formed on a substrate and an AlGaN electron supply layer formed on the channel layer. The source of the FET is connected to the ground, an input signal is input to the gate, and an output signal is output from the drain. The drain is connected to the power supply terminal via the choke element. The amplifying unit 10 may be an FET using a GaAs-based semiconductor, or may include a transistor other than the FET.

  FIG. 7 is a circuit diagram illustrating the switching power supply 12 and the signal generator in the amplifier circuit according to the first embodiment. As shown in FIG. 7, the switching power supply 12 includes FETs 22 and 23, an inductor L1, capacitors C1 and C2, a diode D2, gate drivers 24 and 25, and a level shifter 26. The signal generator 35 includes differential amplifier circuits 30a and 30b, PWM circuits 28a and 28b, AND circuits 32 and 36, and an inverter 34.

  The differential amplifier circuit 30a differentially amplifies the first envelope signal and the voltage at the output terminal Tout and outputs a first error signal. The differential amplifier circuit 30b differentially amplifies the second envelope signal and the voltage at the output terminal Tout, and outputs a second error signal. The PWM circuits 28a and 28b perform PWM processing on the first error signal and the second error signal, respectively, and output a first PWM signal 61 and a second PWM signal 62. The AND circuit 32 performs an AND process on the first PWM signal 61 and the second PWM signal 62 to generate a first AND signal 63. The inverter 34 inverts the first PWM signal 61 and the second PWM signal 62 to generate a first inverted signal 64 and a second inverted signal 65. The AND circuit 36 performs AND processing on the first inverted signal 64 (inverted first PWM signal) and the second inverted signal 65 (inverted second PWM signal) to generate a second AND signal 66. The level shifter 26 converts the voltage or amplitude of the first AND signal 63. The converted first AND signal 63 is input to the gate of the FET 22. The second AND signal 66 is input to the gate of the FET 23.

  The FETs 22 and 23 are n-type MOSFETs. The FET 22 is turned on when the first AND signal 63 is at a high level, and the FET 22 is turned off when the first AND signal 63 is at a low level. When the second AND signal 66 is at a high level, the FET 23 is turned on, and when the second AND signal 66 is at a low level, the FET 23 is turned off. When the FET 22 is turned on and the FET 23 is turned off, the voltage Vsw at the node N1 becomes substantially the voltage of the power supply Vcc. When the FET 22 is turned off and the FET 23 is turned on, the voltage Vsw at the node N1 becomes almost the ground voltage. The inductor L1 and the capacitor C1 are a smoothing circuit that smoothes the voltage Vsw. The smoothed voltage is output to the output terminal Tout. Power is supplied from the output terminal Tout to the power supply terminal of the amplifying unit 10.

  FIG. 8 is a timing chart of the switching power supply 12 and the signal generation unit according to the first embodiment. As shown in FIG. 8, at the time t0, the first PWM signal 61 and the second PWM signal 62 are at a low level. The first AND signal 63 is at a low level. Therefore, the FET 22 is in an off state. The first inverted signal 64 and the second inverted signal 65 are at a high level. The second AND signal 66 is at a high level. The FET 23 is on. The FET 22 is off and the FET 23 is on, and the voltage Vsw at the node N1 is almost the ground voltage.

  At time t1, the first PWM signal 61 becomes high level. Since the second PWM signal 62 is delayed from the first PWM signal 61, it maintains a low level. The first AND signal 63 maintains the low level, and the FET 22 maintains the off state. The first inversion signal 64 becomes low level. The second inverted signal 65 maintains a high level. The second AND signal 66 becomes a low level, and the FET 23 is turned off. Both FETs 22 and 23 are off, and the voltage Vsw at node N1 remains low.

  At time t2, the first PWM signal 61 is maintained at a high level, and the second PWM signal 62 is at a high level. The first AND signal 63 becomes high level. The FET 22 is turned on. The first inverted signal 64 maintains a low level, and the second inverted signal 65 becomes a low level. The second AND signal 66 maintains a low level, and the FET 23 maintains an off state. The FET 22 is on, the FET 23 is off, and the voltage Vsw at the node N1 is substantially the voltage of the power supply Vcc.

  At time t3, the first PWM signal 61 becomes low level, and the second PWM signal 62 maintains high level. The first AND signal 63 is at a low level. The FET 22 is turned off. The first inverted signal 64 is at a high level, and the second inverted signal 65 is maintained at a low level. The second AND signal 66 maintains a low level. The FET 23 remains off. Both FETs 22 and 23 are off, and the voltage Vsw at the node N1 is low.

  At time t4, the first PWM signal 61 maintains the low level, and the second PWM signal 62 becomes the low level. The first AND signal 63 maintains a low level. The FET 22 remains off. The first inversion signal 64 maintains a high level, and the second inversion signal 65 becomes a high level. The second AND signal 66 becomes high level. The FET 23 is turned on. The FET 22 is off and the FET 23 is on, and the voltage Vsw at the node N1 maintains a low voltage.

  In this way, a period in which both FETs 22 and 23 are turned off can be set between a period in which FET 22 is turned on and FET 23 is turned off, and a period in which FET 22 is turned off and FET 23 is turned on. Therefore, a through current from the power supply Vcc to the ground can be suppressed.

  According to the first embodiment, the FET 22 is turned on without intentionally delaying the PWM signal. Thus, since the PWM signal is not intentionally delayed in the negative feedback loop, it is possible to suppress the feedback loop from becoming positive feedback. Therefore, the switching frequency of the switching power supply can be increased and a high-speed response can be achieved.

  According to the first embodiment, the AND circuit 32 includes a first PWM signal 61 (first pulse signal) whose pulse width is modulated based on the envelope voltage of the input signal, and a second PWM signal 62 (delayed from the first PWM signal 61). The first AND signal 63 (first control signal) is generated by performing an AND process with the second pulse signal). The AND circuit 36 generates a second AND signal 66 (second control signal) by performing an AND process on the first inverted signal 64 and the second inverted signal 65. The FET 22 (first switch) operates based on the first AND signal 63. The FET 23 (second switch) operates based on the second AND signal 66.

  Thereby, like the comparative example 1, even if it raises a switching frequency, it can suppress that a feedback loop becomes a positive feedback. Therefore, the response speed can be increased by increasing the switching frequency.

  Further, the FET 22 and the FET 23 are connected in series between a power source Vcc (first power source) and a ground (second power source having a voltage different from that of the first power source). Thereby, as in Comparative Example 1 (FIG. 2), the power loss of the freewheeling diode can be reduced, so that a highly efficient switching power supply can be obtained.

  Further, the PWM circuit 28a generates a first PWM signal 61 based on the first error signal, and the PWM circuit 28b generates a second PWM signal 62 based on the second error signal. Thereby, the second PWM signal 62 can be delayed from the first PWM signal 61.

  Further, the linear power supply 14 outputs power at a voltage that follows the second envelope signal. The combining unit 18 supplies the combined power of the power output from the linear power supply 14 and the power output from the switching power supply 12 to the power supply terminal of the amplification unit 10. Thereby, when the envelope changes at high speed, the linear power supply 14 mainly supplies power, and when the envelope changes at low speed, the switching power supply 12 mainly supplies power. Therefore, a high-efficiency amplifier circuit capable of high-speed response can be realized.

  Further, the differential amplifier circuit 30a generates a first error signal based on the difference between the first envelope signal and the voltage at the output terminal Tout. The differential amplifier circuit 30b generates a second error signal based on the second envelope signal and the voltage at the output terminal Tout. Thereby, the voltage of the output terminal Tout can be controlled to a voltage corresponding to the envelope.

  The delay circuit 21 delays the input signal. The envelope detection circuit 16a (first detection circuit) detects the envelope of the input signal before being input to the delay circuit 21 as the first envelope signal. The envelope detection circuit 16b (second detection circuit) detects the envelope of the input signal delayed by the delay circuit 21 as a second envelope signal. Thereby, the first envelope signal and the second envelope signal can be generated.

  The characteristics of the first envelope signal and the second envelope signal are preferably almost the same. It is preferable that the characteristics of the differential amplifier circuits 30a and 30b, the characteristics of the PWM circuits 28a and 28b, and the characteristics of the AND circuits 32 and 36 are almost the same. As a result, the period in which both FETs 22 and 23 are off can be generated almost symmetrically.

  FIG. 9 is a block diagram of an amplifier circuit according to the second embodiment. As shown in FIG. 9, in the amplifier circuit 102, the envelope detection circuit 16 generates a first envelope signal from the envelope of the input signal. A delay circuit 21 delays the first envelope signal to generate a second envelope signal.

  According to the second embodiment, the envelope detection circuit 16 (detection circuit) detects the envelope of the input signal as the first envelope signal. The delay circuit 21 generates a second envelope signal by delaying the first envelope signal. Thereby, the first envelope signal and the second envelope signal can be generated. In the first embodiment, a characteristic difference between the first envelope signal and the second envelope signal is likely to occur due to the characteristic difference between the envelope detection circuits 16a and 16b. In the second embodiment, since there is only one envelope detection circuit 16, a characteristic difference between the first envelope signal and the second envelope signal hardly occurs.

  FIG. 10 is a block diagram of an amplifier circuit according to the third embodiment. As shown in FIG. 10, the amplifier circuit 104 includes a baseband processor 40 (processor), DACs (Digital Analog Converters) 42 and 44, and a modulator 46. The baseband processor 40 realizes the functions of the delay circuits 20 and 21, the envelope detection circuits 16a and 16b, and the signal generation unit 35 by digital signal processing. The DAC 42 converts the second envelope signal, which is a digital signal, into an analog signal. The second envelope signal converted into the analog signal is input to the linear power supply 14. The DAC 44 converts an input signal that is a digital signal into an analog signal. The input signal converted into the analog signal is modulated by the modulator 46. The modulated input signal is input to the driver amplifier 11. Other configurations are the same as those in the first embodiment, and a description thereof will be omitted.

  As in the third embodiment, at least part of the signal processing can be performed by digital signal processing. As a result, the delay time can be easily controlled. Further, the characteristics of the first envelope signal and the second envelope signal can be made almost the same. The characteristics of the differential amplifier circuits 30a and 30b, the characteristics of the PWM circuits 28a and 28b, and the characteristics of the AND circuits 32 and 36 can be made almost the same.

  As a processor such as the baseband processor 40, for example, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or a digital signal processor (DSP) can be used.

  In the first to third embodiments, the FETs 22 and 23 are described as examples of switches. However, the switches may be switches other than FETs or switches such as thyristors. Further, the FETs 22 and 23 may be p-type FETs.

  Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims. It can be changed.

DESCRIPTION OF SYMBOLS 10 Amplification part 12 Switching power supply 14 Linear power supply 16a, 16b Envelope detection circuit 18 Synthesis | combination part 20, 21 Delay circuit 22, 23 FET
28a, 28b PWM circuit 30a, 30b Differential amplifier circuit 32, 36 AND circuit 35 Signal generator

Claims (8)

An amplifying unit to which an input signal is input;
Generating a first control signal by performing an AND process on a first pulse signal whose pulse width is modulated based on an envelope voltage of the input signal and a second pulse signal delayed from the first pulse signal; A signal generator that generates a second control signal by performing an AND process on the inverted signal of the first pulse signal and the inverted signal of the second pulse signal;
A first switch that operates based on the first control signal; and a second switch that operates based on the second control signal. A switching power supply that supplies the first power to follow,
An amplifying circuit comprising:   The signal generator generates the first pulse signal based on a first envelope signal corresponding to an envelope voltage of the input signal, and the second pulse signal based on a second envelope signal obtained by delaying the first envelope signal. The amplifier circuit according to claim 1, wherein: A linear power source that outputs a second power based on the second envelope signal;
A combining unit that supplies power obtained by combining the first power and the second power to a power supply terminal of the amplifying unit;
The amplifier circuit according to claim 2, further comprising:   The signal generation unit generates the first pulse signal based on a difference between the first envelope signal and a voltage of an output terminal of the switching power supply, and the second envelope signal and a voltage of the output terminal of the switching power supply 4. The amplifier circuit according to claim 2, wherein the second pulse signal is generated based on: A delay circuit for delaying the input signal;
A first detection circuit that detects an envelope voltage of the input signal before being input to the delay circuit as the first envelope signal;
A second detection circuit that detects an envelope voltage of the input signal delayed by the delay circuit as the second envelope signal;
The amplifier circuit according to claim 2, further comprising: A detection circuit for detecting an envelope of the input signal as the first envelope signal;
A delay circuit for generating the second envelope signal by delaying the first envelope signal;
The amplifier circuit according to claim 2, further comprising:   The first switch is connected in series between a first power source and a second power source, and the second switch is connected in series with the first switch between the first power source and the second power source. The amplifier circuit according to claim 1, wherein the amplifier circuit is provided.   8. The amplifier circuit according to claim 7, wherein the switching power supply includes a smoothing circuit that smoothes a voltage at a node between the first switch and the second switch and outputs the smoothed voltage to a power supply terminal of the amplifier.

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