JP2015041999A5 - - Google Patents
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- JP2015041999A5 JP2015041999A5 JP2013173885A JP2013173885A JP2015041999A5 JP 2015041999 A5 JP2015041999 A5 JP 2015041999A5 JP 2013173885 A JP2013173885 A JP 2013173885A JP 2013173885 A JP2013173885 A JP 2013173885A JP 2015041999 A5 JP2015041999 A5 JP 2015041999A5
- Authority
- JP
- Japan
- Prior art keywords
- signal
- envelope
- power
- switch
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- 238000001514 detection method Methods 0.000 claims 3
- 230000003111 delayed Effects 0.000 claims 2
- 238000000034 method Methods 0.000 claims 2
- 230000003321 amplification Effects 0.000 claims 1
- 230000000875 corresponding Effects 0.000 claims 1
- 238000009499 grossing Methods 0.000 claims 1
- 230000000051 modifying Effects 0.000 claims 1
- 238000003199 nucleic acid amplification method Methods 0.000 claims 1
Claims (6)
前記入力信号のエンベロープ電圧に基づいてパルス幅が変調される第１パルス信号と、前記第１パルス信号より遅延した第２パルス信号と、のＡＮＤ処理を行なうことにより第１制御信号を生成し、前記第１パルス信号の反転信号と前記第２パルス信号の反転信号とのＡＮＤ処理を行なうことにより第２制御信号を生成する信号生成部と、
前記第１制御信号に基づき動作する第１スイッチと、前記第２制御信号に基づき動作する第２スイッチと、を有し、前記増幅部の電源端子に、前記電源端子の電圧が前記エンベロープ電圧に追従するように第１電力を供給するスイッチング電源と、
を具備することを特徴とする増幅回路。 An amplifying unit to which an input signal is input;
Generating a first control signal by performing an AND process on a first pulse signal whose pulse width is modulated based on an envelope voltage of the input signal and a second pulse signal delayed from the first pulse signal; A signal generator that generates a second control signal by performing an AND process on the inverted signal of the first pulse signal and the inverted signal of the second pulse signal;
A first switch that operates based on the first control signal; and a second switch that operates based on the second control signal. The voltage of the power terminal is set to the envelope voltage at the power terminal of the amplifier. A switching power supply that supplies the first power to follow,
An amplifying circuit comprising:
前記第１電力と前記第２電力とを合成した電力を、前記増幅部の電源端子に供給する合成部と、
を具備することを特徴とする請求項２記載の増幅回路。 A linear power source that outputs a second power based on the second envelope signal;
A combining unit that supplies power obtained by combining the first power and the second power to a power supply terminal of the amplification unit;
The amplifier circuit according to claim 2, further comprising:
前記遅延回路に入力する前の前記入力信号のエンベロープ電圧を前記第１エンベロープ信号として検出する第１検出回路と、
前記遅延回路により遅延した前記入力信号のエンベロープ電圧を前記第２エンベロープ信号として検出する第２検出回路と、
を具備することを特徴とする請求項２または３記載の増幅回路。 A delay circuit for delaying the input signal;
A first detection circuit that detects an envelope voltage of the input signal before being input to the delay circuit as the first envelope signal;
A second detection circuit that detects an envelope voltage of the input signal delayed by the delay circuit as the second envelope signal;
Amplifier circuit according to claim 2 or 3 further characterized in that comprises a.
前記第１エンベロープ信号を遅延させることにより前記第２エンベロープ信号を生成する遅延回路と、
を具備することを特徴とする請求項２または３記載の増幅回路。 A detection circuit for detecting an envelope of the input signal as the first envelope signal;
A delay circuit for generating the second envelope signal by delaying the first envelope signal;
Amplifier circuit according to claim 2 or 3 further characterized in that comprises a.
前記スイッチング電源は、前記第１スイッチと前記第２スイッチとの間のノードの電圧を平滑化し前記増幅部の電源端子に出力する平滑回路を有することを特徴とする請求項１から５のいずれか一項記載の増幅回路。 The first switch is connected in series between a first power source and a second power source, and the second switch is connected in series with the first switch between the first power source and the second power source. and,
The switching power supply, any of claims 1 to 5, characterized in that it comprises a smoothing circuit voltage of the node smoothes and outputs to the power supply terminal of the amplifying section between the second switch and the first switch An amplifier circuit according to one item.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2013173885A JP2015041999A (en) | 2013-08-23 | 2013-08-23 | Amplification circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2013173885A JP2015041999A (en) | 2013-08-23 | 2013-08-23 | Amplification circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2015041999A JP2015041999A (en) | 2015-03-02 |
| JP2015041999A5 true JP2015041999A5 (en) | 2016-10-13 |
Family
ID=52695889
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2013173885A Pending JP2015041999A (en) | 2013-08-23 | 2013-08-23 | Amplification circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2015041999A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021205882A1 (en) * | 2020-04-06 | 2021-10-14 | ローム株式会社 | Switching circuit, switching power supply, gate driver circuit for switching power supply, and control circuit for switching power supply |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002119053A (en) * | 2000-10-10 | 2002-04-19 | Onkyo Corp | Switching regulator |
| JP2002230905A (en) * | 2001-01-29 | 2002-08-16 | Niigata Seimitsu Kk | Device and method for reproducing voice |
| JP2004128639A (en) * | 2002-09-30 | 2004-04-22 | Denon Ltd | Class d amplifier |
| US7190150B2 (en) * | 2005-02-28 | 2007-03-13 | Freescale Semiconductor, Inc. | DC—DC converter for power level tracking power amplifiers |
| JP2007124574A (en) * | 2005-10-31 | 2007-05-17 | Sharp Corp | Class d amplifier and infrared ray data receiver employing the same |
| JP5003134B2 (en) * | 2006-01-10 | 2012-08-15 | 日本電気株式会社 | Amplifier |
-
2013
- 2013-08-23 JP JP2013173885A patent/JP2015041999A/en active Pending
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