JP2015038688A - Memory unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory unit capable of safely completing writing on a memory even when a power failure occurs during data writing on the memory and capable of reducing communication delay by using information representing a flight state of an aircraft.SOLUTION: The memory unit has a relay circuit that switches a control circuit between a relay connection and a through connection on the basis of a flight state. When the flight information is "stable operation", the control circuit is set to the through connection to directly perform the communication between the memory control means and the memory to thereby reduce communication delay. When the flight information is not "stable operation", the control circuit is set to the relay connection so as to output a writing stop command to the memory when the control circuit receives a voltage-low signal.

Description

  The present disclosure relates to a memory device capable of storing data of a backbone system mounted on an aircraft.

  U.S. Pat. No. 6,057,051 discloses an environmentally protected and reliable fixed memory array suitable for use for an aircraft flight decoder system that can be stored in the event of a collision. The erase / write protection circuit is designed to disable both the read and write functions of the memory unit and disable the memory control lines when the voltage of the power source is low, thereby enabling various system It is intended to prevent erroneous data accumulation in the memory unit resulting from the low voltage operation of the circuit.

JP-T 61-501176

  The present disclosure can safely finish writing to the memory even if the power is shut down while writing data to the memory, and can reduce communication delay by using information indicating the operation status of the aircraft. A memory device is provided.

  A memory device according to the present disclosure is a memory device that is used in an aircraft body and can read / write data from / to an external memory, and receives an input-related voltage drop detection circuit that detects power-off and an aircraft-related information from the outside. Memory control that determines whether the flight status is “stable operation” or “power shutdown” based on the received aircraft-related information and outputs a write command to the memory when an external data write instruction is issued And a relay circuit that determines whether or not to connect the data communication line connecting the memory control unit and the memory to the control circuit based on the flight state, and the input voltage drop detection circuit detects the power shutdown When the flight state is “stable operation”, the power supply detection signal is output to the memory control unit and the relay circuit. Pass through the control circuit and switch to relay the control circuit when the power is cut off. The control circuit detects that the relay circuit has lost power when the data communication line is switched to relay the control circuit in the relay circuit. When the signal is received, the write stop command is output to the memory.

  The memory control device according to the present disclosure can suppress data destruction by safely ending the writing even when the power is cut off during the data writing to the memory. Furthermore, communication delay can be reduced by using information indicating the operational status of the aircraft.

1 is a block diagram showing a configuration of a memory device according to a first embodiment. 3 is a flowchart showing the operation of the memory device according to the first embodiment.

  Hereinafter, embodiments will be described in detail with reference to the drawings as appropriate. However, more detailed description than necessary may be omitted. For example, detailed descriptions of already well-known matters and repeated descriptions for substantially the same configuration may be omitted. This is to avoid the following description from becoming unnecessarily redundant and to facilitate understanding by those skilled in the art.

  The inventor (s) provides the accompanying drawings and the following description in order for those skilled in the art to fully understand the present disclosure, and is intended to limit the subject matter described in the claims. Not what you want.

(Embodiment 1)
Hereinafter, the first embodiment will be described with reference to FIGS. 1 and 2.

[1-1 Configuration]
FIG. 1 is a diagram illustrating a configuration of the memory device according to the first embodiment.

  The memory device 100 is a device for recording data used in the aircraft system 101. The memory device 100 includes a power supply circuit 102, a communication circuit 103, memory control means 104, a relay circuit 105, and a memory 106.

  The power supply circuit 102 generates power for use inside the memory device 100 from a power supply unit (not shown) of the aircraft system 101, and supplies power to the communication circuit 103, the memory control unit 104, the relay circuit 105, and the memory 106. Is supplied (broken line in FIG. 1). The power supply circuit 102 includes an input voltage drop detection circuit 107 and a voltage holding circuit 108. The input voltage drop detection circuit 107 outputs a voltage drop detection signal to the memory control means 104 and the relay circuit 105 when the power from the power supply unit of the aircraft system 101 drops. The voltage holding circuit 108 holds the voltage inside the memory device 100 for a certain period.

  The communication circuit 103 receives flight phase information indicating the operational state of the aircraft from the aircraft system 101. The flight phase information includes at least “stable operation (ground mode)”, “power cut-off”, and “stable operation (in-flight mode)”. “Stable operation (ground mode)” refers to a state where the power of the airplane is supplied from the towing car. “Power off” refers to the state in which the power supply from the ground disappears when the airplane is pulled away from the towing car before takeoff, as well as in the state of running until just before takeoff, and after landing, State, as well as the state from when the airplane is connected to the towing car and powered from the ground. “Stable operation (in-flight mode)” refers to a state in which the aircraft is generating power and supplying power.

  The memory control unit 104 outputs a write command to the memory 106 when there is a data write instruction from the aircraft system 101. The memory control unit 104 outputs a write stop command to the memory 106 when a data write stop instruction is issued from the aircraft system 101. Further, the memory control means 104 outputs a relay switching signal when it is determined that the power interruption is likely to occur.

  The relay circuit 105 relays commands and data to the memory 106 based on an instruction from the memory control unit 104. The relay circuit 105 includes a control circuit 109 and a relay switching circuit 110. When receiving the voltage drop detection signal, the control circuit itself outputs a write prohibit command. Based on the relay switching signal from the memory control unit 104 and the voltage drop detection signal from the power supply circuit 102, the relay circuit 105 passes the command and data from the memory control unit 104 as they are and sends them to the memory 106. Switching to command or data transmission via the circuit 109 is performed. When receiving the relay switching signal, the control circuit 109 switches the relay switching circuit 110 to the point a. On the other hand, when the control circuit 109 does not receive the relay switching signal, the control circuit 109 switches the relay switching circuit 110 to the point b.

  When the memory 106 receives a write command from the memory control means 104, it writes data. When the memory 106 receives a write stop command from the memory control means 104, the memory 106 stops writing data.

[1-2 Operation]
The operation of the memory device 100 configured as described above will be described in detail with reference to the flowchart shown in FIG.

  The communication circuit 103 acquires flight phase information from the aircraft system 101 (step S100). For example, when the aircraft is waiting at the passenger terminal, the flight phase information is “stable operation (ground mode)”.

  The memory control means 104 determines from the flight phase information acquired by the communication circuit 103 whether or not the current state is likely to cause a power shutdown (step S101). If it is determined that it is likely to occur, the process proceeds to step S102. If it is determined that it is not likely to occur, the process proceeds to step S106. For example, when the flight phase information is “power cut-off”, the power cut-off is likely to occur when the flight phase information is pulled away from the towing car, and thus the process proceeds to step S102.

  When it is determined that power interruption is likely to occur, the memory control unit 104 outputs a relay switching signal to the relay circuit 105. When receiving the relay switching signal from the memory control means 104, the relay circuit 105 switches the relay switching circuit to point a so as to send the command and data via the control circuit 109 (step S102).

  In the relay circuit 105, the memory control unit 104 relays the control circuit 109 to perform writing to the memory 106 (step S103).

  When the control circuit 109 receives the voltage drop detection signal (step S104), the relay circuit 105 outputs a write stop command to the memory 106. When the memory 106 receives this write stop command, the memory 106 stops the data write process (step S105). As described above, when the control circuit 109 receives the voltage drop detection signal, the write stop command is output by itself. Therefore, even if the memory control unit 104 delays the output of the write stop command in another process, the memory 106 Can receive a write command.

  On the other hand, when it is determined in step S101 that power interruption is unlikely to occur, the relay circuit 105 does not receive the relay switching signal from the memory control means 104 and sets the relay switching circuit 110 to the point b so as not to pass through the control circuit 109. Switching (step S106). When the memory 106 receives the write command, the memory 106 performs a data write process (step S107).

[1-3 Effects, etc.]
As described above, in the first embodiment, the memory device 100 can safely stop writing to the memory 106 even when the power is cut off.

  Also, communication delay can be reduced by efficiently switching between connecting the control circuit so as to relay based on the flight phase information and connecting the control circuit so as to pass through.

  In the first embodiment, the flight phase information is used as the information indicating the operational status of the aircraft. However, altitude information and speed information of the aircraft may be used. For example, when the speed of the aircraft exceeds 50 km / h, it may be determined that the power interruption is unlikely to occur.

  In the first embodiment, a memory for writing or reading by a command is used. However, a memory having a data write protection function by a reset signal may be used. For example, if the control circuit receives a voltage drop detection signal when the power supply is likely to be shut down, the memory may receive the reset signal and do not perform writing if the reset signal is sent to the memory. good.

  In the first embodiment, only one power supply circuit is provided, but a plurality of power supply circuits may be used. For example, the voltage drop detection signal may be output only when the input voltage drop detection circuit drops the supply of all power supply circuits.

  As described above, the embodiments have been described as examples of the technology in the present disclosure. For this purpose, the accompanying drawings and detailed description are provided.

  Accordingly, among the components described in the accompanying drawings and the detailed description, not only the components essential for solving the problem, but also the components not essential for solving the problem in order to illustrate the above technique. May also be included. Therefore, it should not be immediately recognized that these non-essential components are essential as those non-essential components are described in the accompanying drawings and detailed description.

  Moreover, since the above-mentioned embodiment is for demonstrating the technique in this indication, a various change, substitution, addition, abbreviation, etc. can be performed in a claim or its equivalent range.

  The present disclosure is applicable to a device mounted on an aircraft and having a memory.

DESCRIPTION OF SYMBOLS 100 Memory device 101 Aircraft system 102 Power supply circuit 103 Communication circuit 104 Memory control means 105 Relay circuit 106 Memory 107 Input voltage drop detection circuit 108 Voltage holding circuit 109 Control circuit 110 Relay switching circuit

Claims (3)

A memory device used in an aircraft body and capable of reading / writing data from / to an external memory,
An input voltage drop detection circuit that detects power-off,
Receives aircraft-related information from outside, determines whether the flight status is “stable operation” or “power-off” based on the received aircraft-related information, and writes when there is an instruction to write data from outside A memory control unit for outputting a command to the memory;
A relay circuit for determining whether to connect a data communication line connecting the memory control unit and the memory to a control circuit based on the flight state;
The input voltage drop detection circuit outputs a power drop detection signal to the memory control unit and the relay circuit when detecting a power shutdown.
The relay circuit is switched to pass through the control circuit when the flight state is “stable operation”, and to relay the control circuit when the power supply is cut off,
When the relay circuit receives the power drop detection signal when the data communication line is switched to relay the control circuit in the relay circuit, the control circuit itself issues a write stop command to the memory. A memory device for outputting. The memory device according to claim 1, wherein the aircraft-related information is flight phase information indicating an operation state of the aircraft. The aircraft related information is speed information of an aircraft,
The memory device according to claim 1, wherein the control unit determines “stable operation” when the aircraft-related information is greater than a predetermined value.

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