JP2015029152A - Multilayer ceramic capacitor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multilayer ceramic capacitor which has a sufficient reliability, and enables the suppression of delamination between an internal electrode and a dielectric layer.SOLUTION: A multilayer ceramic capacitor comprises: a ceramic elemental body 10 including dielectric layers 1 and internal electrodes 2 arranged between the dielectric layers; and external electrodes provided to electrically connect with the corresponding internal electrodes 2. The internal electrodes are each arranged between dielectric layers 1 in a wavy form as a crown-like portion 41 and a valley-like portion 42 are repeated in any of the case of viewing the ceramic elemental body from a first or second end face of the ceramic elemental body, and the case of viewing from first or second side face of the ceramic elemental body; the distance P between the crown-like portions is in a range of 100-150 μm. The distance between the internal electrodes adjacent to each other is 0.7-0.9 μm. The internal electrodes have a thickness of 0.6-0.8 μm. The number of layers of the internal electrodes is equal to or less than 400.

Description

  The present invention electrically connects an internal electrode to a ceramic body having a dielectric layer made of a dielectric ceramic and a plurality of internal electrodes stacked via the dielectric layer and positioned at a plurality of interfaces between the dielectric layers. The present invention relates to a multilayer ceramic capacitor having a structure provided with an external electrode.

  One typical ceramic electronic component is, for example, a multilayer ceramic capacitor as disclosed in Patent Document 1.

  As shown in FIG. 4, the multilayer ceramic capacitor includes a pair of ceramic laminates (ceramic bodies) 110 in which a plurality of internal electrodes 102 (102a, 102b) are laminated via a ceramic layer 101 which is a dielectric layer. The end surface 103 (103a, 103b) has a structure in which a pair of external electrodes 104 (104a, 104b) are disposed so as to be electrically connected to the internal electrode 102 (102a, 102b).

  In the multilayer ceramic capacitor disclosed in Patent Document 1, a conductive paste (oxide conductive paste) containing an oxide containing zinc having a sintering temperature close to that of the dielectric is used as a conductive paste for forming an internal electrode. Thus, a multilayer ceramic capacitor having an internal electrode with a high coverage is obtained.

  Further, in Patent Document 1, by using a conductive oxide mainly composed of zinc containing any one of Al, Ga, Si, and Sn, conductivity, sintering temperature, sintering, which are important in a conductive paste, are used. It is said that the behavior can be controlled.

  However, in the case of a multilayer ceramic capacitor, the internal electrode and the dielectric (ceramic) constituting the dielectric layer usually differ greatly in constituent material and composition, so the adhesion between the two is weak, and the shrinkage rate when fired Is also different.

  Therefore, for example, even if an internal electrode having a high coverage is formed by the method of Patent Document 1, separation between the internal electrode and the dielectric layer is caused by a difference in shrinkage rate between the internal electrode and the dielectric in the firing process. As a result, there is a problem that a multilayer ceramic capacitor having high characteristics cannot be obtained.

JP2013-12418A

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a multilayer ceramic capacitor that can suppress peeling between the internal electrode and the dielectric layer and has sufficient reliability.

In order to solve the above problems, the multilayer ceramic capacitor of the present invention is
A ceramic body comprising a dielectric layer made of a dielectric ceramic, and a plurality of internal electrodes stacked via the dielectric layer and positioned at a plurality of interfaces between the dielectric layers, A second main surface opposite to the first main surface, a first end surface orthogonal to the first main surface, a second end surface opposite to the first end surface, and the first The dielectric has a rectangular parallelepiped shape including a first side surface orthogonal to an end surface and a second side surface facing the first side surface, and a direction from the first main surface toward the second main surface is the dielectric. A ceramic body in which the layers and the internal electrodes are stacked and the plurality of internal electrodes are alternately drawn to the first end face and the second end face;
A multilayer ceramic capacitor comprising a pair of external electrodes disposed on the ceramic body so as to be electrically connected to the internal electrodes drawn out to the first end surface and the second end surface;
The internal electrode is in a curved state in which peaks and valleys repeat in both cases when viewed from the first or second end surface side and when viewed from the first or second side surface side. It is disposed between the dielectric layers, and the distance between one mountain and the mountain adjacent to the one mountain is in the range of 100 to 150 μm.

  In the multilayer ceramic capacitor of the present invention, it is preferable that the distance between the adjacent internal electrodes is in the range of 0.7 μm to 0.9 μm.

  In the multilayer ceramic capacitor of the present invention, the distance between the internal electrodes, that is, the thickness of the dielectric layer interposed between the internal electrodes is preferably in the range of 0.7 μm to 0.9 μm. When the thickness is less than 0.7 μm, the withstand voltage characteristic is lowered, and when it exceeds 0.9 μm, it is difficult to obtain a required capacity.

  Moreover, it is preferable that the thickness of the said internal electrode exists in the range of 0.6 micrometer-0.8 micrometer.

  If the thickness of the internal electrode is less than 0.6 μm, the internal electrode may be damaged due to the curved shape such that the peaks and valleys repeat as described above. Since it becomes difficult to give a curved shape such that the valley repeats, the thickness of the internal electrode is preferably in the range of 0.6 μm to 0.8 μm.

  Moreover, it is preferable that the number of layers of the internal electrode is 400 or less.

  In the case of a multilayer ceramic capacitor that has been multilayered so that the number of internal electrode layers exceeds 400, the dielectric layer is usually designed to be thin, and the internal electrode is curved so that peaks and valleys repeat. If this is given, the risk of lowering the withstand voltage increases. Therefore, it is desirable to apply the present invention to an internal electrode having 400 layers or less.

  In the multilayer ceramic capacitor of the present invention, peaks and valleys are repeated both when the internal electrode is viewed from the first or second end surface side and when viewed from the first or second side surface side. Since it is arranged between the dielectric layers in such a curved state and the interval between one mountain and the adjacent mountain is 100 to 150 μm, it is adjacent to the internal electrode mountain. Since the valleys of the dielectric layers are joined, the valleys of the internal electrodes and the peaks of the adjacent dielectric layers are joined, and the internal electrodes and the dielectric layers are firmly engaged. It is possible to provide a highly reliable multilayer ceramic capacitor by suppressing and preventing the occurrence of delamination.

  In the multilayer ceramic capacitor of the present invention, the interval between one mountain and the adjacent mountain is in the range of 100 to 150 μm because the withstand voltage decreases when the distance between one mountain and the adjacent mountain is less than 100 μm. When the thickness exceeds 150 μm, the effect of suppressing delamination between the internal electrode and the dielectric layer is reduced.

It is a front sectional view showing the composition of the multilayer ceramic capacitor concerning one embodiment of the present invention. 1 is a perspective view showing an external configuration of a multilayer ceramic capacitor according to an embodiment of the present invention. It is a figure showing composition of a multilayer ceramic capacitor concerning one embodiment of the present invention, and is a sectional view expanding and showing an important section. It is front sectional drawing which shows the structure of the conventional multilayer ceramic capacitor.

  Embodiments of the present invention will be described below to describe the features of the present invention in more detail.

  FIG. 1 is a front sectional view showing a configuration of a multilayer ceramic capacitor 50 according to one embodiment (Embodiment 1) of the present invention, and FIG. 2 is a perspective view showing an external configuration of the multilayer ceramic capacitor 50.

As shown in FIGS. 1 and 2, the multilayer ceramic capacitor 50 includes a dielectric layer 1 made of a dielectric ceramic and a plurality of internal electrodes 2 (2a, 2b) disposed at a plurality of interfaces between the dielectric layers 1. And a pair of external electrodes 5 (5a, 5b) disposed on the outer surface of the ceramic body 10 so as to be electrically connected to the internal electrodes 2 (2a, 2b). Yes.
An auxiliary electrode 6 (6a, 6b) is disposed between the internal electrode 2 (2a, 2b) and a first main surface 11a and a second main surface 11b of the ceramic body 10, which will be described later. ing. The auxiliary electrode 6 (6a, 6b) is electrically connected to an external electrode having the same potential as the adjacent internal electrode 2 (2a, 2b). However, it may not be electrically connected to the external electrode.
The auxiliary electrode 6 (6a, 6b) may be provided only on the first main surface 11a side, or may be provided only on the second main surface 11b side.
Further, a plurality of auxiliary electrodes 6 (6a, 6b) may be provided.
It is also possible to adopt a configuration in which the auxiliary electrode 6 (6a, 6b) is not provided.

The dielectric layer 1 constituting the ceramic body 10 is formed of a BaTiO ₃ based ceramic dielectric. Incidentally, with respect Ti100 moles of BaTiO _3, Dy 1.0 mol part, Mg is added to a 1.3 molar parts, and further added Mn.
The dielectric layer 1 is not limited to a BaTiO ₃ -based ceramic dielectric but may be formed of other ceramic dielectrics such as a CaZrO ₃ -based material.
The internal electrode 2 is a metal layer mainly composed of a base metal such as Ni or Cu.

  The ceramic body 10 has a rectangular parallelepiped shape, and includes a first main surface 11a, a second main surface 11b facing the first main surface 11a, and a first main surface 11a orthogonal to the first main surface 11a. An end surface 21a, a second end surface 21b facing the first end surface 21a, a first side surface 31a orthogonal to the first end surface 21a, and a second side surface 31b facing the first side surface 31a are provided. .

  When the direction connecting the first main surface 11a and the second main surface 11b is the height direction, the height direction is the stacking direction of the dielectric layer 1 and the internal electrodes 2 (2a, 2b). .

  A plurality of internal electrodes 2 (2a, 2b) are alternately drawn out on the first end face 21a and the second end face 21b, the internal electrode 2a is drawn out on the first end face 21a, and the second end face The internal electrode 2b is drawn out to 21b.

  In the multilayer ceramic capacitor 50 according to this embodiment, the external electrode 5 (5a, 5b) has a structure including the sintered metal layer 12 (12a, 12b) and the plating layer 32 (32a, 32b). ing.

  The sintered metal layer 12 (12a, 12b) is a baked electrode (thick film electrode) formed by applying and baking a conductive paste containing Cu powder or Ni powder as a conductive component on the ceramic body 10. The constituent material of the sintered metal layer 12 (12a, 12b) is not limited to the above-described Cu or Ni, and other metal materials can also be used.

The sintered metal layer 12 (12a, 12b) is formed from the first end surface 21a and the second end surface 21b of the ceramic body 10 and the first and second main surfaces 11a, 11b of the ceramic body 10 and It is formed so as to go around the first and second side surfaces 31a and 31b.
The thickness of the sintered metal layer 12 is usually desirably in the range of 0.5 μm to 10 μm.
However, the thickness of the sintered metal layer 12 is not limited to the above range, and may be other thicknesses.

  The plating layer 32 (32a, 32b) is formed so as to cover the entire sintered metal layer 12 (12a, 12b).

  In this embodiment, the plating layer 32 (32a, 32b) includes the Ni plating layer 33 (33a, 33b) formed on the sintered metal layer 12 (12a, 12b) and the Ni plating layer 33 (33a, 33b). 33b) a plating layer having a two-layer structure including the Sn plating layer 34 (34a, 34b) formed thereon.

  In the multilayer ceramic capacitor 50, the boundary between the auxiliary electrode 6 (6a, 6b) and the outer ceramic layer (that is, the ceramic layer on the first main surface 11a and the second main surface 11b side). Is provided with 69% or more of a boundary layer containing Mg and Mn. The auxiliary electrode 6 (6a, 6b) has a continuity of 60% or more. Furthermore, segregated materials containing Si are present in 39% or more of the defect portions, which are regions where continuity is interrupted. The molar ratio Mn / Mg of the Mn content to the Mg content in the boundary layer is not particularly limited, but is particularly preferably in the range of Mn / Mg = 0.005 to 0.7.

  The presence of the boundary layer of the auxiliary electrode 6 (6a, 6b) was confirmed as follows. First, the multilayer ceramic capacitor was polished by a polishing machine in such a manner that the surface defined by the length direction and the thickness direction was exposed. At this time, after polishing to a depth of about ½ in the width direction of the multilayer ceramic capacitor, sagging of the internal electrode due to the polishing was removed.

  Then, on the polished end face polished as described above, a straight line substantially perpendicular to the internal electrode 2 is drawn (assumed) at the central position in the length direction of the multilayer ceramic capacitor. And the area | region (boundary layer) where the boundary part of the auxiliary electrode 6 (6a, 6b) and the said straight line orthogonally crossed was observed by magnification 10,000 times using the electron microscope. And in this embodiment, the presence of the boundary layer of the auxiliary electrode 6 (6a, 6b) was confirmed by setting the width of the observation visual field to 10 μm and performing observation with FE-WDX.

The thickness of the internal electrode 2 (2a, 2b) was determined as follows.
First, the polishing end face was divided into three equal parts in the thickness direction, and was divided into three regions: an upper region, an intermediate region, and a lower region.

  And in each area | region, except the outermost internal electrode 2, the thickness of the internal electrode 2 of the position orthogonal to said straight line was measured at random 5 layers each, and the average value was calculated | required. The thickness of the internal electrode was measured using a scanning electron microscope. However, parts that could not be measured due to a lack of internal electrodes were excluded from the measurement target.

  In addition, the thickness of the dielectric layer 1 is measured by randomly measuring five layers of the dielectric layer 1 at positions orthogonal to the straight line in each of the three regions, the upper region, the middle region, and the lower region. The average value was obtained. The thickness of the dielectric layer was measured using a scanning electron microscope.

  However, the outermost dielectric layer positioned outside the outermost internal electrode 2 located on the outermost side in the stacking direction, and two or more dielectric layers connected to each other due to the lack of the internal electrode are observed. Parts that could not be measured due to reasons such as

  Moreover, the area | region (boundary layer) of the location where the boundary part of auxiliary electrode 6 (6a, 6b) and said straight line orthogonally crossed was observed by magnification 10,000 times using the electron microscope. In this embodiment, the width of the observation visual field was 10 μm, and observation was performed with FE-WDX.

  In the multilayer ceramic capacitor of this embodiment, as schematically shown in FIG. 3, the internal electrode 2 is viewed from the first or second end face 21a, 21b (FIG. 2) side, and the first Alternatively, in any case when viewed from the second side surfaces 31a and 31b (FIG. 2), the crest 41 and the trough 42 are disposed between the dielectric layers 1 in a curved state such that the crest 41 and the trough 42 are repeated.

  The interval P between one peak 41 (41a) of the internal electrode 2 and the adjacent peak 41 (41b) is configured to be in the range of 100 to 150 μm. .

  Further, the distance H from the top of the peak 41 to the bottom of the valley 42 in the internal electrode 2 is configured to be 1 to 10 μm.

  In this embodiment, the distance between the internal electrodes 2 adjacent to each other through the dielectric layer is configured to be in the range of 0.7 μm to 0.9 μm.

  Further, the thickness of the internal electrode is configured to be in the range of 0.6 μm to 0.8 μm.

  Furthermore, the multilayer ceramic capacitor of this embodiment is configured such that the number of layers of the internal electrode 2 is 400 or less.

  In addition, the aspect of the internal electrode in the present invention, that is, when viewed from the first or second end face 21a, 21b side, and when viewed from the first or second side face 31a, 31b (FIG. 2) side Even in the case, a mode in which the crest 41 and the trough 42 are arranged in a curved state such that the crests 41 and the troughs 42 are repeated is, for example, that the surface defined by the thickness direction and the width direction of the multilayer ceramic capacitor is laminated. It can confirm by grind | polishing to the center part of the length direction of a ceramic capacitor, and observing by SEM.

  Further, the surface defined by the thickness direction and the length direction can be confirmed by polishing to the center in the width direction of the multilayer ceramic capacitor and observing with a SEM. Of the plurality of mountains, the distance between each mountain is preferably constant, but it is not necessarily constant. However, it is preferable that the distance between at least two peaks is in the range of 100 to 150 μm. In addition, it is not always necessary that all the internal electrodes are in a curved state, and there may be relatively many peaks in the central portion of the internal electrodes.

  With this configuration, the crest 41 of the internal electrode 2 and the valley 42 of the adjacent dielectric layer 1 are joined, and the trough 42 of the internal electrode 2 and the crest 41 of the adjacent dielectric layer 1 are joined. Thus, the internal electrode 2 and the dielectric layer 1 are reliably engaged. As a result, it is possible to suppress or prevent the occurrence of delamination between the internal electrode 2 and the dielectric layer 1, and to obtain a highly reliable multilayer ceramic capacitor 50.

In this embodiment, as the multilayer ceramic capacitor 50,
(A) Multi-layer ceramic capacitor having dimensions including an external electrode: length (L): 1.0 mm, width (W): 0.5 mm, height (T): 0.5 mm;
(B) Multi-layer ceramic capacitors having dimensions including the external electrode, the length (L): 0.6 mm, the width (W): 0.3 mm, and the height (T): 0.3 mm;
(C) A monolithic ceramic capacitor having dimensions including the external electrode of length (L): 0.4 mm, width (W): 0.2 mm, and height (T): 0.2 mm was produced.

  However, the present invention is not limited to the monolithic ceramic capacitor having the dimensions as described above, and can be applied to monolithic ceramic capacitors having different dimensions.

Next, a method for manufacturing the multilayer ceramic capacitor 50 will be described.
First, a ceramic raw material slurry in which a binder and a solvent are mixed and dispersed in a dielectric ceramic powder mainly composed of BaTiO ₃ or CaZrO ₃ is thinly stretched on a resin film such as a PET film and formed into a sheet shape. A ceramic green sheet is prepared.

  Then, a conductive paste is printed on the ceramic green sheet using a method such as screen printing or gravure printing to form an internal electrode pattern.

  Next, a predetermined number of ceramic green sheets on which internal electrode patterns are formed and ceramic green sheets on which internal electrode patterns are not formed (ceramic green sheets for outer layers) are stacked in a predetermined order.

  As shown in FIG. 3, when the internal electrode 2 is viewed from the first or second end face 21a, 21b side, or from the first or second side face 31a, 31b (FIG. 2) side, Even in the case, in order to realize a curved structure in which the peaks 41 and the valleys 42 repeat, for example, in the step of laminating the ceramic green sheets, as a suction head for sucking and holding the ceramic green sheets, peaks and valleys are formed on the suction surface. It is possible to apply a method of using a suction head having a curved shape that repeats the above and laminating the ceramic green sheets by sequentially holding the ceramic green sheets with the suction head.

  However, the method for providing the internal electrode 2 with a curved structure in which the peaks 41 and the valleys 42 are repeated is not limited to the method described above.

  And the obtained laminated block is pressed and each ceramic green sheet is crimped | bonded. In pressing the laminated block, for example, the pressure-bonding block is sandwiched between resin films and pressed by a method such as isostatic pressing.

  Thereafter, the pressed laminated pressure-bonded body is divided into rectangular parallelepiped-shaped chips (pieces) using a method such as pressing and cutting, and barrel polishing is performed.

  The barrel-polished chip (the piece that becomes the ceramic body 10 (FIG. 1) after firing) is heated to a predetermined temperature to remove the binder, and then fired at, for example, 900 to 1000 ° C. to obtain a rectangular parallelepiped. A shaped ceramic body is obtained.

  Then, the other end face side of the ceramic body is held, and one end face of the ceramic body is immersed in a conductive paste layer formed by applying a conductive paste containing Cu powder or Ni powder on the surface plate. Thus, the conductive paste is applied to one end surface of the ceramic body and dried.

  Next, a conductive paste is applied and dried on the other end face of the ceramic body in the same manner.

  Then, a sintered metal layer is formed by baking the conductive paste at one end and the other end of the ceramic body applied as described above.

Thereafter, Ni plating and Sn plating are performed in this order on the sintered metal layer to form a Ni plating layer and a Sn plating layer.
Thereby, the multilayer ceramic capacitor 50 according to the embodiment of the present invention having the structure as shown in FIGS.

<Test>
In order to confirm the effect of the present invention, the dimensions including the external electrode are a multilayer ceramic capacitor having a length (L): 0.6 mm, a width (W): 0.3 mm, and a height (T): 0.3 mm. The internal electrode has a curved structure with peaks and valleys as described above, and the intervals P (FIG. 3) between the peaks and the peaks are different in the range of 50 μm to 200 μm. 6 multilayer ceramic capacitors (samples) were produced.
In addition, the distance H (FIG. 3) from the top of the peak 41 to the bottom of the valley 42 in the internal electrode was set to 1 to 10 μm.

  The pitch P between the peaks (FIG. 3) is determined by, for example, polishing the surface defined by the thickness direction and the width direction of the multilayer ceramic capacitor up to the center in the length direction of the multilayer ceramic capacitor and observing with a SEM. Examined.

  In addition, as a comparative sample, a multilayer ceramic capacitor having an internal electrode not provided with peaks and valleys was produced.

  And about each sample produced as mentioned above, the capacity | capacitance increase rate, the withstand voltage fall rate, and the peeling strength of the internal electrode were investigated. In addition, the number of samples was 20 for each sample.

(A) Capacity increase rate Investigate the size of the capacity acquired in the samples (multilayer ceramic capacitors) of sample numbers 1 to 6 and the multilayer ceramic capacitor (comparative sample) provided with internal electrodes not provided with peaks and valleys, The ratio (volume increase rate) (%) ((A / B) × 100) of the volume size A acquired in the samples of sample numbers 1 to 6 to the volume size B acquired in the comparative sample is obtained. It was.
In addition, the capacity | capacitance of each sample was calculated | required with the capacity | capacitance measuring device.

(B) Decrease rate of withstand voltage (ratio of withstand voltage value of samples Nos. 1 to 6 to withstand voltage value of comparative sample)
The withstand voltage values of the samples Nos. 1 to 6 and the multilayer ceramic capacitor (comparative sample) provided with the internal electrodes without the peaks and valleys were obtained, and the withstand voltage values A of the Nos. 1 to 6 samples were compared. The ratio of the sample to the withstand voltage value D (decrease ratio of withstand voltage) (%) ((C / D) × 100) was determined.
In addition, the withstand voltage value of each sample was obtained by changing the voltage and applying the voltage when the insulation resistance value fell below the specified value as the withstand voltage.

(C) Peel strength of internal electrode of each sample The peel strength of the internal electrode of each sample was determined by a surface cutting test.
The results are shown in Table 1.

  Sample numbers 1, 2 and 6 with a sample number marked with * in Table 1 are samples in which the interval between the peaks is not within the scope of the present invention, and other samples (sample numbers 3, 4 and 5). Sample) is a sample having the requirements of the present invention.

  In the case of samples Nos. 1 and 2 where the distance between the peaks is less than 100 μm, it was confirmed that the withstand voltage reduction rate was large and the required withstand voltage performance could not be satisfied.

  Further, in the case of the sample No. 6 in which the distance between the peaks was 200 μm, it was confirmed that the peel strength of the internal electrical strength was lowered, which was not preferable.

  On the other hand, it was confirmed that the samples Nos. 3, 4 and 5 having a crest-to-crest interval of 100 to 150 μm had good capacity and withstand voltage performance and sufficiently high peel strength of the internal electrodes. .

  From the above results, it can be seen that according to the present invention, it is possible to provide a highly reliable multilayer ceramic capacitor that can suppress peeling between the internal electrode and the dielectric layer and has sufficient withstand voltage performance.

  In addition, this invention is not limited to the said embodiment, A various application and deformation | transformation are possible within the scope of the invention.

DESCRIPTION OF SYMBOLS 1 Dielectric layer 1a Outermost dielectric layer 2 (2a, 2b) Internal electrode 5 (5a, 5b) External electrode 6 (6a, 6b) Auxiliary electrode 10 Ceramic body 11a First main surface 11b ceramic body 11b Ceramic Second main surface 12 of element body 12 (12a, 12b) Sintered metal layer 21a First end surface of ceramic element body 21b Second end surface of ceramic element body 31a First side surface 31b of ceramic element body 31b Second side surface 32 (32a, 32b) Plating layer 33 (33a, 33b) Ni plating layer 34 (34a, 34b) Sn plating layer 41 (41a) Mountain (one mountain)
41 (41b) Mountain adjacent to one mountain
50 Multilayer Ceramic Capacitor H Distance from the top of the mountain to the bottom of the valley P Distance between the mountain and the mountain L Length of the multilayer ceramic capacitor T Height of the multilayer ceramic capacitor W Width of the multilayer ceramic capacitor

Claims (4)

A ceramic body comprising a dielectric layer made of a dielectric ceramic, and a plurality of internal electrodes stacked via the dielectric layer and positioned at a plurality of interfaces between the dielectric layers, A second main surface opposite to the first main surface, a first end surface orthogonal to the first main surface, a second end surface opposite to the first end surface, and the first The dielectric has a rectangular parallelepiped shape including a first side surface orthogonal to an end surface and a second side surface facing the first side surface, and a direction from the first main surface toward the second main surface is the dielectric. A ceramic body in which the layers and the internal electrodes are stacked and the plurality of internal electrodes are alternately drawn to the first end face and the second end face;
A multilayer ceramic capacitor comprising a pair of external electrodes disposed on the ceramic body so as to be electrically connected to the internal electrodes drawn out to the first end surface and the second end surface;
The internal electrode is in a curved state in which peaks and valleys repeat in both cases when viewed from the first or second end surface side and when viewed from the first or second side surface side. A multilayer ceramic capacitor, wherein the multilayer ceramic capacitor is disposed between the dielectric layers, and a distance between one mountain and the mountain adjacent to the one mountain is in a range of 100 to 150 μm.   The multilayer ceramic capacitor according to claim 1, wherein a distance between the adjacent internal electrodes is in a range of 0.7 μm to 0.9 μm.   3. The multilayer ceramic capacitor according to claim 1, wherein a thickness of the internal electrode is in a range of 0.6 μm to 0.8 μm.   The multilayer ceramic capacitor according to claim 1, wherein the number of layers of the internal electrodes is 400 or less.

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