JP2015028824A - Memory chip test circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a test circuit capable of shortening test time and specifying a circuit generating a failure.SOLUTION: A memory chip test circuit includes: a determination circuit for outputting a first determination signal expressing whether an internal circuit is normally operated or not and a second determination signal expressing whether read data coincide with expected value data or not; a test result signal generation circuit for switching a change detection signal of the second determination signal and a memory clock in accordance with a change detection signal of the first determination signal and outputting a first test result signal; a failure separation circuit which outputs a switching signal expressing whether both of a first case where write data before and after passing a mode switching circuit coincide with each other and a second case where the memory clock is normally operated exist or not, and when at least one of the first case and the second case does not exist, outputs error data which is a fixed value; and a test result output circuit for switching the first test result signal and the error data in accordance with the switching signal and outputting a second test result signal.

Description

  The present invention relates to a memory chip test for testing a function of a memory chip in a semiconductor integrated circuit having a SiP (system in package) configuration in which a memory chip and a logic chip are housed in one package to constitute a predetermined system. It relates to the circuit.

  There is provided a semiconductor integrated circuit having a SiP configuration in which a memory chip and a logic chip that executes a predetermined function such as image processing using the data stored in the memory chip are housed in one package to constitute a predetermined system. It's being used.

  Hereinafter, an example of a conventional semiconductor integrated circuit having a SiP configuration will be described.

  FIG. 10 is a block diagram showing a configuration of a conventional semiconductor integrated circuit 110 having a SiP configuration. A semiconductor integrated circuit 110 shown in the figure is a schematic diagram of the semiconductor integrated circuit 110 described in FIG. 2 of Patent Document 1, and a memory chip 112 and a logic chip 114 are housed in one package 116 to constitute a predetermined system. doing.

The logic chip 114 includes a logic circuit 118 that performs a predetermined function, a memory chip test circuit 120 that performs an operation test of the memory chip 112, an access signal from the logic circuit 118, and a test access signal from the memory chip test circuit 120. And a selector / input / output circuit 122 that switches between the two.
A select signal SEL is output from the memory chip test circuit 120 and input to the selector / input / output circuit 122. In response to the select signal SEL, the selector / input / output circuit 122 connects the access signal from the logic circuit 118 and each corresponding signal of the memory chip 112 during normal operation, and during the memory chip test, the memory chip test circuit 120. Are switched so as to connect the test access signals from the memory and the corresponding signals of the memory chip 112.

Next, FIG. 11 is a block diagram showing a configuration of the memory chip test circuit 120 shown in FIG. A memory chip test circuit 120 shown in the figure is a schematic diagram of the one described in FIG. 5 of Patent Document 1, and includes a memory chip control circuit 124 that generates a test access signal, expected value data EXV, and the like, and a memory chip 112. Test data determination circuit 132 having a determination circuit 126 for determining whether or not the read data from and the expected value EXV match, and a flip-flop (FF) 128 and an OR circuit 130 for holding the determination result ERROR in the case of mismatch And.
The memory chip test circuit 120 further sets an initialization circuit 134 for initializing the memory chip, a self-test circuit 136 for checking the functions of the memory chip control circuit 124 and the test data determination circuit 132, and a test mode. And a test mode setting circuit 138.

  In the memory chip test circuit 120, the memory chip 112 is initialized by the initialization circuit 134 at the time of the memory chip test, and then the function check of the internal circuit of the memory chip test circuit 120 is performed by the self test circuit 136. . Thereafter, when the test mode setting circuit 138 sets the test mode, the memory chip control circuit 124 tests the memory chip 112 according to the test mode, and the test data determination circuit 132 outputs the test result signal. It is held and output to the outside.

As described above, in the semiconductor integrated circuit 110 of Patent Document 1, when the memory chip test is performed by the memory chip test circuit 120, the initialization of the memory chip 112, the self test of the memory chip test circuit 120, and the test of the memory chip 112 are performed. Performed sequentially in order. Therefore, there is a problem that the test time becomes long and the test cost increases.
Further, in the memory chip test circuit 120 of Patent Document 1, only a determination result of whether or not a defective bit exists in the memory chip 112 can be known from the test result signal. Therefore, it is very difficult to identify which of the internal circuits of the memory chip 112, the selector / input / output circuit 122, and the memory chip test circuit 120 is defective. .

  As prior art documents relevant to the present invention, there are Patent Documents 2 to 4 in addition to Patent Document 1.

JP 2003-77296 A JP-A-11-260096 JP 11-260098 A JP 2008-102785 A

  An object of the present invention is to provide a memory chip test circuit that can solve the problems of the prior art, shorten the test time, and further identify a circuit in which a failure occurs.

In order to achieve the above object, the present invention provides a semiconductor integrated circuit in which a memory chip and a logic chip for controlling the operation of the memory chip are housed in one package to constitute a predetermined system. A memory chip test circuit comprising:
A memory chip control circuit for generating first write data, a control signal, and expected value data for read data from the memory chip for controlling the operation of the memory chip;
Based on the first determination signal indicating whether or not the memory chip control circuit and its own internal circuit are operating normally, the read data and the expected value data are identical. A determination circuit that outputs a second determination signal indicating whether or not
As the first test result signal, when the internal circuit is operating normally according to the change detection signal of the first determination signal, the change detection signal of the second determination signal is output, A test result signal generation circuit that outputs a memory read clock or a memory write clock when the circuit is not operating normally;
The first write data matches the second write data input to the memory chip after the first write data passes through a mode switching circuit that switches between a normal operation and a test operation. In the first case, and at least one of the first and second cases, a switching signal indicating whether or not the memory read clock and the memory write clock are operating normally A fault isolation circuit that outputs error data that is a fixed value when there is not,
As the second test result signal, the first test result signal is output in the first case and the second case according to the switching signal, and at least one of the first and second cases. The present invention provides a memory chip test circuit comprising a test result output circuit for outputting the error data when not one of them.

Here, the determination circuit includes:
A frequency dividing circuit for generating a divided clock obtained by dividing the memory read clock by two;
A read data inversion circuit that switches and outputs the read data and the inverted data of the read data for each cycle of the memory read clock according to the divided clock;
A read data comparison circuit that compares the output signal of the read data inversion circuit with the expected value data and outputs the comparison result as the first determination signal;
And a pulse width detection circuit that detects that the pulse width of the first determination signal is longer than one cycle of the memory read clock and outputs the detection result as the second determination signal. .

The test result signal generation circuit includes:
A detection circuit for a first determination signal that detects whether or not the first determination signal changes and outputs a change detection signal of the first determination signal as a detection result;
A second determination signal detection circuit that detects whether or not the second determination signal changes, and outputs a change detection signal of the second determination signal as a detection result;
A first selector for switching and outputting the memory read clock or the memory write clock and the change detection signal of the second determination signal according to the change detection signal of the first determination signal; preferable.

In addition, the fault isolation circuit is
A write data comparison circuit that compares the first write data and the second write data and outputs a write data comparison signal that is the comparison result;
A clock detection circuit that detects whether or not the memory write clock and the memory read clock are operating normally, and outputs a clock detection signal that is a detection result;
In response to the write data comparison signal, a first fixed value is output when the first and second write data do not match, and the read data is output when the first and second write data match. A second selector to output;
In response to the clock detection signal, when at least one of the memory write clock and the memory read clock is defective, a second fixed value is output, and the memory write clock and the memory read clock operate normally. A third selector that outputs an output signal of the second selector when
A logic circuit that takes the logic of the write data comparison signal and the clock detection signal and outputs it as the switching signal;
A parallel-serial conversion circuit that performs parallel-serial conversion on the output signal of the third selector and outputs the error data is preferably provided.

Further, the test result output circuit includes:
In response to the switching signal, the error data is output when the first and second write data do not match, and when at least one of the memory write clock and the memory read clock is defective, It is preferable to include a fourth selector that outputs the first test result signal when the first and second write data match and the memory write clock and the memory read clock are operating normally. .

According to the present invention, after the initialization, a test (self test) of the internal circuit of the memory chip test circuit, the mode switching circuit, etc. can be performed simultaneously with the test of the memory chip. Therefore, the test time can be shortened compared to the conventional case, and the test cost can be reduced.
In the present invention, when a problem occurs, the approximate location where the problem occurs can be identified based on the second test result signal. Thereby, the debugging time at the time of malfunction occurrence can be shortened, and the debugging efficiency can be improved.

1 is a block diagram of an embodiment showing a configuration of a semiconductor integrated circuit 10 on which a memory chip test circuit 18 of the present invention is mounted. FIG. 2 is a circuit diagram illustrating a configuration of a determination circuit 28 illustrated in FIG. 1. 3 is a timing chart showing the operation of the determination circuit 28 during normal operation. 6 is a timing chart illustrating the operation of the determination circuit when read data does not match. 4 is a timing chart showing the operation of the determination circuit when one of the memory chip control circuit and the internal circuit of the determination circuit is not operating normally. FIG. 2 is a circuit diagram illustrating a configuration of a test result signal generation circuit 30 illustrated in FIG. 1. FIG. 2 is a circuit diagram illustrating a configuration of a defect isolation circuit 32 illustrated in FIG. 1. FIG. 2 is a circuit diagram illustrating a configuration of a test result output circuit 34 illustrated in FIG. 1. It is a conceptual diagram showing the difference in the processing flow of the conventional memory chip test circuit 120 and the memory chip test circuit 18 of the present invention. It is a block diagram showing the structure of the semiconductor integrated circuit 110 of the conventional SiP structure. FIG. 11 is a block diagram illustrating a configuration of a memory chip test circuit 120 illustrated in FIG. 10.

  Hereinafter, a memory chip test circuit of the present invention will be described in detail based on a preferred embodiment shown in the accompanying drawings.

FIG. 1 is a block diagram of an embodiment showing a configuration of a semiconductor integrated circuit 10 on which a memory chip test circuit 18 of the present invention is mounted. A semiconductor integrated circuit 10 shown in FIG. 1 has a SiP configuration in which a memory chip 12 and a logic chip 14 are housed in one package 16 to constitute a predetermined system.
In the package 16, each signal (control signal, write data, read data) of the logic chip 14 is connected to each signal of the corresponding memory chip 12.

  The memory chip 12 is a semiconductor memory having various configurations such as DRAM (Dynamic RAM (Random Access Memory)), SRAM (Static RAM), PRAM (Programmable RAM), etc., which are made into one chip.

The logic chip 14 is a one-chip logic circuit that performs a predetermined function including a function of controlling the operation of the memory chip 12 (writing data into the memory chip 12 and reading data from the memory chip 12). It is.
The logic chip 14 includes an internal circuit (not shown) including a control circuit that controls the operation of the memory chip 12 during a normal operation, a memory chip test circuit 18 that tests the memory chip 12 during a test operation, and a memory chip test. A mode switching circuit 20 that switches between a normal operation and a test operation according to a mode switching signal (not shown) output from the circuit 18 is provided.

In the semiconductor integrated circuit 10, during normal operation, the mode switching circuit 20 performs switching so that each signal of the internal circuit of the logic chip 14 and each corresponding signal of the memory chip 12 are connected according to the mode switching signal. . Thereby, the operation of the memory chip 12 is controlled by the internal circuit of the logic chip 14.
On the other hand, during the test operation, the mode switching circuit 20 performs switching so that each signal of the memory chip test circuit 18 and each corresponding signal of the memory chip 12 are connected according to the mode switching signal. Thereby, the operation of the memory chip 12 is controlled by the memory chip test circuit 18.

  Next, the memory chip test circuit 18 will be described.

  During the test operation, the memory chip test circuit 18 generates various test signals for testing the memory chip 12, the internal circuit of the memory chip test circuit 18, the mode switching circuit 20 of the logic chip 14, and the like. And output the test result signal. The memory chip test circuit 18 includes an initialization circuit 22, a test mode setting circuit 24, a memory chip control circuit 26, a determination circuit 28, a test result signal generation circuit 30, a defect isolation circuit 32, and a test result output circuit. 34.

  The initialization circuit 22 initializes the memory chip 12 and the internal circuit of the memory chip test circuit 18 in accordance with a signal S1 input from the outside of the memory chip test circuit 18.

The test mode setting circuit 24 controls the write data W_Data and other control signals such as memory address, data write signal, and data read signal during the test operation according to the signal S2 input from the outside of the memory chip test circuit 18. The test mode is determined to determine how to control etc and expected value data.
Various test modes are conventionally used, but the test mode setting circuit 24 can adopt various test modes including a conventionally known test mode.

  The signals S1 and S2 may be input, for example, from the internal circuit of the logic chip 14 to the memory chip test circuit 18, or may be input directly from the external pin of the package 16 to the memory chip test circuit 18.

  The memory chip control circuit 26 outputs write data W_Data and a control signal etc for controlling the operation of the memory chip 12 and expected value data for read data from the memory chip 12 at the time of initialization and test operation. Is to be generated.

  During the test operation, the initialization circuit 22 first initializes the memory chip 12 and the internal circuit of the memory chip test circuit 18 in accordance with the signal S1.

The memory chip control circuit 26 generates write data W_Data and a control signal etc according to the initialization signal input from the initialization circuit 22. In response to these signals, the memory chip 12 is initialized.
Although omitted in FIG. 1 to avoid complication, the determination circuit 28, the test result signal generation circuit 30, and the fault isolation circuit 32 are also initialized by the initialization signal.
Further, the mode switching circuit 20 is switched so as to connect each signal of the memory chip test circuit 18 and each corresponding signal of the memory chip 12 in accordance with the initialization signal.

Subsequently, the test mode setting circuit 24 sets the test mode in accordance with the signal S2. The memory chip 12 is tested by the memory chip test circuit 18 in accordance with the setting of the test mode.
In addition to the write data W_Data and the control signal etc supplied to the memory chip 12 during the test operation, the memory chip control circuit 26 generates expected value data for comparison with the read data from the memory chip 12. Thereby, the test of the memory chip 12 is performed, and the test (self test) of the memory chip test circuit 18, the internal circuit of the logic chip 14, the mode switching circuit 20 of the logic chip 14 and the like is simultaneously performed.

  The determination circuit 28 inverts the read data from the memory chip 12 (in this embodiment, the read data R_Data that has passed through the defect isolation circuit 32) every cycle of the memory read clock and the expected value data ( (The same data as the write data W_Data generated by the memory chip control circuit 26), and as a result of the comparison, intentionally and mismatched states are intentionally generated alternately for each cycle of the memory read clock. Thus, a determination signal A (first determination signal) indicating whether the internal circuits of the memory chip control circuit 26 and the determination circuit 28 (self) are operating normally is generated, and based on this determination signal A A determination signal B (second determination signal) indicating whether the read data and the expected value data match. It is intended to be generated.

The determination signal A toggles L (matched state) and H (mismatched state) for each cycle of the memory read clock during normal operation when the internal circuits of the memory chip control circuit 26 and the determination circuit 28 are operating normally. The signal is fixed to L or fixed to H when the internal circuit of the memory chip control circuit 26 and the determination circuit 28 is not operating normally.
In the determination signal B, when the read data from the memory chip 12 and the write data to the memory chip 12 do not match, in other words, the determination signal A toggles L and H for each cycle of the memory read clock. This signal is used to detect that the pulse width of the determination signal A is longer than one cycle of the memory read clock during an abnormal operation that is not operating normally.

The test result signal generation circuit 30 determines whether the internal circuit of the memory chip control circuit 26 and the determination circuit 28 is operating normally according to the change detection signal of the determination signal A as the first test result signal C. Accordingly, the memory read clock or memory write clock generated by the internal circuit of the logic chip 14 and the change detection signal of the determination signal B are switched and output.
The test result signal generation circuit 30 outputs a change detection signal of the determination signal B as the first test result signal C when the internal circuits of the memory chip control circuit 26 and the determination circuit 28 are operating normally. When the internal circuits of the control circuit 26 and the determination circuit 28 are not operating normally, a memory read clock or a memory write clock is output.

  The defect isolation circuit 32 includes write data W_Data (first write data) generated by the memory chip control circuit 26 and write input to the memory chip 12 after the write data W_Data has passed through the mode switching circuit 20. Data WB_Data (second write data) is compared to detect whether or not they match, and whether or not both the memory write clock and the memory read clock are operating normally (stopped) Or not). The write data W_Data and the write data WB_Data to the memory chip 12 are logically equal data. From the fault isolation circuit 32, a switching signal SW, read data R_Data, and error data Er_Data are output.

The switching signal SW is a signal indicating whether or not the first case where the write data W_Data and WB_Data match and the second case where the memory read clock and the memory write clock are operating normally.
The read data R_Data is data after the read data from the memory chip 12 has passed through the defect isolation circuit 32. In the first case and the second case, the read data from the memory chip 12 and the read data R_Data are logically equal data.
The error data Er_Data is a fixed value output when it is not at least one of the first and second cases (in the case of this embodiment, one of the fixed values A and B is converted into serial data) Is).

  As shown in FIG. 1, the fault isolation circuit 32 is further input to the memory chip 12 after the control signal etc generated by the memory chip control circuit 26 and the control signal etc have passed through the mode switching circuit 20. The control signal etc may be compared to detect whether or not they match.

The test result output circuit 34 switches and outputs the first test result signal C and the error data Er_Data according to the switching signal SW as the second test result signal.
The test result output circuit 34 outputs the first test result signal C as the second test result signal when the switching signal SW is H, that is, in the first case and the second case. On the other hand, the test result output circuit 34 outputs the error data Er_Data when the switching signal SW is L, that is, when it is not at least one of the first and second cases.

  The second test result signal may be output from the memory chip test circuit 18 to the internal circuit of the logic chip 14 for processing, or may be processed from the memory chip test circuit 18 via an external pin of the package 16, for example. May be output directly to and monitored externally.

  Next, the determination circuit 28 will be described.

  FIG. 2 is a circuit diagram showing a configuration of determination circuit 28 shown in FIG. The determination circuit 28 shown in the figure includes a frequency dividing circuit 36, a read data inversion circuit 38, a read data comparison circuit 42, and a pulse width detection circuit 44.

The frequency dividing circuit 36 generates a frequency divided clock obtained by dividing the memory read clock by 2, and includes an inverter 46 and a flip-flop (FF) 48.
An initialization signal is input to the reset terminal RB of the FF 48, and a memory read clock is input to the clock input terminal. A frequency-divided clock is output from the data output terminal Q of the FF 48, and the frequency-divided clock is inverted by the inverter 46 and input to the data input terminal D of the FF 48.

In the frequency divider 36, when the initialization signal becomes L, the FF 48 is initialized and the frequency-divided clock becomes L. In response to this, the output signal of the inverter 46 (inverted signal of the divided clock) becomes H.
After the initialization signal becomes H, the output signal H of the inverter 46 is held in the FF 48 in synchronization with the rising edge of the memory read clock, and the divided clock becomes H. That is, the divided clock is inverted from L to H. Thereafter, the frequency-divided clock repeats inversion of H and L in synchronization with the memory read clock. That is, a signal obtained by dividing the memory read clock by two is generated as the divided clock.

The read data inverting circuit 38 switches and outputs the read data R_Data from the memory chip 12 and its inverted data for each cycle of the memory read clock according to the divided clocks L and H. An inverter 50 and a selector 52 are provided.
Read data R_Data is input to the inverter 50. The read data R_Data is input to the input terminal A0 of the selector 52, the output signal of the inverter 50 is input to the input terminal A1, and the divided clock is input to the selection input terminal.

In the read data inverting circuit 38, when the divided clock becomes L, the selector 52 selects the input terminal A0, and the read data R_Data is output from the selector 52 as it is. On the other hand, when the divided clock becomes H, the input terminal A1 is selected by the selector 52, and the output signal of the inverter 50, that is, the inverted data of the read data R_Data is output from the selector 52.
Thereafter, as the output signal of the selector 52, the read data R_Data and its inverted data are alternately output according to the divided clocks L and H, that is, for each cycle of the memory read clock.

The read data comparison circuit 42 compares the output signal of the read data inversion circuit 38 with the expected value data, and outputs the comparison result as a determination signal A. Circuit 60.
An initialization signal is input to the reset terminal RB of the FFs 54 and 56, and a memory read clock is input to the clock input terminal. The output signal of the read data inversion circuit 38 and the expected value data are input to the data input terminals D of the FFs 54 and 56, respectively. The EXOR circuit 58 receives the output signals of the FFs 54 and 56, that is, the output signal of the read data inversion circuit 38 and the expected value data synchronized with the rising edge of the memory read clock. The output signal of the EXOR circuit 58 is input to the OR circuit 60, and the determination signal A is output from the OR circuit 60.

In the read data comparison circuit 42, when the initialization signal becomes L, the FFs 54 and 56 are initialized, and the output signals of the FFs 54 and 56 become L.
After the initialization signal becomes H, the output signal of the read data inversion circuit 38 and the expected value data are held in the FFs 54 and 56 in synchronization with the rising edge of the memory read clock, respectively. That is, the output signals of the FFs 54 and 56 are obtained by delaying the output signal of the read data inversion circuit 38 and the expected value data by one cycle of the memory read clock.
When the output signal of the read data inversion circuit 38 output from the FFs 54 and 56 matches the expected value data, L is output from the EXOR circuit 58, and H is output from the EXOR circuit 58 if the two do not match. The That is, when the read data R_Data and the expected value data match, the output signal of the EXOR circuit 58 intentionally generates a match state and a mismatch state every cycle of the memory read clock. A signal in which L and H are inverted is repeated.
As described above, by comparing the inverted data obtained by inverting the read data R_Data with the expected value data for each cycle of the memory read clock, both the output in the case of coincidence and the output in the case of non-coincidence are confirmed. Therefore, based on the determination signal A, it is possible to detect whether or not a failure has occurred in the internal circuit of the memory chip test circuit 18 that generates expected value data and the internal circuit of the determination circuit 28. .
In the example of FIG. 2, the output signal of the EXOR circuit 58 further passes through the OR circuit 60 and is output from the determination circuit 28 as the determination signal A.

The pulse width detection circuit 44 determines that the H pulse width of the determination signal A is longer than the time of one cycle of the memory read clock (in this embodiment, the time is two cycles or more), that is, It detects that a mismatch of the read data R_Data has occurred, and outputs the detection result as a determination signal B, and includes an FF 62 and an AND circuit 64.
An initialization signal is input to the reset terminal RB of the FF 62, and a memory read clock is input to the clock input terminal. The determination signal A is input to the data input terminal D of the FF62. The AND circuit 64 receives the determination signal A and the signal output from the data output terminal Q of the FF 62, and the AND circuit 64 outputs the determination signal B.

In the pulse width detection circuit 44, when the initialization signal becomes L, the FF 62 is initialized, and the output signal of the FF 62 becomes L.
After the initialization signal becomes H, the determination signal A is held in the FF 62 in synchronization with the rising edge of the memory read clock. That is, the output signal of the FF 62 is obtained by delaying the determination signal A by the time of one cycle of the memory read clock.
If the H pulse width of the determination signal A is one cycle of the memory read clock, that is, in the normal operation in which the read data R_Data and the expected value data match, L is output from the AND circuit 64. On the other hand, when the H pulse width of the determination signal A becomes longer than the time of one cycle of the memory read clock, that is, in the case of an abnormal operation in which the two do not match, H is output from the AND circuit 64. In the example of FIG. 2, H is output from the AND circuit 64 from the timing when the H pulse width of the determination signal A becomes longer than the time of one cycle of the memory read clock until the determination signal A becomes L. Is done.
The output signal of the AND circuit 64, that is, the output signal of the pulse width detection circuit 44 is output from the determination circuit 28 as the determination signal B.

  Hereinafter, the operation of the determination circuit 28 will be described.

FIG. 3 is a timing chart showing the operation of the determination circuit 28 during normal operation.
As shown in this timing chart, consider a case where read data is read from the memory chip 12 in the order of 1, 2, 3, 4, 5, 6,... In synchronization with the rising edge of the memory read clock.

In the determination circuit 28 shown in FIG. 2, the output signal ((1 ′) in FIG. 2) of the inverter 50 of the read data inversion circuit 38 is the inverted data of the read data 1, 2, 3, 4, 5, 6,. 1, -2, -3, -4, -5, -6,... ("-" Represents inverted data).
The selector 52 of the read data inverting circuit 38 outputs read data when the divided clock is L, and inverted data when the divided clock is H. Therefore, the output signal of the selector 52 ((2 ′) in FIG. 2) is 1, −2, 3, −4, 5, −6,.
Subsequently, the output signal (3 ′ in FIG. 2) of the FF 54 of the read data comparison circuit 42 is delayed from the output signal of the selector 52 by the time of one cycle of the memory read clock to be 1, −2, 3, -4, 5, -6, and so on. Similarly, the output signal of the FF 56 of the read data comparison circuit 42 ((4 ′) in FIG. 2), the expected value data is delayed by the time of one cycle of the memory read clock, and therefore synchronized with the output signal of the FF 54. Then, 1, 2, 3, 4, 5, 6,.
As a result, the determination signal A is L when the output signals of the FFs 54 and 56 ((3 ′) and (4 ′) in FIG. 2) are 1, 1 and H, when −2 and 2, respectively. Inversion of L and H is repeated such that time is L, -4,4 is H, 5,5 is L, -6,6 is H, and so on.

Subsequently, the output signal (5 ′ in FIG. 2) of the FF 62 of the pulse width detection circuit 44 is delayed by one cycle of the memory read clock from the determination signal A, and becomes a signal that repeats inversion of L and H. .
As a result, when the determination signal A is H, the output signal of the FF 62 is L, and when the determination signal A is L, the output signal of the FF 62 is H. Therefore, the determination signal B maintains the L state.
Thus, during normal operation, the determination signal A repeats inversion of L and H, and the inversion signal B maintains the L state.

  Next, FIG. 4 is a timing chart showing the operation of the determination circuit 28 when the read data does not match. The timing chart shown in the drawing represents a case where 3 of the read data is X (fixed value of L or H) in the timing chart shown in FIG.

In this case, in the timing chart at the time of normal operation shown in FIG. 3, the output signal of the inverter 50 of the read data inversion circuit 38 ((1 ′) in FIG. 2) −3, the output signal of the selector 52 ((2 in FIG. 2) 3) and 3 of the output signal of the FF 54 of the read data comparison circuit 42 ((3 ′) in FIG. 2) are all X in the timing chart shown in FIG.
As a result, the determination signal A becomes H when the output signals of the FFs 54 and 56 ((3 ′) and (4 ′) in FIG. 2) are X and 3, and −4 from the start timing of −2 and −2. , 4 until the timing of the end of 4 for the period of 3 cycles of the memory read clock.

The output signal (5 ′ in FIG. 2) of the FF 62 of the pulse width detection circuit 44 is delayed from the determination signal A by the time of one cycle of the memory read clock.
As a result, the determination is made based on the timing when the output signal ((5 ′) in FIG. 2) of the FF 62 becomes H (the timing when the H pulse width of the determination signal A becomes longer than one cycle time of the memory read clock). Until the timing when the signal A becomes L, the determination signal B becomes H.
Thus, when the read data does not match, the H pulse width of the determination signal A becomes longer than the time of one cycle of the memory read clock, and the inverted signal B becomes H accordingly.

Next, FIG. 5 is a timing chart showing the operation of the determination circuit 28 when one of the memory chip control circuit and the internal circuit of the determination circuit 28 is not operating normally.
As shown in this timing chart, when one of the internal circuits of the memory chip control circuit 26 and the determination circuit 28 is not operating normally, the determination signal A is fixed to L or fixed to H.

  Next, the test result signal generation circuit 30 will be described.

  FIG. 6 is a circuit diagram showing the configuration of the test result signal generation circuit 30 shown in FIG. The test result signal generation circuit 30 shown in the figure includes a determination signal A detection circuit 66, a determination signal B detection circuit 68, and a selector 70.

A determination signal A detection circuit (first determination signal detection circuit) 66 detects whether L and H of the determination signal A change, and outputs a change detection signal of the determination signal A as the detection result. It has a FF72.
The initialization signal is input to the reset terminal RB of the FF 72, and the determination signal A is input to the clock input terminal. H is input to the data input terminal D of the FF 72 (power supply is connected), and a change detection signal of the determination signal A is output from the data output terminal Q.

In the determination signal A detection circuit 66, when the initialization signal becomes L, the FF 72 is initialized, and the output signal of the FF 72, that is, the change detection signal of the determination signal A becomes L.
When the determination signal A changes from L to H after the initialization signal becomes H, H input to the data input terminal D is held in the FF 72, and the change detection signal of the determination signal A becomes H. On the other hand, if the determination signal A is fixed to L or fixed to H after the initialization signal becomes H, the change detection signal of the determination signal A remains in the L state after initialization.

A determination signal B detection circuit (second determination signal detection circuit) 68 detects whether or not L and H of the determination signal B change, and outputs a change detection signal of the determination signal B as the detection result. And includes an OR circuit 74 and an FF 76.
A signal output from the data output terminal Q of the FF 76 and the determination signal B are input to the OR circuit 74. An initialization signal is input to the reset terminal RB of the FF 76, and a memory read clock is input to the clock input terminal. The output signal of the OR circuit 74 is input to the data input terminal D of the FF 76, and the change detection signal of the determination signal B is output from the data output terminal Q.

In the detection signal 68 of the determination signal B, when the initialization signal becomes L, the FF 76 is initialized, and the output signal of the FF 76, that is, the change detection signal of the determination signal B becomes L. Since the state after initialization of the determination signal B is L, the output signal of the OR circuit 74 is L.
When the determination signal B changes from L to H after the initialization signal becomes H, the output signal of the OR circuit 74 becomes H. The output signal of the OR circuit 74 is held in the FF 76 in synchronization with the rising edge of the memory read clock, and H is output as the change detection signal of the determination signal B. When the change detection signal of the determination signal B becomes H, since the output signal of the OR circuit 74 is fixed to H by the output signal of the FF 76 even if the determination signal B becomes L thereafter, the change of the determination signal B The detection signal is also fixed to H. On the other hand, if the determination signal B remains L after the initialization signal becomes H, the output signal of the OR circuit 74 remains L and the change detection signal of the determination signal B is also initialized. It will be in the state of L after that.

The selector (first selector) 70 switches and outputs the memory write clock or memory read clock and the change detection signal of the determination signal B in accordance with the change detection signal of the determination signal A.
A memory write clock or a memory read clock is input to the input terminal A0 of the selector 70, a change detection signal of the determination signal B is input to the input terminal A1, and a change detection signal of the determination signal A is input to the selection input terminal. The

  When the change detection signal of the determination signal A is L, that is, when the determination signal A is fixed to L or H, the selector 70 selects the input terminal A0 and the selector 70 outputs a memory write clock or a memory read clock. . On the other hand, when the change detection signal of the determination signal A is H, that is, when the determination signal A changes from L to H, the selector 70 selects the input terminal A1, and the selector 70 outputs the change detection signal of the determination signal B. Is done. The output signal of the selector 70 is output from the test result signal generation circuit 30 as the first test result signal C.

  In the circuit configuration of FIG. 6, since the value of the determination signal B is held (fixed) when a mismatch occurs, only the minimum determination result that the determination signal B has changed from L to H is output. However, the present invention is not limited to the configuration of FIG. 6 and may be configured to hold a lot of other error information.

  Next, the defect isolation circuit 32 will be described.

  FIG. 7 is a circuit diagram showing the configuration of the defect isolation circuit 32 shown in FIG. The defect isolation circuit 32 shown in the figure includes a write data comparison circuit 78, a clock detection circuit 80, selectors 82 and 84, an AND circuit 86, and a parallel-serial conversion circuit 88.

The write data comparison circuit 78 compares the write data W_Data generated by the memory chip control circuit 26 with the write data WB_Data input to the memory chip 12 after the write data W_Data passes through the mode switching circuit 20. A write data comparison signal that is the comparison result is output, and includes FFs 90 and 92, an EXOR circuit 94, an OR circuit 96, and a NOR circuit 98.
An initialization signal is input to the reset terminals RB of the FFs 90 and 92, and a memory read clock is input to the clock input terminals. Write data W_Data and WB_Data are input to the data input terminals D of the FFs 90 and 92, respectively. A signal output from the data output terminal Q of the FFs 90 and 92 is input to the EXOR circuit 94. The output signal of the EXOR circuit 94 passes through the OR circuit 96, and further passes through an internal circuit (not shown), and is then input to the NOR circuit 98 and inverted as a write data comparison signal.

In the write data comparison circuit 78, when the initialization signal becomes L, the FFs 90 and 92 are initialized, and the output signals of the FFs 90 and 92 become L. In response to this, the output signal of the EXOR circuit 94 is L, and the output signal of the OR circuit 96 is also L. The output signal of the NOR circuit becomes H.
After the initialization signal becomes H, the write data W_Data and WB_Data are held in the FFs 90 and 92 in synchronization with the rising edge of the memory read clock, respectively. That is, the output signals of the FFs 90 and 92 are obtained by delaying the write data W_Data and WB_Data by the time of one cycle of the memory read clock. When the write data W_Data and WB_Data output from the FFs 90 and 92 match, L is output from the EXOR circuit 94, and when both do not match, H from the EXOR circuit 94 is output.
In the example of FIG. 7, the output signal of the EXOR circuit 94 further passes through the OR circuit 96, an internal circuit (not shown) and the NOR circuit 98, is inverted, and is output from the write data comparison circuit 78.

The clock detection circuit 80 detects whether or not both the memory write clock and the memory read clock are operating normally, and outputs a clock detection signal that is the detection result. The clock detection circuit 80 and the AND circuit 104.
An initialization signal is input to the reset terminals RB of the FFs 100 and 102, and a memory write clock and a memory read clock are input to the clock input terminals, respectively. H is input to the data input terminal D of the FFs 100 and 102 (connected to the power source). A signal output from the data output terminal Q of the FFs 100 and 102 is input to the AND circuit 104, and a clock detection signal is output from the AND circuit 104.

In the clock detection circuit 80, when the initialization signal becomes L, the FFs 100 and 102 are initialized, and the output signals of the FFs 100 and 102 become L. In response to this, the output signal of the AND circuit 104 becomes L.
When both the memory write clock and the memory read clock change from L to H after the initialization signal becomes H, that is, when both the memory write clock and the memory read clock are operating normally, the FFs 100 and 102 H input to the data input terminal D is held in the FFs 100 and 102, and the output signals of the FFs 100 and 102 become H. In response to this, the output signal of the AND circuit 104 becomes H.
On the other hand, if at least one of the memory write clock and the memory read clock is fixed to L or H after the initialization signal becomes H, that is, if at least one of the memory write clock and the memory read clock is defective, The output signals of the corresponding FFs 100 and 102 remain in the L state after initialization. In response to this, the output signal of the AND circuit 104 also remains in the L state after initialization.

The selector (second selector) 82 switches between a fixed value A (first fixed value) and read data from the memory chip 12 in accordance with a write data comparison signal that is an output signal of the write data comparison circuit 78. Output.
A fixed value A is input to the input terminal A0 of the selector, read data is input to the input terminal A1, and a write data comparison signal is input to the selection input terminal.

  When the write data comparison signal is L, that is, when the write data W_Data and WB_Data do not match, the selector 82 selects the input terminal A0 and the selector 82 outputs the fixed value A. On the other hand, when the write data comparison signal is H, that is, when the write data W_Data and WB_Data match, the selector 82 selects the input terminal A1, and the selector 82 outputs read data.

The selector (third selector) 84 switches between a fixed value B (second fixed value) and an output signal of the selector 82 in accordance with a clock detection signal that is an output signal of the clock detection circuit 80 and outputs it. It is.
A fixed value B is input to the input terminal A0 of the selector 84, an output signal of the selector 82 is input to the input terminal A1, and a clock detection signal is input to the selection input terminal.

  When the clock detection signal is L, that is, when at least one of the memory write clock and the memory read clock is defective, the selector 84 selects the input terminal A0 and the selector 84 outputs the fixed value B. On the other hand, when the clock detection signal is H, that is, when both the memory write clock and the memory read clock are operating normally, the selector 84 selects the input terminal A1, and the selector 84 outputs the output signal of the selector 82. Is done. The output signal of the selector 84 is output from the defect isolation circuit 32 as read data R_Data.

  That is, when the write data comparison signal and the clock detection signal are H, that is, when the write data W_Data and WB_Data match and both the memory write clock and the memory read clock are operating normally, the read data R_Data is Data read from the memory chip 12 is output.

  On the other hand, when at least one of the write data comparison signal and the clock detection signal is L, the selector 84 outputs fixed values A and B. In this case, since the switching signal SW becomes L, the test result output circuit 34 described later outputs error data Er_Data, and a first test result signal generated using the fixed values A and B as the read data R_Data. C is not output.

  The fixed values A and B are parallel data having different predetermined bit lengths. The fixed values A and B are arbitrary.

The AND circuit 86 outputs a logical product of a write data comparison signal that is an output signal of the write data comparison circuit 78 and a clock detection signal that is an output signal of the clock detection circuit 80.
The AND circuit 86 receives a write data comparison signal and a clock detection signal, and the AND circuit 86 outputs a switching signal SW.

  If both the write data comparison signal and the clock detection signal are H, that is, if the write data W_Data and WB_Data match and both the memory write clock and the memory read clock are operating normally, the AND circuit 86 H is output. If at least one of the two is L, that is, if the write data W_Data and WB_Data do not match, and if at least one of the memory write clock and the memory read clock is defective, the AND circuit 86 performs L Is output. The output signal of the AND circuit 86 is output from the defect isolation circuit 32 as the switching signal SW.

  In this embodiment, the AND circuit 86 that takes the logical product of the write data comparison signal and the clock detection signal is used. However, the present invention is not limited to this, and the write is performed according to the polarity of the input / output signal. A logic circuit that takes the logic of the data comparison signal and the clock detection signal can be used.

The parallel-serial conversion circuit 88 performs parallel-serial conversion on the output signal of the selector 84, that is, the fixed value A or the fixed value B, and outputs the result.
The output signal of the selector 84 is input to the parallel-serial conversion circuit. The output signal of the parallel-serial conversion circuit 88 is output from the defect isolation circuit 32 as error data Er_Data.

  Even when the read data R_Data is output from the selector 84, the parallel-serial conversion circuit 88 performs parallel-serial conversion of the read data R_Data, and outputs error data Er_Data. However, in this case, since the switching signal SW becomes H, the test result output circuit 34 described below outputs the first test result signal C and does not output the error data Er_Data.

  Finally, the test result output circuit 34 will be described.

FIG. 8 is a circuit diagram showing the configuration of the test result output circuit 34 shown in FIG. The test result output circuit 34 shown in FIG.
The selector (fourth selector) 106 responds to the switching signal SW, which is the output signal of the fault isolation circuit 32, and also outputs error data Er_Data, which is the output signal of the fault isolation circuit 32, and the output signal of the test result signal generation circuit 30. The first test result signal C is switched and output.
The error data Er_Data is input to the input terminal A0 of the selector 106, the first test result signal C is input to the input terminal A1, and the switching signal SW is input to the selection input terminal.

When the switching signal SW is L, that is, when the write data W_Data and WB_Data do not match, and when at least one of the memory write clock and the memory read clock is defective, the selector 106 sets the input terminal A0. The error data Er_Data, that is, fixed value A or fixed value B serial data is output from the selector 106.
On the other hand, when the switching signal SW is H, that is, when the write data W_Data and WB_Data match and both the memory write clock and the memory read clock are operating normally, the selector 106 selects the input terminal A1, A first test result signal C is output from the selector 106.
The output signal of the selector 106 is output from the test result output circuit 34 as a second test result signal.

  The memory chip test circuit 18 can identify the test result as shown in Table 1 below based on the second test result signal.

As shown in FIG. 9, in the conventional memory chip test circuit 120 shown in FIGS. 10 and 11, initialization, self test, and memory chip test are sequentially performed in this order.
On the other hand, in the memory chip test circuit 18 of the present embodiment, as shown in FIG. 9, after the initialization, when the test of the memory chip 12 is performed, the internal circuit of the memory chip test circuit 18, the logic chip 14 A test (self-test) of the mode switching circuit 20 or the like can be performed. Therefore, in the memory chip test circuit 18, the test time can be shortened compared with the conventional case, and the test cost can be reduced.
In addition, the memory chip test circuit 18 can identify the approximate location where a problem has occurred when a problem occurs. Thereby, the debugging time at the time of malfunction occurrence can be shortened, and the debugging efficiency can be improved.

In the above embodiment, the semiconductor integrated circuit 10 on which one memory chip 12 is mounted has been described as an example. However, the present invention is not limited to this, and a semiconductor integrated circuit on which two or more memory chips 12 are mounted. Is equally applicable.
In the above-described embodiment, the specific circuit configurations of the determination circuit 28, the test result signal generation circuit 30, the failure isolation circuit 32, and the test result output circuit 34 have been described. However, the present invention includes circuits having these configurations. Without being limited thereto, circuits having various configurations that can perform the same function can be employed. Further, the value after initialization of each signal in the memory chip test circuit 18, the signal polarity, and the like may be changed as appropriate.

The present invention is basically as described above.
Although the present invention has been described in detail above, the present invention is not limited to the above-described embodiment, and it is needless to say that various improvements and modifications may be made without departing from the gist of the present invention.

10, 110 Semiconductor integrated circuit 12, 112 Memory chip 14, 114 Logic chip 16, 116 Package 18, 120 Memory chip test circuit 20 Mode switching circuit 22, 134 Initialization circuit 24, 138 Test mode setting circuit 26, 124 Memory chip control Circuit 28, 126 Judgment circuit 30 Test result signal generation circuit 32 Fault isolation circuit 34 Test result output circuit 36 Divider circuit 38 Read data inversion circuit 42 Read data comparison circuit 44 Pulse width detection circuit 46, 50 Inverters 48, 54, 56, 62, 72, 76, 90, 92, 100, 102, 128 Flip-flop (FF)
52, 70, 82, 84, 106 Selector 58, 94 EXOR circuit 60, 74, 96, 130 OR circuit 64, 86, 104 AND circuit 66 Detection circuit for determination signal A 68 Detection circuit for determination signal B 78 Write data comparison circuit 80 clock detection circuit 88 parallel serial conversion circuit 98 NOR circuit 118 logic circuit 122 selector / input / output circuit 132 test data determination circuit 136 self test circuit

Claims (5)

In a semiconductor integrated circuit in which a memory chip and a logic chip for controlling the operation of the memory chip are housed in one package to constitute a predetermined system, the memory chip is a memory chip test circuit included in the logic chip,
A memory chip control circuit for generating first write data, a control signal, and expected value data for read data from the memory chip for controlling the operation of the memory chip;
Based on the first determination signal indicating whether or not the memory chip control circuit and its own internal circuit are operating normally, the read data and the expected value data are identical. A determination circuit that outputs a second determination signal indicating whether or not
As the first test result signal, when the internal circuit is operating normally according to the change detection signal of the first determination signal, the change detection signal of the second determination signal is output, A test result signal generation circuit that outputs a memory read clock or a memory write clock when the circuit is not operating normally;
The first write data matches the second write data input to the memory chip after the first write data passes through a mode switching circuit that switches between a normal operation and a test operation. In the first case, and at least one of the first and second cases, a switching signal indicating whether or not the memory read clock and the memory write clock are operating normally A fault isolation circuit that outputs error data that is a fixed value when there is not,
As the second test result signal, the first test result signal is output in the first case and the second case according to the switching signal, and at least one of the first and second cases. A memory chip test circuit, comprising: a test result output circuit that outputs the error data when not one of them. The determination circuit includes:
A frequency dividing circuit for generating a divided clock obtained by dividing the memory read clock by two;
A read data inversion circuit that switches and outputs the read data and the inverted data of the read data for each cycle of the memory read clock according to the divided clock;
A read data comparison circuit that compares the output signal of the read data inversion circuit with the expected value data and outputs the comparison result as the first determination signal;
2. A pulse width detection circuit that detects that the pulse width of the first determination signal is longer than one cycle of the memory read clock and outputs the detection result as the second determination signal. The memory chip test circuit according to 1. The test result signal generation circuit includes:
A detection circuit for a first determination signal that detects whether or not the first determination signal changes and outputs a change detection signal of the first determination signal as a detection result;
A second determination signal detection circuit that detects whether or not the second determination signal changes, and outputs a change detection signal of the second determination signal as a detection result;
A first selector that switches and outputs the memory read clock or the memory write clock and a change detection signal of the second determination signal according to a change detection signal of the first determination signal. 3. The memory chip test circuit according to 1 or 2. The defect isolation circuit is:
A write data comparison circuit that compares the first write data and the second write data and outputs a write data comparison signal that is the comparison result;
A clock detection circuit that detects whether or not the memory write clock and the memory read clock are operating normally, and outputs a clock detection signal that is a detection result;
In response to the write data comparison signal, a first fixed value is output when the first and second write data do not match, and the read data is output when the first and second write data match. A second selector to output;
In response to the clock detection signal, when at least one of the memory write clock and the memory read clock is defective, a second fixed value is output, and the memory write clock and the memory read clock operate normally. A third selector that outputs an output signal of the second selector when
A logic circuit that takes the logic of the write data comparison signal and the clock detection signal and outputs it as the switching signal;
4. The memory chip test circuit according to claim 1, further comprising: a parallel-serial conversion circuit that performs parallel-serial conversion on an output signal of the third selector and outputs the error data as the error data. 5. The test result output circuit includes:
In response to the switching signal, the error data is output when the first and second write data do not match, and when at least one of the memory write clock and the memory read clock is defective, 2. A fourth selector that outputs the first test result signal when the first and second write data match and the memory write clock and the memory read clock are operating normally. The memory chip test circuit of any one of -4.