JP2015004841A - Pixel circuit and driving method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce gradation data variation in data programming while attaining high definition by reducing a holding capacity size.SOLUTION: A driving method of a pixel circuit which comprises a light-emitting element including a capacitive component, a first transistor, a second transistor, a holding capacitor and a third transistor and in which the capacitive component and the holding capacitor are capacitively coupled, includes: an initializing step pf supplying a first voltage and writing a voltage greater than a threshold voltage of the first transistor into the holding capacitor; a compensating step of supplying a gradation data voltage and writing a threshold voltage into the holding capacitor via the first and second transistors in an ON state; a data program step of supplying a second voltage and, after turning off the second transistor, writing a voltage of first data determined by the gradation data voltage and the threshold voltage into the holding capacitor; and a light-emitting step of turning on the second transistor after turning off the third transistor, and causing the first transistor to emit the light-emitting element on the basis of the first data.

Description

  The present invention relates to a pixel circuit in an electro-optical device and a driving method thereof.

  2. Description of the Related Art In recent years, organic EL display devices using self-luminous elements such as a liquid crystal display (LCD) and an organic EL display are widely used as a display device replacing a CRT display (Cathode Ray Tube display). In particular, organic EL displays are attracting much attention as low power consumption and thin displays.

  The light emission luminance of the organic EL element changes depending on the current flowing through the element. However, depending on the characteristics variation of the thin film transistor (TFT) element used in the active matrix panel (TFT threshold voltage (VTH) variation, mobility (μ) variation), However, the current flowing through the organic EL element is different, resulting in display unevenness and degrading display quality.

  Therefore, in order to suppress the influence of drive transistor characteristic variations on the display, a technology for reducing the VTH (threshold) variation of transistors by providing a constant current circuit that keeps the current flowing through the organic EL constant, a so-called VTH compensation technology has been developed. Has been.

  The VTH compensation circuit can reduce the influence of the VTH variation of the drive transistor, and can accurately control the amount of current supplied to the light emitting element with the input image data. Therefore, it is possible to effectively compensate for the VTH variation inherent to the drive transistor, and to significantly improve the display uniformity of the organic EL display. However, the VTH compensation circuit is generally known to have a circuit configuration including six transistors and one storage capacitor, and the number of elements per pixel increases, which is an obstacle to high definition. In addition, it can be a cause of yield reduction.

  Japanese Patent Application Laid-Open No. 2004-228561 discloses a technique for configuring a VTH compensation circuit with fewer transistors and storage capacitors than conventional ones. With this technique, the number of elements per pixel can be reduced as compared with the conventional VTH compensation circuit, and high definition and yield improvement are possible.

JP 2003-271095 A

  According to the pixel circuit of Patent Document 1, when sampling the gradation data voltage by capacitive coupling of the storage capacitor and the parasitic capacitance of the current control element during data programming, a leakage current is generated in which charge flows to the EL power source via the drive transistor. To do. As a result, the gradation data voltage is attenuated, and a sufficient charge cannot be held in the storage capacitor. In order to hold a sufficient charge, it is necessary to increase the storage capacitor size. However, since the storage capacitor occupies a large proportion of the unit pixel circuit, increasing the capacitor size is a great disadvantage for high definition. The above-described data programming method using capacitive coupling is affected by the transistor parasitic capacitance. However, in general, a drive transistor having a large transistor size has a large parasitic capacitance, so that gradation data voltage variation occurs.

  An object of the present invention is to reduce gradation data variation during data programming while achieving high definition by reducing the storage capacity size.

  A driving method of a pixel circuit according to an embodiment of the present invention includes a light emitting element that includes a capacitive component and whose gradation is determined by a supplied current, and the light emitting element according to a gradation data voltage supplied to a gate electrode. A first transistor that controls the magnitude of the supply current of the first transistor, a second transistor connected between the light emitting element and the first transistor, one electrode connected to the gate electrode of the first transistor, and the other A third capacitor connected between the gate electrode of the first transistor and a signal line; and a storage capacitor that is capacitively coupled to the capacitive component; A pixel circuit driving method including: turning on the third transistor; supplying a first voltage from the signal line to the one electrode; and supplying the first voltage to the storage capacitor. An initialization step of writing a voltage higher than a threshold voltage of the transistor, and supplying the grayscale data voltage from the signal line to the one electrode, and holding the voltage via the first transistor and the second transistor which are in the on state A compensation step of writing the threshold voltage into a capacitor; and supplying a second voltage from the signal line to the one electrode and turning off the second transistor, and then turning on the second transistor with the gradation data voltage and the threshold voltage. A data program step of writing a voltage of the determined first data, and after turning off the third transistor, turning on the second transistor and causing the first transistor to pass a current based on the first data, thereby causing the light emitting device to A light emitting step of emitting light.

  According to this pixel circuit driving method, it is possible to reduce gradation data variation during data programming while achieving high definition by reducing the storage capacitor size.

  In another preferred aspect, a reverse bias may be applied to the diode component of the light emitting element in the initialization step and the compensation step.

  According to this pixel circuit driving method, the leakage current of the light emitting element can be further suppressed, and the contrast ratio can be improved by suppressing black floating.

  In another preferred embodiment, in the initialization step, a voltage larger than the threshold voltage may be written to the storage capacitor by causing a current to flow through the first transistor turned on by the first voltage.

  According to this pixel circuit driving method, the number of wirings and switch elements can be further reduced, which is advantageous for high definition.

  In another preferred embodiment, the first voltage, the second voltage, and the gradation data voltage may be supplied by a single data line.

  According to this pixel circuit driving method, the number of wirings and switch elements can be further reduced, which is advantageous for high definition.

  In another preferred embodiment, each of the first to third transistors is a p-channel transistor, the light emitting element is connected to an anode power supply, and the first transistor is connected to a cathode power supply. In the initializing step, the first voltage is lower than the gradation data voltage, the other electrode supplies a voltage higher than the first voltage, and in the compensating step, The threshold voltage is written by passing a current to the cathode power supply via the first transistor through the storage capacitor, and the second voltage may be lower than the gradation data voltage in the data programming step.

  According to this pixel circuit driving method, it is possible to reduce gradation data variation during data programming while achieving high definition by reducing the storage capacitor size.

  In another preferred embodiment, each of the first to third transistors is an n-channel transistor, the light emitting element is connected to a cathode power supply, and the first transistor is connected to an anode power supply. In the initializing step, the first voltage is higher than the grayscale data voltage, and the other electrode supplies a voltage lower than the first voltage. In the compensating step, The threshold voltage is written by passing a current from the anode power supply through the first transistor through the storage capacitor, and the second voltage may be higher than the gradation data voltage in the data programming step.

  According to this pixel circuit driving method, a circuit using an n-channel semiconductor such as amorphous silicon or an oxide semiconductor can be formed.

  A pixel circuit according to an embodiment of the present invention includes a light emitting element that includes a capacitance component and whose gray scale is determined by a supplied current, and a supply current to the light emitting element according to a gray scale data voltage supplied to a gate electrode. A first transistor for controlling the size of the first transistor, a second transistor connected between the light emitting element and the first transistor, one electrode connected to the gate electrode of the first transistor, and the other electrode A storage capacitor connected to the first transistor via the second transistor and capacitively coupled to the capacitance component; and a third transistor connected between a gate electrode of the first transistor and a signal line. And the gradation of the light emitting element is determined by the voltage of the first data determined by the threshold voltage of the first transistor and the gradation data voltage stored in the storage capacitor.

  According to this pixel circuit driving method, it is possible to reduce gradation data variation during data programming while achieving high definition by reducing the storage capacitor size.

  According to the present invention, it is possible to reduce variations in gradation data during data programming while achieving high definition by reducing the storage capacity size.

Schematic which shows an example of a structure of the light emission display apparatus in Embodiment 1 of this invention. FIG. 3 is a circuit diagram illustrating an example of a circuit configuration of a unit pixel according to the first embodiment of the present invention. FIG. 3 is a circuit diagram illustrating an operation of a unit pixel according to the first embodiment of the present invention. 2 is a timing chart of unit pixels in Embodiment 1 of the present invention. 4 is a timing chart of the light-emitting display device according to the first embodiment of the present invention. The figure which showed the drive method in Embodiment 1 of this invention. VGS voltage change for each VTH during VTH compensation of the present invention. VGS voltage change by μ during data programming of the present invention. The circuit diagram which shows an example of the circuit structure of the unit pixel in Embodiment 2 of this invention. The circuit diagram which shows the operation | movement of the unit pixel in Embodiment 2 of this invention. 6 is a timing chart of unit pixels in Embodiment 2 of the present invention. The timing chart of the light emission display apparatus in Embodiment 2 of this invention.

  Hereinafter, a pixel circuit for driving a light emitting element according to the present invention and a display device using the same will be described with reference to the drawings. However, the pixel circuit for driving the light-emitting element of the present invention and the display device using the pixel circuit can be implemented in many different modes, and are interpreted as being limited to the description of the embodiment modes shown below. is not. Note that in the drawings referred to in this embodiment, the same portions or portions having similar functions are denoted by the same reference numerals, and repetitive description thereof is omitted.

(Embodiment 1)
A configuration and an operation method of the light-emitting display device according to Embodiment 1 will be described with reference to FIGS. FIG. 1 is a schematic diagram illustrating an example of a configuration of a light-emitting display device according to Embodiment 1 of the present invention. In the light emitting display device, pixel circuits 100 are arranged in a matrix of n rows and m columns, and each pixel circuit is controlled by a scan driver 10, an emission driver 20, an EL power source scan driver 30, and a data driver 40. Here, n = 1, 2, 3,..., M = 1, 2, 3,..., For example, if n = 3, the pixel circuit group arranged in the third row indicates m = 3 indicates a pixel circuit group arranged in the third column. Although FIG. 1 illustrates a pixel circuit with 3 rows and 3 columns, the present invention is not limited to this mode, and the numbers of n and m can be arbitrarily determined.

  The scan driver 10 is a drive circuit that selects a row in which data is written, and supplies a gate control signal SCAN (n) to gate control lines 11 to 13 provided corresponding to the pixel circuits 100 in each row. In the first embodiment, the gate control signal SCAN (n) controls the transistor M3 (see FIG. 2) connected between the drive transistor M1 (see FIG. 2) and the data line 45. In this example, the gate control signal SCAN (n) is predetermined for each row. Are sequentially selected in the order of

  The emission driver 20 is a drive circuit that controls the timing of supplying the power supply voltage to the light emitting elements, and sends an emission control signal EM (n) to the emission control lines 21 to 23 provided corresponding to the pixel circuits 100 in each row. Supply. In the first embodiment, the gate control signal EM (n) controls the transistor M2 (see FIG. 2) connected between the driving transistor and the light emitting element.

  The EL power supply scan driver 30 is a circuit that switches and supplies a power supply voltage for initializing the storage capacitor of the pixel circuit and a cathode voltage at the time of light emission of the light emitting element, and is provided corresponding to the pixel circuit 100 in each row. The EL power control signal ELVSS (n) is supplied to the EL power control lines 31 to 33. In the first embodiment, the EL power supply control signal ELVSS (n) is connected to one of the source and drain electrodes of the driving transistor M1, and the initialization voltage or cathode voltage of the storage capacitor C1 is set according to each period of circuit operation. Supply (see FIG. 2). In this embodiment, the initialization voltage corresponds to the high level of the cathode power supply ELVSS, and the cathode voltage corresponds to the low level of the cathode power supply ELVSS.

  The data driver 40 determines a gradation based on the input image data, and applies a data voltage corresponding to the determined gradation via data lines 41 to 43 provided corresponding to the pixel circuits 100 of each column. Drive circuit to be supplied to the pixel circuit 100. In addition, the switching circuit 50 provided between the data driver 40 and the pixel circuit region causes each data line to have the gradation data voltage VDATA or the initialization power supply voltage VINIT of the driving transistor in accordance with each period of circuit operation. Supplied.

  FIG. 2 is a circuit diagram showing an example of the circuit configuration of the unit pixel in Embodiment 1 of the present invention. FIG. 2 shows a case where all the transistors constituting the pixel circuit are p-channel type. One pixel circuit includes a drive transistor M1, an emission transistor M2, a switch transistor M3, a holding capacitor C1, and a light emitting element 1, and the light emitting element 1 includes a diode D1 and a capacitive component CEL. As described above, one pixel circuit includes three transistors, one storage capacitor, and a light emitting element including a parasitic capacitance component.

  The connection relationship of each element of the unit pixel 100 will be described with reference to FIG. The electrode on the anode side of the light emitting element 1 is connected to the anode power source ELVDD. The gate electrode of the driving transistor M1 that controls the magnitude of the supply current to the light emitting element 1 according to the voltage supplied to the gate electrode is connected to the data line via the switch transistor M3 controlled by the gate control signal SCAN (n). 45. A switch transistor M2 controlled by an emission control signal EM (n) is connected between the cathode electrode of the light emitting element 1 and one of the source and drain electrodes of the drive transistor M1. The other electrode of the source or drain of the driving transistor M1 is connected to the cathode power source ELVSS. The storage capacitor C1 for storing gradation data has one electrode connected to the gate electrode of the drive transistor M1, the other electrode connected to the cathode side electrode of the light emitting element 1, and the other electrode connected to the switch transistor M2. And is connected to one of the source and drain of the driving transistor M1.

  In the present embodiment, the transistors constituting the pixel circuit are all p-channel type. When a “low level” control signal is applied to the gate electrode of the transistor, the transistor is turned on, Become. On the other hand, when a “high level” control signal is applied to the gate electrode of the transistor, the transistor is turned off and becomes non-conductive.

  FIG. 3 is a circuit diagram showing the operation of the unit pixel in Embodiment 1 of the present invention, and FIG. 4 is a timing chart of the unit pixel in Embodiment 1 of the present invention. 3 and 4 are divided into (a) initialization period, (b) VTH compensation + mobility compensation period, (c) data program period, and (d) light emission period, respectively. Refers to the same thing. Moreover, the arrow in FIG. 3 represents the direction of an electric current.

(A) Initialization period The initialization voltage VINIT is supplied to the data signal DT, the gate control signal SCAN (n) becomes low level, the switch transistor M3 is turned on, and the node N1 (the gate electrode and the storage capacitor of the drive transistor M1) The initialization voltage VINIT is supplied to a node common to one electrode of C1. Here, the initialization voltage VINIT is a fixed voltage for turning on the driving transistor M1. A high level is supplied to the cathode power source ELVSS, and the emission control signal EM (n) becomes a low level and the emission transistor M2 is turned on, whereby the node N2 (the other electrode of the storage capacitor C1 and the capacitance component CEL of the light emitting element 1) A high level of the cathode power supply ELVSS is supplied to a node common to the cathode side). At this time, a high level of the cathode power supply ELVSS is supplied to at least VINIT with a voltage higher than the threshold voltage VTH of the drive transistor M1, that is, a voltage higher than VINIT + VTH, and the holding capacitor C1 and the capacitance component CEL are connected between the respective electrodes. Charge corresponding to the potential difference is accumulated. At this time, a voltage higher than VTH is applied between the electrodes of the storage capacitor C1. Hereinafter, in this specification, this state is expressed as a voltage larger than VTH written in the storage capacitor C1.

(B) VTH Compensation + Mobility Compensation Period The data signal DT is switched from the initialization voltage VINIT to the gradation data voltage VDATA by the switching circuit 50, and the gate control signal SCAN (n) is maintained at the low level, so that VDATA is It is supplied to the node N1. At this time, the potential of the node N2 also changes according to the difference between the gradation data voltage VDATA and the initialization voltage VINIT due to capacitive coupling of the storage capacitor C1. Here, a voltage higher than VINIT is supplied as VDATA, and the potential of the node N2 rises according to the voltage value of VDATA supplied in each pixel circuit. Further, the cathode power source ELVSS is at a low level in a state where the emission control signal EM (n) is maintained at a low level. The potential difference between the source and drain of the drive transistor M1 is reversed from the initialization period, and the charge accumulated in the storage capacitor C1 and the capacitance component CEL of the light emitting element 1 moves so as to flow to the cathode power supply ELVSS through the drive transistor M1. By this movement, the potential of the node N2 is lowered and becomes VTH + VDATA, which is stabilized by turning off the driving transistor M1. At this time, VDATA is supplied to the node N1, and the node N2 is stabilized at VTH + VDATA. That is, VTH is written to the storage capacitor C1. In this way, charges corresponding to the VTH specific to M1 are held in C1 and CEL, and the driving transistor M1 supplies a current compensated for VTH and mobility to the light emitting element 1 in the subsequent light emission period. Here, the anode power source ELVDD is set to a voltage lower than VTH + VDATA even when VDATA is the smallest so that no current flows through the light emitting element 1, and a reverse bias is applied to the diode component D1 of the light emitting element 1.

(C) Data Program Period The data signal DT is switched from the gradation data voltage VDATA to the initialization voltage VINIT by the switching circuit 50, and the gate control signal SCAN (n) is maintained at the low level, so that VINIT is supplied to the node N1. Is done. At this time, the potential on the node N2 side of the storage capacitor C1 also changes in accordance with the difference between the initialization voltage VINIT and the gradation data voltage VDATA due to capacitive coupling of the storage capacitor C1 as described above. Here, since the emission control signal EM (n) is high and the emission transistor M2 is off and the node N2 is in a floating state, the capacitively coupled holding capacitor C1 and the capacitance component CEL of the light emitting element 1 In the meantime, the charge moves between the storage capacitor C1 and the capacitance component CEL of the light emitting element 1 so as to compensate for the potential change on the node N2 side of the storage capacitor C1. At this time, since the switch transistor M2 is turned off, the charge movement occurs only between C1 and CEL and is not affected by the leakage of the driving transistor M1 or the parasitic capacitance. In the first embodiment, when the storage capacitor C1 and the capacitance component CEL of the light emitting element 1 have the same capacitance value, the amount of charge moving from CEL to C1 is (VDATA−VINIT) / 2. At this time, VINIT is supplied to the node N1, VTH + (VDATA + VINIT) / 2 is supplied to the node N2, and a voltage determined by the difference between VDATA and VTH is written to the storage capacitor C1. Here, although the potential of the node N2 is lower than the potential of the anode power supply ELVDD, no current flows through the light emitting element 1 because the switch transistor M2 is turned off. At the end of this period, the gate control signal SCAN (n) becomes high level and the switch transistor M3 is turned off, so that the node N1 is fixed to VINIT.

(D) Light emission period When the emission control signal EM (n) becomes a low level and the emission transistor M2 is turned on, data is written in the storage capacitor C1 between the gate electrode of the driving transistor M1 and one of the source and drain electrodes. The light-emitting element 1 emits light by determining the amount of current of the drive transistor M1 according to the voltage. At this time, the voltage determined by the VDATA and VTH is written in C1, the VTH and mobility of M1 are compensated, and a current dependent on VDATA is supplied to the light emitting element 1.

  FIG. 5 shows a timing chart of the light emitting display device according to the first embodiment of the present invention, and FIG. 6 shows a driving method according to the first embodiment of the present invention. The operation of the plurality of pixel circuits will be described with reference to FIGS.

  The operation of the pixel circuit 100A in the first column and the first row and the pixel circuit 100B in the first column and the second row in the pixel circuit in FIG. 1 will be described using the timing chart of FIG. First, in the period of (1) in FIG. 5, VINIT is supplied to DT, SCAN (1) is at a low level, and a high voltage is supplied to ELVSS (1), so that initialization of the pixel circuit 100A is performed. Done. At this time, the pixel circuit 100A corresponds to (a) the initialization period.

  In the period (2) in FIG. 5, VDATA is supplied to DT and ELVSS (1) is at a low level, so that in the pixel circuit 100A, a voltage corresponding to the threshold voltage unique to the driving transistor is written in the storage capacitor. At this time, the pixel circuit 100A corresponds to (b) VTH compensation + mobility compensation period.

  In the period of (3) in FIG. 5, VINIT is supplied to DT and EM (1) becomes high level, so that charge transfer occurs between the capacitance component of the light emitting element and the storage capacitor in the pixel circuit 100A. As a result, a voltage determined by VDATA and VTH is written in the storage capacitor C1 in the storage capacitor. In addition, SCAN (2) becomes low level during the same period, and a high voltage is supplied to ELVSS (2), whereby the pixel circuit 100B is initialized. At this time, the pixel circuit 100A corresponds to (c) a data program period, and the pixel circuit 100B corresponds to (a) an initialization period.

  In the period of (4) in FIG. 5, VDATA is supplied to DT. However, since SCAN (1) becomes high level and M3 of the pixel circuit 100A is turned off, the node N1 is fixed to VINIT. In addition, when ELVSS (2) is at a low level, in the pixel circuit 100B, a voltage corresponding to the threshold voltage unique to the driving transistor is written in the storage capacitor. At this time, the pixel circuit 100A corresponds to a transition period between (c) a data program period and (d) a light emission period, and the pixel circuit 100B corresponds to (b) a VTH compensation + mobility compensation period.

  In the period of (5) in FIG. 5, VINIT is supplied to DT, and EM (1) goes to a low level, whereby the emission transistor M2 of the pixel circuit 100A is turned on and current flows through the light emitting element to emit light. Further, when EM (2) is at a high level, in the pixel circuit 100B, charge transfer occurs between the capacitance component of the light emitting element and the storage capacitor, and as a result, a voltage determined by VDATA and VTH is written to the storage capacitor. . At this time, the pixel circuit 100A corresponds to (d) the light emission period, and the pixel circuit 100B corresponds to (c) the data program period.

  As described above, in the present embodiment, data program and light emission such as line sequential initialization and VTH compensation are alternately repeated, and the operation is performed by progressive driving as shown in FIG.

  Next, VTH compensation and mobility compensation according to the present invention will be described with reference to FIGS. FIG. 7 shows changes in VGS voltage for each VTH during VTH compensation according to the present invention, and FIG. 8 shows changes in VGS voltage due to μ during data programming according to the present invention. IDS is a drain-source current, and VGS is a gate-source voltage. 7 and 8, the ELVDD side of the drive transistor is the source and the ELVSS side is the drain. In FIG. 7, the characteristic of the transistor having the cut-off voltage 1 is referred to as VTH1, and the characteristic of the transistor having the cut-off voltage 2 is referred to as VTH2.

  3 and 4, the initialization power supply VINIT is supplied to the gate electrodes of the two transistors in the period of (a) in FIGS. 3 and 4, and the VTH1 is in the X1 state and the VTH2 is in the X2 state. The amount of current that flows depends on the variation of the current.

  Next, the charge accumulated in the storage capacitor C1 and the capacitance component CEL of the light emitting element in the period of FIGS. 3 and 4 flows to ELVSS through the driving transistor M1, so that the VGS of M1 is decreased. When the cut-off voltages Y1 and Y2 are reached, each M1 is turned off.

  In the present embodiment, the gradation data voltage VDATA is supplied to the gate electrode of the drive transistor M1 during the period of (b) in FIGS. 3 and 4, and the cutoff voltage depends on the value of VDATA as shown in FIG. Is different. Here, since the transistors having both characteristics are cut off at the same current value, not only the case where the respective threshold voltages are different, but also the transistor having different mobility has an effect of correcting the variation.

  As described above, not only VTH between different transistors but also variations in mobility can be corrected by the driving method shown in this embodiment, so that the gradation of the pixel circuit can be adjusted more accurately by VDATA.

  In this embodiment, initialization, VTH compensation, mobility compensation, data program, and light emission control can be performed using three transistors and one storage capacitor.

  In the present embodiment, in the (b) VTH compensation + mobility compensation period, the gradation data voltage VDATA is supplied to the gate electrode of the drive transistor M1, so that VTH compensation and mobility compensation can be performed simultaneously. Is possible.

  In the present embodiment, in the data program period (c), the switch transistor M3 is turned off to separate the drive transistor M1, the storage capacitor C1, and the capacitance component CEL of the light emitting element, thereby suppressing the leakage current via M1. In addition, a data program in which the influence of the parasitic capacitance of M1 is suppressed is possible. As a result, the size of the storage capacitor C1 can be reduced, which is advantageous for high definition and high image quality.

(Embodiment 2)
A configuration and an operation method of the light-emitting display device according to the second embodiment will be described with reference to FIGS. FIG. 9 is a circuit diagram showing an example of a circuit configuration of a unit pixel in Embodiment 2 of the present invention. In this embodiment, the case where all the transistors constituting the pixel circuit are n-channel type is shown. Differences from the first embodiment will be described.

  The element constituting the unit pixel 101 includes three transistors, one storage capacitor, and a light emitting element including a parasitic capacitance component. Hereinafter, the connection relationship of each element of the unit pixel 101 shown in FIG. 9 will be described. An electrode on the cathode side of the light emitting element 1 is connected to a cathode power source ELVSS. The gate electrode of the driving transistor M1 that controls the magnitude of the supply current to the light emitting element 1 according to the voltage supplied to the gate electrode is connected to the data line via the switch transistor M3 controlled by the gate control signal SCAN (n). 46. A switch transistor M2 controlled by an emission control signal EM (n) is connected between the anode-side electrode of the light emitting element 1 and one of the source and drain electrodes of the drive transistor M1. The other electrode of the source or drain of the driving transistor M1 is connected to the anode power source ELVDD. The storage capacitor C1 for storing gradation data has one electrode connected to the gate electrode of the driving transistor M1, the other electrode connected to the anode side electrode of the light emitting element 1, and the other electrode connected to the switch transistor M2. And is connected to one of the source and drain electrodes of the drive transistor M1.

  FIG. 10 is a circuit diagram showing the operation of the unit pixel in the second embodiment of the present invention, and FIG. 11 is a timing chart of the unit pixel in the second embodiment of the present invention. 10 and 11, they are divided into (a) initialization period, (b) VTH compensation + mobility compensation period, (c) data program period, and (d) light emission period, respectively. Refers to the same thing. Moreover, the arrow in FIG. 10 represents the direction of electric current.

(A) Initialization period The initialization voltage VINIT is supplied to the data signal DT, the gate control signal SCAN (n) becomes high level, the switch transistor M3 is turned on, and the node N3 (the gate electrode and the storage capacitor of the drive transistor M1) The initialization voltage VINIT is supplied to a node common to one electrode of C1. Here, the initialization voltage VINIT is a fixed voltage for turning on the driving transistor M1. A low voltage is supplied to the anode power source ELVDD, the emission control signal EM (n) becomes high level, and the emission transistor M2 is turned on, whereby the node N4 (the other electrode of the holding capacitor C1 and the capacitance component CEL of the light emitting element 1). A low level of the anode power supply ELVDD is supplied to a node common to the anode side). At this time, the low level of the anode power source ELVDD is supplied with a voltage lower than the threshold voltage VTH of the drive transistor M1 at least with respect to VINIT, and the potential of the node N4 is lowered, so that a voltage higher than VTH is applied to the storage capacitor C1. Written.

(B) VTH Compensation + Mobility Compensation Period The data signal DT is switched from the initialization voltage VINIT to the grayscale data voltage VDATA by the switching circuit 50, and the gate control signal SCAN (n) is maintained at a high level. It is supplied to the node N3. At this time, the potential of the node N4 also changes according to the difference between the gradation data voltage VDATA and the initialization voltage VINIT due to capacitive coupling of the storage capacitor C1. Here, a voltage lower than VINIT is supplied as VDATA, and the potential of the node N4 decreases according to the voltage value of VDATA supplied in each pixel circuit. Further, the anode power source ELVDD becomes high level while the emission control signal EM (n) is maintained at high level. The potential difference between the source and drain of the drive transistor M1 is reversed from the initialization period, and the charge moves so as to flow from the anode power source ELVDD to the storage capacitor C1 and the capacitance component CEL of the light emitting element 1 through the drive transistor M1. By this movement, the potential of the node N4 rises, becomes VDATA−VTH, and is stabilized by turning off the driving transistor M1. At this time, VDATA is supplied to the node N3, and the node N4 is stabilized at VDATA−VTH. Therefore, the difference VTH is written in the storage capacitor C1. In this way, charges corresponding to VTH unique to M1 are held in C1 and CEL, and VTH compensation and mobility compensation are performed in connection with the subsequent operation. Here, the cathode power supply ELVSS is set to a voltage higher than VDATA−VTH even when VDATA is the largest so that no current flows through the light emitting element 1, and a reverse bias is applied to the diode component D1 of the light emitting element 1. .

(C) Data Program Period The data signal DT is switched from the gradation data voltage VDATA to the initialization voltage VINIT by the switching circuit 50, and the gate control signal SCAN (n) is maintained at a high level, whereby VINIT is supplied to the node N3. Is done. At this time, the potential on the node N4 side of the storage capacitor C1 also changes in accordance with the difference between the initialization voltage VINIT and the gradation data voltage VDATA due to capacitive coupling of the storage capacitor C1 as described above. Here, since the emission control signal EM (n) is low and the emission transistor M2 is off and the node N4 is in a floating state, the capacitively coupled holding capacitor C1 and the capacitance component CEL of the light emitting element 1 In the meantime, charges move between the storage capacitor C1 and the capacitance component CEL of the light emitting element 1 so as to compensate for the potential change on the node N4 side of the storage capacitor C1. At this time, since the switch transistor M2 is turned off, the charge movement occurs only between C1 and CEL and is not affected by the leakage of the driving transistor M1 or the parasitic capacitance. In the second embodiment, when the storage capacitor C1 and the capacitance component CEL of the light emitting element 1 have the same capacitance value, the amount of charge transferred from C1 to CEL is (VDATA−VINIT) / 2. At this time, VINIT is supplied to the node N3, (VDATA−VINIT) / 2−VTH is supplied to the node N4, and a voltage determined by the difference between VDATA and VTH is written to the storage capacitor C1. Here, the potential of the node N4 is higher than the potential of the cathode power supply ELVSS, but no current flows through the light emitting element 1 because the switch transistor M2 is turned off. At the end of this period, the gate control signal SCAN (n) goes low and the switch transistor M3 is turned off, so that the node N3 is fixed at VINIT.

(D) Light emission period When the emission control signal EM (n) is at a high level and the emission transistor M2 is turned on, data is written in the storage capacitor C1 between the gate electrode of the drive transistor M1 and one of the source and drain electrodes. The light-emitting element 1 emits light by determining the amount of current of the drive transistor M1 according to the voltage. At this time, the voltage determined by the VDATA and VTH is written in C1, the VTH and mobility of M1 are compensated, and a current dependent on VDATA is supplied to the light emitting element 1.

  FIG. 12 shows a timing chart of the light-emitting display device according to Embodiment 2 of the present invention. As described above, when all the transistors of the pixel circuit are changed to the n-channel type, the high level / low level of the control signal is reversed. That is, the timing chart shown in FIG. 12 is obtained by reversing the high level / low level shown in FIG. 5, and the driving of each transistor of the pixel circuit is the same as that in the first embodiment, and thus the description thereof is omitted here.

  As described above, the present invention can be implemented even when the transistors of the pixel circuit are all n-channel transistors. Since an n-channel transistor has higher mobility than a p-channel transistor, in addition to the advantages obtained in Embodiment 1, a circuit that requires higher speed operation can be realized.

  In addition, since a pixel circuit can be formed using only n-channel transistors, the present invention can be applied to a display device formed using an amorphous silicon transistor or an oxide semiconductor transistor.

  In the first and second embodiments of the present invention, the pixel circuit configuration including three transistors and one storage capacitor has been described as an example. However, various forms can be used without departing from the spirit of the present invention. Can take. For example, the number of transistors, the number of storage capacitors, and the number of signal lines may be increased for the purpose of adding an additional function to the present invention.

  In the first or second embodiment, the initialization is performed by supplying a voltage from ELVDD or ELVSS. However, the initialization method is not limited to this embodiment, and the threshold value of the driving transistor M1 is not limited. A voltage larger than the voltage VTH only needs to be written in the storage capacitor C1. For example, a power supply line can be connected to the node N2 or the node N4 via a switch, and a desired voltage can be supplied from the power supply line by turning on the switch in the initialization period.

  In the first or second embodiment, the gradation data voltage VDATA and the initialization voltage VINIT are supplied by the same signal line. However, the present invention is not limited to this method, and different signal lines are used. A signal may be supplied.

  In the timing chart in the first or second embodiment, the operation in which the periods (a) to (d) are simultaneously switched is illustrated. However, the timing of each signal is shifted within a range in which the object of the present invention can be achieved. be able to. For example, in the data program period, when the charge is transferred between the storage capacitor C1 and the capacitance component CEL of the light emitting element 1, the emission transistor M2 is turned off, thereby affecting the influence of the leakage of the drive transistor M1 and the parasitic capacitance. Suppress. The timing at which the data signal DT is switched from the grayscale data voltage VDATA to the initialization voltage VINIT may be controlled so as to coincide with the timing at which M2 is turned off or later than the timing at which M2 is turned off. That is, the control may be performed so that the data signal DT is switched from the gradation data voltage VDATA to the initialization voltage VINIT after M2 is turned off.

In the timing chart in the first or second embodiment, the emission transistor M2 is turned on after a certain period of time in which the switch transistor M3 is turned off in the data program period to the light emission period. Signal timing can be shifted. For example, the timing for turning on M2 may be controlled to be the same as the timing for turning off M3 or to be later than the timing for turning off M3. That is, control may be performed so that M2 is turned on after M3 is turned off.

  As described above, according to the inventions described in Embodiments 1 and 2, gradation data variation during data programming can be reduced while achieving high definition by reducing the storage capacitor size.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention.

DESCRIPTION OF SYMBOLS 1: Light emitting element 10: Scan driver 20: Emission driver 30: EL power supply scan driver 40: Data driver 100, 100A, 100B: Pixel circuit 11, 12, 13: Gate control signal line 21, 22 , 23: Emission control signal line, 31, 32, 33: EL power supply control line, 41, 42, 43: Data line, 50: Switching circuit

Claims (7)

A light-emitting element including a capacitive component and whose gradation is determined by a supplied current;
A first transistor that controls a magnitude of a current supplied to the light emitting element in accordance with a grayscale data voltage supplied to the gate electrode;
A second transistor connected between the light emitting element and the first transistor;
One electrode is connected to the gate electrode of the first transistor, the other electrode is connected to the first transistor via the second transistor, and a storage capacitor capacitively coupled to the capacitance component;
And a third transistor connected between the gate electrode of the first transistor and a signal line.
An initialization step of turning on the third transistor, supplying a first voltage from the signal line to the one electrode, and writing a voltage larger than a threshold voltage of the first transistor to the storage capacitor;
A compensation step of supplying the grayscale data voltage from the signal line to the one electrode and writing the threshold voltage to the storage capacitor via the first transistor and the second transistor which are in an on state;
A data program step of supplying a second voltage from the signal line to the one electrode and turning off the second transistor and writing a voltage of the first data determined by the gradation data voltage and the threshold voltage to the storage capacitor. When,
And a light emitting step in which the light emitting element emits light when the second transistor is turned on after the third transistor is turned off and the first transistor passes a current based on the first data. A driving method of a pixel circuit.   2. The pixel circuit driving method according to claim 1, wherein a reverse bias is applied to the diode component of the light emitting element in the initialization step and the compensation step.   2. The initialization process, wherein a voltage larger than the threshold voltage is written to the storage capacitor when a current flows through the first transistor turned on by the first voltage. 3. A driving method of a pixel circuit according to 2.   4. The pixel circuit driving method according to claim 1, wherein the first voltage, the second voltage, and the grayscale data voltage are supplied by a single data line. 5. Each of the first to third transistors is a p-channel transistor, the light emitting element is connected to an anode power source, and the first transistor is connected to a cathode power source.
In the initialization step, the first voltage is lower than the gradation data voltage, and the other electrode supplies a voltage higher than the first voltage,
In the compensation step, the threshold voltage is written by causing a current to flow to the cathode power supply via the first storage capacitor.
5. The pixel circuit driving method according to claim 1, wherein, in the data programming step, the second voltage is lower than the gradation data voltage. 6. The first to third transistors are all n-channel transistors, the light emitting element is connected to a cathode power supply, and the first transistor is connected to an anode power supply.
In the initialization step, the first voltage is higher than the gradation data voltage, and the other electrode supplies a voltage lower than the first voltage.
In the compensation step, the threshold voltage is written by passing a current from the anode power source through the storage capacitor and the first transistor,
5. The pixel circuit driving method according to claim 1, wherein in the data programming step, the second voltage is higher than the grayscale data voltage. 6. A light-emitting element including a capacitive component and whose gradation is determined by a supplied current;
A first transistor that controls a magnitude of a current supplied to the light emitting element in accordance with a grayscale data voltage supplied to the gate electrode;
A second transistor connected between the light emitting element and the first transistor;
One electrode is connected to the gate electrode of the first transistor, the other electrode is connected to the first transistor via the second transistor, and a storage capacitor capacitively coupled to the capacitance component;
A third transistor connected between a gate electrode of the first transistor and a signal line;
The pixel circuit according to claim 1, wherein the gray level of the light emitting element is determined by a voltage of first data determined by a threshold voltage of the first transistor and the gray level data voltage stored in the storage capacitor.

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