JP2015002405A - Noise detection circuit and reception circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To detect noise mixed in an external input signal in real time, and implement a reception circuit having a noise protection function of protecting data in the event of an error due to noise.SOLUTION: The reception circuit has: a first circuit 21 for capturing a first signal Din according to a timing signal CLK to output a second signal Dp; a holding circuit 22 for capturing Dp according to CLK to output a third signal Dd; a noise detection circuit 24 for detecting whether or not Din changes during a first period shorter than one period which includes a change timing of CLK, and if there is a change, outputting a selection signal Select; and a selection circuit 23 for capturing Dp and Dd, and outputting Dp if Select has not been output and Dd if Select has been output. The noise detection circuit has a signal generation circuit 25 for generating a fourth signal Xcheck during the first period, and a detection circuit 26 for detecting whether or not Din changes during the first period according to the fourth signal, and if there is a change, outputting Select in synchronism with the end of the first period.

Description

  The disclosed technology relates to a noise detection circuit and a reception circuit.

  Signals are transmitted between LSI chips or between a plurality of circuit blocks in a housing and between housings. The receiving circuit takes in the data signal from the transmission path in synchronization with the clock signal by a latch circuit or the like. The data signal is transmitted when a multi-bit data signal is transmitted in parallel, or after the multi-bit data signal is converted into a 1-bit data signal after parallel-serial conversion, and the received 1-bit data signal is transmitted as a multi-bit data. The signal may be converted from serial to parallel. The disclosed technique is applied to any of the above cases.

  A transmission path for transmitting a data signal receives various disturbance noises from the surroundings. This disturbance noise has a narrow width, and if it is mixed at the timing when the receiving circuit takes in the data signal, it affects the received data and generates an error. However, even if it is mixed at other timings, it is not affected. Even if the data signal is mixed in at the timing of taking it in, no error occurs if the amplitude of the disturbance noise is small. Hereinafter, noise mixed in the data signal received at the input portion of the receiving circuit may be referred to as external noise, and a noise detection circuit that detects such external noise may be referred to as an external noise detection circuit.

  A system using an LSI, such as a microcontroller, performs various operations such as control according to received data. When an error occurs in the received data, a problem such as a malfunction may occur. Therefore, in a system using an LSI such as a microcontroller, it is desired to protect the system from external noise and improve a safety function.

  When realizing a noise detection circuit for detecting external noise, it is conceivable to form the noise detection circuit using an analog circuit in relation to the width and amplitude of the noise. Then, the noise protection (protection) circuit is operated based on the detection signal. However, such an external noise detection circuit and a noise protection circuit cannot be applied to a development environment that does not use an analog circuit such as an FPGA (Field Programmable Gate Array). In addition, since the analog circuit needs to be adjusted at the time of arrangement and wiring, and the characteristics of each device also change, the LSI including the analog circuit has a problem that the manufacturing process at the time of mass production becomes complicated.

  In addition, it has been proposed that the external noise detection circuit is realized by a digital circuit including a three-stage flip-flop that operates according to a clock signal to protect the internal circuit from noise. In this external noise detection circuit, it is determined that no noise is received only when the three stages of flip-flops (three-stage protection circuit) all have the same value, the output value of the third stage flip-flop is latched, and the internal circuit take in. However, since this external noise detection circuit uses a three-stage flip-flop, its use is limited because of a large delay from the input of the data signal to the incorporation into the internal circuit.

JP-A-11-187312 Japanese Utility Model Publication No. 3-69931 JP 2008-104039 A JP 2009-27335 A

  In recent years, with the improvement of the operating frequency of systems including LSIs, including a noise detection circuit for external noise that is configured only with digital circuits that have been difficult until now, and that can detect noise even at a high operating frequency, and a noise protection function There is a need for a receiver circuit.

  Furthermore, a noise detection circuit and a reception circuit for external noise that can broaden the application range by placing importance on real-time characteristics with little signal delay are important.

  Therefore, a noise detection circuit that reliably detects noise (pulse) having the smallest possible width at the timing of latching an external input signal is desired. Furthermore, when such a noise detection circuit detects the occurrence of an error due to noise, it is desired to implement a noise protection function for protecting data in the receiving circuit.

  In addition, it is desired that such a noise detection circuit and reception circuit also have real-time characteristics by latching an external input data signal for synchronization and then directly inputting it to a subsequent circuit.

  The noise detection circuit according to the first aspect includes a signal generation circuit and a detection circuit. The signal generation circuit generates the first signal for a first period shorter than one cycle of the timing signal including the timing of changing the potential of the timing signal. The detection circuit detects whether or not the potential of the second signal has changed during the first period in response to the first signal, and generates an error signal when it has changed.

  The receiving circuit according to the second aspect includes a first circuit, a holding circuit, a noise detection circuit, and a selection circuit. The first circuit captures the first signal according to the timing signal, and outputs the captured first signal as a second signal. The holding circuit takes in the second signal output from the first circuit in accordance with the timing signal and outputs it as a third signal. The noise detection circuit detects whether or not the first signal has changed in a first period shorter than one cycle of the timing signal, including the change timing of the potential of the timing signal, and outputs a selection signal when it has changed. The selection circuit receives the second signal and the third signal, and outputs the second signal when the selection signal is not output, and outputs the third signal when the selection signal is output. The noise detection circuit detects and changes whether the potential of the first signal has changed in the first period in response to the signal generation circuit that generates the fourth signal during the first period and the fourth signal A detection circuit that outputs a selection signal in synchronization with the end of the first period.

According to the first and second aspects, a noise detection circuit which is formed of a digital circuit and has a small area and does not require adjustment like an analog circuit, and a reception circuit including a noise protection function are realized.
The noise detection circuit and the reception circuit reliably detect a noise component mixed in the monitoring data every cycle at a low cost, have high real-time characteristics, and perform data protection for the subsequent circuit. Further, since the noise detection circuit and the reception circuit are formed only by digital circuits, they are applied to the FPGA as they are and can perform logic simulation, thereby reducing the verification period.

FIG. 1 is a diagram showing an example of a data signal receiving circuit having an external noise detecting circuit formed only of a digital circuit. FIG. 2 is a block diagram illustrating a configuration of the receiving circuit according to the first embodiment. FIG. 3 is a diagram illustrating a configuration of a receiving circuit according to the second embodiment. 4A and 4B are diagrams showing a phase shift circuit, where FIG. 4A shows a circuit configuration and FIG. 4B shows an operation time chart. FIG. 5 is a time chart illustrating an operation example of the receiving circuit according to the second embodiment. FIG. 6 is a time chart illustrating another operation example of the receiving circuit according to the second embodiment. FIG. 7 is a time chart illustrating still another operation example of the receiving circuit according to the second embodiment. FIG. 8 is a time chart showing still another operation example of the receiving circuit of the second embodiment. FIG. 9 is a diagram illustrating a configuration of a receiving circuit according to the third embodiment. FIG. 10 is a diagram illustrating a configuration of a modified example of the receiving circuit according to the third embodiment. FIG. 10A illustrates the overall configuration, and FIG. 10B illustrates a circuit diagram of the switching signal generation circuit. FIG. 11 is a diagram illustrating a configuration of a receiving circuit according to the fourth embodiment. 12A and 12B are diagrams showing a phase shift circuit in the receiving circuit of the fourth embodiment. FIG. 12A is a circuit diagram and FIG. 12B is a time chart showing the operation. FIG. 13 is a diagram showing an example of a circuit device to which the receiving circuits of the first to fourth embodiments are applied, and shows an example applied to a microcomputer system.

  Before describing the embodiment, a general description of an external noise detection circuit that detects noise contamination in a received data signal, and a reception circuit that has a noise protection function that protects a system signal when noise contamination is detected Explain technical techniques.

  There is known an external noise detection circuit using a delay difference between an original data signal and a data signal delayed by an analog delay circuit formed by a capacitor, a resistor, a simulation circuit, and the like. However, since the application range of analog circuits is limited and the manufacturing process becomes complicated, external noise detection circuits including analog circuits are not targeted here, but external noise detection circuits using digital circuits are targeted. To do.

  FIG. 1 is a diagram showing an example of a data signal receiving circuit having an external noise detecting circuit formed only of a digital circuit.

  The receiving circuit of FIG. 1 includes an external noise detection circuit 10 and a capture circuit 15 that captures a data signal into an internal circuit. The external noise detection circuit 10 receives the data signal Din at the first stage, and outputs three-stage D-type flip-flops (FF) 11-13 that latch the output Q of the previous stage according to the clock signal CLK, and outputs of the FF11-13. Negative exclusive OR gate (NXOR) 14. The acquisition circuit 15 is in an operating state by the output of the NXOR 14, has a D-FF 15 that latches the output of the third-stage FF 13 in synchronization with the CLK, and outputs it as an output data signal Dout. The receiving circuit of FIG. 1 determines that there is no error in the received data when all the outputs of the three stages of D-FFs are equal, and takes in the internal circuit.

  The receiving circuit of FIG. 1 has a problem that the amount of delay until the data signal Din is taken into the internal circuit is large because the data signal Din is taken in via a three-stage flip-flop that operates according to CLK.

  The receiving circuits of the embodiments described below are all formed by digital circuits, reliably detect noise components mixed in the input data signal to be monitored every cycle, and protect the data signals taken into the internal circuit with a small delay amount. .

FIG. 2 is a block diagram illustrating a configuration of the receiving circuit according to the first embodiment.
The receiving circuit according to the first embodiment includes an acquisition circuit 21, a holding circuit 22, a noise detection circuit 24, and a selection circuit 23. The capture circuit 21 captures the capture target signal Din according to the capture timing signal, and outputs the captured capture target signal Din as the capture signal Dp. Here, the capture timing signal is shown as a clock signal CLK. The holding circuit 22 takes in the take-in signal Dp according to the take-in timing signal CLK and outputs it as a one-cycle delayed take-in signal Dd. The noise detection circuit 24 detects whether or not the capture target signal Din has changed during a predetermined period shorter than one cycle of CLK before and after the change edge corresponding to the capture timing of the capture timing signal CLK. The noise detection circuit 24 is invalid when the capture target signal Din does not change, and outputs a selection signal Select that is valid when it changes. When the Select is invalid, the holding circuit 22 takes in Dp according to CLK, and when it is valid, stops the taking according to CLK and maintains the held data as it is. The selection circuit 23 receives the capture signal Dp and the 1-cycle delay capture signal Dd, and outputs the capture signal Dp when the Select is invalid, and outputs the 1-cycle delay capture signal Dd when the Select is valid. The noise detection circuit 24 includes an effective signal generation circuit 25 and a target change detection circuit 26. The valid signal generation circuit 24 generates a valid signal Xcheck that is valid for a predetermined period shorter than one cycle of CLK before and after the change edge corresponding to the fetch timing of the fetch timing signal CLK. The target change detection circuit 26 detects whether or not the capture target signal Din has changed during the period in which the valid signal Xcheck is valid, and becomes invalid if it does not change in synchronization with the end of the valid period. A selection signal Select that is effective when it has changed is output.

  The take-in circuit 21 and the holding circuit 22 are realized by, for example, a latch circuit such as a flip-flop that operates in response to a rising edge of CLK. Here, when the input data signal is stable for a predetermined period before and after the rising edge of CLK, it is determined that noise is not mixed. A stable period before the rising edge of CLK is called a setup period, and a stable period before the rising edge of CLK is called a hold period.

  The external noise is generally a pulse having a small width, and the receiving circuit of the embodiment targets the noise having a small width and prevents the occurrence of an error due thereto.

  As described above, the data signal Din is required to be stable for a predetermined period before and after the rising edge of CLK, but no particular problem occurs even if noise is mixed in other periods. The noise detection circuit 24 performs monitoring during a period during which Xcheck including a predetermined period (setup period + hold period) before and after the rising edge of CLK is valid, and the data signal Din changes from L to H and from H to L or It detects that a reverse pulse-like change has occurred. In other words, the noise detection circuit 24 does not determine that noise is mixed when Din changes only from one of L to H or from H to L during the period in which Xcheck is valid.

Although the receiving circuit of the first embodiment has been described, a specific embodiment for realizing the receiving circuit of the first embodiment will be described below.
FIG. 3 is a diagram illustrating a configuration of a receiving circuit according to the second embodiment.
The receiving circuit according to the second embodiment takes in the data signal Din to be monitored transmitted through the data bus 30 in synchronization with the clock signal CLK.

  The receiving circuit according to the second embodiment includes a D-type flip-flop (D-FF) 31 for capturing, a holding D-FF 32, a selector 33, and a noise detecting circuit 34. The take-in D-FF 31 latches Din in synchronization with CLK and outputs it as a take-in data signal Dp. The holding D-FF 32 latches Dp in synchronization with CLK and outputs it as a one-cycle delay fetch data signal Dd. Therefore, Dd is a signal obtained by delaying Dp by one CLK period. However, the holding D-FF 32 stops latching new data when Select is valid (H). In other words, in the holding D-FF 32, CLK is gated by Select. The selector 33 inputs Dp and Dd, selects and outputs Dp when Select is invalid (L), and Dd when Select is valid (H). The output data signal Dout from the selector 33 is latched by the D-FF 101 in the subsequent circuit 100.

The noise detection circuit 34 includes a phase shift circuit 35, a change detection circuit 36, and an inverter 41 that inverts Din.
4A and 4B are diagrams showing the phase shift circuit 35, where FIG. 4A shows a circuit configuration and FIG. 4B shows an operation time chart.

  As illustrated in FIG. 4A, the phase shift circuit 35 includes a double circuit 61, an inverter 62, and a D-FF 63. The double circuit 61 converts CLK to a doubled clock signal having a double frequency. The inverter 62 inverts the doubled clock signal output from the double circuit 61 and outputs an inverted doubled clock signal. The D-FF 63 latches CLK in synchronization with the inverted double clock signal.

In FIG. 4B, A indicates CLK, B indicates an inverted double clock signal, and C indicates D-FF 63. As shown in the figure, the output of the D-FF 63 is a signal obtained by shifting the phase of CLK by 90 degrees (1/4).
As described above, the phase shift circuit 35 shifts the phase of CLK by 90 degrees and outputs a signal as the valid signal Xcheck indicating that monitoring is in progress.

  The change detection circuit 36 includes a first D-FF 42, a second D-FF 43, an AND gate 44, and a third D-FF 45. The first D-FF 42 and the second D-FF 43 are in an operating state only during a period in which Xcheck is valid, and the data input is fixed to “High (H)”. The first D-FF 42 uses Din as a clock input, changes the output P-Data to H in synchronization with the rising edge of Din in the operating state, and changes the P-Data to “L (Low)” when in the inoperative state. To change. Similarly, the second D-FF 43 receives the inverted Din inverted by the inverter 41 as a clock input, changes the output N-Data to H in synchronization with the rising edge of the inverted Din in the operating state, and becomes N− when inactive. Change Data to L. The AND gate 44 receives P-Data and N-Data, calculates a logical product, and outputs it as an error signal Error. The third D-FF 45 latches Error in synchronization with the rising edge of Xcheck, and outputs it as a selection signal Select.

FIG. 5 is a time chart illustrating an operation example of the receiving circuit according to the second embodiment.
As shown in FIG. 5, Xcheck indicating that monitoring is in progress is a signal obtained by shifting the phase of CLK by 90 degrees and is valid during L. In other words, Xcheck is a signal that is valid for 90 degrees (1/4 phase) before the rising edge of CLK and 90 degrees (1/4 phase) after the rising edge. In the second embodiment, the data signal Din changes from L to H and from H to L or vice versa during a period in which Xcheck including a predetermined period (setup period + hold period) before and after the rising edge of CLK is valid. Detects a change in shape. In other words, when Din changes only from one of L to H or from H to L during the period in which Xcheck is valid, it is not determined that noise is mixed.

  In the operation example shown in FIG. 5, during monitoring that Xcheck is valid, Din changes from H to L before the rising edge of CLK, and from L to H after the rising edge of CLK. This is a case where it is determined that there is contamination. The output N-Data of the D-FF 43 changes to H according to the change of Din from H to L, and the output P-Data of the D-FF 42 changes to H according to the change of Din from L to H. Then, the error signal Error output from the AND gate 44 changes to H. Further, when Xcheck changes from L to H in accordance with the end of monitoring, D-FF 45 latches Error and Select changes to H. In response to this, the selector 33 changes from the state of selecting the Dp output from the first D-FF 31 to the state of selecting the one-cycle delayed capture data signal Dd output from the second D-FF 32. The second D-FF 32 does not perform latching while the Select is H, and holds the one-cycle delayed capture data signal Dd. Dout is taken into the D-FF 101 of the subsequent circuit 100 at the next rising edge of CLK.

  In the next CLK cycle, P-Data, N-Data and Error change to L if Din does not change in pulse during monitoring, and when Xcheck changes from L to H in accordance with the end of monitoring, Select changes to L and returns to the normal state. In other words, the noise protection period indicated by the broken line in FIG. 5 is set to Dout using Dd instead of Dp.

FIG. 6 is a time chart illustrating another operation example of the receiving circuit according to the second embodiment.
In the operation example shown in FIG. 6, Din changes from H to L after the rising edge of CLK during monitoring in which Xcheck is valid, and does not change from L to H during monitoring. In this case, it is not determined that noise is mixed. The output N-Data of the D-FF 43 changes to H according to the change of Din from H to L. However, since Din does not change from L to H, the output P-Data of the D-FF 42 maintains L. . Therefore, the error signal Error output from the AND gate 44 maintains L, and the Select also remains L.

  In FIG. 6, Din maintains the state changed to L until after the next rising edge of CLK. In other words, it is a normal data signal change, and Dp output from the first D-FF 31 is the next to CLK. Changes to L at the rising edge of. In response to this, the output Dout of the selector 33 also changes to L. The one-cycle delayed capture data signal Dd output from the second D-FF 32 changes to L at the next rising edge of CLK that is further delayed by one cycle.

  As described above, in the operation example of FIG. 6, an operation of selecting a normal Dp and outputting it as Dout is performed.

FIG. 7 is a time chart illustrating still another operation example of the receiving circuit according to the second embodiment.
In the operation example shown in FIG. 7, Din does not change during monitoring in which Xcheck is valid, changes in a pulse shape during non-monitoring in which Xcheck is invalid, and is a case where noise is not determined. Since Xcheck is invalid, P-Data and N-Data do not change, and the same operation as when there is no normal noise is performed.

FIG. 8 is a time chart showing still another operation example of the receiving circuit of the second embodiment.
In the operation example shown in FIG. 8, Din changes from H to L during a period when Xcheck is invalid (during non-monitoring), and changes from L to H during a period when Xcheck is valid (during monitoring). This is a case where it is not determined that noise is mixed. In this operation example, since Xcheck is invalid and non-monitoring is in progress, the output N-Data of the D-FF 43 does not change with respect to the change of Din from H to L. On the other hand, in response to a change in the monitored Din from L to H when Xcheck is valid, the output P-Data of the D-FF 42 changes from L to H. However, since N-Data is L, the error signal Error output from the AND gate 44 is maintained at L, and Select remains L, and the same operation as in the case where there is no normal noise is performed.

  The operation of the receiving circuit of the second embodiment has been described above. In the second embodiment, the above operation is repeated every CLK cycle to continuously monitor noise contamination. Then, according to the monitoring result of noise contamination, the above operation is performed as appropriate. When the influence of noise occurs on the captured data Dp, the propagation of noise is prevented by using the data of the cycle before CLK. Protect the downstream circuit.

  The receiving circuit of the second embodiment is an example in which the input data signal Din is 1 bit. Next, a third embodiment applied when the data signal is a plurality of bits will be described.

FIG. 9 is a diagram illustrating a configuration of a receiving circuit according to the third embodiment.
The receiving circuit of the third embodiment takes in N-bit data signals Din0 to DinN-1 to be monitored transmitted through the N-bit parallel data bus 30 in synchronization with the clock signal CLK.

  The receiving circuit of the third embodiment includes N capture D-FF groups 31A, a holding D-FF group 32A, a selector group 33A, and a noise detection circuit 34A. The noise detection circuit 34A includes a phase shift circuit 35, a change detection circuit group 36A, and an inverter group 41A. Individual elements in each group perform the same operations as the corresponding elements in the second embodiment. In other words, the receiving circuit of the third embodiment provides the receiving circuit of the second embodiment in parallel for N bits except for the phase shift circuit 35, and uses the phase shift circuit 35 in common. Therefore, when noise is mixed in the data signal of each bit, each bit is replaced with the data of the previous cycle, but the other bits are not affected. Further explanation is omitted.

FIG. 10 is a diagram illustrating a configuration of a modified example of the receiving circuit according to the third embodiment. FIG. 10A illustrates the overall configuration, and FIG. 10B illustrates a circuit diagram of the switching signal generation circuit.
As shown in FIG. 10A, the receiving circuit of the modified example of the third embodiment is different from the circuit of FIG. 9 in that a switching signal generating circuit 38 is provided. The switching signal generation circuit 38 receives N selection signals Select0-SelectN-1 output from the N change detection circuit groups 36A of the noise detection circuit 34A, and outputs one selection signal Select. One selection signal Select is H if at least one of the N selection signals Select0-SelectN-1 is H.

  As shown in FIG. 10B, for example, the switching signal generation circuit 38 is realized by a multi-input OR gate 39 that receives N selection signals Select0-SelectN-1.

FIG. 11 is a diagram illustrating a configuration of a receiving circuit according to the fourth embodiment.
The receiving circuit of the fourth embodiment takes in the data signal Din to be monitored in synchronization with the clock signal CLK.

  The receiving circuit of the fourth embodiment includes an acquisition D-FF 31, a holding D-FF 32, a selector 33, and a noise detection circuit 34B. The noise detection circuit 34B includes a phase shift circuit 39, a change detection circuit 36, and an inverter 41. In other words, in the receiving circuit of the fourth embodiment, the phase shift circuit 39 is different from the phase shifting circuit of the receiving circuit of the second embodiment, and the other parts are the same.

  12A and 12B are diagrams showing a phase shift circuit 39 in the receiving circuit of the fourth embodiment. FIG. 12A is a circuit diagram and FIG. 12B is a time chart showing the operation.

  As shown in FIG. 12A, the phase shift circuit 39 includes a PLL macro circuit 71, a first frequency dividing D-FF 72, a second frequency dividing D-FF 73, and a third frequency dividing D-. FF74. The PLL macro circuit 71 receives a quadruple frequency CLK having a frequency four times that of the clock signal used for capture, and controls the phase of the quadruple frequency clock signal CLK to match the phase of the output C. The first frequency-dividing D-FF 72 divides the quadruple clock signal by two and outputs anti-phase two-frequency clock signals A and B. The second frequency dividing D-FF 73 divides the frequency-divided clock signal A by 2 and outputs the output C as the clock signal CLKB. The output C is fed back to the PLL macro circuit 71, and the PLL macro circuit 71 matches the phase of the quadruple clock signal with the phase of the output C. The clock signal CLKB is supplied as a clock signal to the capturing D-FF 31 and the holding D-FF 32. The third frequency dividing D-FF 74 divides the frequency-divided clock signal B by 2 and outputs the output D as the valid signal Xcheck.

  In FIG. 12B, A-D corresponds to each clock signal in FIG. The output D is a signal obtained by shifting the output C by ¼ phase. In other words, the valid signal Xcheck is a signal obtained by accurately shifting the clock signal CLKB supplied as a clock signal to the capturing D-FF 31 and the holding D-FF 32 by ¼ phase.

  The operation of the receiving circuit of the fourth embodiment is the same as that of the receiving circuit of the second embodiment. However, Xcheck accurately determines the clock signal CLKB of the D-FF 31 for capture and the D-FF 32 for holding to be 1 / This is a signal shifted by four phases. Therefore, the valid period of the valid signal Xcheck can be set more accurately with respect to the take-in timing (the rising edge of CLKB) of the take-in D-FF 31.

The receiving circuits according to the first to fourth embodiments described above are formed by only digital circuits without using an analog circuit that needs to be adjusted. Therefore, the receiving circuits can be applied to an FPGA and the like, and a logic simulation is also possible. The time required for verification can also be shortened.
In addition, the receiving circuits of the first to fourth embodiments have a small circuit scale and are low in cost, and effectively detect noise components mixed in the monitoring data every cycle. Furthermore, since the detection of noise contamination can be performed with a small delay, it has real-time characteristics and data protection for the subsequent circuit can be performed.

FIG. 13 is a diagram showing an example of a circuit device to which the receiving circuits of the first to fourth embodiments are applied, and shows an example applied to a microcomputer system.
The microcomputer system 80 includes a CPU 81, a ROM 82, a RAM 83, a peripheral (peripheral) device interface (I / F) 84, an I / O port 85, and an internal bus 86. The CPU 81, ROM 82, RAM 83, and peripheral I / F 84 are connected via an internal bus 86. The I / O port 85 is connected to the peripheral I / F 84 via a multi-bit parallel signal path, and receives data from a device external to the system. The I / O port 85 includes a multi-bit receiving circuit formed by the receiving circuits of the first to fourth embodiments having a noise protection function.

  Although the embodiment has been described above, it goes without saying that various modifications are possible. For example, the valid signal here is a ¼ shift signal of CLK, but other signals may be generated and used in accordance with the setup and hold periods.

  The embodiment has been described above, but all examples and conditions described herein are described for the purpose of helping understanding of the concept of the invention applied to the invention and technology. In particular, the examples and conditions described are not intended to limit the scope of the invention, and the construction of such examples in the specification does not indicate the advantages and disadvantages of the invention. Although embodiments of the invention have been described in detail, it should be understood that various changes, substitutions and modifications can be made without departing from the spirit and scope of the invention.

21 acquisition circuit 22 holding circuit 23 selection circuit 24 noise detection circuit

Claims (9)

A signal generation circuit for generating a first signal during a first period shorter than one cycle of the timing signal, including a timing of changing a potential of the timing signal;
A detection circuit that detects whether or not the potential of the second signal has changed during the first period in response to the first signal, and that generates an error signal when the second signal has changed; circuit. The timing signal is a first clock signal;
The noise detection circuit according to claim 1, wherein the signal generation circuit generates the first signal by shifting the phase of the first clock signal by ¼. The signal generation circuit includes:
A PLL circuit for adjusting a phase of a reference clock signal having a frequency N times that of the first clock signal and outputting a second clock signal;
A frequency dividing circuit that divides the second clock signal to generate the first clock signal and the first signal;
The noise detection circuit according to claim 2, wherein the PLL circuit matches a phase of the second clock signal with a phase of the first clock signal output from the frequency dividing circuit. The detection circuit includes:
A first latch circuit and a second latch circuit which are in an operation state in accordance with the first signal and whose output potential changes in accordance with a change in potential of the second signal and an inverted signal of the second signal;
4. A gate circuit that calculates a logical product of an output of the first latch circuit and an output of the second latch circuit and outputs an operation result as the error signal. 5. The noise detection circuit according to any one of claims.   The noise detection circuit according to claim 4, wherein the detection circuit includes a third latch circuit that latches the error signal according to a change in the potential of the first signal and outputs a selection signal. A first circuit that captures a first signal according to a timing signal, and outputs the captured first signal as a second signal;
A holding circuit that takes in the second signal output from the first circuit according to the timing signal and outputs the second signal as a third signal;
A noise detection circuit that detects whether or not the first signal has changed in a first period shorter than one cycle of the timing signal, including a change timing of the potential of the timing signal, and outputs a selection signal when it has changed When,
A selection circuit that receives the second signal and the third signal and outputs the second signal when the selection signal is not output, and outputs the third signal when the selection signal is output; Have
The noise detection circuit includes:
A signal generating circuit for generating a fourth signal during the first period;
Detecting whether or not the potential of the first signal has changed during the first period in response to the fourth signal, and detecting the output of the selection signal in synchronization with the end of the first period when it has changed A receiver circuit comprising: a circuit; The receiving circuit receives a plurality of the first signals, and has a plurality of the first circuits, a plurality of holding circuits, and a plurality of the selection circuits corresponding to the plurality of first signals,
The receiving circuit according to claim 6, wherein the noise detection circuit detects whether or not the plurality of first signals have changed in the first period.   The receiving circuit according to claim 7, wherein the noise detection circuit outputs the plurality of selection signals to the plurality of selection circuits according to whether or not the plurality of first signals have changed. .   The receiving circuit according to claim 7, wherein the noise detection circuit outputs the selection signal to the plurality of selection circuits when even one of the plurality of first signals changes.

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