JP2014534529A5 - - Google Patents

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Publication number
JP2014534529A5
JP2014534529A5 JP2014539104A JP2014539104A JP2014534529A5 JP 2014534529 A5 JP2014534529 A5 JP 2014534529A5 JP 2014539104 A JP2014539104 A JP 2014539104A JP 2014539104 A JP2014539104 A JP 2014539104A JP 2014534529 A5 JP2014534529 A5 JP 2014534529A5
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JP
Japan
Prior art keywords
interconnect circuit
request
banks
processor cores
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2014539104A
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English (en)
Japanese (ja)
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JP2014534529A (ja
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Publication date
Priority claimed from US13/285,629 external-priority patent/US9330002B2/en
Application filed filed Critical
Publication of JP2014534529A publication Critical patent/JP2014534529A/ja
Publication of JP2014534529A5 publication Critical patent/JP2014534529A5/ja
Pending legal-status Critical Current

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JP2014539104A 2011-10-31 2012-10-29 ネットワークプロセッサにおけるマルチコア相互接続 Pending JP2014534529A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/285,629 2011-10-31
US13/285,629 US9330002B2 (en) 2011-10-31 2011-10-31 Multi-core interconnect in a network processor
PCT/US2012/062378 WO2013066798A1 (en) 2011-10-31 2012-10-29 Multi-core interconnect in a network processor

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2017213851A Division JP6676027B2 (ja) 2011-10-31 2017-11-06 ネットワークプロセッサにおけるマルチコア相互接続

Publications (2)

Publication Number Publication Date
JP2014534529A JP2014534529A (ja) 2014-12-18
JP2014534529A5 true JP2014534529A5 (OSRAM) 2015-10-29

Family

ID=47144154

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2014539104A Pending JP2014534529A (ja) 2011-10-31 2012-10-29 ネットワークプロセッサにおけるマルチコア相互接続
JP2017213851A Active JP6676027B2 (ja) 2011-10-31 2017-11-06 ネットワークプロセッサにおけるマルチコア相互接続

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2017213851A Active JP6676027B2 (ja) 2011-10-31 2017-11-06 ネットワークプロセッサにおけるマルチコア相互接続

Country Status (6)

Country Link
US (1) US9330002B2 (OSRAM)
JP (2) JP2014534529A (OSRAM)
KR (2) KR102409024B1 (OSRAM)
CN (1) CN103959261B (OSRAM)
DE (1) DE112012004551B4 (OSRAM)
WO (1) WO2013066798A1 (OSRAM)

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US9892063B2 (en) * 2012-11-27 2018-02-13 Advanced Micro Devices, Inc. Contention blocking buffer
US9652396B2 (en) 2013-12-27 2017-05-16 Samsung Electronics Co., Ltd. Cache element processing for energy use reduction
US9811467B2 (en) * 2014-02-03 2017-11-07 Cavium, Inc. Method and an apparatus for pre-fetching and processing work for procesor cores in a network processor
US9432288B2 (en) 2014-02-28 2016-08-30 Cavium, Inc. System on chip link layer protocol
US10592459B2 (en) * 2014-03-07 2020-03-17 Cavium, Llc Method and system for ordering I/O access in a multi-node environment
US9372800B2 (en) 2014-03-07 2016-06-21 Cavium, Inc. Inter-chip interconnect protocol for a multi-chip system
US9411644B2 (en) 2014-03-07 2016-08-09 Cavium, Inc. Method and system for work scheduling in a multi-chip system
US9529532B2 (en) * 2014-03-07 2016-12-27 Cavium, Inc. Method and apparatus for memory allocation in a multi-node system
US9436972B2 (en) * 2014-03-27 2016-09-06 Intel Corporation System coherency in a distributed graphics processor hierarchy
US10235203B1 (en) * 2014-03-31 2019-03-19 EMC IP Holding Company LLC Techniques for increasing storage system performance in processor-bound workloads with large working sets and poor spatial locality
US10740236B2 (en) * 2017-05-12 2020-08-11 Samsung Electronics Co., Ltd Non-uniform bus (NUB) interconnect protocol for tiled last level caches
US10592452B1 (en) 2018-09-12 2020-03-17 Cavium, Llc Low latency interconnect protocol for coherent multi-chip communication
US11442868B2 (en) * 2019-05-24 2022-09-13 Texas Instruments Incorporated Aggressive write flush scheme for a victim cache

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JPS58220287A (ja) * 1982-06-15 1983-12-21 Nec Corp メモリアクセス制御装置
US4977498A (en) * 1988-04-01 1990-12-11 Digital Equipment Corporation Data processing system having a data memory interlock coherency scheme
JP4240610B2 (ja) * 1998-11-27 2009-03-18 株式会社日立製作所 計算機システム
JP2002149353A (ja) * 2000-11-08 2002-05-24 Nec Corp ディスクアレイ制御装置及びディスクアレイ制御方法
US7248585B2 (en) * 2001-10-22 2007-07-24 Sun Microsystems, Inc. Method and apparatus for a packet classifier
US7873785B2 (en) * 2003-08-19 2011-01-18 Oracle America, Inc. Multi-core multi-thread processor
US7133950B2 (en) 2003-08-19 2006-11-07 Sun Microsystems, Inc. Request arbitration in multi-core processor
US7290116B1 (en) 2004-06-30 2007-10-30 Sun Microsystems, Inc. Level 2 cache index hashing to avoid hot spots
US7606998B2 (en) * 2004-09-10 2009-10-20 Cavium Networks, Inc. Store instruction ordering for multi-core processor
US7941585B2 (en) * 2004-09-10 2011-05-10 Cavium Networks, Inc. Local scratchpad and data caching system
US20060112226A1 (en) * 2004-11-19 2006-05-25 Hady Frank T Heterogeneous processors sharing a common cache
US7477641B2 (en) * 2004-12-30 2009-01-13 Intel Corporation Providing access to data shared by packet processing threads
US7661006B2 (en) * 2007-01-09 2010-02-09 International Business Machines Corporation Method and apparatus for self-healing symmetric multi-processor system interconnects
US7793038B2 (en) * 2007-06-26 2010-09-07 International Business Machines Corporation System and method for programmable bank selection for banked memory subsystems
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US8195883B2 (en) * 2010-01-27 2012-06-05 Oracle America, Inc. Resource sharing to reduce implementation costs in a multicore processor

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