JP2014530422A - Method and buffer system for controlling buffer mapping - Google Patents

Abstract

The present invention relates to a method for controlling buffer mapping and a buffer system. The method includes changing a target data book that is mapped from at least one data block in the underlying storage medium to a buffer in the underlying storage medium at a preset time period. One or more data blocks in the underlying storage medium can be mapped to only one target data block in the buffer, the underlying storage medium buffer includes a flash memory medium, and the modified target data in the buffer The block contains the target data block with the maximum rewrite time in the current buffer. This technical solution optimizes the service life of the flash memory medium.

Description

  The present invention relates to a cache mapping technique for a cache system, and more particularly, to a method and a cache system for controlling cache mapping when a flash memory medium is used as a cache.

  A flash memory medium is a non-volatile storage having a long service life, and can maintain stored data information when power is turned off. In the prior art, flash memory media is a foundation that can be traditional disk storage systems such as hard disks and hard disk arrays to alleviate performance constraints caused by insufficient input / output performance of the underlying storage media. Often used as a cache for an underlying storage medium.

  In general, when a flash memory medium is used as a cache, the mapping policy adopted between the cache and the underlying storage medium is N-way set associative mapping. In N-way set associative mapping, depending on the size of the cache that serves as the mapping target, the underlying storage medium that serves as the mapping source is divided into multiple sets, where the capacity of each set is the cache capacity. Equal to size. Depending on the number and size of target data blocks contained in the cache, each set of underlying storage media is divided into the same number of regions (i.e., data blocks), and the size of each region is determined by the cache size. Matches the size of one of the target data blocks. Within one set of underlying storage media, different data blocks correspond to different target data blocks in the cache. Within a different set of underlying storage media, data blocks at corresponding locations are mapped to the same target data block in the cache.

  FIG. 1 shows an example of N-way set associative mapping. In this example, the flash memory medium that functions as a cache is divided into four target data blocks, target data block 0 to target data block 3, and the hard disk that functions as a mapping source includes two sets, each set The block is divided into data blocks corresponding to the four target data blocks in the cache, and the size of each data block in the hard disk matches the size of each target data block in the flash memory medium. In this example, the N-way set associative mapping relationship between the hard disk and the cache is as follows. That is, the data block 0 in the first set (including data block 0 to data block 3) and the data block 4 in the second set (including data block 4 to data block 7) of the hard disk are flash memory media. Is mapped to target data block 0 in the first set of hard disks, data block 1 in the first set of hard disks and data block 5 in the second set are mapped to target data blocks 1 in the flash memory medium, and Data block 2 in the first set and data block 6 in the second set are mapped to target data block 2 in the flash memory medium, and data block 3 in the first set of hard disks and in the second set Data block 7 is mapped to target data block 3 in the flash memory medium. Wrapped. According to this mapping relationship, data in data block 0 and data block 4 are cached in target data block 0, data in data block 1 and data block 5 are cached in target data block 1, data block 2 The data in the data block 6 is cached in the target data block 2, and the data in the data block 3 and the data block 7 is cached in the target data block 3.

  However, in the prior art, the mapping relationship between the cache and the underlying storage medium is generally static. The target data block in the cache, to which the data block in the underlying storage medium is mapped throughout the work process of the system, generally remains unchanged. As a result, when flash memory media is used as a cache, for application scenarios where data in the local area in the system is accessed abnormally frequently, the flash memory to which the frequently accessed data in the system is mapped The number of times of erasing the medium area of the medium is very high. Since the number of erases of flash memory media is limited, the media area of flash memory media to which frequently accessed data is mapped reaches the limit of erase counts more quickly than other areas, and as a result, The entire flash memory medium becomes unavailable.

  In view of the shortcomings of the prior art, embodiments of the present invention are a method and cache system for controlling cache mapping, wherein frequently accessed data on the system is directed to certain target data blocks on the cache. A cache mapping that is not statically mapped and that introduces a dynamic mapping policy between the cache and the underlying storage medium to optimize the service life of the flash memory medium acting as a cache. A method and cache system for controlling are provided.

  An embodiment of the present invention is a method for controlling cache mapping, the step of changing a target data block in a cache of an underlying storage medium at a preset time interval, the underlying storage medium At least one data block in the target is mapped to the target data block, and one or more data blocks in the underlying storage medium are mapped to only one target data block in the cache, and the underlying storage medium The method includes a step of modifying, wherein the cache includes a flash memory medium, and the modified target data block in the cache includes the target data block in the cache that currently has the maximum number of erases.

An embodiment of the present invention is a method for controlling cache mapping comprising:
Monitoring the number of erasures of each target data block in the cache of the underlying storage medium, where one or more data blocks in the underlying storage medium are only one target data block in the cache Monitoring the cache of the underlying storage medium mapped to and including the flash memory medium;
When the erase count difference between the target data block having the maximum erase count and the target data block having the minimum erase count in the cache reaches a preset erase threshold, at least in the underlying storage medium Modifying a target data block in the cache to which one data block is mapped, wherein the modified target data block in the cache includes a target data block in the cache that currently has the maximum number of erasures Step to change,
And continuously monitoring the number of erases generated after each target data block in the cache has been modified.

  An embodiment of the present invention is an underlying storage medium and a flash memory medium coupled to the underlying storage medium and functioning as a cache for the underlying storage medium, wherein one of the underlying storage media The step of changing the target data block in the cache of the underlying storage medium with a flash memory medium and a preset time interval in which one or more data blocks are mapped to only one target data block in the cache. At least one data block in the underlying storage medium is mapped to the target data block, and the modified target data block in the cache includes a target data block in the cache that currently has the maximum number of erasures, A professional configured to take steps to change To provide a cache system including a Tsu support.

An embodiment of the present invention is an underlying storage medium and a flash memory medium coupled to the underlying storage medium and functioning as a cache for the underlying storage medium, wherein one of the underlying storage media A flash memory medium in which one or more data blocks are mapped to only one target data block in the cache, monitoring the number of erases of each target data block in the cache, and maximum erasure in the cache When the difference in the number of erases between the target data block having the number of times and the target data block having the minimum number of erases reaches a preset erase threshold, at least one data block in the underlying storage medium is Change the target data block in the cache to be mapped A step, the steps changed target data block in the cache, containing the target data block having in the cache, the maximum number of erasures currently changing,
And a processor configured to continually monitor the number of erases generated after each target data block in the cache is modified.

  According to the method and apparatus of an embodiment of the present invention, a target data block in a cache to which at least one data block in an underlying storage medium is mapped is changed, and at least one data block is A data block corresponding to a target data block that currently has an erase count is included. In this way, the service life of the flash memory medium functioning as a cache is optimized.

  The objects, features, characteristics, and advantages of the present invention will become apparent from the following detailed description with reference to the accompanying drawings.

It is a figure which shows an example with N way set associative mapping. 2 is a schematic flowchart of a method for controlling cache mapping according to the first embodiment of the present invention; FIG. 6 is a schematic diagram of mapping relationships during different switching periods in an example of controlling cache mapping by employing the method according to the first embodiment of the present invention. FIG. 6 is a schematic diagram of mapping relationships during different switching periods in an example of controlling cache mapping by employing the method according to the first embodiment of the present invention. FIG. 6 is a schematic diagram of mapping relationships during different switching periods in an example of controlling cache mapping by employing the method according to the first embodiment of the present invention. FIG. 6 is a schematic diagram of mapping relationships during different switching periods in another example of controlling cache mapping by employing the method according to the first embodiment of the present invention. FIG. 6 is a schematic diagram of mapping relationships during different switching periods in another example of controlling cache mapping by employing the method according to the first embodiment of the present invention. FIG. 6 is a schematic diagram of mapping relationships during different switching periods in another example of controlling cache mapping by employing the method according to the first embodiment of the present invention. FIG. 6 is a schematic diagram of mapping relationships during different switching periods in another example of controlling cache mapping by employing the method according to the first embodiment of the present invention. FIG. 6 is a schematic diagram of mapping relationships during different switching periods in another example of controlling cache mapping by employing the method according to the first embodiment of the present invention. FIG. 6 is a schematic diagram of mapping relationships during different switching periods in another example of controlling cache mapping by employing the method according to the first embodiment of the present invention. 4 is a schematic flowchart of a method for controlling cache mapping according to a second embodiment of the present invention; FIG. 6 is a schematic diagram of mapping relationships in an example of controlling cache mapping by employing a method according to the second embodiment of the present invention. FIG. 6 is a schematic diagram of mapping relationships in an example of controlling cache mapping by employing a method according to the second embodiment of the present invention. 1 is a diagram illustrating a cache system according to an embodiment of the present invention. FIG.

  Embodiments of the present invention provide a method and cache system for controlling cache mapping. The method includes changing a target data block in a cache of an underlying storage medium at a preset time interval, wherein at least one data block in the underlying storage medium is mapped to the target data block; One or more data blocks in the underlying storage medium are mapped to only one target data block in the cache, the underlying storage medium cache includes a flash memory medium, and the modified target in the cache The data block includes a modifying step that includes a target data block in the cache that currently has the maximum number of erasures.

  Each embodiment of the invention is described in detail below with reference to the accompanying drawings.

  FIG. 2 is a schematic flowchart of a method for controlling cache mapping according to the first embodiment of the present invention. In this embodiment, a flash memory medium is used as a cache, the underlying storage medium is, for example, a hard disk, and one or more data blocks in the underlying storage medium are one target data in the cache. Mapped to block only. The flash memory medium includes a solid disk, that is, an SSD (solid storage disk).

  As shown in FIG. 2, the method for controlling cache mapping according to the first embodiment includes the following steps.

  Step S201. Triggering a timer to start timing according to a preset switching period T;

  Step S202: At least one data block in the hard disk is mapped to one target data block in the cache so that the number of erases of the target data block in the cache is close to each other after one switching cycle. A step of changing to each switching period of the switching cycle, wherein the number of switching periods included in one switching cycle is equal to or greater than the number N of target data blocks included in the cache.

  FIGS. 1 and 3 to 5 show specific examples of controlling cache mapping by employing the method according to the first embodiment of the present invention. In this example, each data block in the hard disk is mapped to a different target data block in the cache so that each data block in the hard disk is mapped to a different target data block in the cache during different switching periods of one switching cycle. The target data block is changed in each switching period of one switching period, and the number of switching periods included in one switching period is equal to the number N of target data blocks included in the cache. In this example, for example, but not by way of limitation, the cache has four target data blocks, the hard disk includes two sets, each set corresponding to four target data blocks in the cache. Divided into data blocks, the size of each data block in the hard disk matches the size of each target data block in the flash memory medium.

  As shown in Figures 1 and 3-5, this example employs a periodic round-robin dynamic switching policy, and the number of switching periods included in one switching period is included in the cache. Equal to the number of target data blocks N, where N is an integer greater than 0, and in this example N = 4. In this example, the mapping target corresponding to each data block in the hard disk is switched after each switching period. Each data block in the hard disk is mapped to a different target data block during different switching periods.

  Specifically, in this example, the mapping relationship shown in FIG. 1 is first employed. As shown in FIG. 1, in this example, initially, the mapping relationship between the hard disk and the cache is as follows. That is, hard disk data block 0 and data block 4 are mapped to cache target data block 0, hard disk data block 1 and data block 5 are mapped to cache target data block 1, and hard disk data block 2 and Data block 6 is mapped to target data block 2 of the cache, and data block 3 and data block 7 of the hard disk are mapped to target data block 3 of the cache. The number is the number of data blocks or target data blocks.

  At the end of the first switching period (referred to as the first period for short), the data cached in each target data block in the flash memory medium is migrated to another target data block The In this example, for example, the valid data currently cached in the target data block 0 in the flash memory medium is moved to the target data block 1, and the valid data currently cached in the target data block 1 is the target data block. 2, the valid data currently cached in the target data block 2 is moved to the target data block 3, and the valid data currently cached in the target data block 3 is moved to the target data block 0. After the data in the cache is moved, the target data block to which each data block in the hard disk is mapped is changed accordingly according to the movement in the data in the target data block. After this move, the mapping relationship obtained by modification is shown in FIG.

  Similarly, when the second period ends, valid data currently cached in the target data block 0 in the flash memory medium is moved to the target data block 1 and is currently cached in the target data block 1 Valid data is moved to target data block 2, valid data currently cached in target data block 2 is moved to target data block 3, and valid data currently cached in target data block 3 is target data block Moved to 0. After this move, the mapping relationship between the cache and the hard disk is modified according to this move, and the mapping relationship after the modification is shown in FIG.

  Similarly, when the third period ends, valid data currently cached in the target data block 0 in the flash memory medium is moved to the target data block 1 and is currently cached in the target data block 1 Valid data is moved to target data block 2, valid data currently cached in target data block 3 is moved to target data block 3, and valid data currently cached in target data block 3 is target data block Moved to 0. After this move, according to this modification, the mapping relationship between the cache and the hard disk is modified, and the mapping relationship after the modification, that is, the mapping relationship obtained by the modification is shown in FIG. Similarly, when the fourth period ends, after the move is performed, the mapping relationship is modified accordingly, and the mapping relationship obtained by modification is shown in FIG. 1, ie obtained by modification. The mapping relationship returns to the mapping relationship of the first period. In this way, one switching cycle ends. The switching process for the next switching period can then continue.

  In this embodiment, after moving the data cached in the target data block, the target data block to which the data block is mapped updates the cache metadata stored in the flash memory medium and / or in memory. This can be changed.

  In scenarios where local areas are frequently accessed, such as data blocks on a hard disk, frequently accessed local areas on the hard disk are not only statically mapped to fixed target data blocks, but also to flash memory. In order to extend and optimize the service life of the medium, frequently accessed data blocks in the hard disk are mapped to different target data blocks in the flash memory medium in each switching period of one switching period. Furthermore, after one round robin switching period as described above, the number of erases of the target data block in the flash memory medium is close to each other and close to the average value, and the service life of the flash memory medium is optimized As described above, the number of erasures of the target data block is evenly distributed.

  In this embodiment, in the dynamic switching of the mapping relationship, according to the number sequence of the target data blocks in the cache, the data in each target data block in the cache is the number of target data blocks in a round-robin fashion. Are moved to target data blocks having adjacent numbers. This example is merely an illustrative example and other round robin formats are applicable. For example, when the switchover period ends, the data currently cached in target data block 0 is moved to target data block 3, and the data currently cached in target data block 3 is moved to target data block 2. , The data currently cached in target data block 2 is moved to target data block 1, and the data currently cached in target data block 1 is moved to target data block 0 Data cached in the target data block is moved. Then, the target data block to which each data block in the underlying storage medium, such as the hard disk, is mapped is changed accordingly, and the mapping relationship between the hard disk and the cache is changed accordingly.

  Naturally, in addition to the round robin format described above, at least one of the underlying storage media in the underlying storage medium is subject to the proximity of the target data block erasures in the cache after one switch period. Other ways of changing the target data block in the cache to which the data block is mapped are also applicable. Proximity to each other may indicate that the number of erasures of the target data block is close to the average value.In detail, the difference in the number of erasures between the target data blocks is preset as the difference in the number of erasures. It means that it is less than the threshold. The difference threshold can be set according to requirements or specific application scenarios.

  When the periodic round robin dynamic switching policy is adopted, the user can flexibly set the switching period according to the application scenario, and the switching period is relatively short. However, every time the mapping target is switched, all valid data in the cache is moved so that a periodic round robin dynamic switching policy is more appropriate for caches with small capacity.

  6 to 11 show another example of controlling the cache mapping by adopting the method according to the first embodiment of the present invention. In this example, to change the target data block in the cache to which each data block in the hard disk is mapped so that the number of erases of the target data block in the cache is close to each other after one switching period A periodic-arrangement dynamic switching mapping policy is employed. In this example, the number of switching periods included in one switching period is equal to N × (N−1), where N is the number of target data blocks included in the cache and N is 0. It is a larger integer. For example, in this example, N = 3. Therefore, in this example, one switching cycle includes six switching periods.

  In this example, the flash memory medium is used as a cache and the underlying storage medium is used, for example, as a hard disk. For example, but not by way of limitation, the cache has three target data blocks, the hard disk contains two sets, each set corresponding to three data blocks, corresponding to the three target data blocks in the cache. The size of each divided data block in the hard disk matches the size of each target data block in the flash memory medium.

  In this example, the data cached in the target data block that currently has the maximum number of erases in the cache is in the cache other than the target data block that has the maximum number of erases in each switching period of one switching cycle. Is exchanged with the data cached in the target data block, the data in the latter target data block is exchanged a minimum number of times in the current switching period, and the latter target data block Unlike the target data block that exchanges data with the target data block that currently has the maximum number of erases in the switching period, i.e., the data is moved to each other and the corresponding data block in the hard disk is mapped to As the data cached in the target data block is moved, it is changed accordingly. Each target data block in the cache has N-1 opportunities to become the target data block with the maximum erase count, i.e., in one switching period, each target data block has a maximum erase count. Corresponding to the most frequently accessed data block in different N-1 periods.

  For example, at the beginning of the switching cycle, it is assumed that the target data block 0 in the flash memory medium has the maximum number of erases, which means that data block 0 and data block 3 in the hard disk mapped to the target data block 0 Indicates the most frequently accessed. In addition to the target data block 0, the target data block includes a target data block 1 and a target data block 2. As shown in FIG. 6, in this example, before the first period ends, the mapping relationship between the hard disk and the cache is as follows. That is, hard disk data block 0 and data block 3 are mapped to cache target data block 0, hard disk data block 1 and data block 4 are mapped to cache target data block 1, and hard disk data block 2 and Data block 5 is mapped to target data block 2 in the cache.

  In this example, for example, when the first period ends, valid data currently cached in the target data block 0 in the flash memory medium is moved to the target data block 1, and the current cache in the target data block 1 is The valid data being moved is moved to the target data block 0. The target data block in the cache and the data in the hard disk, where data block 0 and data block 3 in the hard disk are mapped according to the movement to the data in the target data block after the data in the cache is moved The target data block in the cache to which block 1 and data block 4 are mapped is changed accordingly. After this move, the mapping relationship obtained by modification is shown in FIG. At this point, the most frequently accessed data block 0 and data block 3 are mapped to the target data block 1.

  When the second period ends, valid data cached in the target data block 1 that currently has the maximum number of erases in the flash memory medium is moved to the target data block 2 and is cached in the target data block 2 The valid data being moved is moved to the target data block 1. After data movement in the cache, data block 0 and data block 3 in the hard disk are mapped according to movement in the target data block, target data block in the cache and data block 2 in the hard disk And the target data block in the cache to which the data block 5 is mapped are changed accordingly. After this move, the mapping relationship obtained by modification is shown in FIG. At this point, data block 0 and data block 3 in the hard disk, which are accessed most frequently, are mapped to target data block 2.

  At the end of the third period, valid data cached in the target data block 2 that currently has the maximum number of erases in the flash memory medium is moved to the target data block 0 and is cached in the target data block 0. The valid data being moved is moved to the target data block 2. Depending on the data movement in the target data block after the data movement in the cache. After this move, the mapping relationship obtained by modification is shown in FIG. At this point, data block 0 and data block 3 in the hard disk that are accessed most frequently are mapped to target data block 0.

  When the fourth period ends, valid data cached in the target data block 0 that currently has the maximum number of erases in the flash memory medium is moved to the target data block 1 and is cached in the target data block 1 The valid data being moved is moved to the target data block 0. After moving data in the cache, in response to moving data in the target data block. After this move, the mapping relationship obtained by modification is shown in FIG. At this point, data block 0 and data block 3 in the hard disk, which are accessed most frequently, are mapped to target data block 1.

  When the fifth period ends, valid data cached in the target data block 1 that currently has the maximum number of erases in the flash memory medium is moved to the target data block 2 and is cached in the target data block 2 The valid data being moved is moved to the target data block 1. Depending on the data movement in the target data block after the data movement in the cache. After this move, the mapping relationship obtained by modification is shown in FIG. At this point, data block 0 and data block 3 in the hard disk, which are accessed most frequently, are mapped to target data block 2.

  At the end of the sixth period, valid data cached in the target data block 2 that currently has the maximum number of erases in the flash memory medium is moved to the target data block 0 and is now cached in the target data block 0. The valid data being moved is moved to the target data block 2. Depending on the data movement in the target data block after the data movement in the cache. After this move, the mapping relationship obtained by modification is shown in FIG. At this point, one switching cycle ends, and from FIG. 6, the next switching cycle is continuously executed according to the switching order shown in FIGS.

  In this example, at the end of each period, the target data block that currently has the maximum number of erases, i.e., the target data block switching target to which the most frequently accessed data block is currently mapped, is the target data block's Selected according to a sequence of numbers. In other embodiments, when the number of target data blocks exceeds 3, the data in the switching target is exchanged with other target data blocks a maximum number of times in the current switching period, and the switching target The switching target is the target data block on the condition that it is an arbitrary target data block that is different from the target data block having the maximum number of erasures and the target data block that has just undergone data exchange in the switching period ahead of the cycle. Or may be selected without following the target data block sequence.

  In this embodiment, the target data to which the data block is mapped by updating cache metadata stored in the flash memory medium and / or in memory after movement of the data cached in the target data block It is possible to change the block.

  In scenarios where the local area is frequently accessed, such as data blocks in the hard disk, the frequently accessed local area in the hard disk is not always mapped to a fixed target data block, thereby enabling the service of flash memory media. In order to extend and optimize lifetime, frequently accessed data blocks in the hard disk are mapped to different target data blocks in the flash memory medium in each switching period of one switching period. In addition, after one periodic array switching period as described above, the number of erases of the target data block in the flash memory medium is close to each other and close to the average value, and the service life of the flash memory medium is optimized. As described above, the number of erases of the target data block is evenly distributed. Furthermore, by adopting the periodic array dynamic switching mapping policy of this embodiment, each time the mapping target is switched, only valid data in the two target data blocks in the cache is moved, which is serious for performance. It can be applied to caches of various sizes without affecting them.

  The cyclic dynamic mapping switching method between the underlying storage medium and the cache described above is an application scenario in which the service has a periodic rule, in particular, the service has a periodic rule in the system. Applicable to scenarios where the most frequently accessed data is stored in a fixed location on the hard disk.

  An embodiment of the present invention is a solution for controlling cache mapping, the step of monitoring the number of erasures of each target data block in the cache of the underlying storage medium, and in the underlying storage medium One or more data blocks are mapped to only one target data block in the cache, and the underlying storage media cache includes flash memory media, and monitoring the maximum number of erases in the cache A cache in which at least one data block in the underlying storage medium is mapped when the difference between the target data block having and the target data block having the minimum erase count reaches a preset erase threshold This is a step to change the target data block in The modified target data block in the cache is generated after the modification of each target data block in the cache, including the target data block in the cache that currently has the maximum number of erasures Further providing a solution comprising the step of continuously monitoring the number of erasures.

  FIG. 12 is a schematic flowchart of a method for controlling cache mapping according to the second embodiment of the present invention. In this embodiment, the flash memory medium is used as a cache, and the underlying storage medium is used, for example, as a hard disk. For example, but not by way of limitation, the cache has 4 target data blocks, the hard disk contains 2 sets, each set divided into 4 data blocks corresponding to the 4 target data blocks in the cache The size of each data block in the hard disk matches the size of each target data block in the flash memory medium.

  As shown in FIG. 12, the method for controlling cache mapping according to the present embodiment includes the following steps.

  Step S1201. Monitoring and recording the number of erases of each target data block in the cache.

  Step S1202. The target data block having the maximum number of erases when the erase number difference between the target data block having the maximum number of erases and the target data block having the minimum number of erases reaches a preset erase threshold in the cache Replacing the data cached in the data with the data cached in the target data block having the minimum number of erasures.

  Step S1203. In accordance with the exchange of the target data block, the target data block in the cache to which all data blocks currently mapped to the target data block having the maximum number of erases in the underlying storage medium are mapped accordingly. Changing to a target data block in the cache that is mapped to all data blocks currently mapped to the target data block having the minimum number of erasures. In particular, all data blocks currently mapped to the target data block having the maximum number of erases in the underlying storage medium are mapped to the target data block currently having the minimum number of erases, and the underlying storage medium Of all the data blocks currently mapped to the target data block having the minimum number of erasures are mapped to the target data block currently having the maximum number of erasures. Specifically, the mapping relationship between the data block in the hard disk and the target data block in the cache can be changed by changing the cache metadata.

  Step S1204. After the mapping between the hard disk and the cache is changed, the recorded number of erases of each target data block in the cache is reset, and the process returns to step S1201 to generate each after the mapping change. A step of continuously monitoring and recording the number of erasures of the target data block, and executing step S1203 and step S1204 when the condition is satisfied. For example, a counter can be used to record the number of erases of each target data block. After each mapping change, the counter is reset and then starts counting to record the number of erasures generated after the mapping change.

  FIGS. 1, 13, and 14 show specific examples of controlling cache mapping by employing the method according to the second embodiment of the present invention. In this example, it is initially assumed that the mapping relationship shown in FIG. 1 is adopted between the hard disk and the cache. As shown in FIG. 1, initially, the mapping relationship between the hard disk and the cache is as follows. That is, data block 0 and data block 4 in the hard disk are mapped to target data block 0 in the cache, data block 1 and data block 5 in the hard disk are mapped to target data block 1 in the cache, and data on the hard disk Block 2 and data block 6 are mapped to target data block 2 in the cache, and data block 3 and data block 7 of the hard disk are mapped to target data block 3 in the cache. The number of erases of each target data block in the cache is monitored.

  Assume that target data block 0 currently has a maximum number of erases and target data block 1 currently has a minimum number of erases. As data caching progresses, the number of erases of each target data block is monitored and recorded. When it is determined that the difference in the erase count between the target data block 0 and the target data block 1 has reached the erase threshold S, the data cached in the target data block 0 having the maximum erase count is the smallest All data blocks that are exchanged with data cached in target data block 1 with the number of erases and are currently mapped to target data block 0 in the hard disk (in this example, data block 0 and data Block 4) is mapped to target data block 1, and all data blocks currently mapped to target data block 1 (in this example, data block 1 and data block 5) are mapped to target data block 0 The change is performed. The mapping relationship after the change is shown in FIG. The number of erases of each target data block in the cache is then reset and the number of erases of each target data block in the cache generated after the mapping change is continuously monitored.

  In this example, it is assumed that the number of erases of the target data block 3 is minimized and the number of erases of the target data block 2 is maximized as data caching progresses after the previous exchange. When the difference in the number of erases between the target data block 2 and the target data block 3 reaches the erase threshold S, the data cached in the target data block 2 having the maximum erase number All data blocks that are exchanged with the data cached in the target data block 3 and are currently mapped to the target data block 2 in the hard disk (in this example, data block 2 and data block 6) Is mapped to target data block 3, and all data blocks currently mapped to target data block 3 (in this example, data block 3 and data block 7) are mapped to target data block 2. Executed. The mapping relationship after the change is shown in FIG. Then, the erase count of each target data block in the cache is reset, and the erase count of each target data block in the cache generated after the mapping change is continuously monitored and has the maximum erase count When the erase count difference between the target data block and the target data block with the minimum erase count reaches the preset erase threshold S, the hard disk and cache are similar in the manner described above. The mapping between is changed.

  By using this embodiment, the difference between the maximum erase count and the minimum erase count of the target data block in the flash memory medium and the difference between the maximum erase count and the minimum erase count of the erased block are As a result, it is ensured that the number of erases of each target data block is close to the average value. The difference in the number of erasures of the target data block in the flash memory medium can be controlled by setting the erasing threshold value S. This embodiment is particularly applicable to application scenarios where the service does not have a periodic phenomenon or has a non-trivial periodic phenomenon.

  In implementation of embodiments of the present invention, the number of erasures can be replaced with the number of replacements, which are monitored and recorded to perform dynamic mapping exchanges. As those skilled in the art will appreciate, the operation of replacing data in the cache with other written data is called cache replacement.

  For a specific application, the user may choose a dynamic mapping policy from the dynamic mapping policies described above according to the actual application scenario, adopt that dynamic mapping policy, and need a dynamic mapping policy. If not, it is possible to complete the dynamic mapping policy. Furthermore, after selecting a dynamic mapping policy, the user can set corresponding parameters such as switching period, switching period, and / or erasure threshold via the corresponding interface module according to actual needs. Is also possible. If no dynamic mapping policy is selected, the user can use a default mapping policy, eg, direct mapping, full associative mapping, and N-way set associative mapping.

  The switching method is frequently used in the underlying storage medium so that the target data block in the flash memory medium functioning as a cache does not reach the usage limit quickly, thereby extending the service life of the flash memory medium. In addition to the switching methods described above, other switching orders are used, provided that it allows the data in the data block being accessed not only to always correspond to a fixed target data block in the cache. Those skilled in the art should understand that the mapping switching method is also acceptable.

  Those skilled in the art will know that the service life of the flash memory medium is maximized when the switching method allows the number of erases of each target data block in the cache to be close to each other, eg close to the average value. I want you to understand.

  Reference is now made to FIG. 15, which illustrates a cache system according to an embodiment of the present invention.

  As shown in FIG. 15, a cache system 1500 according to this embodiment of the present invention includes an underlying storage medium 1510 and a flash memory that is coupled to the underlying storage medium and functions as a cache for the underlying storage medium. Medium 1520, with flash memory medium 1520, where one or more data blocks in the underlying storage medium are mapped to only one target data block in the cache, at preset time intervals Modifying the target data block in the cache of the storage medium, wherein at least one data block in the underlying storage medium is mapped to the target data block, and the modified target data block in the cache is Of the target data block that currently has the maximum number of erasures Including click, and a processor 1530 configured to perform the step of changing.

  A processor in the cache system is configured in the cache to which at least one data block in the underlying storage medium is mapped such that the number of erases of the target data block in the cache is close to each other after one switching period. The target data block is changed to each switching period of one switching period, and the number of switching periods included in one switching period is equal to or more than the number N of target data blocks included in the cache. It can be further configured to perform the changing step.

  A processor in the cache system is responsible for each in the underlying storage medium such that each data block in the underlying storage medium is mapped to a different target data block in the cache during different switching periods of one switching period. The target data block in the cache to which the data block is mapped is changed to each switching period of one switching period, and the number of switching periods included in one switching period is included in the cache. It can be further configured to perform a changing step equal to the number of target data blocks that have been generated.

  The processor in the cache system transfers the data of each target data block in the cache according to the sequence of the target data blocks in the cache, in a round robin manner in each switching period of one switching period. To the target data block having a number adjacent to the target data block, and according to the movement of the data in the target data block, the target data block to which each data block in the underlying storage medium is mapped is changed accordingly. Can be further configured to perform the following steps:

  The processor in the cache system transfers the data cached in the target data block currently having the maximum number of erasures in the cache other than the target data block having the maximum number of erasures in each switching period of one switching period. Replacing the data cached in the target data block in the cache, wherein the data in the latter target data block is exchanged a minimum number of times in the current switching period, the latter target data block being In the switching period prior to the current switching cycle, the target data block that currently has the maximum number of erasures is different from the target data block to exchange data, and the corresponding data block in the underlying storage medium is mapped Is And a step of changing the target data block accordingly, one switching period includes N × (N-1) switching periods, and in one switching period, in the cache Each target data block is a target data block having the maximum number of erases in the cache in different N-1 switching periods.

  An embodiment of the present invention is an underlying storage medium and a flash memory medium coupled to the underlying storage medium and functioning as a cache for the underlying storage medium, wherein one of the underlying storage media A flash memory medium in which one or more data blocks are mapped to only one target data block in the cache, monitoring the number of erases of each target data block in the cache, and maximum erasure in the cache When the difference in the number of erases between the target data block having the number of times and the target data block having the minimum number of erases reaches a preset erase threshold, at least one data block in the underlying storage medium is Change the target data block in the cache to be mapped The modified target data block in the cache includes the target data block in the cache that currently has the maximum number of erasures, and after each target data block in the cache is modified And a processor configured to continuously monitor the number of erasures generated in step (b).

  A processor in a cache system for exchanging data cached in a target data block having a maximum erase count with data cached in a target data block having a minimum erase count, and an underlying storage medium All of the data blocks currently mapped to the target data block having the maximum number of erases are mapped to the target data block having the minimum number of erases, and the target data block having the minimum number of erases in the underlying storage medium It is further configurable to perform a change accordingly, so that all currently mapped data blocks are mapped to the target data block having the maximum number of erases.

  Those skilled in the art will appreciate that the functions of the processor in apparatus 1500 can be implemented by software, hardware, or a combination of software and hardware.

  An embodiment of the present invention is a machine-readable storage medium for storing machine-executable instructions, wherein when the machine-executable instructions are executed, the machine caches an underlying storage medium at preset time intervals. Modifying a target data block within the underlying storage medium, wherein at least one data block in the underlying storage medium is mapped to the target data block and one or more data blocks in the underlying storage medium are cached Target data that is mapped to only one target data block in the cache, the underlying storage medium cache contains a flash memory medium, and the modified target data block in the cache currently has the maximum number of erases in the cache It is possible to carry out changing steps, including blocks Further provides a machine-readable storage medium.

  The method maps at least one data block in the underlying storage medium such that the number of erasures of the target data block in the cache are close to each other after the following steps: one switching period The step of changing the target data block in the cache to each switching period of one switching cycle, wherein the number of switching periods included in one switching cycle is the number of target data blocks included in the cache It may further include a changing step that is greater than or equal to N.

  The method includes the following steps: an underlying storage medium such that each data block in the underlying storage medium is mapped to a different target data block in the cache during different switching periods of one switching period The target data block in the cache to which each data block in the cache is mapped is changed to each switching period of one switching period, and the number of switching periods included in one switching period is the cache. It may further comprise a changing step equal to the number N of target data blocks contained within.

  The transmission step described above consists of round-robin the data of each target data block in the cache in each switching period of one switching cycle according to the following steps: a sequence of target data blocks in the cache. In the manner, each data block in the underlying storage medium is mapped in accordance with the step of moving to a target data block having a number adjacent to the number of target data blocks and the movement of data in the target data block And further modifying the target data block accordingly.

  The detection step described above consists of the following steps: erasing the data cached in the target data block that currently has the maximum number of erasures in each switching period of one switching period. Replacing the data cached in the target data block in the cache other than the target data block having a number of times, the data in the latter target data block being exchanged a minimum number of times in the current switching period, The latter target data block is different from the target data block that exchanges data with the target data block that currently has the maximum number of consumptions in the switching period before the current switching cycle, and the underlying storage medium Corresponding data block in And changing the target data block to which the mapping is mapped accordingly, wherein one switching period includes N × (N−1) switching periods, and in one switching period Each target data block in the cache is a target data block having the maximum number of erases in the cache in different N-1 switching periods.

  An embodiment of the present invention is a machine-readable storage medium for storing machine-executable instructions, wherein when the machine-executable instructions are executed, each machine in the cache of the underlying storage medium Monitoring the number of times data blocks are erased, wherein one or more data blocks in the underlying storage medium are mapped to only one target data block in the cache, and the underlying storage medium cache is The monitoring step, including the flash memory medium, and the erase count difference between the target data block with the maximum erase count and the target data block with the minimum erase count in the cache reach a preset erase threshold. At least one data block in the underlying storage medium is mapped Modifying a target data block in the cache, wherein the modified target data block in the cache includes a target data block in the cache that currently has the maximum number of erasures, and each in the cache Further providing a machine-readable storage medium capable of performing the step of continuously monitoring the number of erasures generated after the target data block has been modified.

  The method is based on the following steps: exchanging data cached in a target data block having a maximum number of erases with data cached in a target data block having a minimum number of erases, and All data blocks currently mapped to the target data block with the maximum number of erases in the underlying storage medium are mapped to the target data block with the minimum number of erases and have the minimum number of erases in the underlying storage medium And further performing a corresponding change such that all data blocks currently mapped to the target data block are mapped to the target data block having the maximum number of erasures.

  Various modifications and changes may be made to the methods and apparatus disclosed in the embodiments of the present invention without departing from the essence of the present invention, and these modifications and changes fall within the protection scope of the present invention. It should be understood by those skilled in the art. Therefore, the protection scope of the present invention should be subject to the appended claims.

1500 cash system, equipment
1510 Storage media
1520 Flash memory media
1530 processor

At the end of the third period, valid data cached in the target data block 2 that currently has the maximum number of erases in the flash memory medium is moved to the target data block 0 and is cached in the target data block 0. The valid data being moved is moved to the target data block 2. Target data block in cache and data in hard disk, where data block 0 and data block 3 in hard disk are mapped according to data movement in target data block after data movement in cache The target data block in the cache to which block 1 and data block 4 are mapped is changed accordingly . After this move, the mapping relationship obtained by modification is shown in FIG. At this point, data block 0 and data block 3 in the hard disk that are accessed most frequently are mapped to target data block 0.

When the fourth period ends, valid data cached in the target data block 0 that currently has the maximum number of erases in the flash memory medium is moved to the target data block 1 and is cached in the target data block 1 The valid data being moved is moved to the target data block 0. The target data block in the cache and the data in the hard disk, where data block 0 and data block 3 in the hard disk are mapped according to the movement to the data in the target data block after the data in the cache is moved The target data block in the cache to which block 2 and data block 5 are mapped is changed accordingly . After this move, the mapping relationship obtained by modification is shown in FIG. At this point, data block 0 and data block 3 in the hard disk, which are accessed most frequently, are mapped to target data block 1.

When the fifth period ends, valid data cached in the target data block 1 that currently has the maximum number of erases in the flash memory medium is moved to the target data block 2 and is cached in the target data block 2 The valid data being moved is moved to the target data block 1. Target data block in cache and data in hard disk, where data block 0 and data block 3 in hard disk are mapped according to data movement in target data block after data movement in cache The target data block in the cache to which block 1 and data block 4 are mapped is changed accordingly . After this move, the mapping relationship obtained by modification is shown in FIG. At this point, data block 0 and data block 3 in the hard disk, which are accessed most frequently, are mapped to target data block 2.

At the end of the sixth period, valid data cached in the target data block 2 that currently has the maximum number of erases in the flash memory medium is moved to the target data block 0 and is now cached in the target data block 0. The valid data being moved is moved to the target data block 2. Target data block in cache and data in hard disk, where data block 0 and data block 3 in hard disk are mapped according to data movement in target data block after data movement in cache The target data block in the cache to which block 2 and data block 5 are mapped is changed accordingly . After this move, the mapping relationship obtained by modification is shown in FIG. At this point, one switching cycle ends, and from FIG. 6, the next switching cycle is continuously executed according to the switching order shown in FIGS.

Claims (15)

A method for controlling cache mapping, comprising:
Changing the target data block in the cache of the underlying storage medium at a preset time interval;
At least one data block in the underlying storage medium is mapped to the target data block;
One or more data blocks in the underlying storage medium are mapped to only one target data block in the cache;
The cache of the underlying storage medium includes a flash memory medium;
The method, wherein the modified target data block in the cache includes a target data block in the cache that currently has a maximum number of erases. Changing a target data block in a cache of an underlying storage medium at a preset time interval, wherein at least one data block in the underlying storage medium is mapped to the target data block; Said step is
Target data in the cache to which at least one data block in the underlying storage medium is mapped such that the number of erasures of the target data block in the cache is close to each other after one switching period Changing the block to each switching period of the one switching period, wherein the number of switching periods included in the one switching period is equal to or greater than the number N of the target data blocks included in the cache The method of claim 1, comprising the step of modifying. Changing a target data block in a cache of an underlying storage medium at a preset time interval, wherein at least one data block in the underlying storage medium is mapped to the target data block; The step includes
Each data block in the underlying storage medium such that each data block in the underlying storage medium is mapped to a different target data block in the cache during different switching periods of one switching period. Changing the target data block in the cache to which is mapped in each switching period of one switching period,
2. The method according to claim 1, wherein the number of switching periods included in one switching period is equal to the number N of the target data blocks included in the cache. Changing the target data block in the cache to which each data block in the underlying storage medium is mapped in each switching period of the one switching period;
According to the sequence of the target data blocks in the cache, the data of each target data block in the cache is adjacent to the number of the target data blocks in a round robin manner in each switching period of one switching period. Moving to a target data block having a number, and changing the target data block to which each data block in the underlying storage medium is mapped according to the movement of the data in the target data block Steps,
4. The method of claim 3, comprising: Changing a target data block in a cache of an underlying storage medium at a preset time interval, wherein at least one data block in the underlying storage medium is mapped to the target data block; The step includes
Data cached in a target data block that currently has the maximum number of erases in the cache is replaced with a target in the cache other than the target data block having the maximum number of erases in each switching period of one switching cycle. Exchanging with data cached in a data block, wherein the data in the latter target data block is exchanged a minimum number of times within a current switching period, the latter target data block being Replacing a target data block that exchanges data with the target data block that currently has the maximum number of erasures in a switching period before the switching cycle of:
Changing accordingly the target data block to which the corresponding data block in the underlying storage medium is mapped;
Including
The one switching cycle includes N × (N-1) switching periods,
2. The target data block of the cache in the one switching period is a target data block having the maximum number of erasures in the cache in different N−1 switching periods. The method described in 1. A method for controlling cache mapping, comprising:
Monitoring the number of erasures of each target data block in a cache of an underlying storage medium, wherein one or more data blocks in the underlying storage medium are one target data in the cache Monitoring, wherein only the block is mapped and the cache of the underlying storage medium includes a flash memory medium;
The underlying storage medium when the difference in the erase count between the target data block having the maximum erase count and the target data block having the minimum erase count in the cache reaches a preset erase threshold Changing the target data block in the cache to which at least one data block in the cache is mapped, wherein the changed target data block in the cache is the maximum number of erasures in the cache. Including a target data block that currently has
Continuously monitoring the number of erasures generated after each target data block in the cache is modified. Changing the target data block in the cache to which at least one data block in the underlying storage medium is mapped;
Exchanging data cached in the target data block having the maximum number of erases with data cached in the target data block having the minimum number of erases, in the underlying storage medium; All data blocks currently mapped to the target data block having the maximum erase count are mapped to the target data block having the minimum erase count, and the minimum erase count in the underlying storage medium is Performing a change accordingly such that all data blocks currently mapped to the target data block having are mapped to the target data block having the maximum number of erasures. the method of. The underlying storage medium,
A flash memory medium coupled to the underlying storage medium and functioning as a cache for the underlying storage medium, wherein one or more data blocks in the underlying storage medium are stored in the cache. A flash memory medium that is mapped to only one target data block;
A processor configured to change a target data block in the cache of the underlying storage medium at preset time intervals;
Comprising
At least one data block in the underlying storage medium is mapped to the target data block;
The cache system, wherein the modified target data block in the cache comprises a target data block in the cache that currently has a maximum number of erases. The processor is
Target data in the cache to which at least one data block in the underlying storage medium is mapped such that the number of erasures of the target data block in the cache is close to each other after one switching period Changing the block to each switching period of the one switching period, wherein the number of switching periods included in the one switching period is equal to or greater than the number N of the target data blocks included in the cache 9. The cache system of claim 8, further configured to perform the modifying step. The processor is
Each data block in the underlying storage medium is mapped to a different target data block in the cache in a different switching period of one switching period so that each data block in the underlying storage medium is mapped to a different target data block in the cache. Further configured to change the target data block in the cache to be mapped to each switching period of the one switching period;
9. The cache system according to claim 8, wherein the number of switching periods included in the one switching period is equal to the number N of the target data blocks included in the cache. The processor is
According to the sequence of the target data blocks in the cache, the data of each target data block in the cache is adjacent to the number of target data blocks in a round robin manner in each switching period of the one switching period. Further configured to move to a target data block having a matching number,
11. The cache according to claim 10, wherein in response to movement of data in the target data block, a target data block to which each data block in the underlying storage medium is mapped is changed accordingly. system. The processor is
Data cached in the target data block currently having the maximum number of erasures in the cache is stored in the cache other than the target data block having the maximum number of erasures in each switching period of one switching cycle. Exchanging with data cached in the target data block, the data in the latter target data block being exchanged a minimum number of times in the current switching period, the latter target data block being In the previous switching period, the target data block that exchanges data with the target data block that currently has the maximum number of erasures is different,
Further configured to change accordingly the target data block to which the corresponding data block in the underlying storage medium is mapped,
The one switching cycle includes N × (N-1) switching periods,
In the one switching cycle, each target data block of the cache is different in the N-1 switching period, claim, characterized in that said a target data block having the maximum number of erasures in the cache 6 The cache system described in. The underlying storage medium,
A flash memory medium coupled to the underlying storage medium and functioning as a cache for the underlying storage medium, wherein one or more data blocks in the underlying storage medium are stored in the cache. A flash memory medium that is mapped to only one target data block;
Monitoring the number of erases of each target data block in the cache;
The underlying storage medium when the difference in the erase count between the target data block having the maximum erase count and the target data block having the minimum erase count in the cache reaches a preset erase threshold Changing the target data block in the cache to which at least one data block in the cache is mapped, wherein the changed target data block in the cache is the maximum number of erasures in the cache. Including a target data block that currently has
A processor configured to continuously monitor the number of erases generated after each target data block in the cache has been modified. The processor is
Exchanging data cached in the target data block having the maximum number of erases with data cached in the target data block having the minimum number of erases, in the underlying storage medium; All data blocks currently mapped to the target data block having the maximum erase count are mapped to the target data block having the minimum erase count, and the minimum erase count in the underlying storage medium is And further performing a change accordingly, such that all data blocks currently mapped to the target data block having are mapped to the target data block having the maximum number of erasures , Contract Cache system according to claim 13.   A machine-readable storage medium for storing machine-executable instructions, wherein when the machine-executable instructions are executed, the machine can execute the steps of any one of claims 1 to 7 A machine-readable storage medium.

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