JP4829202B2 - Storage device and memory control method - Google Patents

Description

  The present invention relates to a storage device and a memory control method, and more particularly to a storage device that performs writing / reading of relatively small data using a nonvolatile semiconductor memory and a control method thereof.

  Generally, a magnetic disk storage device has been conventionally used as an auxiliary storage device for information equipment. In this magnetic disk storage device, data writing and reading units are divided into storage units called sectors and stored on a magnetic disk.

  In this conventional magnetic disk storage device, data rewriting is basically performed at the same recording position on the magnetic disk. Further, the magnetic disk storage device stores the magnetic head by accessing the recording position on the magnetic disk while rotating the magnetic disk serving as a storage medium.

  On the other hand, in recent years, auxiliary storage devices using a semiconductor memory as a storage medium have attracted attention. In particular, the use of electrically erasable and rewritable nonvolatile semiconductor memories (for example, EEPROM (Electrically Erasable Programmable Read Only Memory) or a kind of flash memory) is the mainstream of auxiliary storage devices of information equipment. It has become.

  Conventionally, as a memory control method for such a nonvolatile semiconductor memory, a method is known in which the number of times of rewriting a physical block, which is an erasure unit, is counted, and when a predetermined number of times is reached, a transition is made to a spare block. This memory control system further divides the block, counts the number of rewrites in each area, and performs control to shift to a spare area when the number reaches a certain number (see Patent Document 1).

  A memory controller that is connected to a flash memory and controls access from the host system to the flash memory has been proposed. This flash memory has a storage area containing a plurality of physical blocks consisting of a plurality of pages, and data is erased in units of physical blocks, and data is written in units of pages in the erased portion of the physical blocks. Possible memory. Erase or write control of these data is performed by the memory controller.

In addition, in this flash memory, a part of a plurality of pages of each physical block is used as an original data storage unit for writing data before rewriting. In addition, pages other than the original data storage unit are used as update data storage units for writing the rewritten data, and when rewritten data is given from the host system, these are written to the update data storage unit. (See Patent Document 2).
JP 2000-20252 A JP 2007-94571 A

  A flash memory, which is a kind of the above-described nonvolatile memory, is an electrically erasable and rewritable PROM (Programmable Read Only Memory), and the above-mentioned EEPROM (Electrically Erasable PROM) is also a kind thereof. Therefore, the data writing unit and the erasing (rewriting) unit are not the same, and the erasing unit is extremely large.

  Therefore, in order to rewrite data once written, many other data must be erased at the same time. Therefore, when handling a large amount of data as in the technique described in Patent Document 1, the number of times of rewriting in a specific area is managed without worrying about the erasing unit, and when the frequency of rewriting is high, the shift to the replacement area is performed. Like that.

  However, if the same management is performed when handling a small amount of data, an area larger than the memory area to be rewritten is erased each time rewriting is performed. For this reason, there arises a problem that the response performance deteriorates due to the erasing operation or the write position specifying operation that occurs each time. Further, there arises a problem that the allowable number of rewrites of the memory device cannot be secured sufficiently.

  In the technique described in Patent Document 2, when the rewrite data is written, the rewrite data is written into the page of the update data storage unit corresponding to the page of the original data storage unit. There arises a problem that as many as the number of pages in the original data storage section must be prepared.

  For this reason, when rewriting concentrates on a specific page in the original data storage unit, there is a problem that a data portion that is not updated is wasted because the block is replaced without being rewritten.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a storage device and a memory control method capable of reducing the influence of restrictions on the number of erasures of a semiconductor memory and reducing an unnecessary occupied area after rewriting without degrading response performance due to rewriting. Is to provide.

  In order to solve the above problems, a storage device according to the present invention includes a nonvolatile semiconductor memory that erases data in units of physical blocks larger than a unit for writing and reading data to and from a storage area, and an instruction from an external host system. And a memory control unit for controlling reading or writing to the semiconductor memory.

  Here, the storage area is composed of a data block composed of one or a plurality of physical blocks and a replacement block composed of one or a plurality of physical blocks. The data block includes a data area for storing data and an erased block. It consists of a replacement area where data stored in the data area can be rewritten. The replacement block is controlled by the memory control device so as to have an erased area.

Here, the replacement block is controlled so that valid data in the data block can be written to the erased area.
Further, after valid data is written in the replacement block, the data block is controlled so that the data area and the replacement area are erased areas so that they become candidates for the replacement block.

  According to the present invention, even if the semiconductor memory to be used erases data in units of physical blocks larger than the unit of data writing and reading, it is necessary to erase the semiconductor memory for each writing. Therefore, the response performance at the time of writing can be drastically improved.

In addition, since the erasure of the semiconductor memory does not occur every writing, the restriction on the number of erasures of the semiconductor memory can be relaxed.
Further, since “read-modify-write” is not performed for each writing, the response performance can be improved. In addition, since the update data is not associated with each original data, the usability of the overall memory capacity can be improved.

Hereinafter, embodiments of the present invention will be described with reference to FIGS.
FIG. 1 is a diagram showing an example of a hardware configuration for realizing an embodiment of the present invention.
First, the hardware configuration of this embodiment will be described with reference to FIG.

The storage device 6 shown in FIG. 1 is connected to the host device 3 via the data bus 4 so as to be accessible.
The storage device 6 includes a memory control unit 1 and a semiconductor memory 2. The memory control unit 1 includes a microprocessor 11, a memory I / F (interface) control unit 12, a host I / F control unit 13, and a memory 14.

  The microprocessor 11 constructs a logical storage area corresponding to the physical storage area of the storage device 6 in the semiconductor memory 2 and controls writing and reading of data to and from this logical storage area.

  The memory I / F control unit 12 performs access control with the semiconductor memory 2 according to an instruction from the microprocessor 11. Note that the memory I / F control unit 12 is not necessarily required if the microprocessor 11 can directly control the semiconductor memory 2.

  The host I / F control unit 13 controls data transmission / reception with the host device 3 in accordance with data write / read requests from the host device 3. Data write and read requests from the host device 3 are made to a logical storage area constructed in the semiconductor memory 2.

The memory 14 has a logical / physical conversion table 141, a next write page management table 142, a replacement block list table 143, an erase count management table 144, and an erase candidate management table 145.
In the embodiment of the present invention, a memory element such as SRAM (Static Random Access Memory), DRAM (Dynamic RAM), or MRAM (Magneto-resistive RAM) can be used, although the type of memory is not mentioned.

  In the present embodiment, only the configuration of various tables necessary for explanation is described. The contents of the table are set by the microprocessor 11 when the storage device 6 itself is initialized. Further, details of the updating method of each table are not mentioned here.

  The logical / physical conversion table 141 in the memory 14 is a table that associates a logical address indicated by an access from the host device 3 with a physical address on the semiconductor memory 2.

Here, before entering the description of FIG. 2 and subsequent figures, the table configuration in the memory 14 of FIG. 1 described above will be described based on FIGS.
FIG. 7 is a diagram illustrating a configuration example of the logical / physical conversion table 141. 7A shows an initial state, FIG. 7B shows a state after page rewriting, and FIG. 7C shows a state after block replacement.
The logical / physical conversion table 141 includes a logical address 1410 indicated by an access from the host device 3 and a physical address 1411 including a block number and a page number on the semiconductor memory 2.

  Note that the configuration of the logical / physical conversion table 141 shown in FIG. 7 can be easily expanded even when there are a plurality of semiconductor memories 2 by adding a chip number in addition to a block number and a page number.

  The physical address 1411 shown in FIG. 7 changes in the value of the physical address 1411 by an operation described later. For example, the initial state shown in FIG. 7A, the state after page rewriting shown in FIG. 7B, or the state after block replacement shown in FIG. Change to.

  The next write page management table 142 is a table for storing the top address of the page to be written next to each block. FIG. 8 shows a configuration example of the next write page management table 142. 8A shows the initial state, FIG. 8B shows the page after rewriting, and FIG. 8C shows the block replacement.

  The next write page management table 142 includes a block number 1420 indicating the number of each block and a next write page 1421 indicating each page to be written next time. For example, the next write page management table 142 changes to an initial state shown in FIG. 8A, a state after page rewriting shown in FIG. 8B, or a block change shown in FIG. 8C.

The replacement block list table 143 is a table in which blocks to be used next in the replacement block 23 shown in FIG. 3 are arranged. FIG. 9 shows a configuration example of the replacement block list table 143. FIG. 9A shows an initial state, and FIG. 9B shows after block replacement.
The replacement block list table 143 is arranged in the order in which the numbers of usable replacement blocks are used, and when the replacement block is used, for example, the state is changed from the initial state shown in FIG. 9A to the state after the block replacement shown in FIG. 9B. Change.

The erase count management table 144 is a table that holds the erase count of each block. FIG. 10 shows a configuration example of the erase count management table 144. FIG. 10A shows an initial state, and FIG. 10B shows after block replacement processing.
The erasure management table 144 is composed of the block number 1440 of each block and the erase count 1441 of the corresponding block. When the data existing in each block is erased, for example, the initial state shown in FIG. 10A changes to the state after the replacement process shown in FIG. 10B.

The erase candidate management table 145 is a table in which block numbers of blocks to be erased are arranged in the order of erase. FIG. 11 shows a configuration example of the deletion candidate management table 145. FIG. 11A shows an initial state (a state that has never been erased), and FIG. 11B shows a state after block replacement processing.
When a block is erased, the erase candidate management table 145 changes from the initial state shown in FIG. 11A to the state after the block replacement process shown in FIG. 11B.

  The above is the configuration of each table in the memory 14 of FIG. 1 shows only one semiconductor memory 2 for simplification of explanation, the semiconductor memory 2 corresponds to the logical storage area of the storage device 6 as described above. It goes without saying that a plurality of semiconductor memories can be connected and used by managing the physical storage area.

  FIG. 2 is a diagram showing an internal configuration of the semiconductor memory 2 premised on the embodiment of the present invention. FIG. 2 shows a logical storage area constructed in the semiconductor memory 2. The host device 3 shown in FIG. 1 recognizes only this logical storage area for the storage device 6.

  The number 21 in the figure indicates the minimum unit of data erasure, which is called a block. Similarly, the number 211 indicates the minimum unit of data reading and writing, and this is called a page. In FIG. 2, the logical storage area of the semiconductor memory 2 is composed of one or more blocks 21, and the block 21 is composed of one or more pages 211. That is, the logical storage area of the semiconductor memory 2 has m blocks 21 from block 1 to block m (integer), and each block includes n blocks from page 1 to page n (integer). Has a page.

As described above, the host device 3 exchanges data with the storage device 6 via the data bus 4. Here, the data bus 4 is, for example, a SCSI (Small Computer System Interface). Or ATA (Advanced Technology Attachment) is used. However, the embodiment of the present invention is not limited to these data buses, and other data buses can be used as a matter of course.
Data exchange between the semiconductor memory 2 and the memory control unit 1 is performed by the data bus 5. The storage device 6 is a device that stores data based on an instruction from the host device 3.

Next, the use mode of the memory for realizing the memory control system which is a feature of the embodiment of the present invention will be described with reference to FIG.
FIG. 3 is a diagram showing how the memory is used to realize the memory control system that is a feature of the embodiment of the present invention. The logical storage constructed in the semiconductor memory 2 under the control of the memory control unit 1 Indicates the area.

Reference numeral 2 in the figure indicates a logical storage area of the entire memory chip, and its central structure is composed of a data block 22 and a replacement block 23.
The data block 22 is a block composed of one or a plurality of blocks for storing data, and has logical blocks from a block 1 to a block p (integer). Each block includes a data page 222 and a replacement page 223 as shown in the figure.

  The data page 222 has pages that hold data from page 1 to page q (integer), and the replacement page 223 has pages (q + 1) to page n (integer). The replacement page 223 is an erased rewritable page.

  The replacement block 23 is an erased replacement block from the block (p + 1) to the block m (integer), and each block includes erased pages 232 from page 1 to page n (integer). ing.

  Here, the data page 222 is an area where the user can read and write data in accordance with an instruction from the host device. Since the data page 222 cannot be overwritten due to restrictions of the semiconductor memory 2, the overwritten data after the overwriting process under the control of the memory control unit 1 is stored in the replacement page 223.

  If the replacement page 223 cannot be stored, a replacement block 23 is newly allocated and written. At this time, the overwritten data of the replacement page 223 and the non-overwritten data of the data page 222, which are valid portions after the overwriting process, are copied and replaced in the replacement block 23. Further, the replacement page 223 and the data page 222 after replacement are erased to be candidates for the replacement block 23.

  Block p and page q in FIG. 3 are set as initial values when the storage device 6 is manufactured in this embodiment. The setting method of the block p and the page q is not particularly limited, but may be set in advance on a memory or connected to a microprocessor 11 with a debugger.

  Further, it can be realized by issuing and setting a predetermined command from the host device 3. Further, it is possible to manage the table by making the block p and the page q variable, but in this embodiment, they are handled as fixed values for the sake of simplicity.

Based on the above, the operation of the present embodiment will be described based on the flowcharts of FIGS.
The flowcharts shown in FIG. 4 to FIG. 6 show the procedure of the write process and the related block replacement process and block erase process, which are the features of the embodiment of the present invention.
First, processing when a data write request is received from the host apparatus 3 will be described with reference to FIGS.

[Write processing]
The flowchart of FIG. 4 is a flowchart of the writing process to the semiconductor memory 2 of the microprocessor 11. The processing flow will be described below.
First, the microprocessor 11 receives a logical address, data, and data size from the host device 3 via the host I / F control unit 13 (step S700).

  Next, the microprocessor 11 refers to the logical / physical conversion table 141 shown in FIG. 7 in order to confirm the physical address of the semiconductor memory 2 to be written, and the physical address indicating the corresponding block number from the logical address 1410. 1411 is specified (step S701).

  For example, if the logical address 1410 from the host device 3 is 1 when the state of the logical / physical conversion table 141 is the initial state of FIG. 7A, the block number is block 1 of 141.

Next, the microprocessor 11 refers to the next write page management table 142 shown in FIG. 8 and identifies the first next write page 1421 in order to confirm which page in the identified block should be written. (Step S702).
For example, when the next write page management table 142 is in the initial state shown in FIG. 8A, if block 1 is specified in step S701, the next write page 1421 is q + 1.

  Next, in order to confirm whether the spare page in the specified block has sufficient free space, the microprocessor 11 adds the specified next next page to be written and the required number of pages of data to be written and the maximum page. The numbers n are compared (step S703).

  As a result of the comparison in step S703, when the sum of the specified next next write page and the required number of pages of data to be written is smaller than or equal to the maximum page number n, the microprocessor 11 firstly prevents duplication in writing. The value of the next page management table 142 is updated to a value obtained by adding the number of pages to be written (step S704).

  For example, if the next writing page specified in step S702 is q + 1 and the required number of pages of data to be written is one page, the sum is q + 2. The value of q + 2 is rewritten as 1422 after the page rewriting in FIG. 8B.

Next, the microprocessor 11 writes data in the next write page specified in step S702 in the replacement page 223 (step S705).
Next, the microprocessor 11 updates the logical / physical conversion table 141 to the physical address for which writing has been completed for association with the physical address after writing (step S706).

For example, if the next writing page specified in step S702 is q + 1, the page is rewritten as shown in 1412 after page rewriting in FIG. 7B.
Next, the microprocessor 11 reports the end of writing to the host device 3 via the host I / F control unit 13 (step S707).

  Note that, as a result of the comparison in step S703, if the sum of the specified next next page to be written and the required number of pages of data to be written is larger than the maximum page number n, the microprocessor 11 executes block replacement processing (step S710). Then, the end of writing is reported to the host device 3 (step S707).

[Block replacement process]
Next, the block replacement process at step 710 shown in FIG. 4 will be described with reference to the flowchart of FIG.
First, the microprocessor 11 refers to the logical / physical conversion table 141 in order to copy the valid data of the replacement source block to the replacement block, and all pages associated with the corresponding block from the corresponding physical address. Is read (step S711).

  For example, if block 1 must be replaced, if the state of logical / physical conversion table 141 is the state after page rewriting in FIG. 7B, the data of all pages associated with block 1 of physical address 1411 Is read.

Next, the microprocessor 11 updates the data of the page corresponding to the data received in the process of step S700 in FIG. 4 with respect to the read data (step S712).
Next, the microprocessor 11 refers to the replacement block list table 143 to identify one block in the replacement block 23 in order to confirm the replacement block.

In order not to use the identified block redundantly, the content of the replacement block list table 143 is updated by one (step S713).
For example, if the state of the replacement block list table 143 is the initial state of FIG. 9A, the block p + 1 is identified and updated to the state indicated by 1431 after the block replacement of FIG. 9B.

  Here, the microprocessor 11 refers to the write page management table 142 to identify the page to be written in the identified block, and identifies the next write page of the identified block (step S714). ).

  For example, when the block p + 1 is specified in step S713, if the write page management table 142 is after the page rewrite in FIG. 8B, the next write page is 1. In the case of block replacement, since the replacement block is in the state after erasure, it is possible to write from page 1 unconditionally.

Next, the microprocessor 11 writes data from the next write page of the specified replacement block (step S715).
When the data writing is completed in step S715, the microprocessor 11 updates the table by adding the number of pages for which writing has been completed to the contents of the next writing page management table 142 (step S716).

  For example, if the next write page management table 142 is in the state shown after page rewriting in FIG. 8B, the table is updated as shown in 1423 after block replacement in FIG. 8C.

  Next, the microprocessor 11 updates the physical address 1411 of the corresponding logical address 1410 in the logical / physical conversion table 141 for association with the physical address after writing (step S717).

  For example, if the state of the logical / physical conversion table 141 is after page rewriting in FIG. 7B, after updating the table, the state becomes as shown at 1413 after block replacement in FIG. 7C. Here, p + 1 after block replacement is rearranged in the order of the original page.

  Next, the microprocessor 11 adds the replacement source block to the erasure candidate management table 145 so that the replacement source block can be used again (step S718). For example, if the erasure candidate management table 145 is in the initial state of FIG. 11A, block 1 is added as 1451 after the block replacement process of FIG. 11B.

[Reading process]
In response to a data read request from the host device 3, since the number of processes is small, it is shown in the following text without a flowchart.
First, the microprocessor 11 receives a logical address and a data size from the host device 3 via the host I / F control unit 13.

  The microprocessor 11 then refers to the logical / physical conversion table 141 to identify the physical address to be read, and identifies the physical address 1411 from the logical address 1410 designated by the host device 3.

  Next, the microprocessor 11 reads the data of the corresponding page via the memory I / F control unit 12 and transmits the read data to the host device 3 via the host I / F control unit 13. The reading process is realized through the above steps.

[Erase processing]
Next, the flow of block erase processing will be described based on the flowchart of FIG.
When there is no data write or read request from the host device 3, the microprocessor 11 performs an erase process on the block associated with the erase candidate management table 145.

First, the microprocessor 11 refers to the erasure candidate management table 145 and determines whether there is a block to be erased (step S800).
If it is determined in step S800 that there is no block to be erased, the process is terminated.
If there is a block to be erased, the microprocessor 11 adds one erase count of the block to the erase count management table 144 (step S801).

  For example, when referring to the erasure candidate management table 145 in step S800, the microprocessor 11 specifies the block 1 indicated by 1451 if it is in the state after the block replacement process of FIG. 11B. If the erase count management table 144 is in the initial state of FIG. 10A, the erase count of block 1 is set to 1 as in 1442 after the replacement process in FIG. 10B.

Next, the microprocessor 11 erases the data in the block (step S802).
Next, the microprocessor 11 deletes the erased block information in the erase candidate management table 145 and updates the table (step S803).

For example, if the erasure candidate management table 145 is after the B block replacement process in FIG. 11, the microprocessor 11 updates it as in the initial state in FIG. 11A.
Next, the microprocessor 11 returns to the determination process in step S800 in the figure, and continues the process until there is no corresponding block in the erasure candidate management table 145.

  It should be noted that the present invention is not limited to the above-described embodiment example, and can be used by appropriately modifying the above-described embodiment example without departing from the gist of the present invention described in the claims. Nor.

  It is obvious that the present invention relates to a storage device connected to a computer system and has industrial applicability.

It is explanatory drawing which shows the hardware structural example for implement | achieving embodiment of this invention. It is an internal block diagram of a semiconductor memory. It is a figure which shows the usage condition of the memory for implement | achieving a memory control system. It is a flowchart of a writing process. It is a flowchart of a block replacement process. It is a flowchart of a block erase process. FIG. 7A is a diagram showing a configuration example of a logical / physical conversion table, FIG. 7A is in an initial state, FIG. 7B is after page rewriting, and FIG. 7C is after block replacement. 8A and 8B are diagrams illustrating a configuration example of a next write page management table, in which FIG. 8A is in an initial state, FIG. 8B is after page rewriting, and FIG. 8C is after block replacement. FIG. 9A is a diagram illustrating a configuration example of a replacement block list table, FIG. 9A is in an initial state, and FIG. 9B is after block replacement. FIG. 10A is a diagram showing a configuration example of an erasure count management table, FIG. 10A is in an initial state, and FIG. 10B is after block replacement processing. FIG. 11A is a diagram illustrating a configuration example of an erasure candidate management table, FIG. 11A is in an initial state, and FIG. 11B is after block replacement processing.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Memory control part, 2 ... Semiconductor memory, 3 ... Host apparatus, 4 ... Data bus, 5 ... Memory bus, 6 ... Memory | storage device, 11 ... Microprocessor, 12 ... Memory I / F control part, 13 ... Host I / F control unit, 14 ... memory, 141 ... logical / physical conversion table, 142 ... next write page management table, 143 ... alternate block list table, 144 ... erase count management table, 145 ... erase candidate management table, 21 ... block, 211 ... page, 22 ... data block, 23 ... replacement block, 222 ... data page, 223 ... replacement page, 232 ... erased page, 1410 ... logical address, 1411 ... physical address, 1420 ... block number, 1421 ... next write page, 1440 ... Block number, 1441 ... Erase count

Claims (12)

A nonvolatile semiconductor memory that performs data writing to a storage area in a predetermined unit and erases data in a unit of a physical block having a data amount larger than the predetermined unit;
In accordance with an instruction from an external host system, a memory control unit that controls reading or writing to the nonvolatile semiconductor memory;
A storage device comprising:
The storage area of the nonvolatile semiconductor memory is composed of a data block composed of one or a plurality of the physical blocks and a replacement block composed of one or a plurality of the physical blocks,
The data block includes a data area for storing data written in the predetermined unit, and a replacement area in which the data stored in the data area in the same data block can be rewritten in the predetermined unit. ,
The memory control unit corresponds to a logical address indicated at the time of a data write request from the host system in a table storing a physical address of the nonvolatile semiconductor memory corresponding to a logical address related to an instruction from the host system. rewrites the physical address and further manages physical address to write the data is performed during a write request next time the data for the next write area management table, managing the replacement area by users update the next write page And
When new writing to the replacement area in the data block is impossible or when there is a possibility that new writing cannot be performed, the data in the replacement area that has been rewritten and the rewriting is not performed. The storage device, wherein data in the data area is copied to the replacement block, and the replacement block to which the data has been transferred is used as a data block. The storage device according to claim 1.
The memory control unit erases the data area and the replacement area so that the data block in which the rewritten data is stored after being rewritten to the replacement block becomes a candidate for the replacement block. A storage device. The storage device according to claim 1.
A storage device having means for describing the number of times of erasure of each physical block and capable of collectively managing the number of times of erasure. The storage device according to claim 1.
A storage device having means for managing a block to be erased of the physical block, and performing an erasing process in a free time of a microprocessor of the memory control unit. The storage device according to claim 1.
A storage device, wherein after the information held in the next write area management table is updated, data is written to a new replacement area. The storage device according to claim 1.
A storage device, wherein the latest data is rearranged in the order of logical addresses from the host system when valid data in the data block after data writing is transferred to the data area of the replacement block. Compared to a predetermined unit for writing data, a nonvolatile semiconductor memory having a storage area for erasing data in units of physical blocks having a larger amount of data,
A memory control method for performing reading or writing by a memory control unit in accordance with an instruction from an external host system,
The storage area of the nonvolatile semiconductor memory is composed of a data block composed of one or a plurality of the physical blocks and a replacement block composed of one or a plurality of the physical blocks,
The data block includes a data area for storing data written in the predetermined unit, and a replacement area in which the data stored in the data area in the same data block can be rewritten in the predetermined unit. ,
Of the table storing the physical address of the nonvolatile semiconductor memory corresponding to the logical address related to the instruction from the host system, the physical address corresponding to the logical address indicated at the time of the data write request from the host system is rewritten , Furthermore, managing the physical address to write the data is performed during a write request next time the data for the next write area management table manages the spare area by users update the next write page,
When new writing to the replacement area cannot be performed in each of the data blocks, or when there is a possibility that new writing cannot be performed, the data in the replacement area that has been rewritten and the rewriting are performed. A memory control method, wherein data in the data area that is not copied is copied to the replacement block, and the replacement block on which the data is copied is used as a data block. The memory control method according to claim 7 ,
The data area and the replacement area are erased so that the data block in which the rewritten data is stored after rewriting to the replacement block is a candidate for the replacement block. Memory control method. The memory control method according to claim 7 ,
A memory control method characterized in that it is possible to collectively manage the number of erasures by describing the number of erasures for each physical block. The memory control method according to claim 7 ,
A memory control method, comprising: managing a block to be erased of the physical block, and performing an erasure process in a free time of a microprocessor of the memory control unit. The memory control method according to claim 7 ,
A memory control method, comprising: writing data to a new replacement area after updating information held in the next write area management table . The memory control method according to claim 7 ,
A memory control method comprising rearranging the latest data in the order of logical addresses from the host system when transferring valid data in the data block after data is written to the data area of the replacement block.

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