JP2014232954A - Digital data transmitter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a digital data transmitter increasing a data transmission speed with suppressed cost.SOLUTION: The digital data transmitter includes: isolation devices 20a, 20b for transmitting a clock and unit data from a transmission device 10 to a reception device 30 in insulation; a division and rearrangement unit 12 for time dividing and rearranging the unit data into a plurality of divided data in order that one unit data is transmitted through only one of the isolation devices 20a, 20b; synchronous code adder unit 14a, 14b for adding a synchronous code based on a synchronous signal to the divided data; synchronous signal regenerator units 31a, 31b for regenerating a synchronous signal from the transmitted synchronous code; and a line memory 32, a delay circuit 33 and a synthesis unit 34 for restoring the divided data into the unit data at timing based on the clock transmitted through the isolation device 20b and the regenerated synchronous signal.

Description

  The present invention relates to a digital data transmission apparatus that transmits digital data configured in units from a transmission side circuit to a reception side circuit in an electrically insulated state.

  Conventionally, in the field of medical equipment and the like, in order to ensure safety, information transmission has been performed in a state where a patient circuit and a secondary circuit are electrically insulated using an insulated transmission unit such as an isolation device. It has been broken. Here, if an electronic endoscope apparatus as a medical device is taken as an example, a transmitting circuit that transmits an image obtained by imaging with an electronic endoscope is a patient circuit, and a receiving circuit that receives the transmitted image Is a secondary circuit.

  For example, Japanese Patent Application Laid-Open No. 11-317938 discloses a medical image transmission apparatus that insulates and transmits medical images such as endoscopic images used in hospitals or the like using a high-speed photocoupler as an insulating transmission unit. Is described. In the technique described in the publication, a vertical synchronizing signal (15) is generated by a synchronizing signal generator (11) in a secondary circuit which is a receiving side circuit, and is supplied to the secondary circuit, and a photocoupler ( 12) is transmitted as a vertical synchronization signal (16) to the patient circuit which is the transmission side circuit. Therefore, in the technique described in the publication, a dedicated channel for transmitting the synchronization signal is secured, and the transmission of the synchronization signal is not performed from the transmission side circuit to the reception side circuit, but from the reception side circuit. To the transmitter circuit.

  By the way, since the number of pixels of an image sensor built in an electronic endoscope or the like is increasing every year, the data transmission speed is increased when transmitting a moving image at a predetermined frame rate ( That is, it is required to increase the amount of transmission data per unit time).

  In order to simply increase the data transmission speed, it is conceivable to increase the bus width to double, for example. However, in this case, since the number of signal lines and the number of electrical contacts are doubled, the manufacturing cost increases.

  On the other hand, to increase the data transmission speed without increasing the bus width, it is conceivable to increase the number of clocks. However, in this case, the time of skew with respect to the clock cycle (a phenomenon in which signals that should arrive at the same time when signals are transmitted through a plurality of paths arrives at different timings for each path) becomes relatively large. The influence of can not be ignored.

  Here, one isolation device is provided with a plurality of channels for transmitting a signal, but an inter-channel skew occurs between these channels.

  Further, when a plurality of isolation devices are provided between the transmission side circuit and the reception side circuit, in addition to the above-described channel-to-channel skew, device-to-device skew may occur between the isolation devices.

  When such a skew becomes about the clock period or more, there is a possibility that an event in which data cannot be reproduced properly may occur.

  Specifically, when the above-described device-to-device skew between different isolation devices and the above-described channel-to-channel skew in one isolation device are compared, generally, the device-to-device skew is larger than the channel-to-channel skew. it is conceivable that.

  When the transmission data is digital image data, the unit data as a unit is, for example, pixel data, and one pixel data is, for example, 10-bit digital data.

  Then, 10-bit 1-pixel data is divided and transmitted in parallel to a plurality of isolation devices, and a clock and a horizontal synchronization signal are transmitted and received via any one of the plurality of isolation devices. When the clock and sync signal are transmitted on the side and the pixel data and sync signal are latched at the clock edge on the receive side, if the pixel data skew (especially the inter-device skew) is greater than the clock period, the original combination is There is a possibility that data of different combinations are latched and pixel data cannot be received normally. Note that since channel-to-channel skew exceeding the clock period is not expected to occur, channel-to-channel skew can be ignored (that is, unintended bits are latched at the clock edge due to channel-to-channel skew). Never).

Japanese Patent Laid-Open No. 11-317938

  As described above, in order to increase the data transmission speed from the transmission side circuit to the reception side circuit, the cost increases when the bus width is increased, and when the number of clocks is increased while maintaining the bus width, the skew (especially between devices) The unit data could not be restored due to the effect of (skew).

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a digital data transmission apparatus that can increase the data transmission speed while suppressing an increase in cost.

  In order to achieve the above object, a digital data transmission apparatus according to an aspect of the present invention is a digital data transmission that transmits digital data configured in units in a state of being electrically insulated from a transmission side circuit to a reception side circuit. A plurality of insulated transmission units for transmitting unit data and clock data in an electrically insulated state from the transmission side circuit to the reception side circuit; The unit data is time-divided into a plurality of divided data so that the unit data is transmitted through the one isolated transmission unit, and each of the plurality of the isolated transmission units is related to the different unit data in the same clock. A division rearrangement unit that rearranges the divided data to transmit and the transmission side circuit, and the division data is based on a synchronization signal. A synchronization code adding unit for adding a synchronization code to each of the plurality of isolated transmission units, and the synchronization code provided in the receiving circuit and transmitted via each of the plurality of isolated transmission units The synchronization signal reproducing unit that reproduces each of the synchronization signals from, and the reception side circuit, and transmitted through the insulating transmission unit of one of the synchronization signals reproduced by the synchronization signal reproducing unit At any timing based on the synchronization signal regenerated from the synchronization code and the clock data transmitted through the one isolated transmission unit, via any of the isolated transmission units A restoration unit that restores the divided data transmitted to the unit data.

  According to the digital data transmitting apparatus of the present invention, it is possible to increase the data transmission speed while suppressing an increase in cost.

The block diagram which shows the structure of the digital data transmitter in the related technology of embodiment of this invention. The block diagram which shows the structure of the receiving device in the said related technology. In the said related art, the timing chart which shows the clock, horizontal synchronizing signal, and pixel data which are transmitted to the isolation device from a transmission side circuit. 1 is a block diagram showing a configuration of a digital data transmission apparatus according to Embodiment 1 of the present invention. FIG. 2 is a block diagram showing a configuration of a delay circuit in the first embodiment. 4 is a timing chart illustrating a clock, a synchronization code, and pixel data transmitted from a transmission side circuit to an isolation device in the first embodiment. The block diagram which shows the structure of the digital data transmitter in Embodiment 2 of this invention. The block diagram which shows the structure of the delay circuit in the said Embodiment 2. FIG. 9 is a timing chart illustrating a clock, a synchronization code, and pixel data transmitted from a transmission side circuit to an isolation device in the second embodiment.

  First, before describing an embodiment of the present invention, a technique related to the embodiment will be described.

  1 to 3 show techniques related to the embodiment of the present invention. FIG. 1 is a block diagram showing a configuration of a digital data transmitting apparatus, FIG. 2 is a block diagram showing a configuration of a receiving device, and FIG. FIG. 4 is a timing chart showing a clock, a horizontal synchronization signal, and pixel data transmitted from a transmission side circuit to an isolation device.

  As shown in FIG. 1, the digital data transmission apparatus electrically isolates the transmission device 70 in the transmission side circuit and the reception device 90 in the reception side circuit via the first to third isolation devices 80a to 80c. In this state, it is connected so that signal transmission is possible.

  Here, in the digital image data transmitted from the transmission device 70, one pixel is, for example, 10-bit digital data, and each bit is represented by a number from [0] to [9].

  As shown in FIG. 1 and FIG. 3, 1-pixel data (DATA or D for short) composed of 10 bits is divided into three divided data in this example, and the upper 4 bits D [9] to The divided data of D [6] is transmitted through the first isolation device 80a, and the divided data of the middle 3 bits D [5] to D [3] is transmitted through the second isolation device 80b. Divided data of 3 bits D [2] to D [0] is transmitted via the third isolation device 80c.

  Further, the transmission device 70 further transmits a clock CLK and a horizontal synchronization signal HSYNC.

  The clock CLK and the horizontal synchronization signal HSYNC transmitted from the transmission device 70 are transmitted via all of the first to third isolation devices 80a to 80c. That is, each of the first to third isolation devices 80a to 80c is provided with one channel for transmitting a synchronization clock and one channel for transmitting a horizontal synchronization signal.

  Accordingly, the first isolation device 80a is a 6-channel device, the second isolation device 80b is a 5-channel device, and the third isolation device 80c is a 5-channel device.

  Next, as shown in FIG. 2, the receiving device 90 corresponds to the first isolation device 80a, the first line memory 91a that temporarily stores the transmitted divided data DATA1, and the transmitted clock CLK1. And a first write control circuit 93a for receiving the horizontal synchronization signal HSYNC1.

  Further, the receiving device 90 receives the second line memory 91b that temporarily stores the transmitted divided data DATA2, the transmitted clock CLK2, and the horizontal synchronization signal HSYNC2 corresponding to the second isolation device 80b. A second write control circuit 93b.

  The divided data is written into the first and second line memories 91a and 91b in synchronization with the write clock.

  Further, the receiving device 90 includes a delay circuit 92 that performs a delay corresponding to the third isolation device 80c. More specifically, the reception device 90 includes a data delay circuit 92a that delays the received divided data DATA3 based on the received clock CLK3, and a horizontal synchronization signal delay that delays the horizontal synchronization signal HSYNC3 received based on the received clock CLK3. And a circuit 92b.

  In addition, the receiving device 90 includes the first and second line memories 91a, 91a, 91c based on the clock CLK3 received via the third isolation device 80c and the horizontal synchronization signal HSYNC3_DELAY delayed by the horizontal synchronization signal delay circuit 92b. A readout control circuit 94 that controls readout of 91b is provided.

  Next, the operation of such a receiving device 90 will be described.

  The first and second write control circuits 93a and 93b reset the write addresses of the first and second line memories 91a and 91b when receiving the horizontal synchronization signals HSYNC1 and HSYNC2 respectively. As a result, digital data relating to each line of the image is sequentially written from the first address of the first and second line memories 91a and 91b. When the divided data is received, it is written in the memory portion of the write address in synchronization with the clock. Further, in accordance with the next clock, a process of advancing the write address by the amount of already written divided data is performed.

  In addition, the horizontal synchronization signal delay circuit 92b has a maximum time that can be assumed as the inter-device skew with the horizontal synchronization signal HSYNC3 input via the third isolation device 80c as the unit of the input clock CLK3, and the first time. , The time required for writing to the second line memories 91a and 91b is delayed by a predetermined time equal to or greater than the total time (therefore, the data transmission rate defined by the clock is so high that the inter-device skew cannot be ignored). Is assumed).

  The readout control circuit 94 uses the horizontal synchronization signal HSYNC3_DELAY delayed by the horizontal synchronization signal delay circuit 92b as a line readout start timing, and starts from this start timing as a pixel position on the line determined based on the input clock CLK3. Based on the read timing according to the control, the divided data read timing from the first and second line memories 91a and 91b is controlled to be the same as the divided data output timing after being delayed by the data delay circuit 92a.

  Thus, 4-bit data from the first line memory 91a, 3-bit data from the second line memory 91b, and 3-bit data from the data delay circuit 92a are simultaneously output, that is, pixel data restored as 10-bit data. Are output in parallel.

  According to such a configuration as described with reference to FIGS. 1 to 3, the first and second line memories 91a and 91b are written in the same first and second lines as when the divided data is relayed. 2 based on the clock and horizontal synchronization signal from the isolation devices 80a and 80b, and the read from the first and second line memories 91a and 91b is delayed by the clock and delay circuit 92 from the third isolation device 80c. Since the processing is performed based on the horizontal synchronization signal, pixel data can be restored without being affected by the inter-device skew.

  The divided data written in the first and second line memories 91a and 91b is not affected by the inter-device skew as described above, but is affected by the inter-channel skew. However, since it is considered that no inter-channel skew exceeding the clock period is generated as described above, the inter-channel skew can be ignored.

  In the above description, the line memory is used as the memory for storing the divided data. However, it is not necessary to store all the divided data for one line, and the divided data is divided by an amount corresponding to the time during which the inter-device skew can be absorbed. Since it suffices to store data, the memory may be configured as a pixel memory having a capacity for storing divided data relating to a plurality of pixels.

  By the way, the configuration as described with reference to FIGS. 1 to 3 is provided in the first to third isolation devices 80a to 80c in order to transmit 10-bit unit data (pixel data in the above example). The number of channels obtained was 6 + 5 + 5 = 16 channels.

In the following, an embodiment of the present invention in which the number of channels is reduced will be described with reference to the drawings.
[Embodiment 1]

  4 to 6 show the first embodiment of the present invention. FIG. 4 is a block diagram showing a configuration of a digital data transmitting apparatus, FIG. 5 is a block diagram showing a configuration of a delay circuit, and FIG. 6 is a transmission side. 3 is a timing chart showing a clock, a synchronization code, and pixel data transmitted from a circuit to an isolation device.

  In this embodiment, the clock is transmitted to each isolation device, but the synchronization signal is transmitted via a channel for transmitting unit data as a synchronization code. In this embodiment (and other embodiments described later), it is assumed that the data transmission speed defined by the clock is so high that the inter-device skew cannot be ignored.

  The digital data transmitting apparatus transmits digital data configured in unit units from a transmitting circuit to a receiving circuit in an electrically insulated state. Here, in this embodiment, the digital data is digital image data, and the unit is a pixel constituting the image.

  Specifically, as shown in FIG. 3, the digital data transmission apparatus includes a transmission device 10 in the transmission side circuit and a reception device 30 in the reception side circuit, the first and second isolation devices 20a, It is configured to be connected so as to be able to transmit signals in an electrically insulated state via 20b.

  Here, the digital image data to be transmitted by the transmission device 10 is digital data in which one pixel is, for example, 10 bits. Each bit constituting digital data (DATA or also abbreviated as D) is represented by numbers such as [0], [1],.

  First, the isolated transmission unit includes two isolation devices, that is, a first isolation device 20a and a second isolation device 20b in this embodiment, and receives pixel data and clock data from the transmission side circuit to the reception side. It is transmitted to the circuit in an electrically insulated state. In the present embodiment, each of the first isolation device 20a and the second isolation device 20b is configured as a device of 6 channels (for data (DATA): 5 channels, for clock (CLK): 1 channel). The total number of channels is 12, and a reduction in the number of channels is achieved as compared with 16 channels in the example described with reference to FIGS.

  Next, the transmission device 10 includes a clip processing unit 11, a division rearrangement unit 12, a delay circuit 13, and synchronization code addition units 14a and 14b, and is configured as a field programmable gate array (FPGA), for example. ing.

  The clip processing unit 11 performs clipping so that pixel data as unit data does not have a prohibition code in which all bits are composed of a bit value 0 or a bit value 1.

  Since the pixel data of this embodiment is 10-bit digital data, it can take values from 0 to 1023. Of these 1024 values, at least one of the value 0 (all bits are 0) and the value 1023 (all bits is 1) is set as a prohibition code (so both are set as prohibition codes and required. The clip processing unit 11 performs clipping so as not to take the set prohibition code value. In the present embodiment, for example, the value 1023 (all bits are 1) is set as the prohibition code (see also the identification code included in the synchronization code in FIG. 6). In this case, pixel data having a value 1023 (all bits are 1) in the imaging data input to the clip processing unit 11 is clipped to a value 1022.

  When the digital data is digital image data, pixel data with a bit value of 0 for all bits is data of a pixel that is blacked out, and pixel data with a bit value of 1 for all bits is data of a pixel that has been blown out. When all the bits are set to the bit value 0 or 1, the prohibition code has an advantage that there is almost no visual influence on the image.

  The division rearrangement unit 12 time-divides the pixel data into a plurality of divided data so that one pixel data is transmitted through one insulation transmission unit, and each of the plurality of insulation transmission units in the same clock. It rearranges so that the division | segmentation data concerning different pixel data may be transmitted. Therefore, in the present embodiment, any one piece of pixel data is not transmitted across different isolated transmission units.

  The process by this division | segmentation rearrangement part 12 is demonstrated with reference to FIG.

  As described above, in the present embodiment, the pixel data is 10-bit digital data. The first and second isolation devices 20a and 20b are each provided with a 5-channel communication line for data. Therefore, the division rearrangement unit 12 first converts 1-pixel data composed of 10 bits into the first divided data of the upper 5 bits D [9] to D [5] and the lower 5 bits D [4]. The data is divided into two pieces, i.e., second divided data of D [0].

  Here, the pixel data is divided into two equal parts, but it is needless to say that the division mode is appropriately changed according to the number of bits of the pixel data and the number of data channels of the isolation device. For example, if the pixel data is 12 bits and the number of data channels is 5, the pixel data is divided into 3 parts, that is, 5 bits + 5 bits + 2 bits (that is, neither divided nor equally divided).

  Next, the division rearrangement unit 12 rearranges the divided data.

  That is, as illustrated in FIG. 6, the division rearrangement unit 12 uses the first division data D0 [9] to D0 [D0 [0] in which data transmitted via the first isolation device 20a is transmitted at a certain clock. 5], the data is rearranged.

  In the next rearrangement unit 12, in the next clock, the data transmitted through the first isolation device 20a becomes the second divided data D0 [4] to D0 [0] related to the pixel 0, and the second isolator The data is rearranged so that the first divided data D1 [9] to D1 [5] related to the pixel 1 is transmitted via the communication device 20b.

  In the divided rearrangement unit 12, in the next clock, the data transmitted through the first isolation device 20a becomes the first divided data D2 [9] to D2 [5] related to the pixel 2, and the second The data is rearranged so that the second divided data D1 [4] to D1 [0] related to the pixel 1 is transmitted via the isolation device 20b.

  Similarly thereafter, the division rearrangement unit 12 rearranges the data. Therefore, the divided data related to one pixel data, that is, divided data divided into two in this example, is sequentially transmitted in two consecutive clocks, that is, the division by the division rearrangement unit 12 is time division. In this way, pixel data can be transmitted in the order of pixel arrangement on the line.

  More generally, even when the number of isolation transmission units is m (m is a positive integer equal to or greater than 2), the pixel data can be transmitted in the pixel arrangement order on the line (that is, the pixel data in the rear order in the arrangement order is It is preferable that the pixel data is not transmitted prior to the preceding pixel data. For this purpose, the division rearrangement unit 12 performs rearrangement so that, for example, the (n + k−1) th pixel data is transmitted to the kth insulation transmission unit. Here, k is an integer of 1 or more and m or less, and n is an integer of 0 or more.

  The delay circuit 13 is a circuit that delays the vertical synchronization signal VSYNC and the horizontal synchronization signal HSYNC by the time required for processing the pixel data in the clip processing unit 11 and the division rearrangement unit 12.

  The synchronization code adding units 14a and 14b are for adding a synchronization code corresponding to each of the plurality of insulated transmission units to the divided data based on a synchronization signal such as a vertical synchronization signal and a horizontal synchronization signal.

In the present embodiment, as described above, data in which all 10 bits are 1 is used as a prohibition code. Therefore, any one or more bits constituting one pixel data are always 0. . Therefore, when two pixel data transmitted in succession in one isolation device are considered, the longest continuous 1 is
Forward pixel data: 0111111111
Delayed pixel data: 1111111110
This is the case. In this case, the divided data transmitted every clock is
Clock 1: 01111
Clock 2: 11111
Clock 3: 11111
Clock 4: 11110
Thus, the divided data whose all bits are 1 is continuous only for 2 clocks at maximum. Therefore, if the divided data having all the bits of 1 is continued for 3 clocks or more, it can be determined that the identification code is not pixel data.

  For this reason, when i is an integer greater than or equal to 1 and j is an integer greater than or equal to 2, the synchronization code adding units 14a and 14b set the number of bits of the divided data to one pixel by the divided rearrangement unit 12. Creating and adding a synchronization code including an identification code having the same bit value as the prohibition code, which is the number of bits i × (2j−1) obtained by multiplying the number obtained by subtracting 1 from twice the time division number j of the data; It has become. This identification code is data transmitted at successive (2j-1) clocks.

  The synchronization code adding units 14a and 14b further add the timing reference signal TRS to, for example, one clock (that is, 5 bits) for each of the identification codes transmitted via the first and second isolation devices 20a and 20b. Append. Thus, the synchronization code includes an identification code that precedes in time and a timing reference signal TRS that is transmitted following this identification code.

  For example, the synchronization code adding units 14a and 14b add a synchronization code indicating the start of the horizontal line and a synchronization code indicating the end of the horizontal line in response to the horizontal synchronization signal. Here, the synchronization code indicating the start of the horizontal line is added immediately before the effective video period at the end of the blanking period is started, as shown in FIG. The synchronization code indicating the end of the horizontal line is added to the head of the blanking period immediately after the effective video period ends.

  At this time, in the present embodiment, the timing reference signal TRS composed of 5 bits (fourth bit to zeroth bit) as described above is, for example, a bit value 0 or a bit value 1 in which the fourth bit indicates the VSYNC state. The third bit is the bit value 0 or bit value 1 indicating the HSYNC state, the second bit is a code indicating the start and end of the effective pixel (bit value 0 or bit value 1), the first bit and the 0th bit are not used It has become. However, such a configuration of the timing reference signal TRS is, of course, an example, and protection bits may be provided by increasing the number of bits (that is, for a plurality of clocks).

  The receiving device 30 includes synchronization signal reproducing units 31a and 31b, a line memory 32, a delay circuit 33, and a combining unit 34, and is configured as, for example, a field programmable gate array (FPGA).

  The synchronization signal reproducing units 31a and 31b reproduce the synchronization signals from the synchronization codes transmitted through the plurality of insulated transmission units. The synchronization signal reproducing units 31a and 31b always detect whether the data of interest is a synchronization code based on an identification code included in the synchronization code. The synchronization signal reproducing units 31a and 31b reproduce the synchronization signal when the synchronization code is detected.

  The line memory 32 temporarily stores the divided data received following the synchronization code identified by the synchronization signal reproducing unit 31a.

  The writing of the divided data to the line memory 32 is not shown in FIG. 4, but is controlled by a write control circuit similar to the first and second write control circuits 93a and 93b as shown in FIG. Based on the horizontal synchronization signal reproduced by the synchronization signal reproduction unit 31a as a reference, the synchronization is performed in synchronization with the clock acquired via the first isolation device 20a.

  Further, the read of the divided data from the line memory 32 is performed based on the control of the read control circuit similar to the read control circuit 94 as shown in FIG. That is, the read control circuit of the present embodiment is based on the clock received via the second isolation device 20b and the horizontal synchronization signal received via the second isolation device 20b and delayed by the delay circuit 33. Are read out from the line memory 32 at the timing determined in the above.

  The delay circuit 33 performs a delay corresponding to the inter-device skew of the first and second isolation devices 20a and 20b and a delay of one clock related to pixel data transmitted in a time-division manner. is there.

  Here, the delay circuit 33 will be described with reference to FIG.

  The delay circuit 33 includes an inter-device skew delay unit 33a and a one-clock delay unit 33b.

  The inter-device skew delay unit 33a includes a maximum time that can be assumed as an inter-device skew between the first isolation device 20a and the second isolation device 20b, and a time required for writing to and reading from the line memory 32. Data is output after being delayed by a predetermined time longer than the total time.

  The 1-clock delay unit 33b delays the first divided data received in advance by one clock in accordance with time-division transmission of data of one pixel into two clocks (time division The divided data is delayed so as to be synchronized). On the other hand, the second divided data received subsequently is output without passing through the one-clock delay unit 33b.

  As a result, the first divided data and the second divided data related to one pixel data are delayed by the above-described predetermined time and then output from the delay circuit 33 simultaneously.

  Although not shown, the delay circuit 33 delays the horizontal synchronization signal (or further vertical synchronization signal) received through the second isolation device 20b and reproduced by the synchronization signal reproduction unit 31b by the predetermined time described above. The processing to be performed is also performed.

  The combining unit 34 combines two divided data related to one pixel data output from the line memory 32, or combines two divided data related to one pixel data output from the delay circuit 33. The original 10-bit pixel data is restored and output. This is because, as described above, the divided data related to one pixel data is transmitted by only one of the first isolation device 20a and the second isolation device 20b.

  The line memory 32, the delay circuit 33, and the synthesizing unit 34 (and the above-described readout control circuit) are synchronized with a synchronization signal reproduced by the synchronization signal reproducing unit 31b (a plurality of synchronization signals reproduced by the synchronization signal reproducing unit). The first isolation signal at a timing based on the clock signal transmitted via the second isolation device 20b and the synchronization signal reproduced from the synchronization code transmitted via the one isolated transmission unit). A restoration unit is configured to restore the divided data transmitted to the pixel data via the device 20a or the second isolation device 20b (that is, any of the plurality of insulated transmission units).

  According to the first embodiment, the writing to the line memory 32 is performed based on the clock and the horizontal synchronization signal that have passed through the same first isolation device 20a that relayed the divided data, and the line memory 32 Since reading from is performed on the basis of the clock passing through the second isolation device 20b and the horizontal synchronization signal delayed by the delay circuit 33, the pixel data is restored without being affected by the inter-device skew. It becomes possible.

  In addition, since a synchronization signal such as a horizontal synchronization signal or a vertical synchronization signal is transmitted as a synchronization code through a channel for transmitting pixel data, a channel for transmitting the synchronization signal is not necessary, and the transmission side circuit and It is possible to reduce the number of channels of the isolation device that relays to the reception side circuit.

  As a result, it may be possible to reduce the number of isolation devices. As a specific example, the configuration shown in FIG. 1 requires one 6-channel isolation device and two 5-channel isolation devices, which is a total of three, but is shown in FIG. 4 of the present embodiment. In the configuration, two 6-channel isolation devices are sufficient. Thereby, the manufacturing cost can be reduced.

  Further, a synchronization code including an identification code having the same bit value as that of the prohibition code is generated by multiplying the number of bits of the divided data by twice the number of time divisions of one pixel data minus one. Since it is added, the synchronization code can be made as short as possible while reliably distinguishing it from the pixel data.

  In addition, since the pixel data arranged on the line is sequentially transmitted to the plurality of isolation devices, the pixel data can be restored in order without changing the pixel order.

  A digital data transmission device that transmits digital data from a transmission side circuit to a reception side circuit in an electrically insulated state is particularly important in medical equipment. Digital data is digital image data, and a unit is a pixel that constitutes an image. In this case, the configuration of the present embodiment is particularly useful for an electronic endoscope apparatus or the like.

In this way, it is possible to provide a digital data transmission apparatus that can increase the data transmission speed while suppressing an increase in cost.
[Embodiment 2]

  FIGS. 7 to 9 show the second embodiment of the present invention. FIG. 7 is a block diagram showing the configuration of the digital data transmitting apparatus, FIG. 8 is a block diagram showing the configuration of the delay circuit, and FIG. 3 is a timing chart showing a clock, a synchronization code, and pixel data transmitted from a circuit to an isolation device.

  In the second embodiment, portions that are substantially the same as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted as appropriate, and only different points will be mainly described.

  The second embodiment is the same as the first embodiment described above in that the synchronization signal is transmitted as a synchronization code via a channel for transmitting pixel data.

  In the present embodiment, digital image data to be transmitted by the transmission device 10 is digital data in which one pixel is 12 bits.

  The insulated transmission unit includes three isolation devices in this embodiment, that is, a third isolation device 20c is further provided in addition to the first and second isolation devices 20a and 20b. In the present embodiment, each of the first to third isolation devices 20a to 20c is configured as a device of 5 channels (for data (DATA): 4 channels, for clock (CLK): 1 channel), and the total The number of channels is 15 channels.

  Correspondingly, the transmission device 10 is provided with a synchronization code adding unit 14c that transmits the divided data, the synchronization code, and the clock to the third isolation device 20c. Then, the division rearrangement unit 12 transmits the divided data also to the synchronization code adding unit 14c, and the delay circuit 13 transmits the delayed synchronization signal also to the synchronization code adding unit 14c.

  On the other hand, the receiving device 30 is provided with two line memories 32a and 32b, and a synchronization signal reproducing unit 31c is further added. In this embodiment, the synchronization signal reproducing unit 31a is connected to the synthesizing unit 34 via the line memory 32a, and the synchronization signal reproducing unit 31b is connected to the synthesizing unit 34 via the line memory 32b, and the synchronization signal reproducing unit 31c. Are connected to the synthesis unit 34 via the delay circuit 33. Further, the configuration of the delay circuit 33 in the present embodiment is also different from that of the above-described first embodiment, as will be described later with reference to FIG.

  In such a configuration, the division rearrangement unit 12 converts the data of 1 pixel composed of 12 bits, the first division data of the upper 4 bits D [11] to D [8], and the middle 4 bits D The second divided data of [7] to D [4] and the third divided data of lower 4 bits D [3] to D [0] are divided into three.

  Then, the division rearrangement unit 12 rearranges the divided data as shown in FIG.

  That is, the division rearrangement unit 12 causes the data transmitted via the first isolation device 20a to be the first division data D0 [11] to D0 [8] related to the pixel 0 at a certain clock. Sort the data.

  In the next rearrangement unit 12, in the next clock, the data transmitted through the first isolation device 20a becomes the second divided data D0 [7] to D0 [4] related to the pixel 0, and the second isolator The data is rearranged so that the first divided data D1 [11] to D1 [8] related to the pixel 1 is transmitted via the communication device 20b.

  In the next rearrangement unit 12, in the next clock, the data transmitted through the first isolation device 20a becomes the third divided data D0 [3] to D0 [0] related to the pixel 0, and the second The second divided data D1 [7] to D1 [4] related to the pixel 1 are transmitted via the isolation device 20b, and the pixel 2 is transmitted via the third isolation device 20c. The data is rearranged so as to be the first divided data D2 [11] to D2 [8].

  In the division rearrangement unit 12, in the next clock, the data transmitted through the first isolation device 20a becomes the first division data D3 [11] to D3 [8] related to the pixel 3, The third divided data D1 [3] to D1 [0] related to the pixel 1 is transmitted through the second isolation device 20b, and the pixel 2 is transmitted through the third isolation device 20c. Data rearrangement is performed so that the second divided data D2 [7] to D2 [4] are obtained.

  Similarly thereafter, the division rearrangement unit 12 rearranges the data. Accordingly, the divided data obtained by dividing the data into three pieces of pixel data is sequentially transmitted in three consecutive clocks, and the pixel data can be transmitted in the order of arrangement of the pixels on the line.

  Also in the present embodiment, if the clip processing unit 11 uses a prohibition code as data for which all bits are 1 (a numerical value for which all 12 bits have a bit value of 1 is 4095). The identification codes included in the synchronization codes added by the synchronization code adding units 14a, 14b, and 14c are as follows.

  That is, since the number of bits of the divided data is 4, and the time division number of one pixel data by the division rearrangement unit 12 is 3, the identification code is 4 × (2 × 3-1) = 20. , The bit value 1 is a continuous code. This identification code is data transmitted in continuous (2 × 3-1) = 5 clocks.

  In this embodiment, the timing reference signal TRS added after the identification code is, for example, a bit value 0 or bit value 1 indicating the VSYNC state in the third bit, and a bit value 0 or 0 indicating the HSYNC state in the second bit. The bit value 1, the first bit is a code indicating the start and end of an effective pixel (bit value 0 or bit value 1), and the 0th bit is not used.

  Further, the synchronization signal reproduction unit 31c of the reception device 30 detects the synchronization code in the data received from the third isolation device 20c based on the identification code, and reproduces the synchronization signal.

  The line memories 32a and 32b temporarily store divided data received subsequent to the synchronization code identified by the synchronization signal reproducing units 31a and 31b, respectively. The division data is written to the line memories 32a and 32b in synchronization with the acquired clocks via the first and second isolation devices 20a and 20b. In addition, the division data read from the line memories 32a and 32b is performed by using the clock received via the third isolation device 20c and the horizontal synchronization signal received via the third isolation device 20c and delayed by the delay circuit 33. And the timing determined based on the above.

  The delay circuit 33 includes a delay corresponding to an inter-device skew between the first and second isolation devices 20a and 20b and the third isolation device 20c, a delay of one clock related to pixel data transmitted in a time division manner, and 2 clock delays.

  Here, the delay circuit 33 will be described with reference to FIG.

  The delay circuit 33 includes an inter-device skew delay unit 33a, a 1-clock delay unit 33b, and a 2-clock delay unit 33c.

  The inter-device skew delay unit 33a includes a maximum time that can be assumed as an inter-device skew between the first isolation device 20a and the third isolation device 20c, and the second isolation device 20b and the third isolation device 20c. More than the total of the maximum time that can be assumed as the inter-device skew between the time of the larger one (if any) and the time required to write and read the line memories 32a and 32b Data is output after being delayed by a predetermined time.

  The 1-clock delay unit 33b delays the second divided data received by one clock ahead of the third divided data by one clock (delays the time-divided divided data so as to be synchronized). It is.

  The two-clock delay unit 33c delays the first divided data received by two clocks before the third divided data by two clocks (delays the time-divided divided data so that they are synchronized). It is.

  The third divided data is output without passing through either the 1-clock delay unit 33b or the 2-clock delay unit 33c.

  As a result, the first to third divided data relating to one pixel data are delayed by the above-described predetermined time and then simultaneously output from the delay circuit 33.

  Although not shown, the delay circuit 33 also performs a process of delaying the horizontal synchronization signal (or further vertical synchronization signal) received via the third isolation device 20c by the predetermined time described above.

  The synthesizing unit 34 synthesizes the first to third divided data related to one pixel data output from the line memory 32a, the line memory 32b, or the delay circuit 33, and restores the original 12-bit pixel data. Output.

  Therefore, the restoration unit in the present embodiment includes line memories 32a and 32b, a delay circuit 33, and a synthesis unit 34 (and the above-described read control circuit).

  According to the second embodiment, even when digital data is transmitted via the three isolation devices 20a to 20c, substantially the same effects as those of the first embodiment can be obtained.

  When transmitting divided data via a data channel of an isolation device, a clock for transmitting divided data related to a pixel and a pixel to be transmitted via the data channel next to the pixel If a clock that does not transmit divided data occurs between the divided data transmission clock and the clock that transmits the divided data, the data transmission speed is lowered, which is not preferable. Therefore, as can be seen from the first and second embodiments, it is preferable that the number of insulated transmission units and the number of time divisions of unit data into division data by the division rearrangement unit coincide with each other. Actually, in the first embodiment, the number of isolation devices is two, and the number of time divisions of pixel data into divided data is two. In the second embodiment, the number of isolation devices is 3, and the number of time divisions of pixel data into divided data is 3, which is the same.

  In the above description, the digital data transmitting apparatus has been mainly described. However, a control method for controlling the digital data transmitting apparatus as described above may be used, or control for causing a computer to control the digital data transmitting apparatus as described above. It may be a program, a computer-readable recording medium that records the control program, or the like.

  Further, the present invention is not limited to the above-described embodiments as they are, and can be embodied by modifying the constituent elements without departing from the scope in the implementation stage. In addition, various aspects of the invention can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, you may delete some components from all the components shown by embodiment. Furthermore, the constituent elements over different embodiments may be appropriately combined. Thus, it goes without saying that various modifications and applications are possible without departing from the spirit of the invention.

10: Transmitting device (transmission side circuit)
DESCRIPTION OF SYMBOLS 11 ... Clip process part 12 ... Division | segmentation rearrangement part 13 ... Delay circuit 14a, 14b, 14c ... Synchronization code addition part 20a ... 1st isolation device (insulation transmission part)
20b ... 2nd isolation device (insulation transmission part)
20c ... 3rd isolation device (insulation transmission part)
30: Receiving device (receiving side circuit)
31a, 31b, 31c... Synchronous signal reproduction unit 32, 32a, 32b... Line memory (restoration unit, memory)
33 ... Delay circuit (restoration unit)
33a ... Inter-device skew delay unit 33b ... 1 clock delay unit 33c ... 2 clock delay unit 34 ... synthesis unit (restoration unit)
DESCRIPTION OF SYMBOLS 70 ... Transmission device 80a-80c ... 1st-3rd isolation device 90 ... Reception device 91a, 91b ... 1st, 2nd line memory 92 ... Delay circuit 92a ... Data delay circuit 92b ... Horizontal synchronous signal delay circuit 93a, 93b ... First and second write control circuits 94 ... Read control circuits

Claims (5)

A digital data transmitting apparatus for transmitting digital data configured in units from a transmitting circuit to a receiving circuit in an electrically insulated state,
A plurality of insulated transmission units for transmitting unit data and clock data in a state of being electrically insulated from the transmission side circuit to the reception side circuit;
Provided in the transmission side circuit, the unit data is time-divided into a plurality of divided data so that one unit data is transmitted through one insulating transmission unit, and a plurality of the insulations in the same clock. A division rearrangement unit that rearranges each of the transmission units to transmit the divided data according to the unit data different from each other;
A synchronization code adding unit that is provided in the transmission side circuit and adds a synchronization code to the divided data corresponding to each of the plurality of isolated transmission units based on a synchronization signal;
A synchronization signal reproducing unit that is provided in the reception-side circuit and reproduces the synchronization signal from the synchronization code transmitted through each of the plurality of insulated transmission units;
The synchronization signal reproduced from the synchronization code transmitted through the one isolated transmission unit among the synchronization signals provided in the reception-side circuit and reproduced by the synchronization signal reproduction unit; The divided data transmitted through any of the plurality of isolated transmission units is restored to the unit data at a timing based on the clock data transmitted through the isolated transmission unit. A restoration unit;
A digital data transmitting apparatus comprising:   2. The digital data transmitting apparatus according to claim 1, wherein the number of the insulating transmission units and the number of time divisions of the unit data into the divided data by the division rearrangement unit are the same. A clip processing unit that is provided in the transmission side circuit and clips so that the unit data does not take a prohibition code in which all bits are composed of a bit value 0 or a bit value 1;
The synchronization code adding unit includes the synchronization code including an identification code having the same bit value as the prohibited code, which is obtained by multiplying the number of bits of the divided data by a value obtained by subtracting 1 from twice the number of time divisions. Is created and added,
The digital data transmitting apparatus according to claim 2, wherein the synchronization signal reproducing unit reproduces the synchronization signal by identifying the synchronization code based on the identification code. When m is a positive integer of 2 or more, k is an integer of 1 or more and m or less, n is an integer of 0 or more, and the number of the insulated transmission parts is m,
3. The digital data according to claim 2, wherein the rearrangement unit performs the rearrangement so that the k-th isolated transmission unit transmits the (n + k−1) -th unit data. 4. Transmitter device.   3. The digital data transmitting apparatus according to claim 2, wherein the digital data is digital image data, and the unit is a pixel constituting an image.

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