JP2014230998A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine preventing control to a setting change state by a fraudulent act.SOLUTION: In an operation state where setting change operation is performed by a power switch and a setting key switch that can be operated when a front door is in an open state, the opening/closing state of the front door is determined (Sa27b). When it is determined that the front door is in an open state (YES for Sa27b), control is performed to a setting change state. Conversely, when it is determined that the front door is in a closed state, no control is performed to the setting change state (NO for Sa27b) and processing (Sa27c) for disabling progress of a game is performed.

Description

  The present invention relates to gaming machines such as pachinko machines and slot machines. Specifically, the present invention relates to a gaming machine that can change the degree of advantage for a player.

  Conventionally, as an example of such a gaming machine, various devices including a variable display device and a control circuit for controlling these devices are incorporated in the main body, and the front surface of the main body can be opened and closed by a front door. And, by opening the front door and operating a specific operation means built in the main body, it is controlled to the setting change state, and in the setting change state, one of the setting values from a plurality of types of setting values is set. There was something that could be selected and set. The set value determines the probability (winning probability) of allowing the occurrence of a winning (big hit, medium win, small win, bonus, small combination, re-playing combination, etc.). For this reason, the key for opening the front door is held and owned only by a specific store clerk of the game hall, and the setting change can be performed only by a specific store clerk (game room manager) of the game hall. It is configured not to be able to.

  On the other hand, the player's advantage depends on the set value. As a result, the player has performed an illegal act of changing the setting by controlling the setting change state. For example, by opening a hole in the front door or inserting a tool through the gap between the front door and the main unit, operating a specific operating unit or shorting a circuit built in the main unit, There was an act of changing the setting illegally by setting the same operation state as when it was operated.

  As a gaming machine for preventing such illegal acts, a door detection sensor capable of detecting the front door in the closed state is provided, and setting change for changing the setting when the front door is in the closed state in the setting change state There are those that invalidate the signal (for example, see Patent Document 1) and those that report an abnormality (for example, see Patent Document 2).

JP 2004-135844 A JP 2006-61510 A

  However, in the gaming machines described in Patent Documents 1 and 2, even if the front door is in the closed state, it can be controlled to the setting change state. For this reason, even if the front door is in the closed state, there is a possibility that the setting is changed illegally. For example, in the gaming machine described in Patent Document 1, by an action that does not invalidate the setting change signal, and in the gaming machine described in Patent Document 2, by an action that continues the setting change of what is reported to be abnormal In any case, there is a possibility that the setting is changed illegally even though the front door is closed. Furthermore, there is a possibility that the game can proceed after the cheating.

  The present invention has been conceived in view of such circumstances, and an object thereof is to provide a gaming machine that prevents the setting change state from being controlled by an unauthorized act.

(1) A gaming machine (slot machine, pachinko machine, etc.) capable of changing an advantage (for example, a set value) for a player,
An opening / closing body (front door 1b, body frame 914) provided to be openable and closable;
Operating means (power switch 39, setting key switch 37) that can be operated when the opening and closing body is in an open state;
Open / closed state detecting means for detecting the open / closed state of the open / close body (door open detection switch 25, body frame open detection switch 925);
The operation state of the operation means is a specific operation state (an operation state in which a detection signal for specifying that the setting key switch 37 is ON when the power switch 39 is switched from OFF to ON (when the power is turned on)). A specific time determination means (Sa27b) for determining the open / closed state of the open / close body based on the detection result of the open / close state detecting means;
When the open / close body is determined to be in the open state by the specific time determination means, a setting change state in which the advantage can be changed by selecting any one of a plurality of setting values. Control (shift to Sa28), and when it is determined that the opening / closing body is not in the open state, control is not performed to the setting change state (shift to Sa27c); state control means (Sa27b, Sa27c, Sa28, Sa29, FIG. ,
Disabling means (Sa27c, Sa27c ′, Se22a to Se22c, Se35b) that disables the progress of the game when the opening / closing body is determined not to be in the open state by the specific time determining means.

  According to such a configuration, the open / close state of the opening / closing body is determined when the operation state of the operating means becomes the specific operation state, and when it is determined that the opening / closing body is not in the open state, the setting change state is controlled. There is nothing. In other words, if the opening / closing body is not in the open state, the operating means cannot be operated and the specific operation state cannot be obtained. When there is a possibility that an action has been performed, the setting change state is not controlled. Thereby, it can control more reliably to a setting change state by an unauthorized act, and a setting change can be prevented more reliably.

  Further, when an illegal act is performed, the progress of the subsequent game is disabled. For this reason, it is easily specified by the game hall manager or other players that the illegal act has been performed. As a result, fraud can be suppressed by increasing the risk of performing fraud.

  Note that the gaming machine may be any gaming machine that can change the advantage to the player, and a game that can change the display state of the variable display device can be started by setting the number of bets for one game. The display state of the variable display device is changed when a slot machine (see the embodiment), a game medium (for example, a pachinko ball) driven into a predetermined game area (game board) passes through a predetermined start area (start port) It may be a pachinko machine that can be used (see modified examples (5) and (6)).

  Further, the set value may be a value that defines an advantage for the player, and whether or not to permit the derivation of a specific display result (bonus, small combination, re-game combination, big hit, medium hit, small hit, etc.) is permitted. It may be a value that determines the probability that it is determined that the derivation of the specific display result is permitted by the predetermining means for determining whether or not the information advantageous to the player is notified, which is advantageous to the player It may be a value that defines the probability of shifting to a notification state in which information is notified. In addition, a probability that can be controlled in an advantageous state (bonus, assist time (AT), replay time (RT), jackpot, probability fluctuation state, etc.) advantageous to the player may be defined (modified example) (See (10)).

  The specific time determination means may determine the open state of the opening / closing body when the operation state of the operation means becomes the specific operation state, and the operation means when the opening / closing body is in the closed state. It may be determined whether or not the operation state is a specific operation state.

  The operation means may be one operation means for detecting one operation, and includes an operation means for detecting the first operation and an operation means for detecting a second operation different from the first operation. A plurality of types of operation means may be included. The operation state of the operation means may be the state of the operation unit of the operation means (such as a state where the setting key switch is ON), or the state of a signal output from the operation means (the setting key switch is ON). Or the state of a signal output when it is.

  When the front door (front door 1b) provided so that opening and closing is possible and the operation means can be operated by opening the front door, it can be said that the front door is the opening and closing body ( Slot machine). On the other hand, when the gaming machine main body is provided so as to be rotatable with respect to the outer frame, and the gaming machine main body is rotated to be in an open state, the operation means can be operated. It can be said that the gaming machine body is the opening / closing body (see pachinko machine). In other words, the opening / closing body may be a member that makes the operation means operable by opening it.

  (2) When the progress of the game is disabled by the disabling device, the operation state of the operating device becomes an operation state different from the specific operation state, so that the disabling operation cannot be canceled. A deactivation means is provided (Sa27c ′ in FIG. 69).

  According to such a configuration, the immobilization cannot be easily released for a person who has performed an illegal act, but the operation state of the operation means is different from the specific operation state by opening the opening / closing body. If it is a person who can be in a state (for example, a game hall manager), the immobilization can be canceled easily and quickly.

  (3) When the progress of the game is disabled by the disable function, the disabled change canceling means for canceling the disable function is provided by being controlled to the setting change state (FIG. 28). Sc14, Sc15).

  According to such a configuration, the immobilization cannot be easily released for a person who has performed an illegal act, but the operation state of the operation means is different from the specific operation state by opening the opening / closing body. If it is a person who can be in a state (for example, a game hall manager), the immobilization can be canceled easily and quickly.

  (4) The disabling means disables the progress of the game by invalidating a specific game operating means among the game operating means for detecting an operation for advancing the game (FIG. 31). Se35b).

  According to such a configuration, since the specific game operation means is invalidated regardless of the progress state of the game before being disabled, the processing for disabling it can be facilitated.

  (5) Even when the progress of the game is disabled by the disabling device, the disabling is not performed until the timing at which the game proceeds by operating the specific game operation device The same game progress control is performed (see Se35b in FIG. 31).

  According to such a configuration, it is not necessary to perform special control for disabling, and an increase in processing load can be prevented.

(6) Unlike the above-described operation means, game operation means that can be operated by the player (one-sheet BET switch 5, MAXBET switch 6, start switch 7, stop switches 8L, 8C, 8R, checkout switch 10),
Game control means (main control unit) for controlling the progress of a game in response to an operation of the game operation means and transmitting control information (command) based on the progress control of the game. 41),
Effect control means (sub control unit 91) for controlling the effect based on the control information received from the game control means,
The game control means includes
Setting change start control information transmitting means for transmitting setting change start control information (setting start command) to the effect control means when the setting change state starts;
Participation control means for controlling a particular game operation means (stop switches 8L, 8C, 8R) of the game operation means to a participation control state (reel rotation processing) related to the progress control of the game;
Operation control information transmitting means for transmitting operation control information (operation detection command) indicating an operation state of the specific game operation means to the effect control means in a control state other than the participation control state;
Advantage change control means (such as a setting change process) for performing change control for changing the advantage in the setting change state controlled by the state control means without being involved in the operation of the specific game operation means. Including,
The operation control information transmitting means transmits the operation control information to the effect control means even in the setting change state,
The production control means includes
An operation effect executing means for executing an operation effect based on the operation control information (setting start command) received from the game control means;
On the basis of receiving the setting change start control information, an administrator state control means for controlling to an administrator state (administrator mode) accessible to management information managed by the effect control means;
Control means for managers that performs control for managers (browsing management information, changing management information) based on the operation control information received from the game control means in the manager state.

  According to such a configuration, in the control state other than the participation control state in which the specific game operation unit is involved in the game progress control, the operation control information indicating the operation state of the specific game operation unit is transmitted to the effect control unit. Since the transmission is transmitted, it is possible to execute the effect based on the operation of the specific game operation means that is not involved in the progress control of the game. The effect control means controls to the manager state when receiving the setting change start control information indicating that the setting change state has started from the game control means, and also controls the operation from the game control means in the setting change state. Information is transmitted, and the management information managed by the effect control means can be accessed based on the operation control information received in the manager state synchronized with the setting change state. For this reason, without providing game operation means for accessing management information on the side of the production control means, the management information of the management information is utilized by utilizing a specific game operation means that is originally used for controlling the progress of the game by the game control means. Access operation can be performed.

  Note that the operation control information indicating the operation state of the specific game operation means is a state in which the specific game operation means is operated, a state in which the specific game operation means is not operated, It is possible to determine at least one of the fact that the game operation means has changed from an unoperated state to an operated state, and that a specific game operation means has changed from an operated state to an unoperated state. Any information may be used.

  In addition, the management information is information that can be accessed only by an administrator of the gaming machine such as an attendant of a game hall where the gaming machine is installed, for example, security information such as a door opening history that can be viewed only by the administrator, This corresponds to setting information as to whether or not the player can view information such as history information and game description.

  Further, the manager state control means may immediately control to the manager state based on the reception of the setting change start control information, or may further determine in advance after receiving the setting change start control information. When an additional condition such as operation of a given game operation means is satisfied, the administrator state may be controlled.

(7) a variable display device (reels 2L, 2C, 2R) capable of changing a display state;
Advantageous control means for controlling to a state (bonus) advantageous to the player based on the specific display result (bonus) derived as the display result of the variable display device;
Numerical value updating means (random number sequence changing circuit 555) for updating numerical data;
When a variable display condition for performing variable display for deriving a display result after changing the display state in the variable display device is satisfied (when the start switch 7 is operated and a valid start prize is generated). Random number extraction means (random number latch selector 558A) for extracting the numerical data updated by the numerical value updating means as a random number value and storing it in a first numerical data storage area (random number value register R1D);
After the numerical data is stored in the first numerical data storage area by the random number extraction unit, new numerical data is stored by the random number extraction unit until the stored numerical data is read. And numerical data holding means for holding numerical data stored in the first numerical data storage area (prohibition of latching of new numerical data),
Numerical data storage determining means for determining whether or not numerical data is stored in the first numerical data storage area (whether or not a random number latch flag is set) at regular time intervals (approximately 2.24 ms);
When the numerical data storage determination means determines that numerical data is stored in the first numerical data storage area (a random number latch flag is set), the numerical data storage determination means stores the numerical data in the first numerical data storage area. The numeric data holding means cancels the holding of the numeric data by the numeric data holding means, and the read numeric data is stored in a second numeric data storage area (random number value) different from the first numeric data storage area. Numerical data reading means stored in the storage work),
The specified display result using the numerical data stored in the second numerical data storage area according to the probability specified from the selected setting value when starting the change of the display state in the variable display device Predetermining means (internal lottery) for determining whether or not to permit the derivation of.

  According to such a configuration, after the numerical data extracted when the variable display condition is satisfied is stored in the first numerical data storage area, the stored numerical data is read and stored in the second numerical data storage. Until the data is stored in the area, the numerical data stored in the first numerical data storage area is retained and will not be overwritten by new numerical data. However, the numerical data will not change.

  Further, it is determined whether or not numerical data is stored in the first numerical data storage area at regular time intervals. If numerical data is stored in the first numerical data storage area, the first numerical value is stored. The numerical data stored in the data storage area is read out, and the numerical data retention by the numerical data retaining means is released. Even if the numerical data is retained, the state exceeds a certain time. It is possible to store new numerical data without continuing. For this reason, it is possible to acquire numerical data extracted at the timing when the variable display condition is satisfied.

  The numerical data storage determining means determines that new numerical data is stored in the first numerical data storage area, and whenever the numerical data is read from the first numerical data storage area, the second numerical data is stored. The numerical data in the storage area is updated to the numerical data read from the first numerical data storage area, that is, the newly extracted numerical data, and the predetermination means is stored in the first numerical data storage area. Since the numerical data stored in the second numerical data storage area is used instead of the numerical data stored in the first numerical data storage area after the numerical data is read out from the first numerical data storage area, Even if the data changes, the numerical data in the second numerical data storage area used by the predetermining means is not affected. Even in such a case, the variable display condition is not changed. A determination can be made whether to permit the derivation of specific display result using the numerical data extracted in standing timing.

  The numerical data used for determining whether to permit the derivation of the specific display result by the prior determination means may be numerical data stored in the second numerical data storage area. It may be numerical data stored in the second numerical data storage area when performing (slot machine), or numerical data stored in the second numerical data storage area until the determination is made. Is read and stored in a third numerical data storage area different from the second numerical data storage area (for example, a so-called reserved storage area for storing a random number extracted corresponding to the start winning prize) When data reading means is provided, it may be numerical data stored in the third numerical data storage area when making the determination (pachinko machine).

(8) a variable display device (reels 2L, 2C, 2R) capable of changing the display state;
Advantageous control means for controlling to a state (bonus) advantageous to the player based on the specific display result (bonus) derived as the display result of the variable display device;
Numerical value updating means (random number sequence changing circuit 555) for updating numerical data;
When a variable display condition for performing variable display for deriving a display result after changing the display state in the variable display device is satisfied (when the start switch 7 is operated and a valid start prize is generated). Random number extraction means (random number latch selector 558A) for extracting the numerical data updated by the numerical value updating means as a random number value and storing it in a first numerical data storage area (random number value register R1D);
After the numerical data is stored in the first numerical data storage area by the random number extraction unit, new numerical data is stored by the random number extraction unit until the stored numerical data is read. And numerical data holding means for holding numerical data stored in the first numerical data storage area (prohibition of latching of new numerical data),
Interrupt generating means for generating an interrupt (random number latch interrupt) when numerical data is stored in the first numerical data storage area;
In response to the occurrence of the interrupt by the interrupt generation means, reading of the numerical data stored in the first numerical data storage area releases the numerical data holding by the numerical data holding means. And numerical data reading means for storing the read numerical data in a second numerical data storage area (random value storage work) different from the first numerical data storage area;
The specified display result using the numerical data stored in the second numerical data storage area according to the probability specified from the selected setting value when starting the change of the display state in the variable display device Predetermining means (internal lottery) for determining whether or not to permit the derivation of.

  According to such a configuration, after the numerical data extracted when the variable display condition is satisfied is stored in the first numerical data storage area, the stored numerical data is read and stored in the second numerical data storage. Until the data is stored in the area, the numerical data stored in the first numerical data storage area is retained and will not be overwritten by new numerical data. However, the numerical data will not change.

  In addition, when numerical data is stored in the numerical data storage area, an interrupt occurs, and the numerical data stored in the numerical data storage area is read according to the interrupt, and the numerical data holding means holds the numerical data Is released, and the numerical data is immediately read in response to the occurrence of an interrupt, and a new numerical data can be stored. For this reason, it is possible to acquire numerical data extracted at the timing when the variable display condition is satisfied.

  Further, every time numerical data is read from the first numerical data storage area when new numerical data is stored in the first numerical data storage area and an interruption occurs, the numerical data in the second numerical data storage area Is updated to the numerical data read from the first numerical data storage area, that is, the newly extracted numerical data, and the pre-determining means is the numerical data stored in the first numerical data storage area. Since the numerical data stored in the second numerical data storage area is used, the numerical data is changed due to noise on the signal line after the numerical data is read from the first numerical data storage area. However, the numerical data in the second numerical data storage area used by the predetermining means is not affected, and even in such a case, extraction is performed at the timing when the variable display condition is satisfied. Numerical data using a determination can be made whether to permit the derivation of specific display results.

  The numerical data holding means stores the numerical data stored in the first numerical data storage area by the random number extracting means until the stored numerical data is read after the numerical data is stored by the random number extracting means. By prohibiting new extraction, the numerical data stored in the first numerical data storage area may be retained, or numerical data may be stored in the first numerical data storage area by the random number extraction means. After the storage, until the stored numerical data is read, even if the random number extracting means extracts the numerical data, the first numerical data storage area is prohibited to store the first numerical data. The numerical data stored in the numerical data storage area may be held.

  The numerical data used for determining whether to permit the derivation of the specific display result by the prior determination means may be numerical data stored in the second numerical data storage area. It may be numerical data stored in the second numerical data storage area when performing (slot machine), or numerical data stored in the second numerical data storage area until the determination is made. Is read and stored in a third numerical data storage area different from the second numerical data storage area (for example, a so-called reserved storage area for storing a random number extracted corresponding to the start winning prize) When data reading means is provided, it may be numerical data stored in the third numerical data storage area when making the determination (pachinko machine).

  (9) A holding release unit (Sa206, Sm9 to Sm12) for releasing the holding of the numerical data by the numerical data holding unit when the game progress control is started (when the power is turned on, when the voltage is lowered, etc.).

  According to such a configuration, when the progress control of the game is started, the numerical data holding means is released, and the numerical data is read and new numerical data is stored. It becomes possible. For this reason, it is possible to prevent the numerical data stored erroneously in a state where the power supply voltage is unstable, such as when the progress control of the game is started, from being acquired as a random value.

  The holding release unit may release the holding of numerical data by the numerical data holding unit when the power is turned on. Thereby, for example, it is possible to prevent the numerical data stored erroneously in a state where the power supply voltage is unstable at the time of power-on or the like from being acquired as a random value.

Power monitoring means for monitoring a predetermined power supply voltage generated based on power supply to the gaming machine and outputting a detection signal based on the decrease in the predetermined power supply voltage;
After the detection signal is output from the power monitoring means, detection determination means for repeatedly determining the input state of the detection signal;
When the determination that the detection signal is not input by the detection determination means, comprising a power failure recovery control means for resuming the progress control of the game,
After the determination that the detection signal is not input by the detection determination unit, the holding release unit is configured to perform the numerical data before the progress control of the game is resumed by the power interruption recovery control unit. The numerical data held by the holding means may be released. Thereby, it is possible to prevent the numerical data stored in the random number storage means from being erroneously acquired as a random value when the power supply voltage is unstable, for example, when the predetermined power supply voltage is lowered.

(10) power supply monitoring means for monitoring a predetermined power supply voltage generated based on power supply to the gaming machine and outputting a detection signal based on a decrease in the predetermined power supply voltage;
A start command means for performing a start command (user reset) when a predetermined time has elapsed since the detection signal was output from the power monitoring means;
The holding release unit releases holding of numerical data by the numerical data holding unit in a period of waiting for power supply to stop after the detection signal is output from the power supply monitoring unit (FIG. 72). (Refer to Modification (7)).

  According to such a configuration, when the voltage is temporarily reduced, the numerical data is read when the voltage is stored in the numerical data storage area in the period of waiting for the power supply to stop. The holding of numerical data by the numerical data holding means is released. For this reason, even if the voltage temporarily becomes unstable, noise is applied to the signal line, the numerical data is stored in the numerical data storage area, and that state is maintained, it is immediately read out. Thus, new numerical data can be stored in the numerical data storage area. As a result, it is possible to prevent a decision related to the game from being performed using the numerical data held due to noise or the like after the return.

It is a front view of the slot machine of the embodiment to which the present invention is applied. It is an internal structure figure of a slot machine. It is a figure which shows the symbol arrangement | sequence of a reel. It is a block diagram which shows the structure of a slot machine. It is a block diagram which shows the structure of a main control part. It is a figure which shows an example of the address map in a main control part. It is a figure which illustrates the main part of a program management area and a built-in register. It is a figure which shows an example of the setting content in a header and function setting. It is a figure which shows an example of the setting content in 1st random number initial setting, 2nd random number initial setting, and interruption initial setting. It is a figure which shows an example of the setting content in security time setting. It is a figure which shows the structural example etc. of an internal information register. It is a block diagram which shows the structural example of a random number circuit. It is a figure which shows the structural example etc. of a random number sequence change register. It is explanatory drawing which shows the change operation | movement of the random number update rule by a random number sequence change circuit. It is explanatory drawing which shows the change operation | movement of the random number update rule by a random number sequence change circuit. It is a figure which shows the structural example etc. of a random value acquisition register. It is a figure which shows the structural example etc. of a random number latch selection register. It is a figure which shows the structural example of a random value register. It is a figure which shows the structural example etc. of a random number latch flag register. It is a figure which shows the structural example etc. of a random number interrupt control register. It is a figure which shows the structural example etc. of an input port register. It is a figure which shows the object combination of the internal lottery classified according to the structure of the combination determined as a prize, and a game state. It is a flowchart which shows the control content of the starting process (main) which a main control part performs at the time of starting. It is a flowchart which shows the control content of the security check process which a main control part performs. It is a flowchart which shows the control content of the security check process which a main control part performs. It is a flowchart which shows the control content of the random circuit abnormality inspection process which a main control part performs. It is a flowchart which shows the control content of the error process which a main control part performs when an error generate | occur | produces. It is a flowchart which shows the control content of the setting change process which a main control part performs. It is a flowchart which shows the control content of the game process which a main control part performs after a setting change process. It is a flowchart which shows the control content of the BET process which a main control part performs. It is a flowchart which shows the control content of the BET process which a main control part performs. It is a flowchart which shows the control content of the BET process which a main control part performs. It is a flowchart which shows the control content of the timer interruption process (main) which a main control part performs for every fixed interval. It is a flowchart which shows the control content of the timer interruption process (main) which a main control part performs for every fixed interval. It is a flowchart which shows the control content of the random value reading process which a main control part performs in a timer interruption process (main). It is a flowchart which shows the control content of the switch input determination process which a main control part performs in a timer interruption process (main). It is a flowchart which shows the control content of the command transmission process which a main control part performs in the timer interruption 2 of a timer interruption process (main). It is a flowchart which shows the control content of the interruption interruption process (main) performed when a main control part inputs a voltage drop signal from an interruption detection circuit. It is a timing chart for demonstrating operation | movement in a random number circuit. It is a timing chart which shows the relationship between operation of a start switch, and a random value register. It is a timing chart which shows the relationship between operation of a start switch, and a random value register. It is a timing chart which shows the relationship between operation of a start switch, and a random value register. It is a timing chart which shows the relationship between operation of a start switch, and a random value register. It is a timing chart which shows the relationship between operation of a start switch, and a random value register. It is a timing chart which shows the detection condition of a start switch. It is a flowchart which shows the control content of the starting process (sub) which a sub CPU performs at the time of starting. It is a flowchart which shows the control content of the timer interruption process (sub) which a sub CPU performs for every fixed interval. It is a flowchart which shows the control content of the timer interruption process (sub) which a sub CPU performs for every fixed interval. It is a flowchart which shows the control content of the timer interruption process (sub) which a sub CPU performs for every fixed interval. It is a flowchart which shows the control content of the operation detection process 1 which a sub CPU performs in a timer interruption process (sub). It is a flowchart which shows the control content of the operation detection process 2 which sub CPU performs in a timer interruption process (sub). It is a flowchart which shows the control content of the interruption interruption process (sub) performed when a sub CPU inputs a voltage drop signal from an interruption detection circuit. It is a figure which shows the operation switch which is related to the progress control of a game according to a control state, and the operation switch which is not related to the progress control of a game. It is a timing chart which shows the control situation of the main CPU at the time of starting. It is a timing chart which shows the control state of a sub CPU. It is a timing chart which shows the control state at the time of starting of a sub CPU. It is a timing chart which shows the control state at the time of starting of a sub CPU. It is a timing chart which shows the control state at the time of starting of a sub CPU. It is a timing chart which shows the control state at the time of starting of a sub CPU. It is a timing chart which shows the control state at the time of starting of a sub CPU. It is a figure which shows an example of an operation effect. It is a figure which shows the execution condition of a continuous operation effect. It is a figure which shows the browsing condition of stand information. It is a timing chart which shows the control situation of the main CPU and sub CPU at the time of a setting change. It is a timing chart which shows the control condition of the main CPU and sub CPU at the time of setting confirmation. It is a figure which shows an administrator mode screen. It is a figure which shows a history data clear screen. It is a figure which shows an option screen. It is a flowchart which shows the control content of the starting process (main) which a main control part performs at the time of starting in a modification. It is a flowchart which shows the control content of the random value latch interruption process performed every time the main control part latches a random number in a modification. It is a timing chart which shows the relation between operation of a start switch and a random number value register in a modification. It is a flowchart which shows the control content of the power interruption process (main) which a main control part in a modification performs by receiving a voltage drop signal. It is a perspective view of a pachinko machine. It is a perspective view of the pachinko machine which shows the state where the main part frame was opened. It is a perspective view of the pachinko machine which shows the state where the glass door was opened. It is a figure which shows the structure of the back side of a main body frame in the state which open | released the main body frame.

  Embodiments will be described below with reference to the accompanying drawings. In this embodiment, a slot machine is described as an example of a gaming machine. FIG. 1 is a front view showing the overall structure of the slot machine according to this embodiment, and FIG. 2 is a view showing the internal structure of the slot machine. The slot machine 1 includes a housing 1a having an open front surface and a front door 1b pivotally supported on a side end of the housing 1a.

  As shown in FIG. 2, inside the casing 1a of the slot machine 1 according to the present embodiment, reels 2L, 2C, and 2R (hereinafter, left reel, middle reel, right As shown in FIG. 1, a see-through window in which three consecutive symbols out of the symbols arranged on the reels 2L, 2C, and 2R are provided on the front door 1b. It is arranged so that it can be seen from 3.

  As shown in FIG. 3, on the outer periphery of the reels 2L, 2C, and 2R, “black 7”, “net 7 (shaded 7 in the figure)”, “white 7”, “BAR”, “replay”, A plurality of identifiable symbols such as “watermelon”, “black cherry”, “white cherry”, “bell”, and “orange” are drawn in a predetermined order, 21 pieces each. The symbols drawn on the outer peripheries of the reels 2L, 2C, and 2R are displayed in the upper, middle, and lower three stages in the see-through window 3, respectively.

  The reels 2L, 2C, and 2R are provided in correspondence with each other and rotated by reel motors 32L, 32C, and 32R (see FIG. 4), so that the symbols of the reels 2L, 2C, and 2R are continuously provided in the see-through window 3. In addition to being displayed while changing, by stopping the rotation of the reels 2L, 2C, and 2R, three consecutive symbols are derived and displayed on the fluoroscopic window 3 as display results.

  Inside the reels 2L, 2C, and 2R are reel sensors 33L, 33C, and 33R that detect a reference position for each of the reels 2L, 2C, and 2R, and a reel LED 55 that irradiates the reels 2L, 2C, and 2R from the back side. , Is provided. The reel LED 55 includes 12 LEDs corresponding to three consecutive symbols of the reels 2L, 2C, and 2R, and can irradiate each symbol independently.

  A display area 51a of a liquid crystal display 51 (see FIG. 1) is disposed at a position on the front side (player side) of each reel 2L, 2C, 2R of the front door 1b. The liquid crystal display 51 has a normally white liquid crystal panel having transparency in a state where no voltage is applied to the liquid crystal element, and a transmissive region 51b corresponding to the see-through window 3 of the display region 51a. The reels 2L, 2C, and 2R can be visually recognized from the player side through the see-through window 3. In addition, a backlight (not shown) that irradiates the display area 51a from behind is provided on the back surface of the display area 51a excluding the transmissive area 51b. (Not shown) is provided.

  On the front door 1b, a medal insertion unit 4 into which medals can be inserted, a medal payout exit 9 from which medals are paid out, and credits (the number of medals stored as a game value owned by the player) are used for one medal. One bet switch 5 operated when setting the bet number, and using the credit, the maximum bet number (in the present embodiment, of the prescribed number of bets determined in accordance with the gaming state within the range) When the gaming state is RB (BB), 2 is set when the normal gaming state is 3), the MAXBET switch 6 operated when setting, the medal stored as credits, and the medals used for setting the number of bets are settled. Settlement switch 10 operated at the time of (returning medals used for setting credits and bets), start switch 7 operated at the start of the game, reel 2L, C, stop switch 8L is operated to stop each rotation of the 2R, 8C, 8R, but are provided operable by the player.

  The front door 1b also displays a credit indicator 11 that displays the number of medals stored as credits, the number of medals acquired in BB, which will be described later, and an error code that indicates the contents when an error occurs. An auxiliary indicator 12 and a payout indicator 13 for displaying the number of medals paid out due to the occurrence of a prize are provided.

  Further, on the front door 1b, 1BETLED 14 that notifies that the bet number is set to 1 by lighting, 2BETLED 15 that notifies that the bet number is set to 2, and 3 bets are set. 3BET LED 16 to notify when lit, insertion request LED 17 to notify that a medal can be inserted is lit, start valid LED 18 to notify that the game start operation by the operation of the start switch 7 is effective, wait (previous Waiting state LED 19 for informing that it is in the state of waiting for the start of reel rotation since a certain period of time has not elapsed since the start of the game, during replay informing that it is in the replay game described later An LED 20 is provided.

  Inside the MAXBET switch 6, there is provided a BET switch valid LED 21 (see FIG. 4) for notifying by lighting that the betting number setting operation by the operation of the single BET switch 5 and the MAXBET switch 6 is effective. Inside the stop switches 8L, 8C, and 8R, left, middle, and right stop effective LEDs 22L, 22C, and 22R for informing that the reel stop operation by the corresponding stop switches 8L, 8C, and 8R is effective by lighting (FIG. 4).

  Inside the front door 1b, there is a reset switch 23 for detecting a reset operation for releasing an error state described later and a stop state described later by a predetermined key operation, while changing a set value and confirming a set value described later. A set value display 24 for displaying the set value at that time, and a flow path of medals inserted from the medal insertion unit 4 on the side of a hopper tank 34a (see FIG. 2) described later provided in the housing 1a or A medal selector having a insertion medal sensor 31 for detecting a medal that is inserted from the flow path switching solenoid 30 and the medal insertion unit 4 and selectively flows to the hopper tank 34a side to selectively switch to one of the medal payout exits 9 side. (Not shown) is provided.

  As shown in FIG. 2, a reel sensor 33L that can detect the reel reference positions of the reels 2L, 2C, and 2R, the reel motors 32L, 32C, and 32R, and the reels 2L, 2C, and 2R, as shown in FIG. , 33C, 33R (see FIG. 4), an external output board 1000 for outputting an external output signal, a hopper tank 34a for storing medals inserted from the medal insertion section 4, and a hopper tank 34a. The hopper unit 34 including the hopper motor 34b for paying out medals from the medal payout opening 9, and the payout sensor 34c for detecting medals paid out by driving the hopper motor 34b, the power box 100, and the front door 1b being opened. A door opening detection switch 25 for detection is provided.

  On the side of the hopper unit 34, an overflow tank 35 is provided for storing medals overflowing from the hopper tank 34a. Inside the overflow tank 35, a full sensor 35 a made up of a pair of electrically conductive members spaced apart from each other and provided at a height capable of detecting a predetermined amount of stored medals is provided. It is possible to detect that the medal storage amount stored in the inside when it is conductive by contacting through the medal stored in the inside exceeds a predetermined amount, that is, that the overflow tank is full. It has become.

  On the front surface of the power supply box 100 is a stop switch for selecting whether to enable / disable a stop function for controlling the stop state at the end of BB, which will be described later (a state in which the progress of the game is restricted until a reset operation is performed). 36a, automatic checkout for selecting whether the automatic checkout function is effective / invalid for controlling automatic checkout processing (processing for adjusting (returning) medals stored as credits regardless of the player's operation) at the end of BB described later The switch 36b functions as a setting key switch 37 for switching to a setting change state or a setting confirmation state when the power is turned on (starting up), and functions as a reset switch for canceling an error state or a stop state in a normal state. In the state, a reset / setting switch functioning as a setting switch for changing the setting value of the winning probability (outtake rate) of internal lottery described later. Chi 38, the power switch 39 is provided which is operated to ON / OFF the power.

  Further, the door opening detection switch 25 has a side surface provided with a power box 100 on which a setting key switch 37, a reset / setting switch 38, and a power switch 39, which are operated when changing setting values, as will be described later, are provided. It is provided on the opposite side. The power supply box 100 is provided at a lower position inside the housing 1a, whereas the door opening detection switch 25 is provided at an upper position inside the housing 1a. That is, the door opening detection switch 25 is provided at a position diagonal to the position where the power supply box 100 is provided inside the housing 1a.

  Note that the door opening detection switch 25 is provided on the housing 1a as long as it detects the open state of the front door 1b at the side facing the side where the power supply box 100 is provided or at a position opposite to the power supply box 100. It is not limited to that provided, and may be provided inside the front door 1b.

  As the door opening detection switch 25 in the present embodiment, a reflection type optical sensor is employed. For example, the optical sensor includes a light projecting unit that emits light (visible light, infrared light, and the like) and a light receiving unit that detects the light. The light projecting unit emits light in a predetermined direction, and the light receiving unit projects light. The front door 1b is in the closed state by detecting the light reflected by the reflecting member provided on the front door 1b only when the front door 1b is in the closed state among the light emitted from the section. It is configured to be identifiable. The door opening detection switch 25 may be any switch that can detect the open / closed state of the front door 1b. The door open detection switch 25 is not limited to a reflective optical sensor, and may be a transmissive type. It may be a switch that turns ON / OFF according to the open / closed state.

  When a game is played in the slot machine 1 of the present embodiment, first, medals are inserted from the medal insertion unit 4 or the bet number is set using credits. In order to use the credit, the single BET switch 5 or the MAXBET switch 6 may be operated. When a predetermined number of bets determined according to the gaming state are set, the pay lines L1 to L5 (see FIG. 1) become effective, and the operation of the start switch 7 is effective, that is, the game can be started. It becomes a state. In the present embodiment, as the specified number of bets, two gaming states are determined in RB (BB) and three in the normal gaming state. In addition, when a medal is inserted exceeding the maximum number out of the prescribed number corresponding to the gaming state, the amount is added to the credit.

  The winning line is a line that is set to determine whether a combination of symbols displayed on the perspective windows 3 of the reels 2L, 2C, and 2R is a winning symbol combination. In the present embodiment, as shown in FIG. 1, a winning line L1 set across the symbols arranged in the middle stage of each reel 2L, 2C, 2R and the symbols arranged in the upper stage of each reel 2L, 2C, 2R are displayed. The winning line L2 set across the reels 2L, 2C and 2R, the winning line L3 set over the lower symbols, the upper stage of the reel 2L, the middle stage of the reel 2C, the lower stage of the reel 2R, that is, lower right There are 5 types of winning lines L4 set across straddling symbols, the lower line of reel 2L, the middle part of reel 2C, the upper part of reel 2R, that is, the winning line L5 set straddling the symbols lined up to the right It is defined as a line.

  When the start switch 7 is operated in a state where the game can be started, the reels 2L, 2C, and 2R rotate, and the symbols of the reels 2L, 2C, and 2R continuously vary. When any one of the stop switches 8L, 8C, 8R is operated in this state, the rotation of the corresponding reels 2L, 2C, 2R is stopped, and the display result is derived and displayed on the fluoroscopic window 3.

  When one of the reels 2L, 2C, 2R is stopped, one game is completed, and a predetermined symbol combination (hereinafter also referred to as a role) is set on any of the activated pay lines L1 to L5. When the reels 2L, 2C, and 2R are stopped as a display result, a winning occurs, and a predetermined number of medals are given to the player and added to the credit.

  Further, when the credit reaches the upper limit number (50 in the present embodiment), medals are paid out directly from the medal payout opening 9 (see FIG. 1). If a combination of symbols with payout of medals is arranged on a plurality of activated pay lines, the total number of payouts determined for each combination of symbols arranged on the activated pay line is totaled. The total number of medals is awarded to the player.

  However, an upper limit (15 in this embodiment) is set for the number of medals to be awarded in one game. When the total number of medals exceeds the upper limit, the upper limit number of medals is awarded. The Rukoto. In addition, when a combination of symbols accompanying the transition of the gaming state is stopped as a display result of each reel 2L, 2C, 2R on any of the activated pay lines L1 to L5, a game corresponding to the combination of symbols Transition to the state.

  FIG. 4 is a block diagram showing a configuration of the slot machine 1. As shown in FIG. 4, the slot machine 1 is provided with a game control board 40, an effect control board 90, and a power supply board 101. The game state is controlled by the game control board 40, and the game state is controlled by the effect control board 90. The production according to the control is controlled, and the power supply board 101 generates the drive power for the electrical components constituting the slot machine 1 and supplies them to each part.

  The power supply board 101 is supplied with AC100V power from the outside, and a DC voltage necessary for driving the electrical components constituting the slot machine 1 is generated from the AC100V power supply. The game control board 40 and the game control board 40 It is supplied to the production control board 90 connected through the.

  Further, the above-described hopper motor 34b, payout sensor 34c, full sensor 35a, stop switch 36a, automatic checkout switch 36b, setting key switch 37, reset / setting switch 38, and power switch 39 are connected to the power supply board 101. Yes.

  On the game control board 40, the one-sheet BET switch 5, the MAXBET switch 6, the start switch 7, the stop switches 8L, 8C, 8R, the settlement switch 10, the reset switch 23, the insertion medal sensor 31, the door opening detection switch 25, The reel sensors 33L, 33C, and 33R are connected, and the above-described payout sensor 34c, full sensor 35a, stop switch 36a, automatic settlement switch 36b, setting key switch 37, reset / setting switch 38 are connected via the power supply board 101. Are connected, and the detection signals of these connected switches are inputted.

  Further, the game control board 40 includes the credit display 11, the game auxiliary display 12, the payout display 13, 1 to 3 BET LEDs 14 to 16, the insertion request LED 17, the start valid LED 18, the waiting LED 19, the replaying LED 20, and the BET. A switch valid LED 21, left, middle, and right stop valid LEDs 22L, 22C, 22R, a set value display 24, a flow path switching solenoid 30, reel motors 32L, 32C, 32R are connected, and a hopper is connected via the power supply board 101. A motor 34 b is connected, and these electric components are driven based on the control of the main control unit 41 mounted on the game control board 40.

  The game control board 40 includes a main control unit 41, a control clock generation circuit 42, a random number clock generation circuit 43, a switch detection circuit 44, a motor drive circuit 45, a solenoid drive circuit 46, an LED drive circuit 47, and a power interruption detection circuit. 48 and a reset circuit 49 are mounted.

  The main control unit 41 is constituted by a one-chip microcomputer, executes a control program stored in a ROM 506, which will be described later, and performs processing related to the progress of the game, and also includes a control circuit mounted on the game control board 40. Control each part directly or indirectly.

  The control clock generation circuit 42 generates a control clock CCLK serving as an oscillation signal having a predetermined frequency outside the main control unit 41. The control clock CCLK generated by the control clock generation circuit 42 is supplied to the clock circuit 502 via the control external clock terminal EXC of the main control unit 41 as shown in FIG. 5, for example. The random number clock generation circuit 43 generates a random number clock RCLK that is an oscillation signal having a predetermined frequency different from the oscillation frequency of the control clock CCLK, outside the main control unit 41.

  The random number clock RCLK generated by the random number clock generation circuit 43 is supplied to the random number circuit 509 via the random number external clock terminal ERC of the main control unit 41 as shown in FIG. As an example, the oscillation frequency of the random number clock RCLK generated by the random number clock generation circuit 43 may be set to be equal to or lower than the oscillation frequency of the control clock CCLK generated by the control clock generation circuit 42.

  The switch detection circuit 44 takes in detection signals input from switches connected directly to the game control board 40 or via the power supply board 101 and transmits them to the main control unit 41. The motor drive circuit 45 transmits the motor drive signal output from the main control unit 41 to the reel motors 32L, 32C, and 32R. The solenoid drive circuit 46 transmits the solenoid drive signal output from the main control unit 41 to the flow path switching solenoid 30. The LED drive circuit transmits the LED drive signal output from the main control unit 41 to various displays and LEDs connected to the game control board 40.

  The power interruption detection circuit 48 monitors the power supply voltage supplied to the slot machine 1 and outputs a voltage drop signal indicating that to the main control unit 41 when a voltage drop is detected. The reset circuit 49 gives a reset signal to the main control unit 41 in a state where the power supply is unstable, such as when the power is turned on or when the power is turned off.

  FIG. 5 shows a configuration example of the main control unit 41 mounted on the game control board 40. The main control unit 41 shown in FIG. 5 is a one-chip microcomputer, and includes an external bus interface 501, a clock circuit 502, a specific information storage circuit 503, a reset / interrupt controller 504, a CPU 505, a ROM 506, and a RAM 507. A CTC (counter / timer circuit) 508, a random number circuit 509, a PIP (parallel input port) 510, a serial communication circuit 511, and an address decoding circuit 512.

  FIG. 6 shows an example of an address map in the main control unit 41. As shown in FIG. 6, the area from address 0000H to address 1FFFH is allocated to the ROM 506 and includes a user program area and a program management area. FIG. 7A shows an example of the usage and contents of the main part of the program management area in the ROM 506.

  The area from address 2000H to address 20FFH is a built-in register area assigned to the built-in register of the main control unit 41. FIG. 7B shows an example of the usage and contents of the main part of the built-in register area. An area from address 7E00H to address 7FFFH is a work area assigned to the RAM 507, and can be assigned to an I / O map or a memory map. An area from address FDD0H to address FDFBH is an XCS decode area allocated to the address decode circuit 512.

  The program management area is a storage area for storing information necessary for the CPU 505 to execute the user program. As shown in FIG. 7A, the program management area includes a header KHDR, a function setting KFCS, a first random number initial setting KRS1, a second random number initial setting KRS2, an interrupt initial setting KIIS, a security time setting KSES, include.

  A header KHDR stored in the program management area indicates reading setting of internal data in the main control unit 41. FIG. 8A illustrates the correspondence between setting data and operation in the header KHDR. Here, the main control unit 41 can set a ROM read prevention function and a bus output mask function. The ROM read prevention function is a function for permitting or prohibiting the read operation for the data stored in the ROM 506 provided in the main control unit 41. When the read prohibition is set, the data stored in the ROM 506 cannot be read. The bus output mask function is used for address bus output, data bus output, and control signal output in the external bus interface 501 when an external device connected to the external bus interface 501 makes a read request for internal data of the main control unit 41. This function disables reading of internal data from an external device by applying a mask.

  As shown in FIG. 8A, the operation combination of the ROM read prevention function and the bus output mask function is set differently in accordance with the setting data of the header KHDR. Of the setting data shown in FIG. 8A, the setting data for which ROM reading is permitted and the bus output mask is valid is also referred to as bus output mask valid data. Further, the setting data (all “00H”) in which ROM reading is prohibited and the bus output mask is valid is also referred to as ROM reading prohibiting data. The setting data for which ROM reading is permitted and the bus output mask becomes invalid is also referred to as bus output mask invalid data.

  The function setting KFCS stored in the program management area indicates the operation setting of the watchdog timer in the main control unit 41 and the use setting of various function shared terminals. FIG. 8B shows an example of setting contents in the function setting KFCS.

  The bit number [7-5] of the function setting KFCS indicates, for example, permission / prohibition of operation of the watchdog timer that can be set as an interrupt factor in the reset / interrupt controller 504, and a cycle when it is permitted. The bit number [4] of the function setting KFCS indicates that the predetermined function shared terminal (first shared terminal) in the main control unit 41 is the second channel transmission terminal TXB used by the serial communication circuit 511 or the address decoding circuit 512. Is a TXB terminal setting that designates whether to use the chip select output terminal XCS13.

  In the example shown in FIG. 8B, if the bit value in the bit number [4] of the function setting KFCS is “0”, the first shared terminal is used for the second channel transmission in the serial communication circuit 511. This is the setting for the 2-channel transmission terminal TXB. On the other hand, if the bit value is “1”, the first dual-purpose terminal is set to the chip select output terminal XCS13 used in the address decode circuit 512. In the present embodiment, the bit number [4] of the function setting KFCS is set to “0”, and the first shared terminal is set to the second channel transmission terminal TXB, so that serial communication with the effect control board 90 is performed. to enable.

  The bit number [3] of the function setting KFCS indicates that the predetermined function shared terminal (second shared terminal) in the main control unit 41 is the first channel transmission terminal TXA used by the serial communication circuit 511 or the address decoding circuit 512. Is a TXA terminal setting indicating whether the chip select output terminal XCS12 is used. In the example shown in FIG. 8B, if the bit value in the bit number [3] of the function setting KFCS is “0”, the second shared terminal is used for the first channel transmission in the serial communication circuit 511. 1 channel transmission terminal TXA is set. On the other hand, if the bit value is “1”, the second dual-purpose terminal is set to the chip select output terminal XCS12 used in the address decode circuit 512. In the present embodiment, the bit number [3] of the function setting KFCS is set to “0” and the second shared terminal is set to the first channel transmission terminal TXA, but the first channel reception is unused. .

  For the bit number [2] of the function setting KFCS, a predetermined function shared terminal (third shared terminal) in the main control unit 41 is used as the first channel reception terminal RXA used by the serial communication circuit 511, or is used by the PIP 510. This is an RXA terminal setting indicating whether the input port is P5. In the example shown in FIG. 8B, if the bit value in the bit number [2] of the function setting KFCS is “0”, the third shared terminal is used for the first channel reception in the serial communication circuit 511. 1 channel receiving terminal RXA is set. On the other hand, if the bit value is “1”, the third shared terminal is set to the input port P5 used in the PIP 510. In the present embodiment, the bit number [2] of the function setting KFCS is set to “0” and the third shared terminal is set to the first channel reception terminal RXA, but the first channel reception is unused. .

  The bit number [1] of the function setting KFCS is an input used by the PIP 510, or a predetermined function shared terminal (fourth shared terminal) in the main control unit 41 is an external non-maskable interrupt terminal XNMI connected to the CPU 505 or the like. This is an NMI connection setting indicating whether to set the port P4. In the example shown in FIG. 8B, if the bit value [1] in the bit number [1] of the function setting KFCS is “0”, the setting of the external non-maskable interrupt terminal XNMI whose fourth shared terminal is connected to the CPU 505 and the like (CPU connection). On the other hand, if the bit value is “1”, the fourth shared terminal is set for the input port P4 used in the PIP 510 (CPU disconnected). In this embodiment, the bit number [1] of the function setting KFCS is set to “1” and the fourth shared terminal is set to the input port P4 used in the PIP 510, but the input port P4 is unused. Yes.

  The bit number [0] of the function setting KFCS is an input used by the PIP 510, or the predetermined function shared terminal (fifth shared terminal) in the main control unit 41 is set to the external maskable interrupt terminal XINT connected to the CPU 505 or the like. This is an XINT connection setting indicating whether the port is P3. In the example shown in FIG. 8B, if the bit value in the bit number [0] of the function setting KFCS is “0”, the setting of the external maskable interrupt terminal XINT in which the fifth shared terminal is connected to the CPU 505 and the like (CPU connection). On the other hand, if the bit value is “1”, the fifth shared terminal is set for the input port P3 used in the PIP 510 (CPU disconnected). In the present embodiment, the bit number [0] of the function setting KFCS is set to “0”, and the fourth shared terminal is set to the external maskable interrupt terminal XINT connected to the CPU 505 or the like. The voltage drop signal is input.

  The first random number initial setting KRS1 and the second random number initial setting KRS2 stored in the program management area indicate the initial setting of the random number circuit 509. FIG. 9A shows an example of the setting contents in the first random number initial setting KRS1. FIG. 9B shows an example of setting contents in the second random number initial setting KRS2.

  The bit number [3] of the first random number initial setting KRS1 is a random number circuit use setting indicating whether to use the random number circuit 509 or not. In the example shown in FIG. 9A, if the bit value in the bit number [3] of the first random number initial setting KRS1 is “0”, the random number circuit 509 is not used (unused), but “1”. "Is set to use the random number circuit 509 (use). In this embodiment, the random number circuit 509 is set to be usable by setting the bit number [3] of the first random number initial setting KRS1 to “1”.

  The bit number [2] of the first random number initial setting KRS1 uses the random number update clock RGK (see FIG. 12) used for updating the numerical data as the random number value in the random number circuit 509 as the internal system clock SCLK or for the random number This is a random number update clock setting indicating whether the clock RCLK is divided by two. In the example shown in FIG. 9A, if the bit value in the bit number [2] of the first random number initial setting KRS1 is “0”, the internal system clock SCLK is set to be used as the random number update clock RGK. If it is 1 ″, the random number clock RCLK is divided by two and used as the random number update clock RGK. In the present embodiment, the bit number [2] of the first random number initial setting KRS1 is set to “1”, and the random number clock RCLK is divided by two to be used as the random number update clock RGK.

  The bit number [1-0] of the first random number initial setting KRS1 is a random number update rule setting indicating whether or not to change the random number update rule in the random number circuit 509 and the change method in the case of the change. In the example shown in FIG. 9A, if the bit value in the bit number [1-0] of the first random number initial setting KRS1 is “00”, the random number update rule is not changed, and if it is “01”. The setting for changing the random number update rule by software is made after the second round, and if it is “10”, the random number update rule is automatically changed after the second round.

  The bit number [3-2] of the second random number initial setting KRS2 is set to a fixed bit value “00”. Note that “B” of “00B” in FIG. 9B indicates binary display. The bit number [1-0] of the second random number initial setting KRS2 indicates the setting relating to the start value in the numerical data that becomes the random value in the random number circuit 509. In the example shown in FIG. 9B, if the bit value in the bit number [1] of the second random number initial setting KRS2 is “0”, the start value is set to a predetermined default value 0001H, while “1”. Is set to a value based on an ID number, which is unique identification information given to each main control unit 41.

  In the example shown in FIG. 9B, if the bit value in the bit number [0] of the second random number initial setting KRS2 is “0”, the start value is not changed every time the system is reset. When it is 1 ″, the start value is changed every time the system is reset. In addition, when setting the start value to a value based on the ID number, a part or all of the calculation for performing a predetermined scramble process on the ID number and the calculation such as addition / subtraction / multiplication / division using the ID number are performed. It is only necessary to execute and use the calculated value as the start value.

  When the start value is changed at each system reset, for example, the count value of the free run counter built in the main control unit 41 is set to a predetermined internal register (random number start) provided in the main control unit 41 when the system reset occurs. Value register). Then, by using the stored value of the random number start value register as it is at the time of initial setting, or by using a value obtained by substituting the stored value into a predetermined arithmetic function (for example, a hash function), the start value is It may be determined at random.

  The free-run counter only needs to be backed up using a backup power source common to the backup location on the game control board 40. Alternatively, the free-run counter may be backed up by a power source provided separately from a backup power source used for a backup area in the RAM 507 or the like. In this way, the free-run counter is backed up by the backup power supply, so that the count value in the free-run counter is stored for a predetermined period even when the power supply is stopped.

  Note that when two systems (corresponding to the first and second channels) for generating numerical data to be random numbers in the random number circuit 509 are provided, the first shown in FIGS. 9A and 9B. The bit number [3-0] of the random number initial setting KRS1 and the bit number [3-0] of the second random number initial setting KRS2 are used to indicate the initial setting in the first channel. On the other hand, the bit number [7-4] of the first random number initial setting KRS1 and the bit number [7-4] of the second random number initial setting KRS2 (omitted in FIGS. 9A and 9B), the second It may be used as an indication of the initial setting in the channel.

  The interrupt initial setting KIIS stored in the program management area indicates an initial setting related to handling of maskable interrupts generated in the main control unit 41. FIG. 9C shows an example of setting contents in the interrupt initial setting KIIS.

  In the bit number [7-4] of the interrupt initial setting KIIS, the upper 4 bits of the interrupt vector are set. In the bit number [3-0] of the interrupt initial setting KIIS, a combination of priority levels of maskable interrupt factors is set. In the example shown in FIG. 9C, if any of “00H” to “02H” and “06H” is specified by the bit number [3-0] of the interrupt initial setting KIIS, the maskable interrupt from the CTC 508 A combination of priorities with the factor as the highest priority is set. On the other hand, if any one of “03H” and “07H” is specified, a combination of priorities with the highest priority given to the maskable interrupt factor from the random number circuit 509 is set. If either “04H” or “05H” is designated, a combination of priorities that gives the highest priority to the maskable interrupt factor from the serial communication circuit 511 is set. In addition, even if the priority combination has the highest priority for maskable interrupt factors from the same circuit, if the specified value is different, the type of maskable interrupt factor that has the highest priority, the priority combination in the second or lower order, etc. Is different.

  The security time setting KSES stored in the program management area is the frequency at which an abnormality is detected when monitoring the frequency of the random number clock RCLK, the time of the security mode in which the main control unit 41 starts operation (security time). ). Here, when the operation mode of the main control unit 41 is the security mode, a predetermined security check process is executed to check whether or not the contents stored in the ROM 506 have been changed. FIG. 10A shows an example of setting contents in the security time setting KSES.

  Bit number [7-6] of security time setting KSES is a random number clock abnormality detection setting indicating a frequency at which an abnormality is detected when the frequency of random number clock RCLK is monitored. FIG. 10B shows an example of setting contents in the bit number [7-6] of the security time setting KSES. The bit number [7-6] of the security time setting KSES specifies a reference value (determination value) at which the frequency of the random number clock RCLK is detected as abnormal based on the frequency of the internal system clock SCLK. The bit number “5” of the security time setting KSES is set to a fixed bit value “0”.

  The bit number [4-3] of the security time setting KSES indicates a time setting when the security time is extended by a random time every system reset. FIG. 10C shows an example of setting contents in the bit number [4-3] of the security time setting KSES. In the example shown in FIG. 10C, if the bit value in the bit number [4-3] of the security time setting KSES is “00”, the random time extension is not performed. On the other hand, if the bit value is “01”, the short mode is set, and if the bit value is “10”, the long mode is set.

  Here, when the short mode or the long mode is designated, for example, the count value of the free run counter built in the main control unit 41 is set to a predetermined built-in register (variable) included in the main control unit 41 when a system reset occurs. Store in the security time register. Then, the security time can be reduced by using the stored value of the variable security time register as it is at the time of initial setting or by using the value obtained by substituting the stored value into a predetermined arithmetic function (for example, a hash function). What is necessary is just to determine the extension time at the time of extending at random.

  As an example, when the frequency of the internal system clock SCLK is 6.0 MHz, the extension time is randomly determined in the range of 0 to 680 μs (microseconds) in the short mode, and in the range of 0 to 348, 160 μs in the long mode. The extension time is determined at random. As another example, when the frequency of the internal system clock SCLK is 10.0 MHz, the extension time is randomly determined in the range of 0 to 408 μs in the short mode, and in the range of 0 to 208,896 μs in the long mode. The extension time is determined at random. The free-run counter used for randomly determining the extension time for extending the security time for each system reset randomly determines the start value of the random number generated by the random number circuit 509 for each system reset. Therefore, the counter may be the same as the free-run counter used for the purpose, or may be a counter provided separately.

Bit number [2-0] of security time setting KSES indicates time setting when the security time is set to one of a plurality of pre-selectable extended times in addition to the fixed time. FIG. 10D shows an example of setting contents in the bit number [2-0] of the security time setting KSES. In the example shown in FIG. 10D, if the bit value in the bit number [2-0] of the security time setting KSES is “000”, there is no extension time added to the fixed time, and no setting is made. On the other hand, if the bit value is a value other than “000”, it is set to one of a plurality of extension times determined using the cycle T _SCLK of the internal system clock SCLK. In this case, a different extension time is set according to the designated bit value.

  As an example, if the bit value [2-0] of the security time setting KSES is “001” when the frequency of the internal system clock SCLK is 6.0 MHz, about 699.1 ms in addition to the fixed time. An extension time of (milliseconds) is set. As another example, when the frequency of the internal system clock SCLK is 10.0 MHz and the bit value in the bit number [2-0] of the security time setting KSES is “001”, in addition to the fixed time An extension time of about 419.4 ms is set.

  Further, the short mode or the long mode is set by the bit value [4-3] of the security time setting KSES, and the bit value in the bit number [2-0] of the security time setting KSES is set to other than “000”. Thus, it is possible to set an extension time to be added to the fixed time. In this case, both the extension time corresponding to the bit value in the bit number [2-0] and the extension time randomly determined based on the bit value in the bit number [4-3] are fixed times. By adding, the security time for the main control unit 41 to be in the security mode is determined.

  The external bus interface 501 provided in the main control unit 41 shown in FIG. 5 is an interface function between the external bus and the internal bus of the chip constituting the main control unit 41, an address bus, a data bus, and a direction control function of each control signal. Is a bus interface. For example, the external bus interface 501 is connected to an external memory or an external input / output device externally attached to the main control unit 41, and transmits / receives address signals, data signals, various control signals, and the like to / from these external devices. Anything to do. In this embodiment, the external bus interface 501 includes an internal resource access control circuit 501A.

  The internal resource access control circuit 501A controls access to internal data of the main control unit 41 from an external device via the external bus interface 501, and stores internal data such as a game control program and fixed data stored in the ROM 506, for example. This is a circuit for limiting inappropriate external reading. Here, a circuit analysis device such as an in-circuit emulator (ICE) may be connected to the external bus interface 501 as an external device.

  As an example, according to the contents of the header KHDR stored in the program management area of the ROM 506, it is possible to switch between prohibiting or permitting reading of stored data in the ROM 506. For example, if the header KHDR is bus output mask invalid data, the ROM 506 can be read by an external device, and external reading of internal data is permitted. On the other hand, if the header KHDR is bus output mask valid data, the ROM 506 can be read from the external device by masking the address bus output, data bus output and control signal output in the external bus interface 501, for example. Is disabled, and external reading of internal data is prohibited. In this case, when reading of internal data is requested from an external device connected to the external bus interface 501, a predetermined fixed value is output so that internal data cannot be read from the external device. .

  Further, when the header KHDR is ROM read prohibition data, the ROM 506 itself may not be read, and reading of stored data in the ROM 506 may be prevented. For example, in a ROM at the manufacturing stage, by making the header KHDR ROM read prohibition data, the ROM itself is made unreadable, and if it is a development ROM, bus output mask invalid data is written in the header KHDR, Allows verification of internal data by an external device. On the other hand, in the case of a mass production ROM, the bus output mask valid data is written in the header KHDR so that the CPU 505 and the like can read out the ROM 506 inside the main control unit 41 while the ROM 506 by an external device. It suffices to prevent reading of.

  As another example, the internal resource access control circuit 501A has requested that the internal data of the main control unit 41, such as all or part of the stored data in the ROM 506, be read from an external device connected to the external bus interface 501. Is detected. When detecting this read request, the internal resource access control circuit 501A determines whether or not to permit the main control unit 41 to read internal data. For example, it is assumed that all or part of the stored data in the ROM 506 has been encrypted. In this case, if the read request from the external device is a read request for an encryption processing program or key data stored in the ROM 506, the internal resource access control circuit 501A rejects the read request and sets the main control unit 41. Reading of internal data is prohibited. In the external bus interface 501, a switch element is provided between the output port from which data stored in the ROM 506 is output and the internal bus. When the internal resource access control circuit 501 A prohibits reading of the internal data, the switch element May be controlled to be turned off. As described above, the internal resource access control circuit 501A reads the internal data depending on whether or not the read request from the external device requests reading of predetermined internal data (for example, a predetermined area of the ROM 506). You may make it determine whether it prohibits or permits.

  Alternatively, the internal resource access control circuit 501A may determine whether or not a predetermined authentication code has been input from the external device when detecting a read request for internal data. In this case, for example, a predetermined code pattern serving as an authentication code may be stored in advance in the internal resource access control circuit 501A or in a predetermined area of the ROM 506. When an authentication code is input from the external device, this authentication code is compared with the internally stored authentication code. If they match, a read request is accepted and the main control unit 41 is allowed to read internal data. . On the other hand, if the authentication code input from the external device does not match the authentication code stored internally, the read request is rejected and the internal control unit 41 is prohibited from reading the internal data. As described above, the internal resource access control circuit 501A determines whether to prohibit or permit reading of the internal data depending on whether or not the authentication code input from the external device matches the authentication code stored internally. You may make it do. As a result, it is possible to read out the internal data of the main control unit 41 using a correct authentication code obtained in advance by an inspection organization or the like, and to check the validity of the internal data appropriately. .

  As yet another example, a read prohibition flag is provided in the internal resource access control circuit 501A, and reading of the ROM 506 by an external device is prohibited if the read prohibition flag is on. On the other hand, when the reading prohibition flag is in the off state, reading of the ROM 506 by the external device is permitted. Here, the read prohibition flag is off in the initial state, but once the read prohibition flag is turned on, the read prohibition flag cannot be cleared and returned to the off state. That's fine.

  That is, the read prohibition flag can be irreversibly changed from the off state to the on state. For example, the internal resource access control circuit 501A is not provided with a function of clearing the read prohibition flag to turn it off, and is set so that the read prohibition flag cannot be cleared by any instruction. Just do it. Then, the internal resource access control circuit 501A determines whether or not the read prohibition flag is on when the external device requests to read the internal data of the main control unit 41 such as the data stored in the ROM 506. At this time, if the read prohibition flag is on, the read request from the external device is rejected and the main controller 41 is prohibited from reading the internal data.

  On the other hand, if the read prohibition flag is off, the read request from the external device is accepted and the main controller 41 is allowed to read the internal data. With such a configuration, a provider who creates a game control program and stores it in the ROM 506 reads the program that has been debugged from the ROM 506 into an external device while the read prohibition flag is off. Can do.

  Then, when shipping after the debugging work is completed, by setting the read prohibition flag to the on state, external reading of the ROM 506 can be restricted thereafter, and the ROM 506 by the user of the slot machine 1 or the like can be restricted. Can be prevented from being read. As described above, the internal resource access control circuit 501A may determine whether to prohibit or permit reading of internal data depending on whether an internal flag such as a read prohibition flag is off or on. .

  Note that the read prohibition flag is not set irreversibly but can be changed from the on state to the off state, while the read prohibition flag is changed from the on state to the off state to permit reading of internal data. In this case, the external reading of the ROM 506 may be restricted by erasing the data stored in the ROM 506 (for example, flash erasure).

  The clock circuit 502 provided in the main control unit 41 is a circuit that generates the internal system clock SCLK by, for example, dividing the oscillation signal input to the control external clock terminal EXC by two. In the present embodiment, the control clock CCLK generated by the control clock generation circuit 42 is input to the control external clock terminal EXC. The internal system clock SCLK generated by the clock circuit 502 is supplied to various circuits such as the CPU 505 that control the progress of the game in the main control unit 41.

  The internal system clock SCLK is also supplied to the random number circuit 509 and used to monitor the frequency of the random number clock RCLK supplied from the random number clock generation circuit 43. Further, the internal system clock SCLK may be output from the system clock output terminal CLKO connected to the clock circuit 502 to the outside of the main control unit 41. It is desirable that the internal system clock SCLK is not output to the outside of the main control unit 41. As described above, by limiting the external output of the internal system clock SCLK, it becomes difficult to specify the operation cycle of the internal circuit (such as the CPU 505) of the main control unit 41 from the outside. In the case of updating by this, it is possible to prevent the random number update cycle from being specified externally.

  The unique information storage circuit 503 included in the main control unit 41 is a circuit that stores a plurality of types of unique information serving as internal information of the main control unit 41, for example. As an example, the unique information storage circuit 503 stores three types of unique information such as a ROM code, a chip individual number, and an ID number. The ROM 506 code is a 4-byte numerical value generated from stored data in a predetermined area of the ROM 506, and four numerical values with different generation methods may be prepared. The chip individual number is a 4-byte number assigned when the main control unit 41 is manufactured, and indicates a different numerical value for each chip constituting the main control unit 41. The ID number is an 8-byte number assigned when the main control unit 41 is manufactured, and indicates a different numerical value for each chip constituting the main control unit 41.

  Here, the chip individual number may be read from the user program, while the ID number may be set so as not to be read from the user program. Note that the unique information storage circuit 503 may be included in the ROM 506 by using a predetermined area of the ROM 506, for example. Alternatively, the unique information storage circuit 503 may be included in the CPU 505 by using a built-in register of the CPU 505, for example.

  The reset / interrupt controller 504 provided in the main control unit 41 is for controlling various resets and interrupt requests generated inside or outside the main control unit 41. The reset controlled by the reset / interrupt controller 504 includes a system reset and a user reset. The system reset is a reset that occurs when a low level signal is input to the external system reset terminal XSRST for a certain period. User reset occurs when the watchdog timer (WDT) times out and a time-out signal is generated (that is, when the operation of the CPU 505 of the main control unit 41 is stopped for a certain period of time) or when travel outside the designated area is prohibited (IAT). This is a reset caused by a predetermined factor.

  Interrupts controlled by the reset / interrupt controller 504 include a non-maskable interrupt NMI and a maskable interrupt INT. The non-maskable interrupt NMI is an interrupt that is unconditionally accepted even when the CPU 505 is in an interrupt-disabled state. When a low level signal is input to the external non-maskable interrupt terminal XNMI (also used as the input port P4) for a certain period of time. An interrupt that occurs. The maskable interrupt INT is an interrupt that can permit / prohibit acceptance of an interrupt request by a setting instruction of the CPU 505, and multiple interrupts can be executed by setting priority. The maskable interrupt INT is caused by the fact that a low level signal has been input to the external maskable interrupt terminal XINT (also used as the input port P3) for a certain period of time, a time-out has occurred in the timer circuit included in the CTC 508, A plurality of types of interrupt factors are determined in advance, such as the occurrence of an interrupt factor due to data transmission in the serial communication circuit 511 and the occurrence of an interrupt factor due to the acquisition of numerical data as a random value in the random number circuit 509. It only has to be done.

  The reset / interrupt controller 504 includes an interrupt mask register IMR (address 2028H), an interrupt wait monitor register IRR (address 2029H), among the built-in registers included in the main control unit 41 as shown in FIG. Interrupt control and reset management are performed using the monitor monitor register ISR (address 202AH) and the internal information register CIF (address 208CH). The interrupt mask register IMR is a register that sets what is used and what is not used among maskable interrupts INT caused by a plurality of different factors. The interrupt wait monitor register IRR is a register for confirming the generation state of a maskable interrupt request signal for each maskable interrupt factor set by the interrupt initial setting KIIS. The interrupt monitor register ISR is a register for confirming the processing state of the maskable interrupt request signal for each maskable interrupt factor set by the interrupt initial setting KIIS. The internal information register CIF is a register for managing the reset factor generated immediately before and recording the frequency abnormality of the random number clock RCLK.

  FIG. 11A shows a configuration example of the internal information register CIF. FIG. 11B shows an example of setting contents in each bit of the internal information data stored in the internal information register CIF. The internal information data CIF4 stored in the bit number [4] of the internal information register CIF is a random number clock abnormality instruction indicating the presence or absence of a frequency abnormality in the random number clock RCLK. In the example shown in FIG. 11B, when the frequency abnormality of the random number clock RCLK is not detected, the bit value of the internal information data CIF4 is “0”, whereas when the frequency abnormality is detected, the bit value is “1”. The internal information data CIF2 stored in the bit number [2] of the internal information register CIF is a system reset instruction indicating whether or not the reset factor generated immediately before is a system reset. In the example shown in FIG. 11B, when the immediately preceding reset factor is not a system reset (system reset has not occurred), the bit value of the internal information data CIF2 is “0”, whereas when the system reset is a system reset (system reset) When the reset occurs), the bit value becomes “1”.

  The internal information data CIF1 stored in the bit number [1] of the internal information register CIF is a WDT timeout instruction indicating whether or not the reset factor generated immediately before is a user reset due to a watchdog timer (WDT) timeout. . In the example shown in FIG. 11B, when the immediately preceding reset factor is not a user reset due to a watchdog timer timeout (timeout has not occurred), the bit value of the internal information data CIF1 becomes “0”, while the watchdog When a user reset is caused by a timer timeout (timeout occurs), the bit value becomes “1”. The internal information data CIF0 stored in the bit number [0] of the internal information register CIF is an IAT generation instruction indicating whether or not the reset factor generated immediately before is a user reset due to prohibition of travel outside the designated area (IAT). . In the example shown in FIG. 11B, when the reset factor immediately before is not a user reset due to the occurrence of traveling outside the designated area (no IAT occurrence), the bit value of the internal information data CIF0 becomes “0”, while When the user reset is caused by the occurrence of out-of-area travel (the occurrence of IAT), the bit value becomes “1”.

  The CPU 505 provided in the main control unit 41 executes processing for controlling the progress of the game in the slot machine 1 by executing the program read from the ROM 506. At this time, the CPU 505 reads out fixed data from the ROM 506, the CPU 505 writes various data to the RAM 507 and temporarily stores the data, and the CPU 505 stores various data temporarily stored in the RAM 507. The CPU 505 receives the input of various signals from the outside of the main control unit 41 via the external bus interface 501 or the PIP 510, and the CPU 505 receives the input of various signals via the external bus interface 501 or the serial communication circuit 511. A transmission operation for outputting various signals to the outside of the main control unit 41 is also performed.

  As described above, in the main control unit 41, the CPU 505 executes control in accordance with the program stored in the ROM 506. Therefore, hereinafter, the main control unit 41 (or CPU 505) executes (or performs processing) is specifically described. Specifically, the CPU 505 executes control according to a program. The same applies to microcomputers mounted on boards other than the game control board 40.

  A ROM 506 provided in the main control unit 41 stores a user program for game control, fixed data, and the like. The ROM 506 stores a security check program 506A. The CPU 505 reads the security check program 506A stored in the ROM 506 when the main control unit 41 shifts to the security mode in response to the power-on of the slot machine 1 or the occurrence of a system reset, and whether the storage content of the ROM 506 has been changed. Execute security check processing to check whether or not. Note that the security check program 506A may be stored in a built-in memory different from the ROM 506. Further, the security check program 506A may correspond to a security check process for inspecting the storage contents of the external memory externally attached to the main control unit 41 via the external bus interface 501, for example.

  A RAM 507 provided in the main control unit 41 provides a work area for game control. Here, at least a part of the RAM 507 may be a backup RAM backed up by a backup power source. That is, even if the power supply to the slot machine is stopped, at least part of the contents of the RAM 507 is stored for a predetermined period. In this embodiment, all the areas of the RAM 507 are backup RAMs, and all the contents of the RAM 507 are saved for a predetermined period even when the power supply to the slot machine is stopped.

  The CTC 508 provided in the main control unit 41 includes, for example, a built-in 3-channel (PTC0-PTC2) 8-bit programmable timer, and includes a timer circuit that enables real-time interrupt generation and time measurement. Each programmable timer PTC0-PTC2 has a timer value that is updated in response to a change in the count clock signal generated based on the internal system clock SCLK (for example, a falling timing that changes from a high level to a low level). If it is. The CTC 508 may include, for example, an 8-bit programmable counter having 4 channels (PCC0 to PCC3). Each of the programmable counters PCC0 to PCC3 only needs to have its count value updated in response to a signal change of the internal system clock SCLK or occurrence of a timeout in any of the programmable counters PCC0 to PCC3. The CTC 508 resets the start time of the random number generated by the free run counter used for randomly determining the extension time (variable setting time) for extending the security time for each system reset or the random number circuit 509. A free-run counter or the like used for determining each item at random may be included. Alternatively, these free-run counters may be included in an internal circuit of the main control unit 41 different from the CTC 508 such as a backup area of the RAM 507, for example.

  A random number circuit 509 included in the main control unit 41 is a circuit that generates numerical data that is a random value having a predetermined update range, such as a 16-bit random number. In the present embodiment, on the game control board 40 side, numerical data indicating a random number value for internal lottery described later is controlled so as to be countable. In addition, in order to improve a game effect, random numbers other than these may be used. The CPU 505 uses a random counter different from the random number circuit 509 based on the numerical data extracted from the random number circuit 509 to process or update various numerical data by software, thereby indicating numerical data indicating a random value for internal lottery. May be counted. In the following, it is assumed that numerical data indicating random numbers for internal lottery is not processed by software from numerical data extracted by the CPU 505 from the random number circuit 509 serving as hardware. The random number circuit 509 may be built in the main control unit 41 or may be externally attached to the main control unit 41 as a random number circuit chip different from the main control unit 41. .

  The random number for internal lottery is a value used to determine whether or not to allow the generation of a plurality of types of winnings, and takes a value in the range of “0” to “65535” in the present embodiment. .

  FIG. 12 is a block diagram illustrating a configuration example of the random number circuit 509. As shown in FIG. 12, the random number circuit 509 includes a frequency monitoring circuit 551, a clock flip-flop 552, a random number generation circuit 553, a start value setting circuit 554, a random number sequence change circuit 555, a random number sequence change setting circuit 556, and a latch flip-flop. 557A, 557B, random number latch selectors 558A, 558B, and random number value registers 559A, 559B. The random value register 559A and the random value register 559B are respectively a random value register R1D (address 2038H-2039H) and a random value register R2D (address) included in the built-in register of the main control unit 41 as shown in FIG. 203AH-203BH). In the present embodiment, the random number to be acquired is only a random value for internal lottery, and among the latch flip-flops 557A, 557B, the random number latch selectors 558A, 558B, and the random value register 559A, 559B, the latch flip-flop 557B. The random number latch selector 558B and the random number value register 559B are unused.

  The frequency monitoring circuit 551 is a circuit for monitoring the frequency of the random number clock RCLK generated by the random number clock generating circuit 43 and detecting the occurrence of an abnormality. For example, the frequency monitoring circuit 551 monitors an oscillation signal input to the random number external clock terminal ERC, and sets the contents of the bit number [7-6] of the security time setting KSES based on the internal system clock SCLK (FIG. 10B When the frequency abnormality according to the reference) is detected, the bit number [4] of the internal information register CIF is set to “1”. In the present embodiment, the random number clock RCLK generated by the random number clock generation circuit 43 is input to the random number external clock terminal ERC.

  The clock flip-flop 552 is configured using, for example, a D-type flip-flop, and the random number clock RCLK from the random number external clock terminal ERC is input to the clock terminal CK. Further, in the clock flip-flop 552, the negative phase output terminal (inverted output terminal) Q bar is connected to the D input terminal. The random number update clock RGK is output from the positive phase output terminal (non-inverted output terminal) Q, while the latch clock RC0 is output from the negative phase output terminal (inverted output terminal) Q bar. In this case, when the signal state of the random number clock RCLK input to the clock terminal CK changes a predetermined state, the clock flip-flop 552 has a positive phase output terminal (non-inverted output terminal) Q and a negative phase output terminal ( Inverted output terminal) Changes the signal state in the output signal from the Q bar.

  For example, the clock flip-flop 552 has a rising timing at which the signal state of the random number clock RCLK changes from a low level to a high level, or a rising edge at which the signal state of the random number clock RCLK changes from a high level to a low level. The input signal at the D input terminal is captured at any one of the falling timings. At this time, from the positive phase output terminal (non-inverted output terminal) Q, the input signal captured at the D input terminal is output without being inverted, while the negative phase output terminal (inverted output terminal) Q bar is output. From the input signal captured by the D input terminal is inverted and output. Thus, the random number update clock RGK having an oscillation frequency (for example, 10 MHz) that is ½ of the oscillation frequency (for example, 20 MHz) of the random number clock RCLK from the positive phase output terminal (non-inverted output terminal) Q of the clock flip-flop 552. Is output from the negative phase output terminal (inverted output terminal) Q bar, that is, the reverse phase signal (inverted signal) of the random number update clock RGK, that is, the same frequency as the random number update clock RGK and the phase of the random number update clock RGK is π. A different latch clock RC0 is output by (= 180 °).

  The random number update clock RGK output from the clock flip-flop 552 is input to the clock terminal of the random number generation circuit 553 and used for incrementing the count value in the random number generation circuit 553. The latch clock RC0 output from the clock flip-flop 552 is branched into the latch clock RC1 and the latch clock RC2 at the branch point BR1. Therefore, the latch clock RC1 and the latch clock RC2 have the same oscillation frequency, and the signal state changes with a common cycle. Here, examples of changes in the signal state in the latch clock RC1 and the latch clock RC2 include a rising edge that changes from a low level to a high level and a falling edge that changes from a high level to a low level. The latch clock RC1 is input to the clock terminal CK of the latch flip-flop 557A and becomes a random number acquisition clock used to generate the latch signal SL1 at the start of the game.

  The oscillation frequency of the random number clock RCLK and the oscillation frequency of the control clock CCLK generated by the control clock generation circuit 42 are different from each other, and one of the oscillation frequencies is the other oscillation frequency. It is never an integer multiple of. As an example, while the oscillation frequency of the control clock CCLK is 11.0 MHz, the oscillation frequency of the random number clock RCLK may be 9.7 MHz. Therefore, both the random number update clock RGK and the latch clocks RC1 and RC2 are oscillation signals whose signal states change at a different period from the control clock CCLK supplied to the CPU 505. That is, the clock flip-flop 552 is based on the random number clock RCLK generated by the random number clock generation circuit 43, and the random number update clock RGK for updating the count value, or the latch clock that is used as a plurality of random number acquisition clocks. As RC1 and RC2, oscillation signals whose signal states change with a period different from the control clock CCLK and the internal system clock SCLK (the control clock CCLK divided by two) are generated.

  The random number generation circuit 553 is composed of, for example, a 16-bit counter and the like, based on an input such as a random number update clock RGK output from the clock flip-flop 552, from a predetermined initial value within a predetermined range in which numerical data can be updated. It is a circuit that cyclically updates to a predetermined final value. For example, the random number generation circuit 553 responds to the rising edge of the random number update clock RGK, which is an input signal to a predetermined clock terminal, from the initial value set within the range from “0” to “65535” to “65535”. The numerical data is counted up so that one is added at a time. Then, after counting up to “65535”, the numerical data is updated cyclically by counting up from “0” to a numerical value that becomes a final value that is 1 smaller than the initial value.

  The start value setting circuit 554 sets the start value in the count value generated by the random number generation circuit 553 in accordance with the bit value (see FIG. 9B) in the bit number [1-0] of the second random number initial setting KRS2. Set. For example, if the bit number [1-0] of the second random number initial setting KRS2 is “00”, the start value setting circuit 554 sets the start value to the default value “0000H”, and if it is “10”. The value is set based on the ID number. If “01”, the value is changed every time the system is reset. In the present embodiment, the bit number [1-0] of the second random number initial setting KRS2 is set to “10”, and the value based on the ID number is used as the start value in the count value generated by the random number generation circuit 553. Is set.

  The random number sequence change circuit 555 is a circuit that allows the permutation, which is the update order of the numerical data, to be changed to a permutation that conforms to a predetermined random number update rule when the numerical data generated by the random number generation circuit 553 makes a round. For example, the random number sequence change circuit 555 executes bit scramble processing such as bit replacement or transposition in numerical data output from the random number generation circuit 553. The random number sequence changing circuit 555 can change the permutation, which is the update order of the numerical data, by changing the bit scramble key or the bit scramble table used for the bit scramble process, for example.

  The random number sequence change setting circuit 556 determines the update order of the numerical data in the random number sequence change circuit 555 according to the bit value (see FIG. 9A) in the bit number [1-0] of the first random number initial setting KRS1. This is a circuit for performing the setting to be changed. For example, if the bit number [1-0] of the first random number initial setting KRS1 is “00”, the random number sequence change setting circuit 556 sets the random number update rule not to change after the second round, while “01” If so, the random number update rule is changed in response to a change request by software after the second round, and if it is “10”, the random number update rule is automatically changed. In the present embodiment, the bit number [1-0] of the first random number initial setting KRS1 is set to “10”, and the random number update rule is automatically changed.

  When the random number update circuit 556 changes the random number update rule by software in response to the bit number [1-0] of the first random number initial setting KRS1 being “01”, FIG. Of the built-in registers included in the main control unit 41 as shown, the random number update rule RDSC (address 2034H) is used to control the change of the random number update rule. FIG. 13A shows a configuration example of the random number sequence change register RDSC. FIG. 13B shows an example of setting contents in each bit of random number sequence change request data stored in the random number sequence change register RDSC. The random number sequence change request data RDSC0 stored in the bit number [0] of the random number sequence change register RDSC indicates whether or not there is a random number sequence change request when the random number update rule is changed by software. In the example shown in FIG. 13B, when the random number sequence change request is not made by software, the bit value of the random number sequence change request data RDSC0 is “0”. The bit value is “1”.

  FIG. 14 shows an operation example when the random number update rule is changed by software. In this case, when the count value permutation RCN output from the random number generation circuit 553 is cyclically updated from a predetermined initial value to a predetermined final value, the response is that the random number sequence change request data RDSC0 is “1”. Then, change the random number update rule. In the operation example shown in FIG. 14, the random number sequence RSN output from the random number sequence change circuit 555 is “0 → 1 →... → 65535”. Thereafter, it is assumed that “1” is written to the bit number [0] of the random number sequence change register RDSC at a predetermined timing by the CPU 505 executing the user program stored in the ROM 506.

  In response to the bit number [1-0] of the first random number initial setting KRS1 being “01”, the random number sequence change setting circuit 556 reads the random number sequence change request data RDSC0 and the bit value is “1”. In response to “”, a setting for changing the random number update rule is made. At this time, the random number sequence change setting circuit 556 is one of a plurality of types of random number update rules prepared in advance, for example, in response to the count value permutation RCN output from the random number generation circuit 553 reaching a predetermined final value. The random number update rule is changed, for example, by selecting. In the operation example shown in FIG. 14, the random number sequence change circuit 555 outputs numerical data “65535” corresponding to the final value in the count value permutation RCN output from the random number generation circuit 553, and then responds to the random number sequence change request data RDSC0. Change the random number update rule. Thereafter, the random number sequence change circuit 555 outputs “65535 → 65534 →... → 0” as the random number sequence RSN according to the changed random number update rule. The random number sequence change register RDSC is initialized when the random number sequence change setting circuit 556 reads the random number sequence change request data RDSC0. Therefore, until the bit value “1” is written to the bit number [0] of the random number sequence change register RDSC again, the random number sequence RSN output from the random number sequence change circuit 555 is “65535 → 65534 →... → 0”. Become.

  When the CPU 505 executes the user program stored in the ROM 506 and the bit value “1” is written again to the bit number [0] of the random number sequence change register RDSC, the random number update rule is changed again. In the operation example shown in FIG. 14, when the random number sequence change circuit 555 outputs the numerical data “0” corresponding to the final value in the random number sequence RSN, the bit value “1” is written as the random number sequence change request data RDSC0. Change the random number update rule accordingly. Thereafter, the random number sequence changing circuit 555 outputs “0 → 2 →... → 65534 → 1 →... → 65535” as the random number sequence RSN according to the changed random number update rule.

  FIG. 15 shows an operation example when the random number update rule is automatically changed. In this case, in response to the count value permutation RCN output from the random number generation circuit 553 being cyclically updated from a predetermined initial value to a predetermined final value, the random number sequence change setting circuit 556 automatically changes the random number update rule. To change. In the operation example shown in FIG. 15, the random number sequence RSN output from the random number sequence change circuit 555 first is “0 → 1 →... → 65535”.

  When the random number sequence RSN output from the random number change circuit 555 reaches a predetermined final value, the random number sequence change setting circuit 556 follows a predetermined order from among a plurality of types of update rules prepared in advance. The update rule may be changed by selecting the update rule. Alternatively, the random number sequence change setting circuit 556 may change the update rule by selecting an arbitrary update rule from among a plurality of types of update rules. In the operation example shown in FIG. 15, the random number sequence RSN output from the random number sequence change circuit 555 becomes “65535 → 65534 →. Thereafter, due to the second change in the random number update rule, the random number sequence RSN output from the random number sequence change circuit 555 becomes “0 → 2 →... → 65534 → 1 →. In the operation example illustrated in FIG. 15, the random number sequence RSN output from the random number sequence change circuit 555 is “65534 → 0 →... → 32768” due to the third change in the random number update rule. When the fourth random number update rule change is performed, the random number sequence RSN output from the random number sequence change circuit 555 becomes “16383 → 49151 →... → 49150”. When the fifth random number update rule change is performed, the random number sequence RSN output from the random number sequence change circuit 555 becomes “4 → 3 →... → 465553”.

  The latch flip-flop 557A is configured using, for example, a D-type flip-flop. In the latch flip-flop 557A, a wiring from the input port P0 included in the PIP 510 is connected to the D input terminal, and a wiring for transmitting the latch clock RC1 is connected to the clock terminal CK. In the present embodiment, the game start signal SS1 from the start switch 7 is input to the input port P0. The latch flip-flop 557A takes in the game start signal SS1 in response to the rising edge of the latch clock RC1, and outputs it as the game start latch signal SL1. Thus, in the latch flip-flop 557A, the game start signal SS1 is output as the game start latch signal SL1 in synchronization with the rising edge of the latch clock RC1.

  Note that the game start signal SS1 is not limited to that transmitted directly from the start switch 7. As an example, the time when the output signal from the output signal from the start switch 7 is on is measured, and when the measured time reaches a predetermined time (for example, 3 ms), the game start signal SS1 is output. A timer circuit may be provided.

  The random number latch selector 558A is a circuit that takes in the game start latch signal SL1 transmitted from the latch flip-flop 557A and the software random number latch request signal, and selectively outputs either one as the random number latch signal LL1. The random number latch selector 558A controls the output of the random number latch signal LL1 by using a random value fetch register RDLT (address 2032H) among the built-in registers provided in the main control unit 41 as shown in FIG. 7B. The random value acquisition register RDLT is a register used to acquire numerical data in the random number sequence RSN output from the random number sequence change circuit 555 into the random value register 559A by software. The random number latch selection register RDLS has a method of taking in the numerical data in the random number sequence RSN output from the random number sequence changing circuit 555 into the random value register 559A by software or by inputting a signal to the input port P0. It is a register to show.

  FIG. 16A shows a configuration example of the random value fetch register RDLT. FIG. 16B shows an example of the setting contents in each bit of the random number acquisition specification data stored in the random value acquisition register RDLT. The random value acquisition specification data RDLT0 stored in the bit number [0] of the random value acquisition register RDLT indicates whether or not a random value acquisition specification is given to the random value register 559A serving as the random value register R1D. In the example shown in FIG. 16B, when there is no specification of random number acquisition to the random number register R1D by software, the bit value of the random value acquisition specification data RDLT0 is “0”, while the random value acquisition is not performed. The bit value is “1” when an instruction is included.

  FIG. 17A shows a configuration example of the random number latch selection register RDLS. FIG. 17B shows an example of setting contents in each bit of random number latch selection data stored in the random number latch selection register RDLS. The random number latch selection data RDLS0 stored in the bit number [0] of the random number latch selection register RDLS indicates a method of taking in the random number value register 559A serving as the random number value register R1D. In the example shown in FIG. 17B, the bit value of the random number latch selection data RDLS0 is “ 0 ”. On the other hand, when the numerical value data to be a random number value is taken into the random value register R1D in response to the signal input to the input port P0, the bit value of the random number latch selection data RDLS0 is set to “1”. In this embodiment, the bit value of the random number latch selection data RDLS0 is set to “1”, and numerical data that becomes a random value in accordance with the signal input to the input port P0 is taken into the random value register R1D.

  The random value register 559A is a register that stores numerical data in the random number sequence RSN output from the random number sequence change circuit 555 as a random value. FIGS. 18A and 18B show a configuration example of a random value register 559A serving as the random value register R1D. 18A shows the lower byte R1D (L) of the random value register R1D, and FIG. 18B shows the upper byte R1D (H) of the random value register R1D. The random value register 559A is a 16-bit (2-byte) register, and can store a 16-bit random value.

  The random value register 559A takes in the numerical data in the random number sequence RSN output from the random number sequence change circuit 555 as a random value in response to the random number latch signal LL1 supplied from the random number latch selector 558A being turned on. Store with. When the register read signal RRS1 supplied from the CPU 505 is turned on, the random value register 559A is in a readable (enable) state and outputs stored numerical data to an internal bus or the like. On the other hand, when the register read signal RRS1 is in the OFF state, the same value (for example, “65535H” or the like) is always output, and the reading is disabled (disabled). Further, the random value register 559A may be in a state in which the register read signal RRS1 cannot be received when the random number latch signal LL1 is in the ON state. Further, the random value register 559A may be in a state in which the random number latch signal LL1 cannot be received when the register read signal RRS1 is in the on state before the random number latch signal LL1 is in the on state. Good.

  The random value register 559A uses a random number latch flag register RDFM (address 2033H) and a random number interrupt control register RDIC (address 2031H) among the built-in registers provided in the main control unit 41 as shown in FIG. 7B. This enables operation management and interrupt control when latching random numbers. The random number latch flag register RDFM is a register that stores a random number latch flag indicating whether or not numerical data serving as a random number value has been latched corresponding to the random value register 559A. The random number interrupt control register RDIC is a register that sets permission / prohibition of an interrupt that occurs when numerical data that becomes a random number value is latched in the random number value register 559A.

  FIG. 19A shows a configuration example of the random number latch flag register RDFM. FIG. 19B shows an example of setting contents in each bit of the random number latch flag data stored in the random number latch flag register RDFM. The random number latch flag data RDFM0 stored in the bit number [0] of the random number latch flag register RDFM is a random number latch flag indicating whether or not numerical data has been taken into the random number value register 559A serving as the random number value register R1D. In the example shown in FIG. 19B, when the numerical value data is not taken into the random value register R1D (no random value is taken), the bit value of the random number latch flag data RDFM0 becomes “0”, while the numerical data Is taken (with random number fetching), the bit value becomes “1”. In the state where the random number latch flag data RDFM0 is “1”, that is, in the state where the numerical data is captured in the random value register R1D, the new numerical data is stored in the random value register even when a new random number capturing request is generated. In such a state, the numerical data in the random value register R1D is read and new numerical data is captured in the random value register R1D until the random number latch flag data RDFM0 is cleared. It becomes impossible.

  FIG. 20A shows a configuration example of the random number interrupt control register RDIC. FIG. 20B shows an example of setting contents in each bit of random number interrupt control data stored in the random number interrupt control register RDIC. The random number interrupt control data RDIC0 stored in the bit number [0] of the random number interrupt control register RDIC permits an interrupt that occurs when numerical data is fetched into the random number value register 559A serving as the random number value register R1D. This shows the interrupt control setting to enable or disable. In the example shown in FIG. 20B, when interrupting at the time of fetching into the random value register R1D is prohibited (interrupt prohibited), the bit value of the random number interrupt control data RDIC0 is set to “0”, When this interrupt is permitted (interrupt permitted), the bit value is set to “1”. In the present embodiment, the bit value of the random number interrupt control data RDIC0 is set to “0”, and no interrupt is generated even if numerical data is captured in the random value register 559A serving as the random value register R1D.

  The PIP 510 included in the main control unit 41 is, for example, a 6-bit input dedicated port, and includes an input port P0 to an input port P2 serving as a dedicated terminal, and an input port P3 to an input port P5 serving as a function shared terminal. . The input port P3 is also used as an external maskable interrupt terminal XINT connected to the CPU 505 or the like. The input port P4 is also used as an external non-maskable interrupt terminal XNMI connected to the CPU 505 or the like. The input port P5 is also used as the first channel reception terminal RXA used by the serial communication circuit 511. The use setting of the input port P3 to the input port P5 is instructed by the function setting KFCS stored in the program management area.

  The PIP 510 performs state management of the input port P0 to the input port P5 using the input port register PI (address 2090H) among the built-in registers included in the main control unit 41 as shown in FIG. The input port register PI is a register that stores a bit value indicating the input state of the external signal corresponding to each of the input ports P0 to P5.

  FIG. 21A shows a configuration example of the input port register PI. FIG. 21B shows an example of setting contents in each bit of the input port data stored in the input port register PI. The input port data PI5 stored in the bit number [5] of the input port register PI indicates the terminal state (ON / OFF) at the input port P5 that is also used as the first channel receiving terminal RXA. The input port data PI4 stored in the bit number [4] of the input port register PI indicates the terminal state (ON / OFF) at the input port P4 that is also used as the external non-maskable interrupt terminal XNMI. The input port data PI3 stored in the bit number [3] of the input port register PI indicates the terminal state (ON / OFF) at the input port P3 that is also used as the external maskable interrupt terminal XINT. The input port data PI2 stored in the bit number [2] of the input port register PI indicates the terminal state (ON / OFF) at the input port P2. The input port data PI1 stored in the bit number [1] of the input port register PI indicates the terminal state (ON / OFF) at the input port P1. The input port data PI0 stored in the bit number [0] of the input port register PI indicates the terminal state (ON / OFF) at the input port P0.

  An address decoding circuit 512 provided in the main control unit 41 shown in FIG. 5 is a circuit for decoding each functional block in the main control unit 41 and a chip select signal that is a decoding signal for an external device. . By the chip select signal, an internal circuit of the main control unit 41 or an external device as a peripheral device is selectively operated effectively and can be accessed from the CPU 505.

  The ROM 506 provided in the main control unit 41 stores various selection data and table data used for controlling the progress of the game, in addition to the game control user program and the security check program 506A. For example, the ROM 506 stores data constituting a plurality of determination tables, determination tables, setting tables and the like prepared for the CPU 505 to perform various determinations, determinations, and settings. The ROM 506 stores table data constituting a plurality of command tables used for the CPU 505 to transmit control signals serving as various control commands from the game control board 40.

  The RAM 507 provided in the main control unit 41 is provided with a game control data holding area 590 as an area for holding various data used for controlling the progress of the game in the slot machine 1. For example, a DRAM is used as the RAM 507, and a refresh operation is required to maintain the stored data contents. The CPU 505 has a built-in refresh register for performing this refresh operation. For example, the refresh register is composed of 8 bits, and the lower 7 bits are automatically incremented every time the CPU 505 fetches an instruction from the ROM 506. Therefore, the stored value in the refresh register is updated every execution time of one instruction in the CPU 505.

  The main control unit 41 receives the detection state of various switches connected to the game control board 40 from the input port. Then, the main control unit 41 executes basic processing that shifts in stages according to the detection states of various switches input from these input ports.

  Further, the main control unit 41 can execute an interrupt process by interrupting the basic process when an interrupt occurs. In the present embodiment, the external maskable interrupt terminal XINT is connected to the power interruption detection circuit 48 described above, and the main control unit 41 will be described later according to the input of the voltage drop signal output from the power interruption detection circuit 48. Execute the power interruption interrupt processing (main). Further, the main control unit 41 performs a timer interrupt process (main), which will be described later, every time a certain time interval (in this embodiment, about 0.56 ms) occurs in the timer circuit included in the CTC 508. Run.

  The main control unit 41 is set to prohibit other interrupts during the execution of the interrupt process, and when a plurality of interrupts occur at the same time, the main control unit 41 prioritizes according to a predetermined order. An interrupt to be executed is set. In this embodiment, the interruption interrupt process (main) has a higher priority than the timer interruption process (main), and when these interruptions occur simultaneously, the interruption interruption process (main) Is executed with priority.

  If another interrupt factor occurs during the execution of the interrupt process and the interrupt factor continues even after the interrupt process ends, a new interrupt occurs at that point. It will be. For example, if a voltage drop signal is input during execution of the timer interrupt process (main), the power interruption interrupt process (main) is not executed at that time, but the timer interrupt process being executed When the input of the voltage drop signal is continued when (main) is completed, the power interruption interrupt process (main) is executed at that time.

  The main control unit 41 repeatedly loops the process according to the control state until the detection state of the various switches connected to the game control board 40 changes as a basic process, and changes the detection state of the various switches. Execute a process that moves in stages. In addition, the main control unit 41 executes a power interruption interrupt process (main) in response to the input of the voltage drop signal output from the power interruption detection circuit 48, and at a constant time interval (in the present embodiment, about 0. 0). Timer interrupt processing (main) is executed every 56 ms).

  Note that the execution interval of the timer interrupt process (main) is set to a time longer than the sum of the time required to complete the repetition of the process depending on the control state in the basic process and the execution time of the timer interrupt process (main) Therefore, the process that is repeated according to the control state between the current and next timer interrupt processes (main) is completed at least once.

  The main control unit 41 transmits various commands to the effect control board 90. A command transmitted from the game control board 40 to the effect control board 90 is sent in only one direction, and no command is sent from the effect control board 90 to the game control board 40.

  The effect control board 90 is connected to effect devices such as a liquid crystal display 51 (see FIG. 1), an effect LED 52, speakers 53 and 54, and the reel LED 55 described above, which are arranged on the front door 1b of the slot machine 1. These effect devices are driven based on control by a later-described sub-control unit 91 mounted on the effect control board 90.

  In the present embodiment, the sub-control unit 91 mounted on the effect control board 90 performs output control of effect devices such as the liquid crystal display 51, effect effect LEDs 52, speakers 53 and 54, and reel LEDs 55. However, an output control unit that directly controls the output of the effect device is mounted on the effect control board 90 or another board separately from the sub control part 91, and the sub control part 91 is based on a command from the main control part 41. The output pattern of the effect device may be determined, and the output control unit may control the output of the effect device based on the output pattern determined by the sub control unit 91. In such a configuration, the sub control unit 91 and the output The output control of the effect device is performed by both of the control units.

  Moreover, in this Embodiment, although the liquid crystal display 51, the production effect LED52, the speakers 53 and 54, and the reel LED55 are illustrated as a production device, a production device is not restricted to these, For example, it drives mechanically. A display device or a mechanically driven item may be applied as the rendering device.

  The effect control board 90 is composed of a microcomputer having a sub CPU 91a, ROM 91b, RAM 91c, I / O port 91d, etc., and a liquid crystal display connected to the sub control unit 91 for effect control and the effect control board 90. Display control circuit 92 for performing display control of device 51, LED drive circuit 93 for controlling drive of effect LED 52 and reel LED 55, sound output circuit 94 for controlling sound output from speakers 53, 54, when power is turned on or when power is turned off A reset circuit 95 that sometimes gives a reset signal to the sub CPU 91a, a clock device 97 that outputs time information including date information and time information, and a power supply voltage supplied to the slot machine 1 are monitored, and when a voltage drop is detected, A power interruption detection circuit 9 for outputting a voltage drop signal indicating that to the sub-control unit 91 The sub-control unit 91 receives commands transmitted from the main control unit and performs various controls for performing effects, and directly controls each part of the control circuit mounted on the effect control board 90. To control automatically or indirectly.

  Similar to the main control unit 41, the sub control unit 91 has an interrupt function, generates an interrupt when receiving a command from the main control unit 41, and acquires a command transmitted from the main control unit 41. Execute command reception interrupt processing to be stored in the buffer. Further, the sub control unit 91 executes an interrupt process (sub), which will be described later, by generating an interrupt every time the number of input system clocks reaches a certain number, that is, every certain interval. Also, one of the interrupt terminals of the sub control unit 91 is connected to the power interruption detection circuit 98, and the sub control unit 91 is turned on in response to the input of the voltage drop signal output from the power interruption detection circuit 98. Execute interrupt processing (sub).

  Also, unlike the main control unit 41, the sub control unit 91 interrupts the process even when the timer interrupt process (sub) is being executed when an interrupt is generated based on the reception of the command. The command reception interrupt process is executed at the same time, and the command reception interrupt process is executed with the highest priority even if interrupts that trigger the timer interrupt process (sub) occur at the same time. Command reception interrupt processing is also prohibited during the execution of power interruption interrupt processing (sub), but if an interrupt that triggers power interruption interrupt processing (sub) occurs at the same time, command reception Prioritize interrupt processing.

  The sub-control unit 91 is also supplied with backup power at the time of a power failure, and the data stored in the RAM 91c is held while the backup power is supplied.

  In the slot machine 1 of the present embodiment, the medal payout rate changes according to the set value. Specifically, the medal payout rate is changed by using a winning probability corresponding to a set value in an internal lottery described later. The set value is composed of 6 levels of 1 to 6, with 6 being the highest payout rate and the payout rate being lower as the value is decreased in the order of 5, 4, 3, 2, 1. That is, when 6 is set as the set value, the advantage is highest for the player, and as the value decreases in order of 5, 4, 3, 2, 1, the advantage decreases stepwise.

  In order to change the set value, the front door 1b is opened, and the power switch 39 and the setting key switch 37 of the power box 100 provided in the housing 1a are operated to turn on the power of the slot machine 1. In such a case, the slot machine 1 needs to be turned on after the setting key switch 37 is turned on. When the setting key switch 37 is turned on and the power is turned on, the setting value read from the RAM 507 is displayed on the setting value display 24 as a display value, and the setting value can be changed by operating the reset / setting switch 38. Transition to the setting change state. When the reset / setting switch 38 is operated in the setting change state, the display value displayed on the setting value display 24 is updated one by one (when further operation is performed from the setting 6, the display returns to the setting 1). . When the start switch 7 is operated, the display value is determined as the set value. Then, when the setting key switch 37 is turned off, the determined display value (setting value) is stored in the RAM 507 of the main control unit 41, and the state shifts to a state in which the game can proceed. Since the power switch 39 is temporarily turned off, and the setting key switch 37 is turned on to perform the operation of turning on the power switch 39, the operation is shifted to the setting change state. .

  In the present embodiment, since the setting change operation can be performed by opening the front door 1b, it can be said that the front door 1b is an opening / closing body. Moreover, it can be said that the door open detection switch 25 for detecting the open state of the front door 1b is an open / closed state detecting means.

  In order to check the set value, after the game is over, the setting key switch 37 may be turned on with no bet amount set. When the setting key switch 37 is turned on in such a situation, the setting value read out from the RAM 507 is displayed on the setting value display 24, thereby shifting to a setting confirmation state in which the setting value can be confirmed. In the setting confirmation state, the game cannot be progressed, and by turning the setting key switch 37 to the OFF state, the setting confirmation state is ended and the state in which the game can proceed is returned.

  In the slot machine 1 of the present embodiment, when the main control unit 41 detects a voltage drop signal from the power interruption detection circuit 48, a power interruption interrupt process (main) is executed. In the power interruption interrupt processing (main), a register is saved in a stack of a RAM 507, which will be described later, and data for destructive diagnosis in which any bit becomes 1 (5AH in this embodiment), that is, a specification other than 0 The RAM parity adjustment data is calculated so that the RAM parity based on the data stored in all the areas of the RAM 507 becomes 0, and stored in the RAM 507. Note that the RAM parity is a value calculated as an exclusive OR of the values stored in each bit of the corresponding area of the RAM 507 (all areas in this embodiment). For this reason, if the RAM parity based on the data stored in all areas of the RAM 507 is 0, the RAM parity adjustment data is 0, and the RAM parity based on the data stored in all areas of the RAM 507 is 1. In this case, the RAM parity adjustment data is 1.

  The main control unit 41 calculates the RAM parity based on the data stored in all areas of the RAM 507 at the time of activation, confirms the value of the destructive diagnosis data, the RAM parity is 0, and On the condition that the value of the destructive diagnosis data is also correct, the processing state of the main control unit 41 is restored to the state before the power interruption based on the data stored in the RAM 507, but when the RAM parity is not 0 (1 If the value of the data for destructive diagnosis is not correct, it is determined that the RAM is abnormal, the RAM abnormal error code is set in the register, and the RAM abnormal error state is controlled to disable the progress of the game. ing. Unlike the normal error state, the RAM abnormal error state is not canceled even if the reset switch 23 or the reset / setting switch 38 is operated, and a new set value is set in the setting change state described above. It will not be released until

  In the present embodiment, all data stored in the RAM 507 is retained by the backup power source even during a power failure, and the main control unit 41 determines that the data in the RAM 507 is normal when the power is turned on. In this case, the control state is restored to the control state before the power interruption based on the data stored in the RAM 507, but only the data necessary for the return of the control state in the event of a power failure is backed up among the data stored in the RAM 507, It is good also as a structure which returns to the control state before power interruption based on the data backed up at the time of injection | throwing-in.

  In addition, when returning to the control state before the power interruption when the power is turned on, it is not necessary to return all the control states to the control state before the power interruption, and the minimum control state that does not disadvantage the player For example, it is not necessary to restore all the states of the input ports to the state before power interruption.

  Further, when the sub control unit 91 detects the voltage drop signal from the power interruption detection circuit 98, the sub control unit 91 executes a power interruption interrupt process (sub). In the power interruption interrupt processing (sub), the register is saved in a stack of a RAM 91c described later, and destructive diagnosis data in which any bit is 1 is stored in the RAM 91c, and data stored in all areas of the RAM 91c. The RAM parity adjustment data is calculated so that the RAM parity based on 0 becomes 0, and stored in the RAM 91c.

  Then, the sub-control unit 91 calculates the RAM parity based on the data stored in all the areas of the RAM 91c at the time of activation, and sets the data stored in the RAM 91c on the condition that the RAM parity is 0. Based on this, the processing state of the sub-control unit 91 is restored to the state before the power interruption, but when the RAM parity is not 0 (in the case of 1), it is determined that the RAM is abnormal and the RAM 91c is initialized. . In this case, unlike the main control unit 41, only the RAM 91c is initialized, and the performance is not disabled.

  In the present embodiment, all data stored in the RAM 91c is held by the backup power source even during a power failure, and the sub-control unit 91 determines that the data in the RAM 91c is normal when the power is turned on. In this case, the control state is restored to the control state before the power interruption based on the data stored in the RAM 91c, but only the data necessary for the return of the control state in the event of a power failure is backed up among the data stored in the RAM 91c. It is good also as a structure which returns to the control state before power interruption based on the data backed up at the time of injection | throwing-in.

  In addition, when returning to the control state before the power interruption when the power is turned on, it is not necessary to return all the control states to the control state before the power interruption, and the minimum control state that does not disadvantage the player It is only necessary to restore the state of the input port, and it is not necessary to restore the state of the input port or the progress in the case where the production is interrupted in the middle to the state before the power interruption.

  Next, initialization of the RAM 507 of the main control unit 41 will be described. The storage area of the RAM 507 of the main control unit 41 is divided into an important work, a general work, a special work, a set value work, a non-saved work, an unused area, and a stack area.

  The important work is a work in which data which is inconvenient if it is initialized at the end of the BB, such as various display devices, LED display data, I / O input / output data, and game time counter. The general work is a work that stores data that can be initialized at the end of the BB, such as a stop control table, a stop symbol, the number of medals paid out, and the total number of medals paid out in the BB.

  The special work is a work that stores data to be initialized only before the start of setting, such as data for transmitting a command to the effect control board 90 and various software random numbers. The set value work is a work that stores a set value used when a lottery is performed in the internal lottery process. The unsaved work is a work that holds the state of various switches, and a value is always set regardless of whether or not the data in the RAM 507 is destroyed at the time of activation.

  The unused area is an unused area in the storage area of the RAM 507, and is initialized if any one of a plurality of initialization conditions described later is satisfied. The stack area is an area in which data saved from the register of the main control unit 41 is stored, and the unused stack area is one of a plurality of initialization conditions to be described later, like the unused area. However, if it is established, it will be initialized, but the in-use stack area is not initialized because the program continues.

  In the present embodiment, the main control unit 41 stores data in the RAM 507 at the time of start-up with the setting key switch 37 being ON, when a RAM error occurs, at the end of the BB, and at the time of start-up with the setting key switch 37 being OFF. When is not destroyed, when the five initialization conditions at the end of one game are satisfied, four types of initializations that are initialized in accordance with each initialization condition are performed.

  Initialization 1 is a state in which the setting key switch 37 is in an ON state at the time of start-up, and is an initialization performed before the transition to the setting change state or an initialization performed when a RAM abnormality error occurs. In the storage area of the RAM 507, all areas (including the unused area and the unused stack area) other than the used stack area are initialized.

  The information initialized in the initialization 1 includes, for example, information backed up at the time of power interruption (information for specifying the set number of bets, information for specifying BB winning). As a result, when initialization 1 is performed, even if the bet number is set before the power interruption, the bet number is not returned to the set state, and the BB is won before the power interruption. Even if it does, it will not return to the BB winning situation. Thereby, it is possible to prevent the game state before the setting change state from being taken over after entering the setting change state, and to ensure the fairness of the game.

  Initialization 2 is initialization performed at the end of the BB. In initialization 2, a general work, an unused area, and an unused stack area in the storage area of the RAM 507 are initialized. Initialization 3 is an initialization performed when the setting key switch 37 is in an OFF state at the time of startup and the data in the RAM 507 is not destroyed. In the initialization 3, the unsaved work, the unused area, and the The used stack area is initialized. Initialization 4 is initialization performed at the end of one game. In initialization 4, an unused area and an unused stack area in the storage area of the RAM 507 are initialized.

  In this embodiment, the initialization 1 is performed before the setting change state is transferred. However, the initialization 1 is performed at the end of the setting change state, or both before the setting change state and at the end of the setting change state. May be. In this case, if the set value work is initialized, the determined set value is lost. Therefore, the initialization of the set value work is not performed in the initialization at the end of the setting change state.

  In the slot machine 1 according to the present embodiment, the prescribed number of bets that can be set according to the gaming state is determined as described above, and the prescribed number of bets that are determined according to the gaming state is set. It becomes possible to start the game on the condition. In this embodiment, as will be described later, there are a regular bonus (hereinafter referred to as RB), a big bonus (hereinafter referred to as BB), and a normal gaming state as gaming states. 2 is defined as the prescribed number, and 3 is defined as the prescribed number of bets in the normal gaming state. For this reason, if the gaming state is RB or BB, the game can be started if 2 is set as the bet number, and if the bet number is set to 3 in the normal gaming state, the game is started. It becomes possible to make it. In this embodiment, all the pay lines L1 to L5 are activated when a specified number of bets according to the gaming state are set, and as RBs and BBs, All winning lines L1 to L5 are activated when 2 is determined, and all winning lines L1 to L5 are activated when 3 is set as the number of bets in the normal gaming state. Become.

  In the slot machine 1 of the present embodiment, when all the reels 2L, 2C, and 2R are stopped, the winning line that is activated (in this embodiment, all the winning lines are always activated, In the following description, an activated winning line is simply referred to as a winning line). The combination may be a combination of the same symbols or a combination including different symbols.

  The types of winning combinations are determined according to the gaming state, but can be broadly divided into small roles with payout of medals and re-starts that allow the next game to be started without the need to set bets. There are a game combination and a special combination with a transition of the game state. Below, a small role and a re-playing role are collectively called a general role. In order to win each winning combination determined according to the game state, it is necessary to win an internal lottery described later and set a winning flag for the winning combination in the RAM 507.

  Of the winning flags for each of these roles, the winning flags for the small role and the replaying role are valid only in the game in which the flag is set, and are invalid in the next game. It is valid until a combination of combinations permitted by the flag is completed, and is invalid in a game having a combination of combinations permitted. In other words, once the special combination winning flag is won, even if the combination of the combinations permitted by the flag cannot be made, the winning flag is not invalidated and is carried over to the next game. It becomes.

  As the role in this slot machine 1, as shown in FIG. 22, a special bonus such as a big bonus (hereinafter referred to as a big bonus BB), a regular bonus (hereinafter referred to as a regular bonus RB), Cherry, Bell are replayed as a re-playing role.

  Cherry is awarded when the symbol “white cherry” is derived on any of the winning lines for the right reel in any gaming state, and one medal is paid out in any gaming state. If the symbol “white cherry” stops at the upper or lower stage of the right reel, the combination of cherries will be aligned on the two winning lines of the winning lines L2, L5 or the winning lines L3, L4. Since winning a cherry on the winning line, two medals will be paid out.

  A watermelon is awarded when a combination of "Watermelon-Watermelon-Watermelon" or "Watermelon-Watermelon-BAR" is available on any of the winning lines in any game state, and 15 medals at RB and BB Are paid out, and in the normal gaming state, 12 medals are paid out. A bell is awarded when a combination of “bell-bell-bell” is aligned on any of the winning lines in any gaming state, 15 medals are paid out in RB and BB, and 10 in the normal gaming state. A medal is paid out.

  Replay is a combination of “Replay-Replay-Replay”, “BAR-Replay-Replay”, or “Black 7-Replay-Replay” in any of the winning lines in the normal gaming state. Wins when you have the right. When the replay wins, no medals are paid out, but the next game can be started without setting the number of wagers again, so that three medals corresponding to the number of wagers that are not required to be set in the next game are paid out. Is essentially the same.

  RB is won when the combination of “net 7-net 7-black 7” is aligned on any of the winning lines in the normal gaming state, and the gaming state shifts to RB. The RB is a gaming state that is advantageous to the player over other gaming states by increasing the winning probability of the small role, particularly the bell, and when the 12 games are digested after the RB starts, or an 8-game winning ( When the type of a combination is allowed), it ends either whichever comes first.

  BB is a combination of “black 7-black 7-black 7”, “net 7-net 7-net 7” or “white 7-white 7-white 7” in any of the winning lines in the normal gaming state. When the combination is complete, a prize is awarded.

  When BB wins, the gaming state shifts to BB and shifts to RB at the same time. When RB ends, if BB has not ended, it shifts to RB again and is controlled repeatedly until BB ends. The That is, during BB, it is always controlled to RB. The BB ends when the total number of medals paid out to the player in the BB exceeds 465. At the end of the BB, the RB is also ended regardless of whether the RB end condition is satisfied.

  Hereinafter, the internal lottery of the present embodiment will be described. In the internal lottery, it is determined whether or not the above winning combination is permitted before the display results of all the reels 2L, 2C, and 2R are derived and displayed (actually, when the start switch 7 is detected). To do. In the internal lottery, first, a random value for internal lottery (an integer from 0 to 65535) is acquired when the start switch 7 is detected. Specifically, the value of the random number storage work assigned to the RAM 507 is set to the lottery work assigned to the RAM 507. Then, for each combination determined according to the gaming state and whether or not the special combination is carried over, numerical data stored in the lottery work, and determination of each combination determined according to the gaming state, the number of bets and the set value This is done according to the number of values.

  The random value storage work is a storage area for storing numerical data latched in the random value register R1D simultaneously with the operation of the start switch 7, and is latched every time new numerical data is latched in the random value register R1D. The numerical data is read in the subsequent timer interrupt process (main), and the numerical data stored in the random value storage work is updated to the latest latched numerical data.

  In the present embodiment, as shown in FIG. 22, the role that is the subject of the internal lottery differs depending on whether the gaming state is the normal gaming state, RB, or BB. Further, when the gaming state is the normal gaming state, the role to be subject to the internal lottery varies depending on whether or not the special role is being carried over.

  When the gaming state is the normal gaming state and any special combination is not carried over, BB, RB, replay, watermelon, cherry, and bell are sequentially read out as the target combination of the internal lottery.

  When the gaming state is the normal gaming state and any special combination is carried over, replay, watermelon, cherry, and bell are sequentially read out as the target combinations for the internal lottery.

  When the gaming state is RB (including the inside of the BB), watermelon, cherry, and bell are sequentially read out as the subject combination of the internal lottery.

  In the present embodiment, an example is described in which three types of symbol combinations corresponding to BB, three types of symbol combinations corresponding to replay, and two types of symbol combinations corresponding to watermelon are defined. Then, each symbol combination is read out as a target combination. For example, for BB, a combination of “black 7-black 7-black 7”, a combination of “net 7-net 7-net 7”, and a combination of “white 7-white 7-white 7” are subject to internal lottery. Are read in order. Replays and watermelons are also sequentially read out as target combinations for each symbol combination. The number of determination values used in the internal lottery is determined for each symbol combination corresponding to the set values 1 to 6. That is, the winning rate is determined for each symbol combination corresponding to the set values 1 to 6. For this reason, in the internal lottery, the derivation (generation) of the symbol combination is permitted according to the winning rate determined for each symbol combination corresponding to the set value.

  In the internal lottery, the number of judgment values determined according to the internal lottery target, the current game state, and the set value are sequentially added to the internal lottery random value (the value of the lottery work) and added. When the result of overflows, it is determined that the winning combination is won. For this reason, a winning combination will be won with a probability (number of determination values / 65536) according to the number of determination values.

  If a winning combination of any combination is determined, a winning flag corresponding to the winning combination is set in the internal winning flag storage work assigned to the RAM 507. The internal winning flag storage work consists of a 2-byte storage area, of which the upper byte is assigned as the special role storing work in which the winning flag for the special role is set, and the lower byte is the winning of the general role It is assigned as a general role storage work for which a flag is set. Specifically, when a special combination is won, a special combination winning flag indicating that the special combination is won is set in the special combination storing work, and the winning flag set in the general combination storing work is cleared. When a general combination is won, a winning flag for the general combination indicating that the general combination is won is set in the general combination storing work. If no winning combination or winning combination is won, only the general winning combination work is cleared.

Next, stop control of the reels 2L, 2C, 2R will be described.
The main control unit 41 refers to the table index and the table creation data stored in the ROM 506A when the rotation of the reel starts and when the reel stops and the reel that is still rotating still remains. A stop control table is created for each reel that is rotating. When any of the stop switches 8L, 8C, and 8R corresponding to the rotating reel is effectively detected, the stop control table of the corresponding reel is referred to and the slip of the referred stop control table is referred to. Based on the number of frames, control is performed to stop the rotation of the reels 2L, 2C, 2R corresponding to the operated stop switches 8L, 8C, 8R.

  In the table index, an index that indicates the start address of the area in which the data for table creation is stored, from the reference address when referring to the table index, according to the setting state of the winning flag by internal lottery (hereinafter referred to as the internal winning state) Differences up to the address where the data is stored are registered. As a result, a difference corresponding to the internal winning state is acquired, and the corresponding index data can be acquired by adding the difference to the reference address. Even if the winning status of the combination is different, when the same control is applied, the same address is stored as the index data. In such a case, the same table creation data is referred to. Thus, a stop control table is created.

  The table creation data includes a stop control table indicating the number of sliding frames according to the stop operation position, and an address of the stop control table to be referred to according to the reel stop status.

  The stop control table referred to according to the reel stop status is whether all reels are rotating, only the left reel is stopped, only the middle reel is stopped, only the right reel is stopped, It may vary depending on whether the middle reel is stopped, the left and right reels are stopped, the middle and right reels are stopped, and if any reel is stopped, stop Since there may be differences depending on the stop position of the reels already completed, the address of the stop control table to be referenced for each situation is registered for each rotating reel, and based on the top address of the table creation data, It is possible to specify the address of the stop control table that should be referred to according to the status of each, and it is necessary according to each status from this specified address. And to be able to identify the stop control table. Even when the stop status of the reels and the stop position of the stopped reels are different, when the same stop control table is applied, the same address may be registered as the address of the stop control table. In such a case, the same stop control table is referred to.

  The stop control table is data that can specify the number of sliding frames by timing at which the stop operation is performed. In the present embodiment, stepping motors that make one turn at a cycle of 168 steps (0 to 167) are used for the reel motors 32L, 32C, and 32R. That is, when the reel motors 32L, 32C, and 32R are driven for 168 steps, the reels 2L, 2C, and 2R make one round. Then, 21 areas (frames) divided every 16 steps (the number of steps that one symbol moves) are defined for one reel, and these areas are areas 0 to 20 from the reel reference position. A number is assigned.

  On the other hand, the number of symbols arranged on one reel is 21, and symbol numbers 0 to 20 from the reel reference position are assigned to symbols on each reel, so symbols 0 to 20 are assigned to each reel. , Area numbers 0 to 20 are assigned in order. In the stop control table, the number of sliding symbols for each area number is compressed and stored according to a predetermined rule, and the number of sliding symbols for each area number can be acquired by expanding the stop control table. Yes.

  As described above, the stop control table created by referring to the table index and the table creation data corresponds to the area number, and the area corresponding to each area number has a stop reference position (in this embodiment, a perspective window). 3 when the operation of the stop switches 8L, 8C, 8R is detected at the timing (the timing in which the number of steps from the reel reference position is included in the range of the number of steps). This is a table in which the number of frames is set.

  Next, the procedure for creating the stop control table will be described. First, at the start of reel rotation, the top address of the table creation data corresponding to the internal winning state of the game is acquired. Specifically, the table index is first referred to, index data corresponding to the internal winning state is obtained, table creation data is identified based on the obtained index data, and all reels are identified from the identified table creation data. The address of the stop control table for each reel corresponding to the state of rotation is acquired, and the stop control table for each reel stored at the acquired address is expanded to generate a stop control table for all reels.

  Further, when any one reel stops or any two reels stop, the index data acquired at the start of reel rotation, that is, the top address of the table creation data corresponding to the internal winning state of the game The table creation data is identified based on the obtained table creation data, and the address of the stop control table for the unreacted reel corresponding to the stop reel and the area number of the stop position of the reel is obtained from the identified table creation data. The stop control table for each stored reel is expanded to create a stop control table for the unstopped reels.

  Next, when the main control unit 41 effectively detects any one of the stop switches 8L, 8C, and 8R corresponding to the rotating reel, the control when the display result is derived to the corresponding reel is described. To explain, when any operation corresponding to the rotating reel is detected effectively among the stop switches 8L, 8C, 8R, the stop operation position is based on the number of steps from the reel reference position when the stop operation is detected. The number of sliding symbols corresponding to the area number of the specified stop operation position is acquired by referring to the stop control table of the reel where the stop operation is detected. Then, control is performed to rotate and stop the reel by the number of acquired sliding frames.

  Specifically, from the number of steps from the reel reference position at the time when the stop operation is detected, the number of steps from the acquired number of sliding frames to the stop is calculated, and the reel is rotated and stopped by the calculated number of steps. Take control. Thus, the region corresponding to the region number that is the stop position ahead of the number of sliding frames from the region corresponding to the region number of the stop operation position where the stop operation is detected is the stop reference position (in this embodiment, the fluoroscopic window 3 The lower symbol area).

  In the table index of the present embodiment, only one address is stored as index data corresponding to one internal winning state in one gaming state, and one table creation data includes one reel. Only one address is stored as the address of the storage area of the stop control table corresponding to the stop status (and the stop position of the stopped reel). That is, the table creation data corresponding to one internal winning state in one gaming state and the stop control table corresponding to the reel stop status (and the stop position of the stopped reel) are uniquely determined. The stop control table created with reference to is unique for one internal winning state in one gaming state and the reel stop status (and the stop position of the stopped reel). Therefore, when all of the gaming state, the internal winning state, and the reel stop status (and the stop position of the stopped reel) are the same, the reel is based on the same stop control table, that is, the same control pattern. The stop control is performed.

  Further, in the present embodiment, a value of 0 to 4 is determined as the number of sliding frames, and it is possible to stop the reel by drawing a maximum of 4 frames after detecting a stop operation. In other words, the stop position of the symbol can be designated from a range of a maximum of 5 frames including the stop operation position where the stop operation is detected. In addition, since it is necessary to move one frame to move the reel for one symbol, it is possible to stop the reel by pulling in a maximum of four symbols after detecting the stop operation. The symbol stop position can be designated from a range of up to five symbols including the operation position.

  In the present embodiment, when any of the winning combinations is won, the winning combination is drawn to the maximum in the range of 4 frames on the winning line, and the winning combination is drawn not to be aligned on the winning line. Create a stop control table with the number of sliding symbols and perform reel stop control. If none of the roles are won, stop control with the number of sliding symbols that do not match any of the roles A table is created and reel stop control is performed. As a result, when a stop operation is performed, if the winning combination can be stopped on the winning line within the drawing range of a maximum of 4 frames, the control is performed so that the winning combination is stopped. If the winning combination is not drawn, it will be controlled so that it can be stopped in a drawing range of up to 4 frames.

  When a special role and a small role are elected at the same time, such as when a special role is elected while the special role has been carried over from before the previous game, the winning small role is the maximum in the range of 4 frames on the winning line. The number of sliding frames is fixed so that it can be drawn to the limit, and for the stop operation position where the selected small role cannot be drawn in the range of up to 4 frames in the winning line, the winning special role is in the range of 4 frames in the winning line A stop control table in which the number of sliding frames is determined so as to be pulled in as much as possible is created, and the reel stop control is performed.

  As a result, when a stop operation is performed, if it is possible to stop all the small roles that have been selected in the drawing range of up to 4 frames on the winning line and stop them, the control is performed so that the winning combination is stopped. If you can't draw a small role that has been won in the drawing range of up to 4 frames on the line, if you can stop with a special role that has been won in the drawing range of up to 4 frames on the winning line, Control is performed to align and stop them, and a winning combination that has not been won will be controlled to be stopped within the 4-frame pull-in range. That is, in such a case, priority is given to the control for aligning the small combination on the winning line over the special combination, and the special combination can be won only when the small combination cannot be drawn. When a special combination and a small combination can be withdrawn at the same time, only the small combination is withdrawn and the small combination is not aligned on the winning line at the same time as the special combination.

  In this embodiment, when a special role is elected while the special role has been carried over from before the previous game, or when a special role and a small role are won simultaneously, the special role and the small role are won simultaneously. In such cases, the selected special role has priority over the selected special role, and only when the small role cannot be withdrawn, the special role is controlled on the winning line. If both are elected at the same time, priority is given to the control of aligning the special role on the winning line over the small role, and the control of aligning the small role on the winning line may be performed only when the special role cannot be drawn. .

  If a special player and a replaying player are elected at the same time, such as when a replaying player is elected while the special role has been carried over from before the previous game, the winning line will be displayed when the stop operation is performed. In addition, the control is performed so that the symbols of the re-gamer are aligned and stopped within a maximum of 4 frames. In this case, the symbols constituting the re-gamer or the symbols constituting the re-gamer elected at the same time are arranged within 5 symbols for each of the reels 2L, 2C and 2R, that is, at intervals of 4 frames or less. Since it can always be stopped at any position within the 4-frame pull-in range, if the special combination and the re-playing combination are elected at the same time, the timing of the operation of the stop switches 8L, 8C, 8R by the player Without fail, the re-playing role will always be won. That is, in such a case, the control for aligning the re-games on the winning line has priority over the special game, and the re-games will always win. In the case where the special role and the replaying role can be withdrawn at the same time, only the replaying role is drawn in, and the special role is not arranged on the winning line at the same time as the replaying role.

  In the present embodiment, the main control unit 41 rotates the reels for which the stop operation has not yet been detected until the operation of the stop switches 8L, 8C, 8R is detected after the rotation of the reels 2L, 2C, 2R is started. And the control to stop the display result on the corresponding reel is performed on the condition that the operation of the stop switches 8L, 8C, 8R is detected. Even if the reel rotation temporarily stops due to the occurrence of a reel rotation error, the stop operation is still detected until the operation of the stop switches 8L, 8C, and 8R is detected after the reel rotation is restarted. Control is performed to stop the display result of the corresponding reels on the condition that the operation of the stop switches 8L, 8C, and 8R is detected by continuing the rotation of the reels that have not been operated.

  In the present embodiment, the control of stopping the display result on the corresponding reel is performed on the condition that the operation of the stop switches 8L, 8C, and 8R is detected, but the rotation of the reel is started. Then, when a predetermined automatic stop time has elapsed, even if the reel stop operation is not performed, it is assumed that the stop operation has been performed, and automatic stop control is performed to automatically stop each reel. It may be. In this case, since the reels are stopped without the player's operation, it is preferable to derive a display result that does not constitute any combination even if any combination is won.

  Next, a command that the main control unit 41 transmits to the effect control board 90 will be described.

  In the present embodiment, the main control unit 41 makes a BET command, a credit command, an internal winning command, a reel rotation start command, a reel stop command, a winning determination command, a payout start command, a payout end command, A plurality of types of commands including a game state command, a standby command, a stop command, an error command, a return command, a setting start command, a confirmation start command, a confirmation end command, and an operation detection command are transmitted.

  These commands consist of 1-byte type data indicating the command type and 1-byte extension data indicating the command content, and the sub-control unit 91 can determine the command type from the type data.

  The BET command is a command that can specify the number of inserted medals, that is, the number of medals used to set the bet number, and is a state from the end of the game (after setting change) to the start of the game. Sent when a medal is inserted or the bet number is set by operating the single BET switch 5 or the MAXBET switch 6 in a state where is not set. Further, since the BET command is transmitted when the betting number setting operation is performed, it is possible to specify that the betting number setting operation has been performed by receiving the BET command.

  The credit command is a command that can specify the number of medals stored as credits, and is a state from the end of the game (after setting change) to the start of the game, and in a state where a predetermined number of bets is set, Sent when a medal is inserted and credits are added.

  The internal winning command is a command that can specify the winning status of the internal winning flag and the type of the internal winning flag that has been established, and is transmitted when the start switch 7 is operated to start the game. Further, since the internal winning command is transmitted when the start switch 7 is operated, it is possible to specify that the start switch 7 has been operated by receiving the internal winning command.

  The reel rotation start command is a command for notifying the start of reel rotation, and is transmitted when rotation of the reels 2L, 2C, and 2R is started.

  The reel stop command is a command that can specify whether the reel to be stopped is the left reel, the middle reel, or the right reel, the area number of the corresponding reel stop operation position, and the area number of the corresponding reel stop position. And is transmitted every time stop control is performed in accordance with the stop operation of each reel. Since the reel stop command is transmitted when the stop switches 8L, 8C, and 8R are operated, it is possible to specify that the stop switches 8L, 8C, and 8R are operated by receiving the reel stop command. .

  The winning determination command is a command that can specify the presence / absence of winning, the type of winning, and the number of medals to be paid out at the time of winning, and is transmitted after all the reels are stopped and the winning determination is performed.

  The payout start command is a command for notifying the start of payout of medals, and is transmitted when the payout of medals is started by paying out a prize or credit (including medals used for setting the number of bets). The payout end command is a command for notifying the end of payout of medals, and is transmitted when the payout of medals by winning and winning a credit is completed.

  The gaming state command is a command that can specify the gaming state of the next game, and is transmitted when the setting change state ends and when the game ends.

  The standby command is a command indicating a transition to the standby state, and after one game is over, a credit (which was used for setting the bet number) is set when the transition to the standby state is made after a predetermined time without setting the bet number. (Including medals) is sent out after the medal payout is completed and the payout end command is sent.

  The stop command is a command indicating the occurrence or release of the stop state, and after the end of the BB, the stop command indicating the occurrence of the stop state is transmitted when the ending effect waiting time has elapsed, and the reset operation is performed. When the stop state is released, a stop command indicating the release of the stop state is transmitted.

  An error command is a command that indicates the occurrence or cancellation of an error condition and the type of error condition. When an error is determined and controlled to an error condition, an error command indicating the occurrence and type of the error condition is sent and reset. When the error state is canceled after the operation is performed, an error command indicating the cancellation of the error state is transmitted.

  The return command is a command indicating that the main control unit 41 has returned to the control state before the power interruption, and is transmitted when the main control unit 41 returns to the control state before the power interruption.

  The setting start command is a command indicating the start of the setting change state, and is transmitted when shifting to the setting change state. Further, since the control state of the main control unit 41 is initialized with the transition to the setting change state, it can be specified that the control state of the main control unit 41 has been initialized by the setting start command.

  The confirmation start command is a command indicating the start of the setting confirmation state, and is transmitted when shifting to the setting confirmation state. The confirmation end command is a command indicating the end of the setting confirmation state, and is transmitted when the setting confirmation state ends.

  The operation detection command is a command indicating the detection state (ON / OFF) of the operation switches (one-sheet BET switch 5, MAXBET switch 6, start switch 7, stop switches 8L, 8C, 8R), and is transmitted at regular intervals. Is done.

  Among these commands, a setting start command, an error command indicating a RAM error or a random number circuit error, and a return command are generated at a stage before the interrupt is permitted in the startup process, and the specific command assigned to the special work in the RAM 507 is transmitted. Stored in the trust buffer and sent immediately.

  Commands other than the setting start command, the error command indicating the RAM abnormality or the random number circuit abnormality, the return command, and the operation detection command are generated according to the progress of the game in the game process, and are sent to the normal command provided in the special work in the RAM 507. Temporarily stored in the trust buffer and transmitted in the command transmission process executed in the timer interrupt process (main).

  The operation detection command is generated every time the command transmission process is executed five times, stored in the aforementioned specific command transmission buffer, and immediately transmitted. In addition, when the operation detection command transmission time is reached with the unsent command stored in the normal command transmission buffer, priority is given to the transmission of the operation detection command and the normal command transmission buffer stores it. The untransmitted command is transmitted in the next command transmission process, and a plurality of commands are not transmitted in one command transmission process.

  Next, the control of the effect performed by the sub control unit 91 based on the command transmitted from the main control unit 41 to the effect control board 90 will be described.

  When the sub control unit 91 receives a command from the main control unit 41, the sub control unit 91 executes a command reception interrupt process. In the command reception interrupt process, the command acquired from the command transmission line is stored in the reception buffer provided in the RAM 91c.

  In the timer interrupt process (sub), the sub-control unit 91 determines whether or not an unprocessed command is stored in the reception buffer. If an unprocessed command is stored, the sub-control unit 91 is the earliest. The control pattern table stored in the ROM 91b is referred to based on the command received in the stage, and the liquid crystal display 51, effect effect LED 52, speakers 53, 54, reel LED 55, etc. are controlled based on the control contents registered in the control pattern table. Output control of various production devices is performed.

  In the control pattern table, the display pattern of the liquid crystal display 51 corresponding to the type of command, the lighting mode of the lighting effect LED 52, the output mode of the speakers 53 and 54, the lighting mode of the reel LED, etc. Control patterns of these effect devices are registered, and when the sub-control unit 91 receives a command, the sub-control unit 91 stores the control patterns registered corresponding to the effect patterns set in the RAM 91c in the game of the control pattern table. Among these, the control pattern corresponding to the type of the received command is referred to, and the output control of the rendering device is performed based on the control pattern. Thereby, the production according to the production pattern and the progress of the game is executed.

  If the sub-control unit 91 receives a new command during the execution of an effect triggered by the reception of a certain command, the sub-control unit 91 stops the effect based on the control pattern being executed and sets the newly received command. An effect based on the corresponding control pattern is executed. In other words, even if the production is not finished to the end, when a new command is received, the production that was being executed is canceled and a new command is received unless the received new command is not a command that triggers a new production. An effect based on the command is executed.

  In particular, in the present embodiment, when the betting number setting operation is performed during the execution of the effect, that is, when the sub-control unit 91 receives a BET command indicating that the betting number has been set, The production is to be canceled. For this reason, if the player wants to proceed to the next game rather than seeing the production to the end, the production is canceled and the next game can be started. There is no. Further, when a credit or betting amount adjustment operation is performed during the performance, that is, after the sub-control unit 91 receives a game state command indicating the end of the game, it receives an internal winning command indicating the start of the game. When the payout start command is received before, the effect being executed is stopped. Credits and bets are settled when the game is finished. In such a case, the production is continued unnecessarily even though there is an intention to finish the game by ending the performance being executed. It is designed not to be overwhelmed.

  When the internal winning command is received, the effect pattern is selected at a selection rate corresponding to the result of the internal lottery indicated by the internal winning command, and is set in the RAM 91c. The selection rate of the effect pattern is registered in the effect table stored in the ROM 91b, and when the sub control unit 91 receives the internal winning command, the sub control unit 91 stores the effect pattern in the effect table according to the result of the internal lottery indicated by the internal winning command. With reference to the registered selection rate, one of the effect patterns is selected from a plurality of types of effect patterns according to the selection rate, and the selected effect pattern is set in the RAM 91c as the effect pattern of the game. Even if the same command is received, a different control pattern is selected depending on the effect pattern selected when the internal winning command is received. As a result, different effects may be performed depending on the effect pattern.

  Next, various control contents executed by the main control unit 41 in the present embodiment will be described below with reference to FIGS.

  When a reset factor occurs, the main control unit 41 performs a startup process (main) shown in the flowchart of FIG. As a reset factor, a system reset that occurs when a low level signal is input to the external system reset terminal XSRST for a certain period at power-on, a time-out signal of a watchdog timer (WDT), etc. There is a user reset such as the occurrence of prohibition of travel outside designated area (IAT). For this reason, the activation process (main) is a process that is performed when the main control unit 41 is activated when the power is turned on and when the main control unit 41 is activated due to a malfunction.

  In the startup process (main), first, the CPU 505 executes the security check process shown in FIG. 24 based on the security check program 506A read from the ROM 506 (Sa1). At this time, the main control unit 41 enters the security mode, and the game control user program stored in the ROM 506 is not yet executed.

  In the security check process, as shown in FIG. 24, first, a process for determining a time (security time) for controlling to the security mode is executed. At this time, the CPU 505 reads the bit value in the bit number [2-0] of the security time setting KSES stored in the program management area of the ROM 506 (Sa101). Then, it is determined whether or not the read value is “000” (Sa102).

  If the read value is determined to be “000” in Sa102, the steady set time is set to a predetermined fixed time (Sa103). Here, the steady setting time is a constant time component of the security time regardless of the number of executions of the security check process based on the occurrence of a system reset or the like (the number of times the main control unit 41 enters the security mode). The fixed time is an invariant time component determined in advance based on the specification of the main control unit 41 in the security time, and may be any minimum value that can be set as the security time, for example.

  If it is determined in Sa102 that the read value is other than “000”, the extension time selected according to the setting contents shown in FIG. The time is set (Sa104). In this way, when the bit value in the bit number [2-0] of the security time setting KSES is a value other than “000”, the security time as the execution time of the security check process can be selected in advance in addition to the fixed time. It can be set to any one of a plurality of extension times.

  After executing one of the processes of Sa103 and Sa104, the bit value in the bit number [4-3] of the security time setting KSES is read (Sa105). Then, it is determined whether or not the read value is “00” (Sa106).

  If the read value is determined to be “00” in Sa106, the steady setting time is set as the security time (Sa107). On the other hand, if it is determined that the read value is other than “00”, the variable set time determined corresponding to the read value is added to the steady set time and set as the security time (Sa108). . Here, the variable setting time is a time component that changes every time the security check process is executed, and the bit value in the bit number [4-3] of the security time setting KSES is “01” (short). Mode) or “10” (long mode), and changes in different predetermined time ranges.

  For example, when a count value in a predetermined free-run counter is stored in a variable security time register built in the main control unit 41 when a system reset occurs, the variable security time register is stored in the processing of Sa108. By using the value as it is, or by using the value obtained by substituting the stored value for a predetermined arithmetic function (for example, a hash function), the variable set time is random within a predetermined time range at each system reset. What is necessary is just to be determined so that it may change. Thus, when the bit value in the bit number [4-3] of the security time setting KSES is a value other than “00”, the security time that is the execution time of the security check process is set as the security based on the occurrence of the system reset or the like. Each time the check process is executed, it can be changed within a predetermined time range.

  Here, the bit value in the bit number [2-0] of the security time setting KSES is a value other than “000”, and the bit value in the bit number [4-3] of the security time setting KSES is other than “00”. In this case, both the extension time set in step S4 and the variable setting time set in step S8 are added to the fixed time, and the security time is determined. .

  After executing one of the processes of Sa107 and Sa108, the security code stored in the predetermined area of the ROM 506 is read (Sa109). Here, in a predetermined area of the ROM 506, a security code of a calculation result obtained by calculating the data of the stored content by a predetermined calculation formula is stored in advance. As a security code generation method, for example, a hash value is generated using a hash function, an error detection code (CRC code) is used, or an error correction code (ECC code) is used. A generation method may be used. In a predetermined area different from the security code storage area of the ROM 506, an arithmetic expression for specifying the security code by calculation is encrypted and stored in advance.

  Following the processing of step Sa109, the encrypted arithmetic expression is decrypted and restored (Sa110). Thereafter, the storage code in the predetermined area of the ROM 506 is calculated by the arithmetic expression decrypted in Sa110 to specify the security code (Sa111). At this time, the storage data used for the calculation for specifying the security code is, for example, program data corresponding to all or part of the user program different from the security check program 506A among the storage data of the ROM 506, or predetermined table data May be all or a part of the fixed data constituting the. Then, the security code read in Sa109 is compared with the security code specified in Sa111 (Sa112). At this time, it is determined whether or not the security codes match in the comparison result (Sa113).

  If the security codes do not match at Sa113, it is determined that an unauthorized change has been made to the ROM 506, and the operation of the CPU 505 is shifted to the halt state (HALT). On the other hand, if the security codes match in Sa113, it is determined whether or not the security time set in the processing of Sa107 or Sa108 has passed (Sa114). At this time, if the security time has not elapsed, the process of Sa114 is repeatedly executed and waits until the security time elapses. If it is determined in Sa114 that the security time has elapsed, the security check process is terminated, and the value of the program counter built in the CPU 505 is set to the start address (address 0000H) of the user program in the ROM 506. As a result, the operation state of the main control unit 41 shifts from the security mode to the user mode, and execution of the user program stored in the ROM 506 is started.

  After completing the security check process of Sa1, the main control unit 41 initializes the built-in device, peripheral IC, interrupt mode, stack pointer, and the like (Sa2), and then initializes the values of the I register and IY register (Sa3). ). By initialization of the I register and the IY register, an interrupt table address to be referred to when an interrupt occurs is set in the I register, and a reference address for referring to the storage area of the RAM 507 is set in the IY register. . These values are fixed values and are always initialized at startup.

  Next, access to the RAM 507 is permitted (Sa4), the RAM parity of all storage areas (including the unused area and the unused stack area) of the RAM 507 is calculated (Sa5), the abort switch 36, the automatic settlement switch 29 And the validity / invalidity of the stop function and automatic settlement function are set in a specific register of the main control unit 41 (Sa6).

  Next, it is determined whether or not the RAM parity calculated in step Sa5 is 0 (Sa7). If the power interruption interrupt process (main) is normally performed, the RAM parity should be 0. If the RAM parity is not 0 in the step of Sa7, the data stored in the RAM 507 is not normal. In this case, after executing the initialization 1 for initializing all the storage areas except the used stack area in the storage area of the RAM 507 (Sa30), it is determined whether or not the setting key switch 37 is ON. (Sa31) If the setting key switch 37 is ON, the first random number initial setting KRS1 and the second random number initial setting KRS2 stored in the program management area are read, and the random number circuit setting process shown in FIG. 25 is executed. Thereafter (Sa25), the random number circuit abnormality inspection process shown in FIG. 26 is executed in order to inspect the presence or absence of operation abnormality in the random number circuit 509 (Sa26).

  In the random number circuit setting process shown in FIG. 25, first, setting for using the random number circuit 509 is performed based on the bit value in the bit number [3] of the first random number initial setting KRS1 (Sa201). In the present embodiment, the bit value in the bit number [3] of the first random number initial setting KRS1 is set to “1” in advance, and the setting for using the random number circuit 509 is performed corresponding to this bit value. Subsequently, the random number update clock RGK in the random number circuit 509 is set based on the bit value in the bit number [2] of the first random number initial setting KRS1 (Sa202). In the present embodiment, the random number clock RCLK generated by the random number clock generation circuit 43 in response to the bit value [2] of the first random number initial setting KRS1 being “1” in advance. Is set to be a random number update clock RGK.

  After setting in Sa202, a random number update rule is set in the random number circuit 509 based on the bit value in the bit number [1-0] of the first random number initial setting KRS1 (Sa203). In the present embodiment, “10” is set in advance as the bit value in the bit number [1-0] of the first random number initial setting KRS1, and the random number update rule in the random number sequence RSN is automatically changed after the second round. Setting to be made.

  Subsequently, based on the bit value in the bit number [1] of the second random number initial setting KRS2, a start value at start-up in numerical data to be a random value is determined (Sa204). In this embodiment, “1” is set in advance as the bit value in the bit number [1] of the second random number initial setting KRS2, and the start value of the random number is set to a value based on the ID number.

  Further, based on the bit value in the bit number [0] of the second random number initial setting KRS2, it is set whether or not to change the start value of the numerical data to be a random value at every system reset (Sa205). In the present embodiment, the bit value at the bit number [0] of the second random number initial setting KRS2 is set to “0” in advance, and the start value at start-up set in Sa204 is used as it is, and the start in the random number circuit 509 is started. Value. When the setting by the processing of Sa205 is completed, the random number circuit 509 starts a random value generation operation. When the bit value [0] of the second random number initial setting KRS2 is set to “1” in advance, the random number start value is changed every time the system is reset. In this case, for example, when the count value in a predetermined free-run counter is stored in the random number start value register built in the main control unit 41 when a system reset occurs, the random number start is performed in the processing of Sa205. By using the stored value of the value register as it is or by using the value obtained by substituting the stored value for a predetermined arithmetic function (for example, a hash function), the start value of the random number is predetermined at each system reset. (For example, a range including all or part of the numerical data included in the count value permutation RCN generated by the random number generation circuit 553) may be determined at random.

  After executing the processing of Sa205, for example, by reading numerical data stored in the random value register R1D or the random value register R2D, the bit number [1] or the bit number [0] of the random number latch flag register RDFM is read. The bit values of the stored random number latch flag data RDFM1 and random number latch flag data RDFM0 are set to “0”, and each random number latch flag is cleared to an off state (step Sa206). As an example, for the random number latch flag data RDFM1 and the random number latch flag data RDFM0, it is determined whether each value is “1” or “0”, and if the value is “1”, the corresponding random value The random number latch flag may be turned off by reading the register. Alternatively, each random number latch flag may be turned off by reading the random number value register R1D and the random number value register R2D regardless of the values of the random number latch flag data RDFM1 and the random number latch flag data RDFM0. Note that the numerical data read from the random value register R1D or the random value register R2D by the process of step Sa206 may be discarded (erased) as it is without being used for the internal lottery. When the setting by the processing of step Sa206 is completed, the random number circuit 509 may start the random value generation operation.

  Thus, when the execution of game control is started, numerical data can be read from the random value register in the process of step Sa206, and each random number latch flag can be set to the OFF state. As a result, it is possible to prevent numerical data stored in the random value register by mistake when the power supply voltage at the time of power-on is unstable is acquired as a random value.

  Note that the setting by the random number circuit setting process may be performed autonomously by the random number circuit 509 based on the data stored in the program management area without the intervention of the CPU 505. In this case, the random number circuit 509 may be configured not to perform initialization and not to generate a random value when the main control unit 41 is in the security mode. Then, when the CPU 505 reads the user program stored in the ROM 506 in the main control unit 41 and the user mode is started, for example, a control signal for instructing the initial setting to the random number circuit 509 is transmitted from the CPU 505. In response to the above, the random number generation operation may be started after the random number circuit 509 performs initial setting. In particular, when the random number circuit 509 is externally attached to the main control unit 41, even when the main control unit 41 is in the security mode, the random number circuit 509 performs program management independently of the processing in the CPU 505. The random number generation operation may be started after initial setting based on the storage data of the area.

  In the random number circuit abnormality inspection process shown in FIG. 26, first, the random number clock abnormality determination counter is cleared, and the random number clock abnormality determination count value, which is the count value, is initialized to “0” (Sa301). Subsequently, the internal information data CIF4 stored in the bit number [4] of the internal information register CIF is read (Sa302). Then, it is determined whether or not the read value at Sa302 is “1”. At this time, if the frequency monitoring circuit 551 provided in the random number circuit 509 detects a frequency abnormality in the random number clock RCLK from the random number external clock terminal ERC, the bit value “1” is written as the internal information data CIF4. .

  Therefore, when the read value is determined to be “1” in Sa303, the random number clock abnormality determination count value is updated to be incremented by 1 (Sa304). At this time, it is determined whether or not the count value after the update in Sa304 has reached a predetermined clock abnormality determination value (Sa305). Here, the clock abnormality determination value may be a numerical value determined in advance in order to determine that the clock abnormality is detected when the frequency monitoring circuit 551 continuously detects the frequency abnormality of the random number clock RCLK. If the clock abnormality determination value has not been reached in Sa305, the processing returns to Sa302, and determination based on the bit value of the internal information data CIF4 is performed again.

  When the clock abnormality determination value is reached in Sa305, an error code indicating a random circuit abnormality is set in the register (Sa306), and the random circuit abnormality inspection process is terminated.

  If the read value is determined to be “0” in Sa303, the random value abnormality determination counter is cleared, and the random value abnormality determination count value that is the count value is initialized to “0” (Sa307). In the process of Sa303, it is determined that the read value is “0” when the bit value of the internal information data CIF4 read in Sa302 becomes “0” continuously for a plurality of times (for example, twice). May be.

  Subsequent to the processing of Sa307, a check value used for checking whether there is an abnormality in the random number value is set to an initial value “0000H” (Sa308). Then, the stored numerical data as the random value is read from the random value register 559A as the random value register R1D included in the random number circuit 509 (Sa309). For example, in the processing of Sa309, the bit value of the random number latch selection data RDLS0 stored in the bit number [0] of the random number latch selection register RDLS is set to “0”, and fetching of the random number value by software is designated. Subsequently, the bit value of the random value fetch specification data RDLT0 stored in the bit number [0] of the random value fetch specification register RDLT is set to “1”, and fetching to the random value register R1D is designated. Note that setting the bit value in the bit number [0] of the random value fetch specification register RDLT to “1” outputs a latch signal instructing the random number circuit 509 to fetch (latch) numerical data from the CPU 505. It corresponds to that. Thereafter, the numerical value data to be stored as the random number value may be read by turning on the register read signal RRS1 supplied to the random number value register R1D.

  After reading the numerical data in Sa309, the read value is set as the random number inspection reference value (Sa310). Subsequently, the numerical value data to be a random number value is further read from the random value register 559A (Sa311). Note that the reading operation at Sa311 may be performed in the same procedure as the reading operation at Sa309. Further, a sufficient delay time may be provided between the reading operation at Sa309 and the reading operation at Sa311 so that the numerical data in the random number sequence RSN generated by the random number circuit 509 changes. After the numerical data is read in Sa311, an exclusive OR operation between the random number inspection reference value and the read value in Sa311 is executed (Sa312). Further, a logical sum operation between the calculation result at Sa312 and the check value is executed, and the calculation result is updated to be a new check value (Sa313). For example, the check value may be stored in a predetermined area of the RAM 507, and each time the processing of Sa313 is executed, the calculation result obtained by the processing may be saved as a new check value. As a result, changes in all the bits in the numerical data read from the random value register 559A are recorded. If the bit has changed at least once during a plurality of readings, the corresponding bit value in the check value is “1”. "

  Therefore, it is determined whether or not the check value is “FFFFH” (Sa 314), and if it is, since a change in the bit value is recognized for all bits, it is determined that the random value has been updated normally. Then, the random number circuit abnormality inspection process ends. When it is confirmed that the random number value has been updated normally, the bit value of the random number latch selection data RDLS0 stored in the bit number [0] of the random number latch selection register RDLS is set to “1”. It is set to instruct the random value fetching to the random value register R1D according to the signal input to the port P0. In the present embodiment, a wiring for transmitting the game start signal SS1 from the start switch 7 is connected to the input port P0. Thereby, when the game start signal SS1 is turned on, the random number value can be taken into the random value register R1D.

  If the check value is determined to be other than “FFFFH” in Sa314, the random number abnormality determination count value is updated to be incremented by 1 (Sa315). At this time, it is determined whether or not the count value after the update in Sa315 has reached a predetermined random value abnormality determination value (Sa316). Here, if the random number circuit 509 is operating normally, the random value abnormality determination value is determined so that all the bits of the numerical data read from the random value register 559A are changed at least once. Any numerical value determined in advance may be used. If the random value abnormality determination value has not been reached in Sa316, the process returns to Sa311 to perform determination for reading numerical data as a random value from the random number circuit 509 and checking for abnormality.

  If the random value abnormality determination value is reached in Sa316, an error code indicating a random circuit abnormality is set in the register (Sa317), and the random circuit abnormality inspection process is terminated.

  The random number circuit abnormality inspection process is not limited to that executed by the CPU 505, and the random number circuit abnormality inspection process may be executed by a built-in circuit in the main control unit 41 other than the CPU 505. As an example, the random number circuit 509 has a function of executing a random number circuit abnormality inspection process. When a frequency abnormality of the random number clock RCLK is detected or when an abnormality of the random number value is detected, the CPU 505 May be notified. The random number circuit abnormality inspection process may be executed partially or entirely every time a timer interrupt occurs in the main control unit 41, for example.

  After the random number circuit abnormality inspection process in the step of Sa26, it is determined whether or not the random number circuit is abnormal (Sa27a). Whether or not the random number circuit is abnormal is determined by whether or not an error code indicating a random number circuit abnormality is set. If it is determined in step Sa27a that the random number is abnormal, an error command indicating a random circuit error is set in the specific command transmission buffer and transmitted to the sub-control unit 91 (Sa22). (Sa23), the process proceeds to error processing, that is, a RAM abnormal error state.

  If it is determined in step Sa27a that the random number is not abnormal, it is determined whether or not the front door 1b is open based on the detection signal from the door open detection switch (Sa27b).

  If it is determined in step Sa27b that the front door 1b is not open, that is, if it is determined that the front door 1b is closed (closed), the setting key switch is ON but the front door 1b is not open. Is set, a door closing state flag is set (Sa27c), and the process proceeds to Sa16. When the door closing state flag at the time of setting is set, as will be described later, the progress of the game control is stopped and disabled at a predetermined timing.

  Thus, in Sa27b, when the power switch 39 is switched from OFF to ON (when the power is turned on), the setting key switch 37 is in a specific operation state in which a detection signal for specifying ON is output. When the open / close state of the front door 1b is determined and it is determined that the front door 1b is not in the open state, it is regarded as an illegal act and is not controlled to the setting change state. That is, if the front door 1b is not in an open state, the power switch 39 and the setting key switch 37 cannot be operated and cannot enter a specific operation state. When there is a possibility that an illegal act has been performed without being in the open state, the setting change state is not controlled. Accordingly, it is possible to reliably prevent the setting change by being controlled to the setting change state by an illegal act.

  Further, as described in FIG. 2, the door opening detection switch 25 and the power supply box 100 on which the setting key switch 37, the reset / setting switch 38, and the power switch 39 for performing the setting change operation are respectively provided. Since it is provided on different side surfaces in the housing 1a, the difficulty of performing an illegal act on both the door opening detection switch 25 and the power supply box 100 is increased.

  Furthermore, an illegal act may be considered in which the same detection signal as that in the open state is output by the door open detection switch 25 while the front door 1b is closed with respect to the housing 1a. However, as described above, a reflective optical sensor is used as the door opening detection switch 25. For this reason, in order to perform the above fraudulent act, for example, it is difficult to remove the reflecting member. Further, since it can be visually recognized whether or not the reflecting member has been removed, it is possible to easily grasp that an illegal act has been performed. Therefore, it is possible to prevent an illegal act such that the door open detection switch 25 outputs the same detection signal as in the open state while the front door 1b is closed with respect to the housing 1a.

  On the other hand, when it is determined in step Sa27b that the front door 1b is open, a setting start command is set in the specific command transmission buffer and transmitted to the sub-control unit 91 (Sa28). Next, the interruption is permitted (Sa29), and the setting change processing, that is, the setting change state is entered. The setting change process continues until the setting key switch 37 is turned off regardless of the open / closed state of the front door 1b. That is, once the process is shifted to the setting change process, the setting change process is maintained regardless of the open / closed state of the front door 1b until the setting key switch 37 is turned OFF and the setting end condition is satisfied. For this reason, after the power switch 39 and the setting key switch 37 are properly operated and not set in an unauthorized manner and controlled to the setting change state, the door opening detection switch is touched by mistake during the setting change. For example, even if it is erroneously detected that the front door 1b is in the closed state, the setting change state can be maintained and the setting can be changed reliably. For this reason, there is no need for the game hall manager to be bothered by having to turn off the power again to change the setting from the beginning due to an erroneous operation.

  If the setting key switch 37 is OFF in the step of Sa31, an error code indicating RAM abnormality is set in the register (Sa32), an error command indicating RAM abnormality is set in the specific command transmission buffer, and the sub-control unit 91 is set. In response to the transmission (Sa33), the interrupt is permitted (Sa34), and the process proceeds to an error process, that is, a RAM abnormal error state.

  If the RAM parity is 0 in step Sa7, it is further determined whether or not the destructive diagnosis data is normal (Sa8). If power interruption interrupt processing (main) is performed normally, the data for destruction diagnosis should have been set. If the data for destruction diagnosis is not normal in step Sa8 (data for destruction diagnosis is power interruption) Since the data in the RAM 507 is not normal also in cases other than 5A (H) stored at the time, the process proceeds to step Sa30 to execute initialization 1, and then the setting key switch 37 is turned on in step Sa31. If so, the random number circuit setting process (Sa25) and the random number circuit abnormality inspection process (Sa26) are sequentially performed. If the random number circuit is abnormal, the interrupt is permitted after the transmission of the error command indicating the random number circuit abnormality (Sa22). (Sa23), and the process proceeds to error processing. On the other hand, if the random circuit is not abnormal, after transmission of the setting start command (Sa28), the interrupt is permitted (Sa29), and the process proceeds to the setting change process. If the setting key switch 37 is OFF in step Sa31, an error code indicating a RAM abnormality is set (Sa32), an error command indicating a RAM abnormality is transmitted (S33), and then an interrupt is permitted (Sa34). ), Go to error handling.

  If it is determined in step Sa8 that the destructive diagnosis data is normal, the data in the RAM 507 is normal, so the destructive diagnosis data is cleared (Sa9). After initialization 3 for initializing the used stack area (Sa10), it is determined whether the setting key switch 37 is ON (Sa11). If the setting key switch 37 is ON, the process proceeds to step Sa24. Initialization 1 is executed, the random number circuit setting process (Sa25) and the random number circuit abnormality inspection process (Sa26) are sequentially performed. If the random number circuit is abnormal, after transmission of an error command indicating the random number circuit abnormality (Sa22), The interrupt is permitted (Sa23), and the process proceeds to error processing. On the other hand, if the random circuit is not abnormal, after transmission of the setting start command (Sa28), the interrupt is permitted (Sa29), and the process proceeds to the setting change process.

  If the setting key switch 37 is OFF in the step of Sa11, the same random number circuit setting process (Sa13) as the step of Sa25 and the same random number circuit abnormality inspection process (Sa14) as the step of Sa26 are executed, and whether or not the random number circuit is abnormal. Is determined (Sa15).

  If it is determined in step Sa15 that the random number circuit is abnormal, an error command indicating the random number circuit abnormality is set in the specific command transmission buffer, and transmitted to the sub-control unit 91 (Sa22). Permitted (Sa23), the process proceeds to error processing, that is, a RAM abnormal error state.

  If it is determined in step Sa15 that there is no abnormality in the random number circuit, each register is restored to the state before power interruption, that is, the state stored in the stack (Sa16), and the return command is stored in the specific command transmission buffer. It is set and transmitted to the sub-control unit 91 (Sa17). Then, it is determined whether or not the random number value is latched based on the value of the random number latch flag register, that is, whether or not the numerical value data is taken into the random number value register 559A (Sa18), and the random number value must be latched. If the random value is latched, the numerical data stored in the random value register 559A is read (Sa19), and the process proceeds to Sa20. Note that when numerical data is read from the random value register 559 in the step of Sa19, the random number latch flag register is cleared, and the acquisition of new numerical data is permitted. In the step of Sa19, although the numerical data is read, the read numerical data is not used, but is read as a dummy so that new numerical data can be taken in according to the operation of the start switch 7. is there.

  In step Sa20, the return command is set in the specific command transmission buffer, transmitted to the sub-control unit 91, and then interrupts are permitted (Sa21). Return to.

  FIG. 27 is a flowchart showing the control content of error processing executed by the main control unit 41.

  In the error processing, first, the current display state of the game auxiliary display 12 is saved in the stack (Sb1), the error code stored in the register is displayed on the game auxiliary display 12 (Sb2), and the error code is stored in the RAM. It is determined whether or not the error code indicates an abnormal error or a random circuit error (Sb3). If the error code indicates a RAM abnormal error or a random circuit error, the process shifts to a loop process that does not perform any process. .

  If it is determined in step Sb3 that neither the error code indicating a RAM abnormal error nor the error code indicating a random circuit error is detected, an error command indicating the occurrence of the error state and its type is set in the normal command transmission buffer ( Sb4). The error command set in step Sb4 is transmitted to the sub-control unit 91 in the subsequent timer interrupt process (main).

  Next, it is determined whether or not the operation of the reset / setting switch 38 is detected (Sb5). If the operation of the reset / setting switch 38 is not detected, whether or not the operation of the reset switch 23 is further detected. (Sb6), and if the operation of the reset switch 23 is not detected, the process returns to the step Sb5. That is, the game waits in a state where the progress of the game is impossible until the operation of the reset / setting switch 38 or the reset switch 23 is detected.

  When the operation of the reset / setting switch 38 is detected in the step Sb5 or when the operation of the reset switch 23 is detected in the step Sb6, the error code stored in the register is cleared (Sb7 ), The display state of the game auxiliary display 12 is restored to the display state saved in the stack in the step Sb1 (Sb8), and an error command indicating that the error state is released is set in the normal command transmission buffer ( Sb9), the process returns to the original process. The error command set in Sb9 is transmitted to the sub-control unit 91 in the subsequent timer interrupt process (main).

  As described above, in the error processing, if the error processing is not due to the RAM abnormality or the random number circuit abnormality, the reset / setting switch 38 or the reset switch 23 is operated to return to the original processing even when the error state is canceled. However, in the case of error processing due to RAM abnormality or random number circuit abnormality, even if the reset / setting switch 38 or the reset switch 23 is operated, the error state is canceled and the original state is not restored.

  FIG. 28 is a flowchart showing the control content of the setting change process executed by the main control unit 41.

  In the setting change process, first, the setting value stored in the setting value work of the RAM 507 is read out, and the read value is set as a display value (Sc1), and whether or not the display value is out of a settable range (1 to 6). (Sc2), if the display value is within the settable range, the process proceeds to step Sc4. If the display value is outside the settable range, the display value is corrected to 1, and the process proceeds to step Sc4.

  In the step of Sc4, after the display value is displayed on the setting value display 24, the operation waits for detection of the operation of the reset / setting switch 38 and the start switch 7 (Sc5, Sc6). In the step of Sc5, the reset / setting switch When 38 on is detected, the rising edge indicating the rising of the operation switch is cleared (Sc7), the display value is incremented by 1 (Sc8), and the process returns to the step Sc2.

  When the start switch 7 is detected to be on in the step of Sc6, the rising edge is cleared (Sc9), the value displayed on the set value display 24 is updated to 0 (Sc10), and the setting key Wait until the switch 37 is turned off (Sc11).

  If it is determined in step Sc11 that the setting key switch 37 is OFF, the display value is stored in the set value work (Sc12), a game state command is generated, and set in the command transmission buffer (Sc13). The gaming state command set in the step of Sc13 is transmitted to the sub-control unit 91 in the subsequent timer interrupt process (main).

  In the step of Sc14, it is determined whether or not a setting door closed state flag or a disabling flag for disabling the game is set. When it is determined in the step of Sc14 that the flag is not set, the process directly proceeds to game processing. On the other hand, when it is determined in the step of Sc14 that the flag is set, the set flag is cleared (Sc15), and the process proceeds to the game process. As a result, once the set door closing state flag or the disablement flag is set, the flag is not cleared until the setting change state is entered, so that the game can be disabled.

  FIG. 29 is a flowchart showing the control contents of the game process executed by the main control unit 41.

  In the game process, a BET process (Sd1), an internal lottery process (Sd2), a reel rotation process (Sd3), a winning determination process (Sd4), a payout process (Sd5), and a game end process (Sd6) are sequentially executed. When the end-time process ends, the process returns to the BET process again.

  In the BET process in the step of Sd1, the process waits in a state where a bet number can be set, and a process for starting a game when a specified number of bets is set according to the gaming state and the start switch 7 is operated is executed. .

  In the internal lottery process in the step Sd2, a process is performed for determining whether or not the above winning combination is permitted based on the numerical data latched simultaneously with the start of the game by the detection of the start switch 7 in the step Sd1. In this internal lottery process, a winning flag is set in the RAM 507 based on each lottery result.

  In the reel rotation process in the step of Sd3, the process of rotating each reel 2L, 2C, 2R and the operation of the corresponding reel 2L, 2C, 2R in response to the operation of the stop switch 8L, 8C, 8R detected by the player are detected. A process for stopping the rotation is executed.

  In the winning determination process in the step Sd4, when it is determined in the step Sd3 that the rotation of all the reels 2L, 2C, and 2R is stopped, the winning is determined according to the display result derived for each reel 2L, 2C, and 2R. A process of determining whether or not it has occurred is executed.

  In the payout process in step Sd5, when it is determined in step Sd4 that a winning has occurred, processing such as addition of credits and payout of medals is performed based on the number of payouts according to the win.

  In the game end process in the step of Sd6, a process of setting a gaming state in preparation for the next game is executed.

  In the game process, a command is generated according to the progress control of the game and set in the normal command transmission buffer, so that the command set for the sub-control unit 91 in the subsequent timer interrupt process (main) Is to be sent.

  30 to 32 are flowcharts showing the control contents of the BET process executed by the main control unit 41 in step Sd1.

  In the BET process, first, the value of the BET counter in which the value of the betting number is stored in the RAM 507 is cleared (Se1), and a prescribed number (3 regardless of the gaming state in this embodiment) is stored in the RAM 507. It is set (Se2), and it is determined whether or not the game is a replay game based on whether or not the replay game flag indicating that it is a replay game is set in the RAM 507 (Se3).

  If it is determined in step Se3 that the game is a replay game, a BET command indicating that 3 bets have been added is set in the normal command transmission buffer (Se4), and the value of the BET counter is set to 1. Add (Se5) and refer to the prescribed number of bets set in the RAM 507 to determine whether or not the value of the BET counter is the prescribed number, that is, whether or not the bet number as a game start condition is set. If the value of the BET counter is not the specified number, the process returns to the step of Se5. If the value of the BET counter is the specified number, the insertion prohibition flag indicating that the medal cannot be inserted is set in the RAM 507 (Se7). , Go to the step of Se12. The BET command set in step Se4 is transmitted to the sub-control unit 91 in the subsequent timer interrupt process (main).

  If it is determined in the step Se3 that the game is not a replay game, the setting before waiting for input is performed (Se8), and the process proceeds to the step Se9. In the setting before waiting for insertion, the insertion disable flag set in the RAM 507 is cleared, and a medal can be inserted.

  In the step of Se9, it is determined whether or not the value of the BET counter is a specified number, that is, whether or not the number of bets serving as a game start condition is set. Proceeding to the step, if the value of the BET counter is a specified number, it is further determined whether or not any of the switches has been turned OFF (Se10). In the step of Se10, it is determined whether or not any of the switches has been turned off based on whether or not a falling edge indicating the falling of any of the switches is set. Further, since the falling edge is set only when any switch is turned off and all the switches are turned off, in the step of Se10, it is determined whether any switch is turned off or not. In addition, it is also determined whether or not other switches are OFF.

  If it is determined in step Se10 that none of the switches have changed to OFF, or if any switch has changed to OFF but is still ON, the process proceeds to step Se14. If any of the switches changes to OFF and it is determined that all the switches are OFF, the falling edge is cleared (Se11) and the process proceeds to Se12.

  In step Se12, it is determined whether or not numerical data is latched based on the value of the random number latch flag register, that is, whether or not numerical data is captured in the random value register 559A, and the numerical data must be latched. If the numerical data is latched, the numerical data is read from the random value register 559A (Se13), and the process proceeds to Se14. Note that when the numerical data is read from the random value register 559 in the step of Se13, the random number latch flag register is cleared, and the acquisition of new numerical data is permitted. In the step of Se13, although the numerical data is read, the read numerical data is not used, but is read as a dummy so that new numerical data can be taken in according to the operation of the start switch 7. is there. For this reason, although the number of bets serving as a game start condition is set, the switches other than the start switch 7 are operated, and the start switch 7 is in the state where the operation of the start switch 7 is invalidated. Even if numerical data is latched because it has been operated and new numerical data is not imported, all switches are turned off and latched when the start switch 7 is activated. The numerical data that has been read is read as a dummy, and the numerical data can be newly latched at the timing when the start switch 7 is operated thereafter.

  In step Se14, it is determined whether or not an error code is set in the register, that is, whether or not an error is detected. If an error code is set, the process proceeds to error processing shown in FIG.

  If an error code is not set in the step of Se14, it is determined whether or not a medal can be inserted based on whether or not the insertion disable flag is set in the RAM 507 (Se15). When it is determined in step Se15 that the medal can be inserted, the flow path switching solenoid 30 is turned on, and the medal can be inserted using the medal flow path as a path on the hopper tank side. (Se16), the process proceeds to step Se18, and if it is determined that the medal cannot be inserted, the flow path switching solenoid 30 is set to the off state, and the medal flow path is the path on the medal payout exit 9 side. As a result, the insertion of a new medal is prohibited (Se17), and the process proceeds to Step Se18.

  In step Se18, it is determined whether or not the setting key switch 37 is on. If the setting key switch 37 is on, it is determined whether or not the value of the BET counter is 0 (Se19). If the value of the BET counter is 0 in the step Se19, the confirmation start command is set in the normal command transmission buffer (Se20), and the setting confirmation process (Se21), that is, the setting confirmation state is entered. The confirmation start command set in step Se20 is transmitted to the sub-control unit 91 in the subsequent timer interrupt process (main). Moreover, after the setting confirmation process in the step of Se21 is completed, the process returns to the step of Se9.

  In the setting confirmation process, first, the display value of the payout display 13 is saved, the setting value currently set is acquired from the setting value work of the RAM 41c, and the acquired setting value is displayed on the payout display 13. Thereafter, the control waits until the setting key switch 37 is turned off. When the setting key switch 37 is turned off, the display value of the payout display 13 previously saved is restored, and then a confirmation end command is sent to the normal command transmission buffer. To complete the setting confirmation process. The set confirmation end command is transmitted to the sub CPU 91a in the subsequent timer interrupt process (main).

  If the setting key switch 37 is not on in step Se18, or if the value of the BET counter is not 0 in step Se19, the process proceeds to step Se22a to determine whether the door closing state flag is set. judge. When it is determined that the door closing state flag at the time of setting is set, the process proceeds to step Se22b, and it is determined whether or not a currently valid specific operation has been detected. The detection of the specific operation currently effective means detection of the inserted medal sensor 31, detection of the single BET switch 5, detection of the MAXBET switch 6, detection of the settlement switch 10, and the like.

  It should be noted that the specific operation is effectively detected until the operation to the start switch 7 described later is detected even when the set door closed state flag is set, and the corresponding processing is performed. (For example, processing when it is determined YES in each of Se22d, Se39, Se47, and Se56).

  When it is determined in Se22b that a currently valid specific operation has been detected, the process proceeds to step Se22c, and the disabling flag for disabling operation by stopping the progress of the game by disabling the operation of the start switch 7 Set. On the other hand, when it is determined at Se22a that the set door closing state flag is not set, when it is determined at Se22b that a currently valid specific operation is not detected, and when the disabling flag is set at Se22c , Go to the step of Se22d.

  In Se22d, it is determined whether or not the inserted medal sensor 31 has detected the passage of the inserted medal, that is, the presence or absence of the inserted medal flag indicating that the passage of the inserted medal has been detected. If the passage of the inserted medal is not detected in the step of Se22d, the process proceeds to the step of Se33. If the passage of the inserted medal is detected, the inserted medal flag is cleared (Se23), and the non-insertable flag is set in the RAM 507. Whether or not a medal can be inserted is determined based on whether or not a medal can be inserted (Se24). If the medal cannot be inserted, the process proceeds to Step Se33.

  If the medal can be inserted in the step of Se24, the prescribed number of bets set in the RAM 507 is referred to and it is determined whether or not the value of the BET counter is the prescribed number (Se20). If the value is not the prescribed number, a BET command indicating that the bet number is incremented by 1 is set in the normal command transmission buffer (Se26), the BET counter value is incremented by 1 (Se27), and the BET counter value is It is determined whether or not the number is a specified number, that is, whether or not the number of bets serving as a game start condition has been set (Se28). If the value of the BET counter is not the specified number, the process returns to Step Se9. The BET command set in step Se <b> 26 is transmitted to the sub-control unit 91 in the subsequent timer interrupt process (main).

  Further, if the value of the BET counter is the specified number in the step of Se28, that is, if the betting number as the game start condition is set, the process returns to the step of Se12 and the betting number as the game start condition is set. If the numerical data is latched before being performed, the numerical data is read in step Sa13, and new numerical data can be taken in. For this reason, since the number of bets serving as a game start condition is not set and the start switch 7 is operated in a state where the operation of the start switch 7 is invalidated, the numerical data is latched, and the new numerical data Even when the take-in is prohibited, a predetermined number of bets are set as a game start condition, and the numerical data latched when the operation of the start switch 7 is validated is read as a dummy. The numerical data can be newly latched at the timing when the start switch 7 is operated thereafter.

  If the value of the BET counter is a prescribed number in the step of Se25, a credit command indicating the current credit counter value is set in the normal command transmission buffer (Se29), and the credit counter in which the credit value is stored in the RAM 507 is stored. The value is incremented by 1 (Se30), and it is determined whether the value of the credit counter is 50 which is the upper limit value (Se31). If the value of the credit counter is not 50, the process returns to the step of Se9, If the value is 50, the input impossible flag is set in the RAM 507 (Se32), and the process returns to the Se9 step. The credit command set in the step of Se29 is transmitted to the sub-control unit 91 in the subsequent timer interrupt process (main).

  In step Se33, it is determined whether or not an operation of the start switch 7 is detected, that is, whether or not a rising edge indicating a rising edge of the start switch 7 is set. Further, the rising edge is set only when any switch is turned on and all the switches are turned off. Therefore, in the step of Se33, in addition to whether any switch is turned on. Whether or not the other switch is OFF is also determined.

  If it is determined that the operation of the start switch 7 is not detected in the step of Se33, or if another switch for which the start switch 7 is operated is also operated, the process proceeds to the step of Se39, where the start switch 7 If the operation is effectively detected, the rising edge is cleared (Se34), the specified number of bets set in the RAM 507 is referred to, and whether the value of the BET counter is the specified number, that is, the game start condition It is determined whether or not the number of bets to be set is set (Se35a).

  If the value of the BET counter is not the specified number in the step of Se35a, the process returns to the step of Se9, and if the value of the BET counter is the specified number, the process proceeds to the step of Se35b. In Se35b, it is determined whether or not the disabling flag is set. Normally, the setting change operation cannot be performed unless the front door 1b is opened. When it is determined in Se35b that the disabling flag is set, the front door 1b is displayed when the setting change operation is performed. Is in an abnormal state as if it was in a closed state, and therefore the process proceeds to a loop process in which no process is performed. Thereby, the game is disabled until the setting change state is entered. For this reason, it is easily specified by the game hall manager or other players that the illegal act has been performed. As a result, fraud can be suppressed by increasing the risk of performing fraud.

  Further, regardless of the progress status of the game immediately before being disabled, the operation of the start switch 7 when the disable flag is set is invalidated, and therefore disabled when the start switch 7 is operated. The process of determining whether or not the flag is set is performed, and the process proceeds to the loop process when the disablement flag is set, so that the progress of the game thereafter can be disabled. For this reason, it is possible to facilitate the processing for disabling and prevent the processing burden from increasing because there is no need to perform special control for disabling.

  When the game is disabled, for example, when the power is turned on again without turning the setting key switch to the ON state, the process proceeds to the loop process as described in Sa21 and thereafter in FIG. For this reason, the immobilization cannot be canceled. On the other hand, when the game is disabled, for example, when the front door 1b is opened and the setting key switch is turned on and the power is turned on again, as described in and after Sa29 in FIG. The process is shifted to the setting change process of FIG. 28, and the disabled immobilization flag is deleted in Sc15, so that the disabled disabling can be canceled. As described above, the immobilization of the game is canceled by properly shifting to the setting change state. Therefore, a person who has performed a fraudulent act cannot easily release the disabled state of the game, but a person who can operate the setting key switch with the front door 1b opened (for example, a game management) If it is a person), the immobilization can be canceled easily and quickly.

  On the other hand, when it is determined in Se35b that the disabling flag is not set, the process proceeds to step Se36, and the value of the random number storage work is set as a random value for internal lottery in the lottery work (Se36) and cannot be inserted. The flag is set in the RAM 507, the flow path switching solenoid 30 is turned off, the medal flow path is set as a path on the medal payout exit 9 side, and a new medal is prohibited (Se37). Perform (Se38). Then, after the step of Se38, the BET process is terminated and the process returns to the flowchart of FIG.

  In the step of Se39, it is determined whether or not the operation of the single BET switch 5 is detected, that is, whether or not the rising edge indicating the rising of the single BET switch 5 is set. If the operation of the single BET switch 5 is not detected in the step of Se39, the process proceeds to the step of Se47, and if the operation of the single BET switch 5 is detected, the rising edge is cleared (Se40) and set in the RAM 507. With reference to the prescribed number of bets, it is determined whether or not the value of the BET counter is the prescribed number (Se41). If the value of the BET counter is a specified number in the step of Se41, the process returns to the step of Se9. If the value of the BET counter is not the specified number, it is determined whether or not the value of the credit counter is 0 (Se42). If the counter value is 0, the process returns to step Se9. If the value of the credit counter is not 0 in the step of Se42, a BET command indicating that 1 is added to the bet number is set in the normal command transmission buffer (Se43), and 1 is subtracted from the value of the credit counter (Se44). Then, the value of the BET counter is incremented by 1 (Se45), and it is determined whether or not the value of the BET counter is a specified number, that is, whether or not the number of bets serving as a game start condition is set (Se46). If the value of the counter is not a specified number, the process returns to step Se9. The BET command set in the step of Se43 is transmitted to the sub-control unit 91 in the subsequent timer interrupt process (main).

  Further, if the value of the BET counter is the prescribed number in the step of Se46, that is, if the betting number that is the game start condition is set, the process returns to the step of Se12 and the betting number that is the game start condition is set. If the numerical data is latched before being performed, the numerical data is read in step Sa13, and new numerical data can be taken in. For this reason, since the number of bets serving as a game start condition is not set and the start switch 7 is operated in a state where the operation of the start switch 7 is invalidated, the numerical data is latched, and the new numerical data Even when the take-in is prohibited, a predetermined number of bets are set as a game start condition, and the numerical data latched when the operation of the start switch 7 is validated is read as a dummy. The numerical data can be newly latched at the timing when the start switch 7 is operated thereafter.

  In the step of Se47, it is determined whether or not the operation of the MAXBET switch 6 is detected, that is, whether or not the rising edge indicating the rising of the MAXBET switch 6 is set. If the operation of the MAXBET switch 6 is not detected in the step of Se47, the process proceeds to the step of Se61. If the operation of the MAXBET switch 6 is detected, the rising edge is cleared (Se48), and the number of bets set in the RAM 507 , It is determined whether or not the value of the BET counter is the specified number (Se49). If the value of the BET counter is the specified number in the step of Se49, the process proceeds to the step of Se53, and if the value of the BET counter is not the specified number, it is determined whether or not the value of the credit counter is 0 (Se50), If the value of the credit counter is 0, the process proceeds to step Se53. If the value of the credit counter is not 0 in the step of Se50, 1 is subtracted from the value of the credit counter (Se51), 1 is added to the value of the BET counter (Se52), and the process returns to the step of Se49. In the step of Se53, it is determined whether or not the BET counter has been added. If the BET counter has not been added, the process returns to the step of Se9, and if the BET counter has been added, the bet number is added by the added number. The BET command indicating that it has been set is set in the normal command transmission buffer (Se54), and the process proceeds to Se55. The BET command set in step Se54 is transmitted to the sub-control unit 91 in the subsequent timer interrupt process (main).

  In the step of Se55, it is determined whether or not the value of the BET counter is a specified number, that is, whether or not the bet number as a game start condition is set. If the value of the BET counter is not the specified number, the step of Se9 Return to. Further, if the value of the BET counter is the prescribed number in the step of Se55, that is, if the betting number as the game start condition is set, the process returns to the step of Se12 and the betting number as the game start condition is set. If the numerical data is latched before being performed, the numerical data is read in step Sa13, and new numerical data can be taken in. For this reason, since the number of bets serving as a game start condition is not set and the start switch 7 is operated in a state where the operation of the start switch 7 is invalidated, the numerical data is latched, and the new numerical data Even when the take-in is prohibited, a predetermined number of bets are set as a game start condition, and the numerical data latched when the operation of the start switch 7 is validated is read as a dummy. The numerical data can be newly latched at the timing when the start switch 7 is operated thereafter.

  In the step of Se56, it is determined whether or not the operation of the settlement switch 10 has been detected, that is, whether or not a rising edge indicating the rising of the settlement switch 10 has been set. If the operation of the settlement switch 10 is not detected in the step of Se56, the process returns to the step of Se9. If the operation of the settlement switch 10 is detected, the rising edge is cleared (Se57), and the replay game flag is set in the RAM 507. Whether or not the game is a replay game is determined based on whether or not it is played (Se58), and if the game is a replay game, the process returns to step Se9. If the game is not a replay game in the step of Se58, it is determined whether or not the value of the BET counter is 0 (Se59). If the value of the BET counter is 0, the process proceeds to the step of Se61 and the value of the BET counter is 0. Otherwise, a bet amount settlement flag indicating that the already set bet amount is to be settled is set in the RAM 507 (Se60), and the process proceeds to the step of Se61. In step Se61, the hopper motor 34 is driven to pay out medals corresponding to the value stored in the credit counter or BET counter, that is, medals stored as credits or medals used for setting the number of bets. Checkout processing is performed in which the return control is performed. Then, after the settlement process in the step of Se61, the input impossible flag set in the RAM 507 is cleared (Se62), and the process returns to the step of Se9.

  FIG. 33 and FIG. 34 are flowcharts showing the control contents of the timer interrupt process (main) executed by the main control unit 41 by interrupting and executing the activation process and the game process at regular intervals (0.56 ms interval). Note that other interrupts are automatically prohibited during the execution period of the timer interrupt process (main).

  In the timer interrupt process (main), first, a register in use is saved in the stack area (Sk1), and then a port input process for inputting detection data of various switches from the input port is performed (Sk2).

  Next, the branch counter for identifying the timer interrupt to be executed in the timer interrupt process (main) is advanced by 1 from the four types of timer interrupts 1 to 4 (Sk3). In the step of Sk3, 1 is added when the branch counter value is 0 to 2, and is updated to 0 when the counter value is 3. That is, the branch counter value loops in the order of 0 → 1 → 2 → 3 → 0... Each time the timer interrupt process (main) is executed.

  Next, referring to the counter value for branching, it is determined whether it is 2 or 3, that is, timer interrupt 3 or timer interrupt 4 (Sk4), and if it is not timer interrupt 3 or timer interrupt 4, that is, timer interrupt In the case of 1 or timer interrupt 2, it is checked whether the reel motors 32L, 32C, 32R are started or whether they are rotating at a constant speed, and whether the reel motors 32L, 32C, 32R are started or are rotating at a constant speed. For example, the motor phase signal output process for outputting the phase signal data changed in the motor step process of Sk8 described later and the phase signal data changed in the final stop process of Sk21 described later is executed (Sk5).

  Next, referring to the branch counter value, it is determined whether or not it is 1, that is, timer interrupt 2 (Sk7). If it is not timer interrupt 2, that is, timer interrupt 1, reel motor Reel start processing (Sk8) for controlling the step time interval when starting 32L, 32C, 32R, motor step processing (Sk8) for changing phase signal data of the reel motors 32L, 32C, 32R, reel motors 32L, 32C After the stop of 32R, the motor phase signal standby process (Sk9) for changing the phase signal to one-phase excitation after a certain time has been sequentially executed, and then the register saved in the stack area at Sk1 is restored (Sk19), Return to the previous process.

  In the case of timer interrupt 2 in the step of Sk6, LED dynamic display processing for dynamically lighting various indicators (Sk10), control signal output processing for outputting data such as lighting signals of various LEDs to the output port, etc. (Sk11), a time counter update process (Sk12) for updating various time counters, a command transmission process (Sk13) for transmitting a command or an operation detection command stored in the normal command transmission buffer to the sub-control unit 91, After sequentially executing the external output signal update process (Sk14) for updating the external output signal, the register saved in the stack area at Sk1 is restored (Sk19), and the process returns to the process before the interrupt.

  If it is timer interrupt 3 or timer interrupt 4 in the step of Sk4, it is further determined by referring to the branch counter value whether it is 3 or not, that is, timer interrupt 4 (Sk15). If it is not interrupt 4, that is, if it is timer interrupt 3, the passing of the origin of the rotating reels 2L, 2C, 2R (pass of the reel reference position) is checked, and the occurrence of a reel rotation error is detected and stopped. Check if the preparation is complete (whether the stop preparation completion code is set). If the stop preparation is complete and the motor is rotating at a constant speed, operate the stop switch corresponding to the rotating reel. The origin passing process to be validated (Sk16), the switch input judgment process (Sk17) to judge whether or not the detection state of the switches has changed, and the numerical data is read from the random value register R1D After executing random number reading process to be stored in the random number storing work the (SK18) sequentially, and restores the registers saved in the stack area in Sk1 (Sk19), return to the process before the interrupt process.

  If the timer interrupt is 4 in the step of Sk15, the stop stored in the work on the stop reel is stored when the stop operation position is stored in the work on the stop reel with the detection of the stop switches 8L, 8C, 8R. A stop switch process (Sk20) for calculating the stop position after determining the stop position from the operation position and counting the number of steps until the stop calculated in the stop switch process, and when it is time to stop A stop process (Sk21) for starting braking by two-phase excitation and a final stop process (Sk22) for three-phase excitation after a certain time from the start of braking in the stop process are sequentially executed, and then saved in the stack area at Sk1. The register is restored (Sk19), and the process before the interruption is returned.

  FIG. 35 is a flowchart showing the control content of the random number read process executed by the main control unit 41 in the timer interrupt 3 of the timer interrupt process (main) described above.

  In the random value reading process, it is determined whether or not the numerical data is latched based on the value of the random number latch flag register, that is, whether or not the numerical data is taken into the random value register 559A (Sk101). If not latched, the random number reading process is terminated and the process returns to the flowchart shown in FIG.

  If the numerical data is latched in the step of Sk101, the numerical data is read from the random value register 559A (Sk102), and the value stored in the random value storage work is updated to the numerical data read in Sk102 (Sk103). The random number reading process is terminated and the process returns to the flowchart shown in FIG.

  When numerical data is read from the random value register 559 in the step of Sk102, the random number latch flag register is cleared and new numerical data is accepted into the random value register 559.

  FIG. 36 is a flowchart showing the control contents of the switch input determination process executed by the main control unit 41 in the timer interrupt 3 of the timer interrupt process (main) described above.

  In the switch input determination process, the input data of each switch acquired in the port input process is updated (Sk201), and it is determined whether or not the detection state indicated by the previous input data is the same as the detection state indicated by the current input data. If the determination is made (Sk202) and the detection state indicated by the previous input data is not the same as the detection state indicated by the current input data, the flow returns to the flowchart of FIG.

  In the step of Sk202, when the detection state indicated by the previous input data is the same as the detection state indicated by the current input data, that is, when the same detection state is indicated for 2.24 ms, the determined data of the corresponding switch. Is updated (Sk203), and the process proceeds to Step S204. In step S203, the current confirmed data is moved to the previous confirmed data, and the detection state indicated by the input data determined to be the same as the previous time is set as the current confirmed data.

  In the step of Step 204, it is determined whether or not the previous confirmed data after updating and the current confirmed data are the same. If the previous confirmed data and the current confirmed data are the same, the process returns to the flowchart of FIG. .

  If the previous confirmed data and the current confirmed data are not the same in the step of Sk204, it is determined whether a switch in which the previous confirmed data and the current confirmed data are different has changed from OFF to ON (Sk205). If it has changed to ON, it is further determined whether or not another switch is ON (Sk206). If the other switch is ON, the process proceeds to step Sk208. If the other switch is not ON, the corresponding switch is determined. Is set to the rising edge indicating that the value has changed from OFF to ON (Sk207), and the process proceeds to Step S208.

  In step Sk208, it is determined whether a switch in which the final determined data is different from the final determined data has changed from ON to OFF. If the switch has changed from ON to OFF, it is determined whether other switches are ON. If the other switch is ON, the process returns to the flowchart of FIG. 34. If the other switch is not ON, a falling edge indicating that the corresponding switch has changed from ON to OFF is set ( Sk210), the process returns to the flowchart of FIG.

  FIG. 37 is a flowchart showing the control contents of the command transmission process executed by the main control unit 41 in the timer interrupt 2 of the timer interrupt process (main) described above.

  In the command transmission process, first, 1 is subtracted from the value of the transmission counter assigned to the RAM 41c in order to determine whether it is the transmission timing of the operation detection command (Sk131), and it is determined whether the value of the transmission counter is 0 or not. (Sk132).

  When the value of the transmission counter is not 0 in the step of Sk132, the process proceeds to the step of Sk137, and when the value of the transmission counter is 0, that is, when the operation detection command is transmitted, 5 is set in the transmission counter ( Sk133) Acquires definite data of each switch, creates an operation detection command that can specify the detection state (on / off) of each switch (Sk134), and sets the created operation detection command in the specific command transmission buffer (Sk135). Then, the address of the specific command transmission buffer is set (Sk136), and the process proceeds to Step S139.

  In step Sk137, it is determined whether or not there is an untransmitted command in the normal command transmission buffer. If there is no untransmitted command, the command transmission process is terminated and the process returns to the flowchart shown in FIG.

  If there is an untransmitted command in the normal command transmission buffer in step Sk137, the address indicated by the transmission pointer of the normal command transmission buffer is set (Sk138), and the process proceeds to step Sk139.

  In step Sk139, the command stored in the address set in step Sk136 or Sk138 is read, transmitted to the sub CPU 91a, the command transmission process is terminated, and the process returns to the flowchart shown in FIG.

  FIG. 38 is a flowchart showing the control content of the power interruption interrupt process (main) executed by the main control unit 41 interrupting the activation process and the game process when the voltage drop signal from the power interruption detection circuit 48 is input. is there. It should be noted that after the interruption interrupt process (main) is started, other interrupts are automatically prohibited, and interrupts are not permitted except when returning to the original process.

  In the power interruption interrupt process (main), first, all registers that may be in use are saved in the stack area (Sm1). Although the values of the I register and IY register described above are used, they are not stored here because the same fixed value is always set with the initialization at the time of startup.

  Next, the detection data of the voltage drop signal is acquired from the input port, and it is determined whether or not the voltage drop signal is input (Sm2). At this time, if the voltage drop signal is not inputted, the register saved in the stack area in Sm1 is restored (Sm3), and the process before the interruption is returned. At this time, interruption is automatically permitted.

  If a voltage drop signal is input in step Sm2, destruction diagnosis data (in this embodiment, 5A (H)) is set (Sm4), and all output ports are initialized (Sm5). ). Next, RAM parity adjustment data is calculated and set so that the exclusive OR of all storage areas (including unused areas and unused stack areas) in RAM 507 becomes 0 (Sm6), and access to RAM 507 is performed. Prohibited (Sm7).

  Then, except for the determination of whether or not the voltage drop signal is input (Sm8, Sm8 is the same process as Sm2), a loop process in which no process is performed is entered. That is, when the voltage decreases as it is, the operation is stopped internally. Therefore, the main control unit 41 reliably stops operation when power is interrupted. In this loop process, when the voltage is recovered and it is determined in step Sm8 that the voltage drop signal is not input, a process for clearing the random number latch flag is executed.

  That is, the random number latch flag corresponding to the random value register R1D is turned on according to whether or not the bit value of the random number latch flag data RDFM0 stored in the bit number [0] of the random number latch flag register RDFM is “1”. It is determined whether or not there is (step Sm9). If the random number latch flag is on, reading the random number value register R1D clears the bit value of the random number latch flag data RDFM0 to “0” and sets the corresponding random number latch flag to the off state (step) Sm10).

  Further, when the random number latch flag specified by the random number latch flag data RDFM0 is OFF in step Sm9, or after executing the process of step Sm10, the random number stored in the bit number [1] of the random number latch flag register RDFM. It is determined whether or not the random number latch flag corresponding to the random value register R2D is ON according to whether or not the bit value of the latch flag data RDFM1 is “1” (step Sm11). At this time, if the random number latch flag is on, the random number value register R2D is read to clear the bit value of the random number latch flag data RDFM1 to “0”, and the corresponding random number latch flag is turned off (step) Sm12).

  By the processing of step Sm10 and step Sm12, the random number latch flag is turned off, and the random number value register R1D and the random number value register R2D can be set to a state where storage of new numerical data is permitted. Note that the numerical data read from the random value register R1D or the random value register R2D by the processing of step Sm10 or step Sm12 may be discarded (erased) as it is without being used for the internal lottery.

  Further, instead of the processing of step Sm9 to step Sm12, regardless of the values of the random number latch flag data RDFM0 and the random number latch flag data RDFM1, the random number value register R1D and the random number value register R2D are read to thereby set the random number latch flags. Processing to turn off may be performed.

  When the random number latch flag specified by the random number latch flag data RDFM1 is OFF in step Sm11, or after executing the process of step Sm12, the above-described activation process (main) is executed, the RAM parity becomes 0, and If the destructive diagnosis data is normal, the process returns to the original process.

  As described above, when the power supply is resumed and the execution of the game control is started, the numerical data can already be read from the random value register in the processing of steps Sm10 and Sm12, and each random number latch flag is set to the off state. can do. Thereby, it is possible to prevent the numerical data stored in the random value register by mistake in a state where the power supply voltage is unstable when the power interruption occurs, from being acquired as a random value.

  In this embodiment, after prohibiting access to the RAM 507, the output state of the voltage drop signal is monitored, and when the voltage drop signal is not input, it is determined whether the voltage is restored, and the startup process (main) However, no processing is performed in the loop processing. While the loop processing is being performed, the voltage is recovered and the reset signal is input from the reset circuit 49, or the voltage is Based on the occurrence of the watchdog timer (WDT) time-out signal without decreasing, the process may be shifted to the activation process (main). Even in this case, the same processing as Sm9 to Sm12 may be performed before the start processing (main) is started (see FIG. 72).

  As described above, when the setting key switch 37 is in the ON state when the power is turned on, when it is determined that the front door 1b is in the closed state and fraud is being performed (FIG. 23). In NO at Sa27b, the game is disabled until it is properly shifted to the setting change state (Sc15 in FIG. 28).

  In the slot machine 1 of the present embodiment, the main control unit 41 reads and executes the security check program 506A stored in the ROM 506 or the like when the power is turned on or when the system is restarted after occurrence of a system reset. Thus, the security mode is set.

  At this time, a security check process is executed as a process corresponding to the security check program 506A. Here, the security time when the main control unit 41 enters the security mode is stored in advance in the bit number [2-0] or the bit number [4-3] of the security time setting KSES stored in the program management area of the ROM 506. Depending on the bit value, a time component different from the fixed time can be included.

  For example, if the bit value in the bit number [2-0] of the security time setting KSES is a value other than “000”, it can be selected in advance in addition to the fixed time corresponding to the setting content shown in FIG. Any one of a plurality of extended times can be set as a time component included in the security time. If the bit value in the bit number [4-3] of the security time setting KSES is a value other than “00”, the system reset or power-on is performed corresponding to the short mode or the long mode shown in FIG. A variable setting time that changes in a predetermined time range each time is performed can be set as a time component included in the security time.

  Until the security time set in this way elapses, the execution of the user program stored in the ROM 506 is not started. Then, the operation of generating numerical data to be a random number value by the random number circuit 509 may not be started during the period in which the main control unit 41 is in the security mode. This makes it difficult to specify the operation start timing of the random number circuit 509 and the numerical data to be updated from the operation start timing due to power-on, system reset, and so on. By connecting the “board” and inputting an illegal signal at a predetermined timing, it is possible to reliably prevent acts such as illegally winning a special role.

  As an example, the bit value in the bit number [2-0] of the security time setting KSES is set to a different value for each model of the slot machine 1. In this case, the extension time of the security mode can be made different for each model of the slot machine 1, and it becomes difficult to specify the operation start timing of the random number circuit 509 from the operation start timing of the slot machine 1. Further, by setting the bit value in the bit number [4-3] of the security time setting KSES to “01” or “10”, the variable setting time can be varied for each system reset. This makes it extremely difficult to specify the operation start timing of the random number circuit 509 from the operation start timing of the slot machine 1.

  FIG. 39 is a timing chart for explaining the operation of the random number circuit 509 built in the main control unit 41. FIG. 39A shows the control clock CCLK generated by the control clock generation circuit 42 mounted on the game control board 40. FIG. 39B shows the random number clock RCLK generated by the random number clock generation circuit 43. As shown in FIGS. 39A and 39B, the oscillation frequency of the control clock CCLK and the oscillation frequency of the random number clock RCLK are different from each other, and any one of the oscillation frequencies is It does not become an integral multiple of the other oscillation frequency.

  As shown in FIG. 39B, the random number clock RCLK rises from a low level to a high level at timings T10, T11, T12,. The random number clock RCLK is supplied to the random number external clock terminal ERC of the main control unit 41 and is input to the clock terminal CK in the clock flip-flop 552 provided in the random number circuit 509 shown in FIG. The clock flip-flop 552 responds to the rising edge of the random number clock RCLK input to the clock terminal CK with the latch clock RC0 fed back from the negative phase output terminal (inverted output terminal) Q bar to the D input terminal. Are taken in (latched) and output as a random number update clock RGK from the positive phase output terminal (non-inverted output terminal) Q. Thus, as shown in FIG. 39C, the random number update clock RGK rises from the low level to the high level at the timings T10, T12, T14,..., And is half the oscillation frequency of the random number clock RCLK. The signal has an oscillation frequency. For example, when the oscillation frequency of the random number clock RCLK is 20 MHz, the oscillation frequency of the random number update clock RGK is 10 MHz. Since the oscillation frequency of the random number clock RCLK is neither an integer multiple nor a fraction of the oscillation frequency of the control clock CCLK, the oscillation frequency of the random number update clock RGK is the oscillation frequency of the control clock CCLK. Different frequency. The random number generation circuit 553 updates the numerical data in the count value permutation RCN in response to, for example, the rising edge of the random number update clock RGK. The random number sequence change circuit 555 changes the numerical data update order in the count value permutation RCN output from the random number generation circuit 553 based on the setting of the random number update rule by the random number sequence change setting circuit 556 as a random number sequence RSN. Output. Thus, the numerical data in the random number sequence RSN is updated in response to the rising edge of the random number update clock RGK, for example, as shown in FIG.

  The latch clock RC0 output from the clock flip-flop 552 is an inverted signal of the random number update clock RGK, the oscillation frequency is the same as the oscillation frequency of the random number update clock RGK, and its phase is the same as the phase of the random number update clock RGK and π It differs by (= 180 °). The latch clock RC0 is branched into a latch clock RC1 and a latch clock RC2 at a branch point BR1. Therefore, for example, as shown in FIG. 39E, each of the latch clocks RC0, RC1, and RC2 becomes an oscillation signal whose signal state changes in a common cycle. The latch clock RC1 is input to the clock terminal CK of the latch flip-flop 557A. The latch clock RC2 is input to the clock terminal CK of the latch flip-flop 557B.

  The latch flip-flop 557A takes in (latches) the game start signal SS1 transmitted from the start switch 7 and supplied to the input port P0 in response to the rising edge of the latch clock RC1, and latches the game start signal. Output from the output terminal Q as SL1. If the fetching method in random number latch selector 558A is designated as signal input to input port P0, game start latch signal SL1 is output as random number latch signal LL1. Thereby, for example, a game start signal SS1 whose signal state changes between an off state (low level) and an on state (high level) at the timing shown in FIG. 39F is a timing T11 at which the latch clock RC1 rises. After being fetched into the latching flip-flop 557A at T13, T15,..., The random number latch signal LL1 whose signal state changes between the off state and the on state at timings T11 and T13 as shown in FIG. And output from the random number latch selector 558A.

  The random value register 559A serving as the random value register R1D responds to the rising edge of the random number latch signal LL1 input from the random number latch selector 558A to the clock terminal with the numerical data in the random number sequence RSN output from the random number sequence change circuit 555. Then, the numerical data serving as stored data is updated (latched).

  For example, as shown in FIG. 39 (G), when a rising edge occurs in which the random number latch signal LL1 changes from the off state to the on state at timing T11, the random number sequence change circuit 555 outputs it at this timing T11. As shown in FIG. 39 (H), the numerical data in the random number sequence RSN is taken into the random value register R1D and acquired as numerical data that becomes a random value. Accordingly, the random value register 559A serving as the random value register R1D can acquire and store numerical data used as a random number value based on the detection of the operation of the start switch 7.

  Further, if the bit value in the bit number [0] of the second random number initial setting KRS2 as shown in FIG. 9B is set to “1”, for example, numerical data that becomes a random value generated by the random number circuit 509 The start value can be changed at every system reset. Thereby, even if the operation start timing of the random number circuit 509 can be specified, it becomes difficult to specify the numerical data read from the random value register 559A included in the random number circuit 509, which is based on the analysis result of the program. By connecting a so-called “hanging board” and inputting a fraud signal at a predetermined timing, it is possible to reliably prevent an act such as illegally winning a special role.

  As described above, in the present embodiment, by setting the bit value in the bit number [4-3] of the security time setting KSES to a value other than “00”, it changes within a predetermined time range every time the system is reset or the power is turned on. The variable setting time can be set as a time component included in the security time. This makes it difficult to specify the operation start timing of the random number circuit 509 and the numerical data to be updated from the operation start timing due to power-on, system reset, and so on. By connecting the “board” and inputting an illegal signal at a predetermined timing, it is possible to reliably prevent acts such as illegally winning a special role.

  Also, by setting the bit value in the bit number [2-0] of the security time setting KSES to a value other than “000”, any one of a plurality of extension times that can be selected in advance in addition to the fixed time is set as the security time. It can be set as an included time component. This makes it difficult to specify the operation start timing of the random number circuit 509 and the numerical data to be updated from the operation start timing due to power-on, system reset, and so on. By connecting the “board” and inputting an illegal signal at a predetermined timing, it is possible to reliably prevent acts such as illegally winning a special role.

  Further, the oscillation frequency of the random number clock RCLK generated by the random number clock generation circuit 43 and the oscillation frequency of the control clock CCLK generated by the control clock generation circuit 42 are different from each other. The oscillation frequency does not become an integral multiple of the other oscillation frequency. Therefore, the oscillation frequency of the random number update clock RGK and the latch clock RC0 generated by the clock flip-flop 552 of the random number circuit 509 is ½ of the oscillation frequency of the random number clock RCLK, but the oscillation of the control clock CCLK. The frequency and the oscillation frequency of the internal system clock SCLK that is ½ of the oscillation frequency of the control clock CCLK are different. In this way, the control clock CCLK, the internal system clock SCLK, and the random number update clock RGK are prevented from being synchronized. From the operation timing of the CPU 505, the random number circuit 509 generates the random number generation circuit 553 and the random number sequence change circuit 555. It becomes difficult to specify the update timing of the numerical data in the random number sequence RSN to be performed. As a result, it is possible to reliably prevent aiming and the like based on the result of analyzing the update operation of the numerical data serving as the random number value in the random number circuit 509 from the operation timing of the CPU 505. Also, the oscillation frequencies of the latch clocks RC1 and RC2 generated by branching the latch clock RC0 are different from the oscillation frequencies of the control clock CCLK and the internal system clock SCLK. In this way, synchronization between the control clock CCLK and the internal system clock SCLK and the latch clocks RC1 and RC2 is prevented, and the random number circuit 509 takes in numeric data as a random value from the operation timing of the CPU 505. It becomes difficult to specify the timing. As a result, it is possible to reliably prevent aiming and the like based on the result of analyzing the operation of fetching numerical data as a random value in the random number circuit 509 from the operation timing of the CPU 505.

  The random number circuit 509 built in or externally attached to the main control unit 41 outputs from the random number generation circuit 553 in response to the bit value [0] of the second random number initial setting KRS2 being “1”. The start value of the numerical data in the count value permutation RCN and the random number sequence RSN output from the random number sequence change circuit 555 can be changed every time the system is reset. Thereby, even if the operation start timing of the random number circuit 509 can be specified, it becomes difficult to specify the numerical data read from the random value register 559A included in the random number circuit 509, which is based on the analysis result of the program. It is possible to surely prevent an aiming signal or an illegal signal from being input by connecting a so-called “hanging board”.

  In the external bus interface 501 included in the main control unit 41, the internal resource access control circuit 501A restricts external reading by the devices other than the internal circuit such as the CPU 505 for the internal data of the main control unit 41 such as data stored in the ROM 506. Thereby, for example, a program for controlling a game such as a user program stored in the ROM 506 can be prevented from being read from the outside of the main control unit 41 and provided for analysis or the like. Further, it is possible to reliably prevent aiming based on the analysis result of the game control processing program and input of an illegal signal due to connection of a so-called “hanging board”.

  In the random number circuit 509 built in or externally attached to the main control unit 41, when the frequency monitoring circuit 551 detects a frequency abnormality in the random number clock RCLK, the random number circuit 509 is stored in the bit number [4] of the internal information register CIF. The bit value of the information data CIF4 is set to “1”. When the CPU 505 determines that the number of times that the read value of the internal information data CIF4 is continuously determined to be “1” has reached the clock abnormality determination value in step S65, the random number circuit 509 It is determined that an abnormality has occurred in the operating state. If it is determined that an abnormality has occurred in the operation state of the random number circuit 509, the game is controlled to be in an error state and the progress of the game is disabled. Thereby, it is possible to reliably prevent an illegal act by inputting an illegal signal as the random number clock RCLK.

  The CPU 505 built in the main control unit 41 writes the bit value “1” into the random value fetch specification register RDLT corresponding to the output of the latch signal to the random number circuit 509, and reads the random value register 559A a plurality of times. Then, all the bits of the read numerical data are monitored, and it is determined that an abnormality has occurred in the operation state of the random number circuit 509 based on the presence / absence of bit data that does not change. If it is determined that an abnormality has occurred in the operation state of the random number circuit 509, the game is controlled to be in an error state and the progress of the game is disabled. As a result, it is possible to reliably and easily detect that an abnormality has occurred in the operating state of the random number circuit 509 and prevent fraud. In particular, by performing the internal lottery while the numerical data is not normally updated by the random number circuit 509, that is, while the numerical data is fixed, fraud such as always winning a special combination can be prevented.

  The random number circuit 509 built in or externally attached to the main control unit 41 is a numerical data that becomes a random value every time the system is reset when the bit value [0] of the second random number initial setting KRS2 is “1”. Change the start value of. At this time, for example, a start value that is changed at each system reset may be determined using a count value of a free-run counter incorporated in the main control unit 41, for example. As a result, the initial value can be determined by using different initial value determination data depending on the timing of system reset or the like, and illegal acts due to shooting or the like can be prevented.

  In this embodiment, the extension time of the security mode is one of a plurality of extension times that can be selected in advance corresponding to the bit value in the bit number [2-0] of the security time setting KSES. Although the time is not changed at each system reset, the extension time added to the fixed time is determined as one of a plurality of extension times at each system reset, for example, by setting in the user program stored in the ROM 506 You may make it do. In this case, the extension time is defined to be longer than the longest variable setting time. Then, after determining a rough extension time, a detailed extension time may be determined. As a result, the security time for entering the security mode at the time of power-on or system reset can be greatly changed for each system reset, and the operation start timing of the random number circuit 509 is updated or updated from the operation start timing of the slot machine 1. It becomes more difficult to specify numerical data.

  Further, the extension time of the security mode and the like may be determined using an ID number assigned to each chip constituting the main control unit 41. As an example, an extension time corresponding to the calculated value is executed by executing a part or all of an operation for performing a predetermined scramble process on the ID number and an operation such as addition / subtraction / multiplication / division using the ID number. May be set. In this case, the extension time may be randomly determined for each system reset, for example, by changing an arithmetic expression used for determining the extension time for each system reset. Furthermore, the count value of the free-run counter, the ID number, and the like are determined such that, for example, an arithmetic expression for determining the extension time using the ID number is determined corresponding to the count value of the free-run counter stored at the time of system reset. The extended time may be determined randomly at each system reset by using a combination of the above. In addition, when changing the start value of the random number generated by the random number circuit 509 at each system reset, the start value of the random number can be changed by using a combination of the count value of the free-run counter and the ID number. You may decide.

  In the present embodiment, the random number clock generation circuit 43 provided outside the main control unit 41 is used for random numbers having an oscillation frequency different from the oscillation frequency of the control clock CCLK generated by the control clock generation circuit 42. Although the clock RCLK is generated and supplied to the random number circuit 509, the clock signal supplied to the CPU 505 of the main control unit 41 and the clock signal supplied to the random number circuit 509 are common clock generation circuits. May be generated using an oscillation signal generated by one oscillator included in the. In this case, for example, a frequency divider for generating the random number clock RCLK and the control clock CCLK is provided, and the latch clocks RC0, RC1, RC2 and the control clock CCLK or the internal system clock SCLK are synchronized. What is necessary is just to set the frequency division ratio etc. in each frequency divider so that it may become difficult to produce. The control clock generation circuit 42 and the random number clock generation circuit 43 may be provided in whole or in part inside the main control unit 41 or outside the main control unit 41.

  In this embodiment, the random number circuit 509 receives the supply of the random number clock RCLK generated by the random number clock generation circuit 43, and generates the random number update clock RGK and the latch clock RC0 by the clock flip-flop 552. However, an oscillation signal serving as the random number update clock RGK or the latch clock RC0 may be generated outside the random number circuit 509, such as the random number clock generation circuit 43, for example. Alternatively, a circuit for generating the random number update clock RGK and a circuit for generating the latch clock RC0 may be separately provided in the random number circuit 509. As an example, while generating a random number update clock RGK by a flip-flop similar to the clock flip-flop 552, an inversion circuit for inverting the signal state of the random number update clock RGK is provided, and a signal output from the inversion circuit is latched. It may be used as the clock RC0.

  In the random number circuit 509 applied to the present embodiment, when the random number latch flag data RDFM0 is “1”, that is, when the numerical data is captured in the random value register R1D, a new numerical data capturing request is generated. Even in this case, new numerical data is not taken into the random value register R1D. In such a state, the numerical data in the random value register R1D is read and the random number latch flag data RDFM0 is cleared. It is impossible to load new numerical data into the random value register R1D.

  Therefore, as shown in FIG. 40, the game start signal SS1 is input by operating the start switch 7, the numerical data is latched and stored in the random value register R1D, and then the stored numerical data is read out. Until the numerical data of the random value storage work is updated, the random number latch flag data RDFM0 is in a state of “1”, so that the stored numerical data is held, and the game start signal SS1 is input during that time. However, since the new numerical data is not overwritten, the numerical data does not change even if noise is applied to the signal line of the game start signal SS1 due to static electricity or the like.

  Note that the configuration in which new numerical data is not captured in the random value register R1D while the numerical data is captured in the random value register R1D may be a configuration in which latching of the new numerical data is prohibited. In addition, although new numerical data is latched, writing to the random value register R1D may be prohibited.

  As described above, in the present embodiment, in a state in which numerical data is captured in the random value register R1D, a configuration is employed in which the stored numerical data is held until the stored numerical data is read. However, in this case, even when the operation of the start switch 7 is performed during a period in which the game is not effective, the latch is held and the numerical value data is held in the random number value register R1D. When the start switch 7 is operated with the above operation enabled, the internal lottery is performed based on numerical data latched at a timing different from the timing at which the start switch 7 was originally operated to start the game. A new problem will arise.

  On the other hand, in the present embodiment, the random number value is read out every four times (about 2.24 ms) in the timer interrupt process that is executed by interrupting the basic process every about 0.56 ms. It is checked whether or not numerical data is latched in the register R1D, that is, whether or not the random number latch flag is set. If the numerical data is latched in the random value register R1D, the numerical data in the random value register R1D Is read out. As a result, the random number latch flag is cleared, and new numerical data can be taken in. That is, at predetermined time intervals (about 2.24 ms), it is confirmed whether or not numerical data is latched in the random value register R1D, and if it is latched, the numerical data in the random value register R1D is read out, The state where the numerical data is held in the register R1D is released, and a new numerical data can be taken into the random value register R1D.

  For this reason, as shown in FIG. 41, the start switch 7 is operated in a state where the start of the game is not permitted, and numerical data is stored in the random value register R1D. Since the numerical data newly latched in the random value register R1D can be stored within about 2.24 ms, which is the execution interval of the random value reading process, the start switch 7 before the start of the game is permitted. Even if the numerical data latched by the operation is held in the random value register R1D, the numerical data newly latched can be obtained at the timing when the start switch 7 is operated after the start of the game is permitted.

  Further, in the random value reading process, when numerical data is latched in the random value register R1D, not only the numerical data is read, but also the value of the random value storage work in the RAM 507 is updated to the read numerical data. Each time new numerical data is latched in the random value register R1D, the latched numerical data is read in the subsequent random value reading process, and the numerical data stored in the random value storage work is newly latched. It is designed to be updated to numerical data.

  At the start of the game, instead of the numerical data stored in the random value register R1D, the numerical data stored in the random value storage work of the RAM 507 is acquired and the internal lottery is performed, so the numerical value is stored from the random value register R1D. After the data is read, even if the numerical data changes due to noise on the signal line of the start switch, it will not affect the numerical data of the random number storage work used for internal lottery. Even in such a case, the internal lottery can be performed using the numerical data latched at the timing when the start switch 7 is operated.

  In the present embodiment, the value of the random value register R1D is not retained when the power is interrupted, but the RAM 507 to which the random value storage work is assigned retains the stored data even when the power is interrupted. Therefore, even if the operation of the start switch 7 is detected and before the internal lottery starts, even if the value of the random value register R1D disappears due to a momentary power interruption or the like, the numerical data of the random number value storage work is maintained. Numerical data latched at the timing when the start switch 7 is operated can be used for the internal lottery.

  In the present embodiment, when the operation of the start switch 7 is detected, the numerical data stored in the random value storage work in the RAM 507 is set as the lottery work assigned to the RAM 507, and then the internal In the lottery, it is determined whether or not the winning combination has been won by performing an operation on the numerical data set in the lottery work, and the internal lottery is started from the time when the operation of the start switch 7 is detected. Even if the numerical data stored in the random number storage work is updated before the end, the numerical data acquired when the operation of the start switch 7 is detected may be changed before the internal lottery ends. However, when the operation of the start switch 7 is detected, the numerical data stored in the random value storage work of the RAM 507 is CP. Set 505 work register of, it may be a determination of whether the player wins a winning combination by performing subsequent operations on numerical data set in the work register in internal lottery.

  Further, it may be determined whether or not the winning combination has been won by performing an operation on the numerical data stored in the random value storage work. In this case, the operation of the start switch 7 is performed. The numerical data stored in the random number storage work is updated with the newly latched numerical data, for example, by prohibiting timer interrupt processing (main) during the period from the time of detection until the end of the internal lottery By preventing this from happening, it is possible to prevent the numerical data acquired when the operation of the start switch 7 is detected from being changed before the internal lottery is completed.

  Further, in this embodiment, when the detection signals of the switches are inputted at a rate of once every four times of the timer interrupt processing (main) and the states of the detection signals coincide with each other twice, that is, about 2. When the state of the 24 ms period detection signal is the same, the detection state of the corresponding switch is determined. For this reason, it takes about 2.24 ms to detect the operation of the start switch 7 (change from OFF to ON). However, if the random number reading process is shorter than this time, the start switch changes from OFF to ON. There is a possibility that the numerical data of the random number storage work is updated to the newly latched numerical data due to noise or the like between the time of the change and the detection. On the other hand, if the random number reading process is longer than this time, the numerical data latched at the timing of operating the start switch 7 may not be reflected in the numerical data of the random number storage work.

  On the other hand, the random number value reading process is also executed at a rate of once every four times of the timer interrupt process (main), and the minimum time required for updating the numerical data of the random number value storing work is about 2.24 ms. Yes, the numerical data of the random number storage work is not updated to the newly latched numerical data from when the start switch 7 is changed from OFF to ON, and the start switch 7 is operated. The numerical data latched at this timing can be reflected in the numerical data of the random value storage work.

  Further, in the present embodiment, as shown in FIG. 42, when the prescribed number of bets is set in a state where the prescribed number of bets is not set and the game start condition is satisfied, the random number value register R1D Whether or not the numerical data is latched, that is, whether or not the random number latch flag is set. If the numerical data is latched in the random value register R1D, the numerical data in the random value register R1D is dummy. Is read out. As a result, the random number latch flag is cleared, and new numerical data can be taken in.

  For this reason, the start switch 7 is operated before the specified number of bets is set, and the numerical data is stored in the random value register R1D. Even if this state is maintained, the specified number of bets is set. As soon as the game start condition is satisfied, the newly latched numerical data can be stored in the random value register R1D.

  In the present embodiment, a specified number of bets are set, and whether or not the random number latch flag is set when the game start condition is satisfied, that is, before the specified number of bets are set, it is latched. The numerical data stored in the random number register R1D is read out only when the random number latch flag is set. The numerical data stored in the random value register R1D may be read out uniformly when a predetermined number of bets are set and the game start condition is satisfied.

  In the present embodiment, as shown in FIG. 43, even if the start switch 7 is operated in a state where a prescribed number of bets satisfying the game start condition are set, the switches other than the start switch 7 are operated. In this state, the start of the game is prohibited. However, although a prescribed number of bets are set, a switch other than the start switch 7 is operated and the start of the game is stopped. In the prohibited state, when all the switches are turned off and the start of the game is permitted, whether or not numerical data is latched in the random value register R1D, that is, whether or not the random number latch flag is set. If the numerical data is latched in the random value register R1D, the numerical data in the random value register R1D is read as a dummy. Going on. As a result, the random number latch flag is cleared, and new numerical data can be taken in.

  For this reason, although a prescribed number of bets satisfying the game start condition are set, switches other than the start switch 7 are operated, and the start switch 7 is operated in a state where the game start is prohibited. Even if the numerical data is stored in the random value register R1D and the state is maintained, all the switches are turned off and the start of the game is permitted, and at the same time, the numerical data newly latched in the random value register R1D Can be stored.

  In the present embodiment, a prescribed number of bets satisfying the game start condition are set, but a switch other than the start switch 7 is operated and the game start is prohibited. Is whether the random number latch flag is set when all the switches are turned off and the start of the game is permitted, that is, the numerical data latched before the start of the game is permitted is stored in the random value register R1D. Only when the random number latch flag is set, the numerical data stored in the random number register R1D is read, but when the start of the game is permitted, it is uniform. Numerical data stored in the random value register R1D may be read.

  In the present embodiment, when the power is turned on, the control state of the main control unit 41 can be returned to the control state before the power interruption, and a predetermined number of bets satisfying the game start condition are set. In this embodiment, as shown in FIG. 44, in the present embodiment, when returning to the control state before the power interruption when the power is turned on, the time of return, that is, the start of the game is started. When it is permitted, it is confirmed whether or not the numerical data is latched in the random value register R1D, that is, whether or not the random number latch flag is set. If the numerical data is latched in the random value register R1D, The numerical data of the random number value register R1D is read out as a dummy. As a result, the random number latch flag is cleared, and new numerical data can be taken in.

  Therefore, as shown in FIG. 44, after the power is turned on, the reset signal is turned OFF and the main control unit 41 starts its operation, and then the start switch 7 is operated before returning to the control state before the power interruption. Even if the numerical data is stored in the random value register R1D and the state is maintained, the numerical value newly latched in the random value register R1D at the same time that the control state is restored and the start of the game is permitted. Data can be stored.

  Further, not only when the power is turned on, but also when the main control unit 41 is reset due to the occurrence of a reset factor and restarts, the process starts from the beginning of the startup process. When returning to the control state before resetting when the control unit 41 is restarted, whether or not numerical data is latched in the random value register R1D at the time of return, that is, when the start of the game is permitted. That is, whether or not the random number latch flag is set, and if the numerical data is latched in the random value register R1D, the random number latch flag is cleared by reading the numerical data in the random value register R1D as a dummy. Thus, new numerical data can be taken in.

  Therefore, after the main control unit 41 is restarted due to the occurrence of a reset factor, the start switch 7 is operated at a stage before returning to the control state before the reset, and the numerical data is stored in the random value register R1D. Even if is held, the control state is restored and the start of the game is permitted, and at the same time, the newly latched numerical data can be stored in the random value register R1D.

  In particular, when the detection signal from the start switch 7 is input with negative logic, when the voltage supply is unstable, such as during a momentary power failure, an ON (voltage LOW) signal of the start switch 7 is returned before recovery. Although it is highly likely that numerical data will be stored in the random number value register R1D, even in such a case, the control state is restored and the start of the game is permitted, and at the same time, a new value is stored in the random number value register R1D. Thus, it is possible to reliably prevent the numerical data stored in the random number register R1D stored before the return from being held.

  In this embodiment, when returning to the control state before power interruption or after resetting after power-on or reset, it is uniform regardless of whether the control state to be returned is a state where the game can be started or not. The numerical data stored in the random value register R1D is read out, but it is confirmed whether or not the return control state is a state where the game can be started, and the return control state can start the game. The numerical data stored in the random value register R1D may be read only when it is in the state.

  Also, whether or not the random number latch flag is set when the power is turned on or reset, and the control state before power interruption or reset is restored, that is, the numerical data latched before the start of the game is permitted is disturbed. Whether or not the data is stored in the numerical value register R1D is checked, and the numerical value data stored in the random number value register R1D is read only when the random number latch flag is set. Thereafter, the numerical data stored in the random number register R1D may be read out uniformly when the control state before power interruption or before resetting is restored. Furthermore, the numerical data stored in the random value register R1D may be read out uniformly regardless of whether the control state before power interruption or before reset is restored after power-on or reset.

  The main control unit 41 determines whether or not the start switch 7 is operated in a state where the game can be started, based on whether or not a rising edge indicating the rising of the start switch 7 is set.

  The rising edge of the start switch 7 is detected by the start switch 7 in the switch input determination process that is executed once every four times (about 2.24 ms). It is set on condition that the confirmed data based on the state has changed from OFF to ON. Since the deterministic data is data that is updated only when the previous detection state and the current state match each time the switch input determination process is performed, the rising edge of the start switch 7 indicates that the detection state of the start switch 7 is OFF. When the switch is in the state, it is set by detecting the ON of the start switch 7 twice in succession in the switch input determination process.

  On the other hand, since the execution interval of the switch input determination process is about 2.24 ms, the start switch 7 is provided on condition that the ON is continuously detected for at least about 2.24 ms after the start switch 7 is turned on. Rising edge is set, and the operation of the start switch 7 is detected.

  As described above, in the present embodiment, as shown in FIG. 45, on condition that the start switch 7 is continuously detected for a certain period (at least about 2.24 ms) in a state where the game can be started. The operation of the start switch 7 is detected and the game is started, and the game starts even though the start switch 7 is erroneously detected due to noise such as static electricity. Can be prevented.

  In the present embodiment, the operation of the start switch 7 is detected on the condition that the start switch 7 is continuously turned on for a certain period (at least about 2.24 ms) in a state where the game can be started. The game is started. For example, the start switch is confirmed on the condition that the detection state of the start switch 7 is confirmed a plurality of times in one switch input determination process and all of them are determined to be ON. The operation may be detected and the game may be started. Even in such a configuration, the game starts even though the start switch 7 is erroneously detected due to noise such as static electricity. Can be prevented.

  Next, various control contents executed by the sub CPU 91a of the sub control unit 91 will be described below based on the flowcharts of FIGS.

  When a reset signal is input from the reset circuit 95 to the sub control unit 91, the sub CPU 91a performs a startup process (sub) shown in FIG.

  In the startup process (sub), the built-in device, peripheral IC, interrupt mode, stack pointer, etc. are initialized (Sr1), and then access to the RAM 91c is permitted (Sr2). Then, the RAM parity of all the storage areas of the RAM 91c is calculated (Sr3), and it is determined whether or not the RAM parity is 0 (Sr4).

  If the data in the RAM 91c is normal, the RAM parity should be 0. If the RAM parity is 0 in the step Sr4, the data stored in the RAM 91c is normal, and the process proceeds to the step Sr5. Restore the control state before power interruption. In step Sr5, output control of the effect device is performed according to the restoring pattern A, not the control pattern set in the control pattern storage area, and then the process proceeds to step Sr9.

  If the RAM parity is not 0 in the step of Sr4, the data stored in the RAM 91c is not normal. Therefore, after initialization of the RAM 91c (Sr6), the pattern 0 is set in the control pattern storage area (Sr7), and the control is performed. After the output control of the effect device is performed according to the pattern B being restored, not the pattern 0 set in the pattern storage area, the process proceeds to step Sr9.

  In step Sr9, a recovery waiting flag indicating that a return command, an error command indicating RAM abnormality or random number circuit abnormality or a setting start command is waiting to be received is set in the RAM 91c, and interruption is permitted (Sr10). .

  After that, in the timer interrupt process (sub), it is determined whether a return command, an error command indicating a RAM error or a random number circuit error, or a setting start command is received, and a recovery waiting flag is cleared, a return command, a RAM error Alternatively, it waits until the recovery waiting time elapses without receiving any error command or setting start command indicating a random circuit error (Sr11, Sr12), and it is determined that the recovery waiting flag is not set in the step of Sr11. In other words, if any of a return command, an error command indicating a RAM error or a random number circuit error, or a setting start command is received, the process proceeds to a loop process.

  If it is determined in step Sr12 that the recovery waiting time has passed without receiving any of the return command, the error command indicating the RAM abnormality or the random number circuit abnormality, or the setting start command, the game control board 40 is operated normally. It shifts to a connection error notification state for notifying that it is not connected.

  Next, timer interrupt processing (sub) that is periodically executed by the sub CPU 91a at intervals of 1.12 ms will be described based on the flowchart of FIG.

  As shown in FIG. 47, in the timer interrupt process (sub), first, a power interruption interrupt is prohibited (Ss1), and whether a command is stored in the reception buffer, that is, a command is received from the main CPU 41a. It is determined whether or not (Ss2). If no command is stored in the reception buffer in step Ss2, it is determined whether or not a recovery waiting flag is set (Ss3). If a recovery waiting flag is not set, the process proceeds to step Ss43 to recover. If the wait flag is set, the process proceeds to step Ss47.

  If a command is stored in the reception buffer in the step of Ss2, the command is acquired from the reception buffer (Ss4), it is determined whether or not the recovery waiting flag is set (Ss5), and the recovery waiting flag is set. If not, the process proceeds to step Ss19.

  If the recovery wait flag is set in step Ss5, it is determined whether or not the acquired command is a return command (Ss6). If it is not a return command, the process proceeds to step Ss9. Is cleared (Ss7), and a detection state storage area to be described later and an operation history flag, a time lapse flag, a continuous operation counter, and a detection history made up of an operation time counter to be described later are initialized (Ss8), and the process proceeds to step Ss40.

  In step Ss9, it is determined whether or not the acquired command is a setting start command. If it is not a setting start command, the process proceeds to step Ss14. If the command is a setting start command, the recovery waiting flag is cleared (Ss10), and the RAM 91c. (Ss11), an administrator mode indicating that the administrator mode is controlled is set in the RAM 91c (Ss12), and an administrator mode screen (to be described later) is displayed in the control pattern storage area. A pattern is set (Ss13), and the process proceeds to step Ss40.

  In step Ss14, it is determined whether or not the acquired command is an error command indicating a RAM abnormality or a random circuit abnormality error. If it is not an error command indicating a RAM abnormality or a random circuit abnormality error, it is stored in the reception buffer. Of the commands, the command acquired this time is cleared (Ss18), and the process proceeds to step Ss47.

  If the command acquired in step Ss14 is an error command indicating a RAM error or random circuit error, the recovery waiting flag is cleared (Ss15), the RAM 91c is initialized (Ss16), and an error pattern is stored in the control pattern storage area. Set (Ss17), and proceed to step Ss40.

  In step Ss19, it is determined whether the acquired command is a gaming state command. If it is not a gaming state command, the process proceeds to step Ss24. If it is a gaming state command, the gaming state of the next game specified from the gaming state command is determined. Is set in the RAM 91c (Ss20), and it is determined whether or not the administrator mode is set (Ss21).

  If the administrator mode is not set in step Ss21, the process proceeds to step Ss40. If the administrator mode is set, pattern 0 is set in the control pattern storage area (Ss22), and the administrator mode is cleared. (Ss23), go to step Ss40.

  In step Ss24, it is determined whether or not the acquired command is a confirmation start command. If it is not a confirmation start command, the process proceeds to step Ss28. If it is a confirmation start command, the control pattern set in the control pattern storage area is determined. Save (Ss25), set the manager mode in the RAM 91c (Ss26), set the manager pattern in the control pattern storage area (Ss27), and proceed to step Ss40.

  In step Ss28, it is determined whether or not the acquired command is an error command indicating the occurrence of an error. If it is not an error command indicating the occurrence of an error, the process proceeds to step Ss31, and if it is an error command indicating the occurrence of an error, The control pattern set in the control pattern storage area is saved (Ss29), an error pattern is set in the control pattern storage area (Ss30), and the process proceeds to step Ss40.

  In step Ss31, it is determined whether or not the acquired command is an error command indicating error cancellation. If the command is an error command indicating error cancellation, the process proceeds to step Ss34, and if it is not an error command indicating error cancellation, It is determined whether the acquired command is a confirmation end command (Ss32). If the command acquired in step Ss32 is not a confirmation end command, the process proceeds to step Ss35, and if it is a confirmation end command, the administrator mode is cleared (Ss33), and the process proceeds to step Ss34. In step Ss34, the saved control pattern is returned to the control pattern storage area, and the process proceeds to step Ss40.

  In the step of Ss35, it is determined whether or not the acquired command is an internal winning command, and if it is not an internal winning command, the process proceeds to the step of Ss37, and if it is an internal winning command, the effect table stored in the ROM 91b is referred to. An effect pattern is selected at a selection rate according to the result of the internal lottery indicated by the internal winning command, and the selected effect pattern is an effect pattern of the game or an effect pattern (for example, 5 games) from the game (continuous effect) The effect pattern selection process set in the RAM 91c as the pattern) is executed (Ss36), and the process proceeds to the step Ss39.

  In step Ss37, it is determined whether or not the acquired command is an operation detection command. If it is not an operation detection command, the process proceeds to step Ss39. If it is an operation detection command, operation detection processing 1 for updating the detection state of the operation switch is performed. Is executed (Ss38), and the process proceeds to step Ss42.

  In step Ss39, the control pattern table stored in the ROM 91b is referred to, the effect pattern set in the RAM 91c and the control pattern registered corresponding to the acquired command are read out, and the control pattern in the control pattern storage area is read out. Is executed, and the process proceeds to step Ss40.

  In step Ss40, it is determined whether or not the control pattern set in the control pattern storage area matches the output state of the rendering device, and the control pattern set in the control pattern storage region and the output state of the rendering device are determined. If they match, the process proceeds to step Ss42. If they do not match, output control of the effect device is performed according to the control pattern set in the control pattern storage area (Ss41), and the process proceeds to step Ss42.

  In the step of Ss42, the command acquired this time among the commands stored in the reception buffer is cleared, and the process proceeds to the step of Ss43. In step Ss43, the operation detection process 2 for monitoring whether or not the operation switch has been operated for a predetermined time is executed, and the process proceeds to step Ss44.

  In step Ss44, it is determined whether or not the administrator mode is set. If the administrator mode is not set, an operation effect process for performing an operation effect according to the detection state of the operation switch is executed (Ss45). ), And proceeds to step Ss47. If the administrator mode is set in the step of Ss44, an administrator mode process for controlling access to the management information according to the detection state of the operation switch is executed (Ss46), and the process proceeds to the step of Ss47.

  In step Ss47, after updating the values of various counters, the interruption interrupt prohibited in step Ss1 is permitted (Ss48), and the timer interruption process (sub) is terminated.

  FIG. 50 is a flowchart showing the control contents of the operation detection process 1 executed in the timer interrupt process (sub) described above by the sub CPU 91a.

  In the operation detection processing 1, the operation detection command indicates the detection state of each operation switch in the detection state storage area in which the change state (previous detection state and current detection state) of the operation switch is stored for each operation switch. Update according to the detection state (Ss201).

  Next, with reference to the updated detection state storage area, it is determined whether or not the detection state of any of the operation switches has changed from OFF to ON (Ss202). If there is no operation switch that has changed from OFF to ON, Ss206 If there is an operation switch that has changed from OFF to ON, the operation detection flag storage area (rising or falling) indicating that the operation state of the operation switch has changed is stored for each operation switch. Further, a rising flag is set corresponding to the operation switch changed from OFF to ON (Ss203), and a continuous operation counter that counts the number of continuous operations for each operation switch is updated (Ss204). Specifically, the counter values corresponding to those other than the operation switch that has changed from OFF to ON are cleared, and the counter value that corresponds to the operation switch that has changed from OFF to ON is added once.

  Next, the value of the counter corresponding to the operation switch that has changed from OFF to ON among the operation time counters for measuring the time during which each operation switch is continuously operated is initialized (set to 0) (Ss205). , The process proceeds to step Ss206.

  In step Ss206, the updated detection state storage area is referenced to determine whether the detection state of any operation switch has changed from ON to OFF. If there is no operation switch that has changed from ON to OFF, Returning to the flowchart of FIG. 48, if there is an operation switch changed from ON to OFF, a falling flag is set in the operation detection flag storage area corresponding to the operation switch changed from ON to OFF (Ss207). Returning to the flowchart of FIG.

  FIG. 51 is a flowchart showing the control content of the operation detection process 2 executed by the sub CPU 91a in the timer interrupt process (sub) described above.

  In the operation detection process 2, it is determined whether or not there is an operation switch whose current state is ON by referring to the detection state storage area (Ss301). If there is no operation switch whose current state is ON, FIG. Return to the flowchart.

  If there is an operation switch whose current state is ON in step Ss301, the value of the operation time counter of the operation switch whose current state is ON is referred to, and whether or not 10 seconds have passed since the operation switch was turned on. (Ss302), if 10 seconds have not elapsed, the process proceeds to step Ss304, and if 10 seconds have elapsed, a 10-second elapsed flag is set (Ss303), and the process proceeds to step Ss304.

  In step Ss304, the value of the operation time counter of the operation switch whose current state is ON is referred to, and it is determined whether or not 5 seconds have elapsed since the operation switch was turned ON. The process proceeds to step Ss306, and if 5 seconds have elapsed, a 5-second elapsed flag is set (Ss305), and the process proceeds to step Ss306.

  In step Ss306, the value of the operation time counter of the operation switch whose current state is ON is referred to, and it is determined whether or not 3 seconds have elapsed since the operation switch was turned ON. 48, if 3 seconds have passed, a 3 second elapsed flag is set (Ss307), and the flow returns to the flowchart shown in FIG.

  FIG. 52 is a flowchart showing the control contents of the power interruption interrupt process (sub) executed when the sub CPU 91a receives a voltage drop signal from the power interruption detection circuit 98.

  In the power interruption interruption process (sub), first, interruption is prohibited (St1). That is, other interrupt processes are prohibited from being executed at the start of the power interruption interrupt process (sub). Next, all registers that may be in use are saved in the stack area (St2).

  Next, the detection data of the voltage drop signal is acquired from the input port, and it is determined whether or not the voltage drop signal is input (St3). At this time, if the voltage drop signal is not input, the register saved in the stack area at St2 is restored (St4), the interrupt prohibited in the step of St1 is permitted (St5), and the process before the interrupt is performed. Return.

  If a voltage drop signal is input in step St3, all output ports are initialized (St6). Next, the RAM parity adjustment data is calculated and set so that the exclusive OR of all the storage areas of the RAM 91c becomes 0 (St7), and access to the RAM 91c is prohibited (St8).

  Then, except for the determination of whether or not the voltage drop signal is input (St9, where St9 is the same processing as St3), the processing enters a loop process in which no processing is performed. That is, when the voltage decreases as it is, the operation is stopped internally. Therefore, the sub CPU 91a reliably stops operation when power is interrupted. Further, in this loop processing, when the voltage recovers and the voltage drop signal is not input, the above-described activation processing (sub) is executed, and when the RAM parity becomes 0, the original processing is restored. .

  In the present embodiment, after prohibiting access to the RAM 41c, the output state of the voltage drop signal is monitored, and when the voltage drop signal is not input, it is determined whether the voltage is restored, and the startup process (sub) However, no processing is performed in the loop processing, and the voltage is recovered while the loop processing is being performed. Based on the fact that the reset signal is input from the reset circuit 95, You may make it transfer to a starting process (sub).

  The slot machine 1 of the present embodiment includes a single BET switch 5, a MAXBET switch 6, a start switch 7, and stop switches 8L, 8C, and 8R as operation switches for the main CPU 41a to control the progress of the game. Of these operation switches, the start switch 7 is also used for a setting value confirming operation in the setting change state.

  The operation of these switches is not always related to the progress control of the game in all control states constituting from the end of the game to the end of the next game, but is related to the progress control of the game according to the control state. Sometimes it may not be involved.

  As shown in FIG. 53, in the control state from the end of the game (after changing the setting) to the start of the game, the operation of the single BET switch 5, the MAXBET switch 6, and the start switch 7 is involved in the progress control of the game and is stopped. The operation of the switches 8L, 8C, 8R is not involved in the game progress control. Furthermore, even in the control state from the end of the game (after setting change) to the start of the game, the bet number has not reached the specified number, that is, the bet number can be further added, and the game start condition is In a state where it is not established, the operation of the single BET switch 5 and the MAXBET switch 6 is involved in the game progress control, but the operation of the start switch 7 is not involved in the game progress control, while the bet number is defined. In the state where the number has been reached, that is, in the state where the bet number cannot be added and the game start condition is satisfied, the operation of the start switch 7 is involved in the game progress control. 5. The operation of the MAXBET switch 6 is not related to the progress control of the game.

  In the control state from the start of the game to the end of the game, the operation of the stop switches 8L, 8C, 8R is involved in the game progress control, and the operation of the single BET switch 5, the MAXBET switch 6, and the start switch 7 Not involved in progress control. Furthermore, even in the control state from the start of the game to the end of the game, if all the reels are rotating, all the operations of the stop switches 8L, 8C, 8R are involved in the progress control of the game. In the stop state, only the stop switch corresponding to the rotating reel among the stop switches 8L, 8C, and 8R is involved in the progress control of the game, and the stop switch corresponding to the stopped reel is the game switch. Not involved in progress control.

  The control state is not limited to the control state from the end of the game (after changing the setting) to the start of the game, the control state from the start of the game to the end of the game, and from the end of the game (after changing the setting) to the start of the game. Among the control states, the number of bets has not reached the specified number, that is, a state in which the number of bets can be further added, and the control condition in which the game start condition is not satisfied, the number of bets has reached the specified number. State, that is, a state in which the number of bets cannot be added and a game start condition is satisfied, a control state in which all reels are rotating among control states from the start of the game to the end of the game, only the left reel Stopped control state, control state where only the middle reel is stopped, control state where only the right reel is stopped, control state where the left and middle reels are stopped, left and right reels are stopped Control status, right, control state middle reel is stopped, the wait period state, applicable also for each of the states of the payout period medal. Furthermore, even if the operation of the single BET switch 5 or the MAX BET switch 6 is not involved in the progress control of the game in the control state from the end of the game (after the setting change) to the start of the game, the specified number of bets has already been obtained. The control state in which the operation of the single BET switch 5 or the MAXBET switch 6 is not involved in the progress control of the game and the specified number of bets has not been set yet, but no credit remains. In other words, it can be said that the control state is different from the control state in which the operation of the single BET switch 5 or the MAXBET switch 6 is not related to the progress control of the game.

  In the setting change state, the operation of the start switch 7 is involved in the setting value change control, and the operation of the single BET switch 5, the MAXBET switch 6, and the stop switches 8L, 8C, 8R is not involved in the game progress control. Even in the setting change state, the operation of the start switch 7 is involved in the change control of the set value before the set value is determined. However, after the set value is determined, all the operation switches Not involved in change control. Further, in the setting confirmation state, any operation of the single BET switch 5, the MAXBET switch 6, the start switch 7, the stop switches 8L, 8C, and 8R is not involved in the game progress control.

  The main CPU 41a detects these operation switches in a switch input determination process (see FIG. 36) executed during a timer interrupt process (main) executed by interrupting at regular time intervals. In the switch input determination processing, the detection state of the operation switch is monitored, and when any operation switch changes from OFF to ON, edge data (rising edge) indicating that the corresponding operation switch has changed from OFF to ON Is set, and edge data (falling edge) indicating that the corresponding operation switch has changed from ON to OFF is set.

  Then, the main CPU 41a determines whether or not the operation switch has been operated based on whether or not the rising edge of the operation switch related to the progress control of the game is set in accordance with the current control state in the game process. If it is determined and the operation switch is determined to be operated, all edge data is cleared, the game progress control according to the operation switch operation is executed, and a command associated with the game progress control is executed. (BET command, internal winning command, reel stop command, etc.) are set in the normal command transmission buffer.

  When the main CPU 41a determines that the rising edge of the stop switch corresponding to the reel being rotated is set in the reel rotation processing, the main CPU 41a determines whether the detection state of the other operation switches is ON, If it is determined that the detection state of the operation switch is ON, that is, if an operation of a stop switch corresponding to a rotating reel is detected while another operation switch is being operated, the stop operation is valid. Therefore, the corresponding reel stop control is not performed.

  This is because, when two or more operations are detected among the stop switches 8L, 8C, and 8R, if priority is given to the stop control based on one of the operations, the other stop control is delayed, and the stop mode of the reel This is because there is a possibility that a problem such as unnaturalness may occur, and even if the operation of the stop switch corresponding to the rotating reel is detected while the other operation switches are operated as described above, Since the stop control of the reel to be performed is not performed, the stop control of the other reel is not delayed by the stop control of the one reel.

  Further, when the main CPU 41a determines that the rising edge of the stop switch corresponding to the reel being rotated is set in the reel rotation process, the detection state of the other operation switches is not limited to the other stop switches. If it is determined whether or not the detection state of any of the other operation switches is ON, the effective stop operation is not performed and the corresponding reel stop control is not performed. Without extracting only the detection state of the stop switch from the detection state of the operation switch, for example, when ON is set to 1 and OFF is set to 0, the sum of the detection states of all the operation switches is calculated and 2 or more If so, it is possible to collectively determine the detection states of all the operation switches, such as determining that the other operation switches are in the detection state.

  When the main CPU 41a determines that the rising edge of the start switch 7 for determining the set value is set at a stage where the set value has not yet been determined in the setting change state, the other operation switch It is determined whether or not the detection state is ON, and if it is determined that the detection state of any of the other operation switches is ON, control for confirming the set value is not performed.

  This is because, as will be described later, the operation switch used by the main CPU 41a for controlling the progress of the game is diverted as the operation means in the manager mode controlled on the sub CPU 91a side in the setting change state. When the set value is not yet finalized as in the case where the start switch 7 for finalizing the set value is operated while the other operation switches are being operated, the final control of the set value is not performed. Even if the start switch 7 is mistakenly operated simultaneously with the operation of the administrator mode, the setting value is not fixed and the setting value is not set, so that the administrator does not expect it. The setting value is not finalized, and the troublesomeness of having to turn off the power again and change to the setting state from the beginning can be reduced. It has become.

  The main CPU 41a executes a command transmission process (see FIG. 37) for transmitting a command to the sub CPU 91a during the timer interrupt process (main). In the command transmission process, it is determined whether or not a command is stored in the normal command transmission buffer, that is, whether or not a command associated with game progress control is stored, and the command is stored in the normal command transmission buffer. If it is determined that the game is in progress, the command associated with the progress control of the game stored in the normal command transmission buffer is transmitted to the sub CPU 91a.

  In the command transmission process, it is determined whether or not the operation detection command is transmitted. If the operation detection command is transmitted, the single BET switch 5 is used regardless of whether or not the detection state of the operation switch is changed. , MAXBET switch 6, start switch 7, stop switch 8L, 8C, 8R acquisition data indicating the detection state, and based on the acquired determination data, single BET switch 5, MAXBET switch 6, start switch 7, stop An operation detection command capable of specifying the ON / OFF state of each of the switches 8L, 8C, and 8R is created, set in the specific command transmission buffer, and immediately transmitted to the sub CPU 91a. Whether or not it is time to transmit the operation detection command is determined by referring to the value of the transmission counter assigned to the RAM 41c. The transmission counter is decremented by 1 each time the command transmission process is executed, and when the value becomes 0, it is specified that the operation detection command is transmitted. In the embodiment, 5) is set. For this reason, in the present embodiment, the operation detection command is transmitted to the sub CPU 91a once every time the command transmission process is executed five times based on the determined data at that time.

  As described above, the command transmission process is executed once every time the timer interrupt process (main) is executed four times. Therefore, the operation detection command is executed every time the timer interrupt process (main) is executed 20 times. Since the execution interval of the timer interrupt process (main) is about 0.56 ms, the main CPU 41a transmits to the sub CPU 91a once every about 11.2 ms.

  In the present embodiment, the operation detection command is generated by acquiring the fixed data of the single BET switch 5, the MAXBET switch 6, the start switch 7, the stop switches 8L, 8C, and 8R. The detected input data of the single BET switch 5, the MAXBET switch 6, the start switch 7, and the stop switches 8L, 8C, and 8R may be acquired to create an operation detection command.

  Thus, in this embodiment, the main CPU 41a sends an operation detection command that can specify that the single BET switch 5, the MAXBET switch 6, the start switch 7, and the stop switches 8L, 8C, and 8R to the sub CPU 91a. By transmitting to the sub CPU 91a, it is possible to specify that the operation switch detected by the main CPU 41a is operated regardless of whether or not the sub CPU 91a is an operation switch related to game progress control in each control state. Thus, it is possible to produce an effect in response to an operation of an operation switch not involved in the progress control of the game.

  In addition, the main CPU 41a performs the single-sheet BET switch 5, the MAXBET switch 6, the MAXBET switch 6, the start switch 7, the stop switches 8L, 8C, and 8R, regardless of whether any one of them is operated. By periodically transmitting operation detection commands that can specify the ON / OFF states of the start switch 7 and stop switches 8L, 8C, and 8R, the sub CPU 91a periodically determines the ON / OFF states of these operation switches. Even when the sub CPU 91a misses the operation detection command, it is possible to specify the latest detection state for all the operation switches based on the operation detection command transmitted next time. , According to the operation of the operation switch not involved in the game progress control It is possible to reliably execute the production.

  Further, since it is possible to specify the detection state of all the single BET switch 5, MAXBET switch 6, start switch 7, stop switches 8L, 8C, and 8R from the operation detection command, a plurality of switches are provided on the sub CPU 91a side. It is possible to produce effects that reflect the operation status of a plurality of operation switches, such as simultaneous operation of a single switch or operation of only a specific switch, and various effects using operation of the operation switches can be made.

  In addition, the operation detection command is not transmitted every time a timer interrupt process (main) executed by the main CPU 41a at regular intervals is executed, but the timer interrupt process (main) is performed a predetermined number of times ( In this embodiment, since it is transmitted every time it is executed, it is possible to prevent the load on the main CPU 41a from being extremely increased by the transmission of the operation detection command.

  In the present embodiment, the main CPU 41a operates as a single BET switch regardless of whether one of the single BET switch 5, the MAX BET switch 6, the start switch 7, and the stop switches 8L, 8C, and 8R is operated. 5. The configuration is such that an operation detection command that can specify the ON / OFF state of each of the MAXBET switch 6, the start switch 7, the stop switch 8L, 8C, and 8R is transmitted at regular intervals. Only when the state (ON / OFF) changes, an operation detection command indicating that may be transmitted. With such a configuration, transmission of the operation detection command can be reduced as much as possible. In addition to reducing the control load related to the transmission of the operation detection command, the sub CPU 91a side is more than necessary. It requires the operation detection command without receiving.

  Further, when the detection state (ON / OFF) of any operation switch changes, an operation detection command that can specify the detection state of another operation switch in addition to the detection state of the operation switch is sent to the sub CPU 91a. The configuration may be such that the transmission of the operation detection command can be reduced as much as possible, and the sub CPU 91a detects the detection state of the operation switch whose detection state has changed from the operation detection command. In addition, the detection state of other operation means can be specified, and the sub CPU 91a can produce effects reflecting the operation status of the plurality of operation means, and various effects using operation of the operation switches can be performed. Can be anything.

  When the operation detection command is transmitted in the command transmission process, the main CPU 41a does not transmit the command in the normal command transmission buffer even if an untransmitted command remains in the normal command transmission buffer, and the normal command transmission buffer. An untransmitted command set to is transmitted in the next command transmission process. That is, when the operation detection command transmission time comes when the untransmitted command is set in the normal command transmission buffer, priority is given to the transmission of the operation detection command.

  Even if the command in the normal command transmission buffer is not transmitted in a certain command transmission process, it will be transmitted in the next command transmission process, so the timing of the production will not be greatly delayed. Since it is transmitted every time the command transmission process is executed five times, if the operation detection command is not transmitted in the command transmission process when the operation detection command has been transmitted, the state of the previous operation switch detection state Although the interval until the difference is specified becomes longer than the transmission interval of the original operation detection command, there is a possibility that the timing of the production will be greatly delayed, but in this embodiment, as described above, Operations that do not participate in game progress control because sending operation detection commands has priority over unsent commands in the command send buffer It is possible to suppress delays in production due to the operation of the switch as much as possible, and even when commands are continuously transmitted from the main CPU 41a to the sub CPU 91a, the command transmission processing is always executed after the command transmission processing is executed. Since commands are transmitted one by one with an interval until execution, the sub CPU 91a can reliably receive the commands.

  In addition, the command accompanying the game progress control is temporarily set in the normal command transmission buffer in the game processing and transmitted in the subsequent command transmission processing, whereas the operation detection command is stored in the normal command transmission buffer. Is not set, and it is set and transmitted in a specific command transmission buffer different from that, and it is transmitted at regular intervals based on the transmission timing of commands that are irregularly transmitted based on game progress control Even if the transmission timing of the operation detection command to be performed overlaps, the transmission control of these commands is not complicated. In particular, as in the present embodiment, when the transmission timing of the command transmitted irregularly based on the progress control of the game and the transmission timing of the operation detection command transmitted at regular intervals overlap, In giving priority to one of the commands, it is possible to give priority to transmission of one command only by performing control for designating the address of one of the command transmission buffers. Furthermore, like a normal command transmission buffer, a plurality of commands can be stored, and even though a configuration (so-called queue) for transmitting the first stored command is adopted, it is stored later. If you try to prioritize the stored operation detection command, it is necessary to change the transmission order, which makes transmission control extremely complicated. However, store the operation detection command in the normal command transmission buffer. Such a problem does not occur by adopting a configuration for transmitting without transmitting.

  In this embodiment, the command transmission process is configured to give priority to the transmission of the operation detection command over the untransmitted command in the normal command transmission buffer. It is determined whether or not an untransmitted command is set in the normal command transmission buffer before the determination, and if an untransmitted command remains in the normal command transmission buffer, it is stored in the normal command transmission buffer. A configuration in which a set command is transmitted and an operation detection command is not transmitted in the same command transmission processing, that is, a configuration in which transmission of an untransmitted command in the normal command transmission buffer is given priority over an operation detection command may be used. By doing so, the effect according to the progress control of the game changes the detection state of the operation switch. Operation detecting commands sent regardless of whether the absence, i.e., that whether effect is performed is delayed by the transmission of commands indicating an indeterminate state can be prevented.

  In addition, when an untransmitted command is set in the normal command transmission buffer at the transmission timing of the operation detection command, a configuration may be adopted in which both commands are transmitted in the same command transmission process. In this case, it is possible to prevent the timing of the effects from being delayed for both the effects according to the game progress control and the effects associated with the operation of the operation switch not involved in the game progress control.

  Further, as shown in FIG. 54, the main CPU 41a executes a start-up process when the reset signal is turned OFF and starts up, and an interrupt is permitted at the end of the start-up process. Thereafter, a timer interrupt process (main ) At regular intervals. If the main CPU 41a can return to the state before the power interruption, as shown in FIG. 54A, a return command is transmitted to the sub CPU 91a before the interruption is permitted in the startup process. Also, if the main CPU 41a cannot return to the state before the power interruption due to an abnormality in the data stored in the RAM 41c, an error command indicating an abnormality in the RAM or random number circuit is given to the sub CPU 91a before interruption is permitted in the startup process. Send to.

  Further, when the setting key switch 37 is in the ON state and the RAM 41c is initialized and does not return to the state before the power interruption, as shown in FIG. A setting start command is transmitted to the sub CPU 91a before. Of the commands transmitted in the activation process, the return command specifies that the main CPU 41a returns to the state before the power interruption. The error command indicating the RAM abnormality or the random number circuit abnormality and the setting start command indicate the main CPU 41a. Will not be restored to the state before power interruption.

  As described above, the operation detection command is transmitted in the timer interruption process (main), and the interruption process is not permitted until the end of the activation process. Therefore, after the main CPU 41a is activated, the main CPU 41a is not disconnected. An error command indicating that the main CPU 41a is not restored to the state before power interruption or an error command indicating a random circuit error or a setting start command is transmitted. Later, transmission of the operation detection command is permitted.

  As described above, the main CPU 41a does not transmit the operation detection command to the sub CPU 91a until the return command, the error command indicating the RAM abnormality or the random number circuit abnormality, or the setting start command is transmitted to the sub CPU 91a after the power is turned on. Therefore, for example, the sub CPU 91a does not perform an effect in response to an operation specified from the operation detection command in spite of a state where it is not determined whether or not the main CPU 41a is to be restored. It is possible to prevent an effect that is inconsistent with the state of the main CPU 41a from being executed.

  In addition, the main CPU 41a transmits a return command, an error command indicating a RAM abnormality or a random number circuit abnormality, and a setting start command to the sub CPU 91a in the startup process, and then permits an interrupt to perform a timer interrupt process (main ) And the operation detection command is transmitted in the command transmission process, and the return command, the error command indicating the RAM abnormality or the random circuit error, and the setting start command are already transmitted in the command transmission process. In the command transmission process, the return command, the error command indicating the RAM abnormality or the random number circuit abnormality, and the setting start command can be transmitted before the operation detection command.

  In the present embodiment, a return command, an error command indicating a RAM abnormality or a random circuit error, and a setting start command are transmitted to the sub CPU 91a in the startup process, and an operation detection command is transmitted in the command transmission process. However, in the startup process, any one of a return command, an error command indicating a RAM error or random circuit error, or a setting start command is set in the specific command transmission buffer, and after the interrupt is permitted, It is determined whether any of a return command, an error command indicating a RAM error or a random number circuit error, or a setting start command is set in the specific command transmission buffer, and an error command indicating a RAM error or a random number circuit error or a setting start If any of the commands are set The operation detection command may be transmitted on the condition that neither the error command indicating the RAM abnormality or the random number circuit abnormality nor the setting start command is set, which is transmitted to the sub CPU 91a with the highest priority. Even in such a configuration, the return command, the error command indicating the RAM abnormality or the random circuit abnormality, and the setting start command can be transmitted prior to the operation detection command.

  In addition, any one of a return command, an error command indicating a RAM error or a random number circuit error, or a setting start command is set in the normal command transmission buffer in the startup process, and a return command, a RAM error or a random circuit error is set in the command transmission process. Until the error command or setting start command is sent, the operation detection command is prohibited from being sent, and the return command, RAM error or random circuit error command, or setting start command is sent. The operation detection command may be permitted to be transmitted on the condition that the operation detection command is transmitted from the subsequent command transmission process. Even in such a configuration, the return command or the RAM error is detected before the operation detection command. Or error command indicating random circuit error, start setting It is possible to send a command.

  Further, the main CPU 41a is prohibited from interrupting during the timer interrupt process (main), and even if a voltage drop signal is input during that time, the main CPU 41a is interrupted until the timer interrupt process (main) ends. The process (main) is not executed, and the power interruption interrupt process (main) is executed after the timer interrupt process (main) is completed.

  Multiple commands can be stored in the normal command transmission buffer, and the power interruption interrupt processing (main) is executed even when untransmitted commands are stored in the normal command transmission buffer. In the case of returning to the state before the power interruption at the time of subsequent activation, the normal command transmission buffer is restored with an untransmitted command remaining.

  On the other hand, when the operation detection command is the operation detection command transmission time in the command transmission process, the operation detection command is created and transmitted in the command transmission process. And since the command transmission process is executed in the timer interrupt process (main), there is no operation detection command that has not been transmitted at the time of power interruption. It does not return with the transmission operation detection command remaining.

  As described above, in the present embodiment, when the main CPU 41a is restored to the state before the power interruption when the main CPU 41a is started up, if the untransmitted command is stored in the normal command transmission buffer before the power interruption, these Unsent commands stored in the normal command transmission buffer will also be restored, but the operation detection command will not be sent before power interruption, and will not be sent before power interruption. The detected operation detection command is not returned, and an operation detection command that does not reflect the detection state of the operation switch after the return is not transmitted. For this reason, after the power is turned on, it is possible to prevent an effect corresponding to an operation not related to the progress control of the game from being executed even though the operation switch is not operated at all.

  In the present embodiment, as described above, the operation detection command is transmitted without being stored in the normal command transmission buffer in which a command corresponding to the progress control of the game is set. It is possible to prevent the control from becoming complicated when only the command corresponding to the progress control is restored and the operation detection command is not restored.

  In the present embodiment, when the operation detection command is the operation detection command transmission time in the command transmission process, the operation detection command is created and transmitted within the command transmission process, and the timer interrupt process During the execution of (Main), the power interruption interrupt processing is prohibited, so that the operation detection command is not sent before the power interruption. The detection command does not return, but if an unsent operation detection command remains at the time of startup, clearing the unsent operation detection command will result in an operation that has not been sent before the power interruption. The detection command may not be returned. In this case, the command transmission buffer data in which the operation detection command is stored is configured such that the command corresponding to the progress control of the game and the operation detection command are stored in different command transmission buffers. By clearing only the operation detection command, it becomes possible to clear the operation detection command, and there is no need to change the transmission order of the commands stored in the normal command transmission buffer.

  In this embodiment, every time the command transmission process is executed five times in the timer interrupt process (main), that is, the command transmission process is executed in the timer interrupt 2 executed every four times of the timer interrupt process (main). Therefore, an operation detection command is transmitted every 20 timer interruption processes (main). For this reason, it is possible to specify the timing at which the main CPU 41a is activated (the timing at which the reset signal is turned off) and the timing at which the interrupt is permitted from the number of times the operation detection command is transmitted and the operation detection command transmission interval. When the random number counter included in the main CPU 41a is initialized at startup and updated every subsequent timer interrupt process (main), or after initialization at startup and updated at regular intervals (clock signal input, etc.) In addition, if the timing at which the main CPU 41a is activated or the timing at which the interrupt is permitted is specified, the current random number counter value may be specified, and the specified random number counter value may be used for fraud. If the value of the random number counter is related to the game, there is a risk that a significantly unfair result will be obtained.

  On the other hand, in this embodiment, when the main CPU 41a returns to the state before power interruption at the time of startup, the value of the transmission counter before power interruption is also restored, and the value of the transmission counter before power interruption is restored. From the start, when the command transmission process is counted, and when the value of the transmission counter becomes 0, that is, when the command transmission process executed after executing the command transmission process before power interruption reaches 5 times, The first operation detection command is transmitted, and thereafter, the operation detection command is transmitted every five command transmission processes. As shown in FIG. 54A, interrupts are permitted after the main CPU 41a is activated. Later, the number of command transmission processes executed until the first operation detection command is transmitted is not constant, and from the time when the main CPU 41a is started until the first operation detection command is transmitted. Since the required time (t1) is not constant, the timing at which the main CPU 41a is activated (the timing at which the reset signal is turned off) and the interrupt are permitted based on the number of transmissions of the operation detection command and the transmission interval of the operation detection command. It becomes difficult to specify the timing, and it is possible to prevent fraud associated with specifying the timing when the main CPU 41a is activated and the timing when the interrupt is permitted.

  In addition, when the main CPU 41a initializes the RAM 41c at the time of activation, the value of the transmission counter before power interruption is also initialized. In this case, any value from the range of 0 to 3 is set. A value is selected at random, a value obtained by adding 1 to the selected value is set in the transmission counter, and the number of times of command transmission processing is counted from the value, and when the value of the transmission counter becomes 0, that is, 1 at startup When the command transmission process of the number of times randomly selected from ~ 4 is executed, the first operation detection command is transmitted after startup, and thereafter, the operation detection command is transmitted every five command transmission processes. Even in this case, as shown in FIG. 54 (b), after the activation of the main CPU 41a, after the interrupt is permitted, it is executed until the first operation detection command is transmitted. The number of command transmission processes is not constant, and the time (t1 ′) required from when the main CPU 41a is started until the first operation detection command is transmitted is not constant. From the transmission interval, it becomes difficult to specify the timing at which the main CPU 41a is activated (the timing when the reset signal is turned off) and the timing at which the interrupt is permitted. It is possible to prevent fraud that accompanies identification of the timing made.

  In this embodiment, when the main CPU 41a is activated, when returning to the state before power interruption, the transmission timing of the operation detection command is counted from the value of the transmission counter before power interruption, and the RAM 41c is initialized. In this case, the time required from when the main CPU 41a is activated until the first operation detection command is transmitted does not become constant by randomly selecting the value of the transmission counter and counting the transmission timing of the operation detection command. However, in any case, it is necessary until the first operation detection command is transmitted from the activation of the main CPU 41a by randomly selecting the value of the transmission counter and counting the transmission timing of the operation detection command. It is good also as a structure where time does not become fixed.

  Further, each time the main CPU 41a is activated, a different value is set as the initial value of the transmission counter. For example, 2 and 4 are alternately set at each activation, or the initial value of the transmission counter is set to 1, 2, By setting the initial value of the transmission counter according to a predetermined rule, such as setting in the order of 3, 4, 5, etc., the time required from when the main CPU 41a is activated until the first operation detection command is transmitted is constant. It is good also as composition which does not become.

  In the RAM 91c of the sub-control unit 91, a detection state storage area in which the change state of the detection state of the operation switch is stored for each operation switch, and an operation detection flag indicating that the operation state of the operation switch has changed are provided for each operation switch. An operation detection flag storage area to be stored is allocated. Furthermore, the detection state storage area is assigned with a detection state before receiving the operation detection command (previous) and a detection state after receiving the operation detection command (this time). The detection state of each operation switch before and after reception is stored.

  The sub CPU 91a performs the operation detection process 1 when it is determined in the timer interrupt process (sub) that an unprocessed command is stored in the reception buffer. In the operation detection process 1, it is determined whether or not an unprocessed command is an operation detection command. If it is determined that the command is an operation detection command, the current detection state stored in the detection state storage area is changed to the previous detection state. , The detection state of each operation switch indicated by the operation detection command is stored as the current detection state, and when there is an operation switch in which the previous detection state and the current detection state are different, the state has changed from OFF to ON. In this case, a rising flag is set as an operation detection flag corresponding to the operation switch, and when it is changed from ON to OFF, a falling flag is set as an operation detection flag corresponding to the operation switch.

  As described above, in the present embodiment, the main CPU 41a periodically transmits an operation detection command that can specify the detection states of all the operation switches regardless of whether or not the detection state of the operation switches has changed. When the sub CPU 91a receives the operation detection command, the sub CPU 91a updates the detection state of each operation switch before and after receiving the operation detection command stored in the detection state storage area. An operation detection flag corresponding to the operation switch is set, and the sub CPU 91a confirms the presence or absence of the operation detection flag, thereby receiving the operation detection command in addition to the fact that the detection state of the operation switch has changed. How the detection state of each operation switch has changed before and after, that is, whether it has changed from OFF to ON, from ON to OF It has become the one, to be able to determine the changes to.

  For this reason, the sub CPU 91a can perform an effect or change the effect according to not only the timing when the operation of the operation switch is started but also the timing when the operation is released, and is not involved in the progress control of the game. Various effects can be performed according to the operation mode of the operation switch.

  In the present embodiment, the sub CPU 91a can determine how the detection state of each operation switch before and after receiving the operation detection command has changed in addition to the change in the detection state of the operation switch. However, the sub CPU 91a may be configured to be able to determine only that the operation switch has been operated, that is, changed from OFF to ON. With such a configuration, an operation that does not affect the progress control of the game. It is possible to reduce the control load on the sub CPU 91a due to the operation of the switch.

  The detection state storage area stores the detection state of each operation switch, and the sub CPU 91a is set with any operation detection flag, and the change in the detection state of the operation switch corresponding to the operation detection flag is changed. When it is identified, it is possible to identify not only the operation switch whose detection state has changed but also the detection state of other operation switches by checking the detection state of other operation switches in the detection state storage area. .

  For this reason, it is possible to specify a state in which a plurality of operation switches are operated at the same time, and for example, it is possible to produce an effect by operating a plurality of operation switches at the same time, such as an operation effect of pattern 1 or pattern 3 Thus, various effects can be performed depending on how the plurality of operation switches are operated.

  Further, the sub CPU 91a detects the left stop switch when performing the effect by simultaneously operating the operation switches of the left stop switch and the middle stop switch as in the operation effect of the pattern 1 (see FIG. 61 described later). If the middle stop switch operation is detected when the right stop switch is not detected, the stage change effect is performed, but both the left stop switch and the right stop switch are detected. When the operation of the middle stop switch is detected, the operation of the left stop switch and the middle stop switch is detected at the same time as above, but in this case, the stage change effect is not performed. It has become.

  That is, when performing a specific operation effect according to the operation of a specific operation switch, if an operation switch other than the specific operation switch is operated together with the specific operation switch, the specific operation effect is not performed. ing.

  For this reason, a specific operation effect based on an operation of a specific operation switch is performed when the specific operation switch is operated simultaneously with another operation switch or when the other operation switch is operated. Since it is not executed and a specific operation effect is not executed by an erroneous operation, the specific operation effect can be executed only for a player who desires the specific operation effect.

  In addition, when an operation switch other than the specific operation switch is operated together with the specific operation switch as described above, for example, pattern 1 and pattern 3 (see FIG. 61 described later) are not performed by performing a specific operation effect. Even when a part of the operation switches for executing each effect overlaps like the operation effect of (), different effects can be executed. That is, the operation effect of pattern 1 is executed by operating the left stop switch and the middle stop switch simultaneously, and the operation effect of pattern 2 is executed by operating the middle stop switch and the right stop switch simultaneously. When the middle stop switch is operated while the left stop switch and right stop switch are operated at the same time, the left stop switch and middle stop switch are operated simultaneously, or the middle stop switch and right stop switch are operated simultaneously. However, it is not possible to determine whether or not it is possible to assign an effect only to one of the simultaneous operations, but an operation switch other than the specific operation switch is operated together with the specific operation switch. If a specific operation effect is not performed, Even 1 and the case, such as the operation effect of the pattern 2, can be assigned an effect for each of the simultaneous operation as it can be performed more diverse effect by way of the operation of a plurality of operation switches.

  When the detection state of any one of the operation switches is changed from OFF to ON in the operation detection process 1, that is, when the operation of the operation switch is started, the sub CPU 91a corresponds to the corresponding operation among the operation time counters assigned to the RAM 91c. Initializes the switch operation time counter value. The value of the operation time counter is incremented every time the timer interrupt process (sub) is executed, and the elapsed time since the operation switch operation started by referring to the value of the operation time counter Time can be determined.

  The sub CPU 91a executes the operation detection process 2 every time the timer interrupt process (sub) is executed. In the operation detection process 2, it is determined for each operation switch whether or not the current detection state stored in the detection state storage area is ON. If it is ON, that is, if the operation of the operation switch is continued. Refers to the value of the operation time counter of the corresponding operation switch, and if a predetermined time has elapsed, sets a time elapse flag indicating that to the operation switch. In this embodiment, a 3 second elapsed flag, a 5 second elapsed flag, and a 10 second elapsed flag are set as a time elapsed flag when 3 seconds have elapsed, 5 seconds have elapsed, and 10 seconds have elapsed.

  For this reason, the sub CPU 91a can perform an effect upon confirming whether the time lapse flag is set or not when a certain time elapses when the operation switch is continuously operated.

  In the present embodiment, the sub CPU 91a counts the time that has elapsed since the detection state of the operation switch has not changed from ON to OFF after the detection state of the operation switch has changed from OFF to ON. It becomes possible to grasp the continuous operation time of the operation switch on the sub CPU 91a side, and without having a timer for measuring the continuous operation time for each individual switch on the main CPU 41a side, the operation switch can be changed only by changing the program of the sub CPU 91a. It is possible to detect the continuous operation time, but after the operation switch operation has changed from OFF to ON on the main CPU 41a side, the time elapsed without changing from ON to OFF is counted, and this time is specified. By sending a command indicating that the operation switch has been operated continuously for a specified time when the time is reached, In Bed CPU91a side may be able to identify that the operation of the operation switch is operated continuously.

  In addition, when the detection state of any of the operation switches is changed from OFF to ON in the operation detection process 1, that is, when the operation of the operation switch is started, the sub CPU 91a corresponds to the continuous operation counter assigned to the RAM 91c. 1 is added to the value of the continuous operation counter of the operation switch to be operated. The value of the continuous operation counter is cleared by a command from the sub CPU 91a when the detection state of another operation switch changes from OFF to ON or at the start of production, etc. Refer to the value of the continuous operation counter It is possible to determine the number of times that a specific operation switch has been operated continuously from the starting point. Then, the sub CPU 91a can confirm the value of the continuous operation counter, and can produce an effect when the number of continuous operations of the operation switch from a certain starting point has reached the specified number.

  In the present embodiment, the sub CPU 91a counts the number of times that the detection state of the operation switch has changed from OFF to ON, whereby the sub CPU 91a can grasp the number of operation switch continuous operations, and the main CPU 41a. It is possible to detect the number of operation switches by simply changing the program of the sub CPU 91a without having a counter for counting the number of continuous operations for each individual switch on the side. By counting the number of times the operation has changed from OFF to ON, and transmitting the command indicating that the operation switch has been operated the specified number of times when this number reaches the specified number of times, the operation of the operation switch is performed on the sub CPU 91a side. May be specified to have been operated a specified number of times.

  A control pattern storage area in which a control pattern is set is assigned to the RAM 91c of the sub control unit 91, and when the sub CPU 91a receives a command from the main control unit 41, the sub CPU 91a controls the control pattern according to the command. While setting in the pattern storage area, the output state of the rendering device is controlled with reference to the control pattern set in the control pattern storage area.

  For example, as shown in FIG. 55A, when the sub CPU 91a receives a command a corresponding to the progress control of the game, the pattern a corresponding to the command a is set in the control pattern storage area, and at the same time, the effect device To an output state based on the pattern a. As a result, an image based on the pattern a is displayed on the liquid crystal display 51, sound effects based on the pattern a are output from the speakers 53 and 54, and the effect effect LED 52 and the reel LED 55 are turned on based on the pattern a. Thereafter, when a command b corresponding to the progress control of the game is received, the control pattern in the control pattern storage area is updated to the pattern b corresponding to the command b, and when the control pattern in the control pattern storage area is changed, At the same time, the rendering device is controlled to the output state based on the changed pattern b. As a result, the image based on the pattern a displayed on the liquid crystal display 51 is updated to the image based on the pattern b, sound effects based on the pattern b are output from the speakers 53 and 54, and the effect effect LED 52 and the reel LED 55 are displayed on the pattern b. It becomes a lighting mode based on. Further, as shown in FIG. 55B, when the corresponding control pattern receives the same command c as the command a, the control pattern in the control pattern storage area is updated to the pattern a corresponding to the command c. The control pattern of the area itself does not change. In this case, the state is maintained without switching the output state of the effect device.

  Further, the sub CPU 91a is activated before the main CPU 41a when the power is turned on, and if the data in the RAM 91c is normal at the time of activation, the sub CPU 91a is always transmitted when the main CPU 41a is activated as shown in FIG. The control state of the sub CPU 91a is returned to the control state before the power interruption without receiving any of the command, the error command indicating the RAM abnormality or the random circuit error, or the setting start command. Until receiving either an error command indicating an error or a setting start command, output control according to the control pattern set in the control pattern storage area is not performed, and a recovery pattern informing that recovery processing is in progress Output control according to A is performed. As a result, a restoring image indicating that the restoration process is in progress is displayed on the liquid crystal display 51, and the effect effect LED 52 is turned off. Note that there is no output of sound effects from the speakers 53 and 54, and the reel LED 55 is also turned off.

  After that, when a return command is received, output control is performed according to the control pattern set in the control pattern storage area, and at this time, the output state of the rendering device is set from the recovering pattern A to the control pattern storage area The output state is switched according to the control pattern being set. As a result, the restoring image displayed on the liquid crystal display 51 is updated to an image based on the control pattern set in the control pattern storage area, and the control pattern set in the control pattern storage area is changed from the speakers 53 and 54. Based on the sound effect, the effect LED 52 and the reel LED 55 are turned on based on the control pattern set in the control pattern storage area.

  When a return command is received, an operation history consisting of the detection state of the operation switch set in the detection state storage area, the operation detection flag, the operation time counter value, the time elapsed flag, and the continuous operation counter value The detection state and operation history of the operation switch based on the operation detection flag received before the power interruption are not restored even when a return command is received.

  Further, if the data in the RAM 91c is not normal at the time of activation, the sub CPU 91a, as shown in FIG. 57, always returns a return command when the main CPU 41a is activated, an error command or setting indicating a RAM abnormality or a random number circuit abnormality. Even if any of the start commands is not received, the RAM 91c is initialized and the corresponding pattern 0 (normal screen display etc.) is set in the control pattern storage area after initialization, but the return command, RAM error or random circuit error Until receiving either the error command shown or the setting start command, output control according to the pattern 0 set in the control pattern storage area is not performed, and the recovery pattern B for informing that recovery processing is in progress is performed. Output control is performed accordingly. As a result, the restoration-in-progress image same as the restoration-in-progress pattern A is displayed on the liquid crystal display 51. Note that, as in the recovery pattern A, no sound effect is output from the speakers 53 and 54, and the reel LED 55 is also turned off.

  After that, when a return command is received, output control is performed according to the pattern 0 set in the control pattern storage area, and at this time, the output state of the rendering device is set from the recovering pattern B to the control pattern storage area The output state is switched according to the pattern 0. As a result, the restoring image displayed on the liquid crystal display 51 is updated to the normal screen based on the control pattern 0, no sound effect is output from the speakers 53 and 54, and the effect effect LED 52 and the reel LED 55 are turned off. Become.

  Further, when the data in the RAM 91c is not normal, the recovery state when the data in the RAM 91c is normal as an output state until receiving any one of a return command, an error command indicating a RAM error or a random number circuit error, or a setting start command is received. With the middle pattern A, output control is performed according to the restoring pattern B having a different output mode. In the present embodiment, the restoring image is displayed on the liquid crystal display 51 for both the restoring patterns A and B, no sound effect is output from the speakers 53 and 54, and the reel LED 55 is turned off. In the middle pattern A, the effect LED is turned off, while in the pattern B being restored, the effect LED is blinked.

  In addition, an operation history including an operation switch detection state set in the detection state storage area with the initialization of the RAM 91c, an operation detection flag, an operation time counter value, a time elapsed flag, and a continuous operation counter value is also initialized. It becomes.

  Further, when the sub CPU 91a receives the setting start command after the data in the RAM 91c is normal at the time of activation and the control state is returned to the control state before the power interruption, as shown in FIG. When the RAM 91c is initialized, an administrator pattern for enabling access to management information described later is set in the control pattern storage area, and the control pattern in the control pattern storage area is changed to the administrator pattern, the production is almost simultaneously performed. The device is controlled to an output state corresponding to the manager pattern, and the output state of the rendering device is switched from the restoration pattern A to the output state based on the manager pattern. As a result, the restoration-in-progress image displayed on the liquid crystal display 51 is updated to the manager mode screen, a warning sound is output from the speakers 53 and 54, and the effect effect LED 52 and the reel LED 55 are in a blinking state.

  In addition, an operation history including an operation switch detection state set in the detection state storage area with the initialization of the RAM 91c, an operation detection flag, an operation time counter value, a time elapsed flag, and a continuous operation counter value is also initialized. It becomes.

  In addition, when the data in the RAM 91c is not normal and the RAM 91c is initialized and a setting start command is received, the pattern 0 set in the control pattern storage area is updated to the administrator pattern, and the control pattern storage area When the pattern 0 is changed to the manager pattern, the rendering device is controlled to the output state corresponding to the manager pattern almost simultaneously with this, and the output state of the rendering device is changed from the recovering pattern B to the manager pattern. Switch to based output state.

  In addition, an operation history including an operation switch detection state set in the detection state storage area with the initialization of the RAM 91c, an operation detection flag, an operation time counter value, a time elapsed flag, and a continuous operation counter value is also initialized. It becomes.

  In addition, when the sub CPU 91a receives the error command indicating the RAM abnormality or the random number circuit abnormality after the data of the RAM 91c is normal at the time of activation and the control state is returned to the control state before the power interruption, As shown in FIG. 59, when the RAM 91c is initialized, an error pattern is set in the control pattern storage area, and the control pattern storage area is changed to the error pattern, the rendering device is output in accordance with the error pattern almost simultaneously with this. And the output state of the rendering device is switched from the recovering pattern A to the output state based on the error pattern. As a result, the in-restoration image displayed on the liquid crystal display 51 is updated to an error notification image, a warning sound is output from the speakers 53 and 54, and the effect effect LED 52 and the reel LED 55 are in a blinking state.

  In addition, an operation history including an operation switch detection state set in the detection state storage area with the initialization of the RAM 91c, an operation detection flag, an operation time counter value, a time elapsed flag, and a continuous operation counter value is also initialized. It becomes.

  In addition, when the RAM 91c data is not normal but the RAM 91c is initialized and an error command indicating RAM abnormality or random number circuit abnormality is received, the pattern 0 set in the control pattern storage area is updated to an error pattern. When pattern 0 in the control pattern storage area is changed to an error pattern, the rendering device is controlled to an output state corresponding to the error pattern almost simultaneously with this, and the output state of the rendering device is based on the error pattern from the recovering pattern B Switch to output state.

  In addition, an operation history including an operation switch detection state set in the detection state storage area with the initialization of the RAM 91c, an operation detection flag, an operation time counter value, a time elapsed flag, and a continuous operation counter value is also initialized. It becomes.

  Further, the sub CPU 91a, when activated, restores the control state to the control state before power interruption after the data in the RAM 91c is normal, and then returns a command, an error command indicating a RAM abnormality or a random number circuit abnormality, or a setting start command. If the return waiting time elapses without receiving any of the above, the control pattern before power interruption set in the control pattern storage area is saved as shown in FIG. Update the connection error pattern to notify the connection error, and when the control pattern before power interruption in the control pattern storage area is changed to the connection error pattern, the production device is controlled to the output state of the connection error notification almost simultaneously with this, The output state of the effect device is switched from the recovering pattern A to the connection error notification output state. As a result, the restoration-in-progress image displayed on the liquid crystal display 51 is updated to the connection error notification screen, a warning sound is output from the speakers 53 and 54, and the effect effect LED 52 and the reel LED 55 are blinked.

  When the return waiting time has elapsed, an operation consisting of the detection state of the operation switch set in the detection state storage area, the operation detection flag, the operation time counter value, the time elapse flag, and the continuous operation counter value Initialize history.

  In this embodiment, even if the connection error state is entered, the RAM 91c is not cleared, and the control pattern before power interruption set in the control pattern storage area is also saved. If the data in the RAM 91c is normal when the power is turned off and then turned on again after the transition to the state and the sub CPU 91a is restarted, the data is held in the RAM 91c when a return command is received from the main CPU 41a. Based on the data, the control state of the sub CPU 91a and the output state of the rendering device are restored. When the return waiting time has elapsed, an operation consisting of the detection state of the operation switch set in the detection state storage area, the operation detection flag, the operation time counter value, the time elapse flag, and the continuous operation counter value. Since the history is initialized, it does not return.

  In addition, when the data in the RAM 91c is not normal, and after the RAM 91c is initialized, neither a return command, an error command indicating a RAM error or a random number circuit error, or a setting start command has been received, and the return waiting time has elapsed. When the pattern 0 set in the control pattern storage area is updated to the connection error pattern, and the pattern 0 in the control pattern storage area is changed to the connection error pattern, the directing device outputs the connection error notification almost simultaneously with this. And the output state of the rendering device is switched from the recovering pattern B to the connection error notification output state.

  As described above, when the data in the RAM 91c is normal at the time of activation, the sub CPU 91a returns the control state to the control state before the power interruption, but the output state by the effect device until the return command is received from the main CPU 41a. Is not restored, and the output state is also restored when the return command is received, and only the output state by the rendering device may be restored without the main CPU 41a returning to the state before the power interruption. In addition, the control state on the main CPU 41a side when the power is turned on and the output state by the effect device can be matched.

  Further, the sub CPU 91a returns the control state to the control state before the power interruption when the data in the RAM 91c is normal at the time of activation, but the main CPU 41a receives an error command or setting start command indicating a RAM abnormality or a random number circuit abnormality. In other words, when the main CPU 41a side does not return to the state before the power interruption, the RAM 91c is initialized. Even when only the sub CPU 91a side can be restored when the power is turned on, the main CPU 41a And the control state of the sub CPU 91a can be matched.

  Further, the sub CPU 91a determines whether or not the data in the RAM 91c is normal at the time of activation. If not normal, the sub CPU 91a does not wait for reception of a return command, an error command indicating a RAM error or a random number circuit error, or a setting start command. The RAM 91c is initialized, the pattern 0 is set in the control pattern storage area, and then when the return command is received, the output control of the effect device is performed in the output state corresponding to the pattern 0, and the sub CPU 91a Even when the control state before power interruption cannot be restored based on the data in the RAM 91c, when the return command is received from the main CPU 41a, the output of the effect device does not stop and the control pattern is initialized. Accordingly, the output control of the rendering device can be started.

  In addition, the sub CPU 91a produces an effect according to the recovery pattern indicating that the recovery process is in progress until it receives any of the return command, the error command indicating the RAM abnormality or the random circuit error, or the setting start command after the activation. The output of the device is controlled, and even after the power is turned on, even in a state before the output of the rendering device according to the control pattern set in the control pattern storage area starts, what state the sub CPU 91a is currently in Can be easily confirmed from the outside.

  In particular, in the present embodiment, the sub CPU 91a waits for reception of any one of a return command, an error command indicating a RAM abnormality or a random number circuit abnormality, or a setting start command in a state where the sub CPU 91a has returned to the control state before the power interruption. In this case, the output control of the rendering device is performed according to the pattern A being restored, while the sub CPU 91a initializes the RAM 91c, and the error command or setting indicating a return command, a RAM error, or a random circuit error. When waiting for reception of any of the start commands, the output control of the rendering device is performed according to the recovering pattern B having a different output mode from the recovering pattern A. Whether the sub CPU 91a has returned to the control state before the power interruption from the output mode of the rendering device in the output state of the RAM 91 There whether been initialized, it can be confirmed from the outside.

  Further, after the activation, the sub CPU 91a does not receive any of the return command, the error command indicating the RAM abnormality or the random number circuit abnormality, or the setting start command, and if the return waiting time has elapsed, the connection error notification is executed. Thus, it is possible to specify that the connection with the game control board 40 is poor.

  Further, even if the connection error notification is executed, the RAM 91c is not initialized, and when the power is turned on again, it is possible to return to the original control state by receiving a return command from the main CPU 41a. Yes.

  Further, the sub CPU 91a returns the control state to the control state before the power interruption when the data in the RAM 91c is normal at the time of activation, but receives the return information from the main CPU 41a and also returns the output state of the effect device. The operation history consisting of the operation switch detection status set in the detection status storage area, operation detection flag, operation time counter value, time elapsed flag, and continuous operation counter value is initialized. The operation switch detection state and operation history based on the received operation detection flag are not restored, and the operation switch does not participate in the game progress control even though the operation switch is not operated after the power is turned on. It is possible to prevent the performance according to the operation from being executed. For this reason, an effect in which an effect result is not notified by an intervention operation that satisfies the effect condition, such as a continuous operation effect that will be described later, will be produced only when an intervention operation that satisfies the effect condition is performed even after the power is turned on. Because it will not be notified, the value of the production accompanying the player's intervention operation can be increased, and the production conditions are not determined across power interruptions, so operations that satisfy the production conditions are easy to understand It becomes.

  In addition, when the sub CPU 91a receives the return command from the main CPU 41a when the data in the RAM 91c is normal at the time of activation and the control state is returned to the control state before the power interruption, that is, the control state of the main CPU 41a is also returned. The operation switch detection state and operation history are initialized when it is determined that the state on the sub CPU 91a side including the output state of the effect device is restored before the power interruption, and the main CPU 41a side is disconnected. Although all of the data in the RAM 91c is initialized without returning to the previous state, only the operation switch detection state and the operation history are not initialized unnecessarily. The operation switch detection state and operation history are initialized before all the states including the output state are restored. That the detection state and operation history switch will initiate Produce without being initialized can be reliably prevented.

  Further, the sub CPU 91a is configured to initialize the operation switch detection state and operation history at the time of activation, and is stored in the RAM 91c including the operation switch detection state and operation history at the time of power interruption. Since all the data is stored, it is not necessary to select data to be backed up in the process at the time of power interruption, and the process at the time of power interruption can be quickly terminated.

  In the present embodiment, the sub CPU 91a operates when the data in the RAM 91c is normal at the time of activation, and when the control state is returned to the control state before power interruption, when the return command is received from the main CPU 41a. However, when the data in the RAM 91c is normal at the time of startup, the detection state of the operation switch and the operation history are uniformly initialized without waiting for a return command to be received. In such a configuration, the detection state of the operation switch and the operation history are surely initialized at the previous stage regardless of whether or not the output state of the rendering device is restored. Therefore, it is possible to reliably prevent the production from starting without initializing the detection state or operation history of these operation switches. Further, when a configuration is adopted in which the operation switch detection state and the operation history are uniformly initialized without waiting for the reception of the return command, the return command is transmitted when the main CPU 41a returns to the control state before the power interruption. It is good also as a structure which does not.

  In the present embodiment, all data stored in the RAM 91c is backed up when the power is cut off, and the main CPU 91a initializes the detection state of the operation switches and the operation history when the main CPU 91a is activated. The detection status and operation history of the operation switch are not restored, but the detection status and operation history of the operation switch before power failure are not restored by not backing up the detection status and operation history of the operation switch at the time of power interruption. Also good.

  In the present embodiment, the sub CPU 91a executes an operation effect according to the operation switch operation not related to the progress control of the game according to the control state of the main CPU 41a, that is, according to the detection state of the operation switch specified from the operation detection command. .

  FIG. 61 shows an example of the operation effect. The pattern 1 shown in FIG. 61 is a pattern for executing a stage change effect for changing any stage from a plurality of types of effect stages with different types such as the background of the liquid crystal display 51 and the appearing character. In the control state from the end of the game (after setting change) to the start of the game, when the left and middle stop switches 8L, 8C among the stop switches 8L, 8C, 8R are operated simultaneously, that is, the operation switch indicated by the operation detection command Is detected when either of the detection states of the stop switches 8L and 8C is OFF, the detection states of the stop switches 8L and 8C are both ON, and the detection state of the stop switch 8R is changed to OFF. .

  Pattern 2 is a pattern for selecting and determining an effect pattern presented corresponding to each stop switch in the stage change effect, and is a control state from the end of the game (after setting change) to the start of the game, and When any stop switch is operated while the stage change effect is being executed, that is, when the detection state of the operation switch indicated by the operation detection command is the detection state of any stop switch is OFF This is executed when the detection state of the switch changes to ON and the detection state of other stop switches changes to OFF.

  Pattern 3 is a pattern for executing stage information browsing effects such as game history and effect information. Among the stop switches 8L, 8C, and 8R in the control state from the end of the game (after setting change) to the start of the game. When the right stop switches 8C and 8R are operated at the same time, that is, when the detection state of the operation switch indicated by the operation detection command is one of the detection states of the stop switches 8C and 8R is OFF, the stop switches 8C and 8R This is executed when both of the detection states of are changed to ON and the detection state of the stop switch 8L is changed to OFF.

  Pattern 4 is a pattern for outputting sound effects, which is a control state from the end of the game (after setting change) to the start of the game, and any stop switch is operated in a state where the stage change effect is not executed. In other words, when the detection state of the operation switch indicated by the operation detection command is one in which the detection state of one of the stop switches is OFF, the detection state of the stop switch is ON, and the stop switch changes to another stop switch. It is executed with a probability of 100.

  Pattern 5 is a pattern that suggests the possibility of winning a special role, and finally executes a special role selection suggesting effect that informs whether or not a special role has been won, from the start of the game to the end of the game When the MAXBET switch 6 is continuously operated 10 times after performing the effect of instructing the continuous operation of the MAXBET switch 6 in the control state, that is, the detection state of the operation switch indicated by the operation detection command is the detection state of the MAXBET switch 6. Is executed when the value of ON changes alternately ON and OFF 10 times.

  The pattern 6 is a pattern for executing the special role winning suggestion effect as in the case of the pattern 5. After performing the effect instructing the long press of the MAXBET switch 6 in the control state from the start of the game to the end of the game, the MAXBET switch 6 Is continuously operated for 3 seconds, that is, the operation switch detection state indicated by the operation detection command is OFF after the MAXBET switch 6 detection state is OFF and the MAXBET switch 6 detection state is changed to ON. It is executed when 3 seconds elapse without changing.

  The operation effect shown in FIG. 61 is an example of an effect that is executed when an operation not involved in the progress control of the game is performed, and other effects may be applied.

  Next, the special role winning suggestion effect (hereinafter referred to as a continuous operation effect) of the pattern 5 among the operation effects described above will be described.

  The continuous operation effect is executed when a corresponding effect pattern is selected in an effect pattern selection process executed when an internal winning command associated with the start of the game is received.

  In the effect pattern selection process, when the fact that the special role is won is specified from the internal winning command, the effect pattern of the continuous operation effect is higher than when the fact that the special role is not won is specified. Therefore, the expectation for winning the special role can be enhanced only by executing the continuous operation effect.

  In the continuous operation effect, first, an instruction effect instructing that the MAXBET switch 6 is operated 10 times within 5 seconds simultaneously with the start of the game is started. If the MAXBET switch 6 is not operated until the game ends (until all reels stop) after the instruction effect starts, the instruction effect ends at the end of the game. In this case, whether or not the special role is won is not notified following the instruction production.

  Thereafter, when a new game is started (when an internal winning command is received), if the special game has been won by the previous game, the special game will be announced. The notice of winning the special role will continue until these special roles are won (the same applies to notices made under other conditions as shown below).

  If the special role is not won by the previous game, the notification related to the instruction production in the previous game is not performed when a new game is started. However, if the special role is won in the newly started game, the instruction effect for the new continuous operation effect can be started again.

  On the other hand, when the MAXBET switch 6 is first operated by the player before the game is over, the timer for the time limit timer assigned to the RAM 91c is started. The MAXBET switch 6 is not operated up to 10 times (including the operation when the time measurement is started) and all reels are stopped until the time measured by the timer for time limit reaches 5 seconds. In this case, the instruction effect ends at the end of the game, as in the case where the MAXBET switch 6 is not operated at all.

  In this case as well, the presence / absence of the special role will not be announced following the instruction production, and if the special role has been won by the previous game when the new game is started, The winning of the role is announced. If the special role is not won by the previous game, the notification related to the instruction production in the previous game is not performed when a new game is started.

  Further, although all the reels did not stop before the time measured by the timer started by the first operation of the MAXBET switch 6 became 5 seconds, the time measured by the time limit timer becomes 5 seconds. If the MAXBET switch 6 has not been operated up to 10 times before, the instruction effect ends when the time counted by the time limit timer reaches 5 seconds. In this case, regardless of whether or not the special role is won, following the instruction production, it is notified that none of the special roles has been won (losing). This notice of losing ends when the game ends because all reels have stopped.

  Thereafter, if a special role is won by the previous game when a new game is started, the special role is announced. If the special role is not won by the previous game, the notification related to the instruction production in the previous game is not performed when a new game is started.

  If the MAXBET switch 6 is operated 10 times without stopping all the reels until the time measured by the timer started by the first operation of the MAXBET switch 6 reaches 5 seconds, the MAXBET switch 6 When the number of operations reaches 10 times, the instruction effect ends. In this case, if the special role is won, the special effect will be announced following the instruction effect, and if neither is selected, the loss will be notified following the instruction effect.

  Hereinafter, the continuous operation effect will be described based on a specific example. 62A to 62D are timing charts showing the relationship between the progress of the game and the execution mode of the continuous operation effect.

  In the example of FIG. 62A, it is assumed that the special combination is won when the game 1 is started by the player operating the start switch 7. When the continuous operation effect is executed in such a situation, the instruction effect is started from the timing at which the game is started.

  Next, when the player first operates the MAXBET switch 6 at an arbitrary timing until the game 1 is finished (that is, until all reels are stopped), time measurement by the time limit timer is started. The player repeats the operation of the MAXBET switch 6, and before all reels stop, and before the time counted by the time limit timer reaches 5 seconds, the MAXBET switch 6 It is assumed that the number of operations reaches 10 times including the first operation.

  Then, at this time, the instruction effect ends, and it is notified that the special role is won in the game 1 following the instruction effect that has ended. Note that even when the game 2 is started, the bonus winning announcement is continued until the winning special role is won.

  In the example of FIG. 62 (b), it is assumed that no special combination is won when the game 1 is started by the player operating the start lever 11. Even when the continuous operation effect is executed in such a situation, the instruction effect is started from the timing at which the game is started.

  Next, when the player first operates the MAXBET switch 6 at an arbitrary timing until the game 1 is finished (that is, until all reels are stopped), time measurement by the time limit timer is started. The player repeats the operation of the MAXBET switch 6, and before all reels stop, and before the time counted by the time limit timer reaches 5 seconds, the MAXBET switch 6 It is assumed that the number of operations reaches 10 times including the first operation.

  Then, at this time, the instruction effect ends, and it is notified that the special role is not won in the game 1 following the instruction effect that has ended. This loss notification is terminated when the game 1 is completed, but since no special role is won in the game 1, no notification is given when the next game 2 is started.

  In the example of FIG. 62 (c), as in the example of FIG. 62 (a), the continuous operation effect is executed when the special role is won, but the time counted by the time limit posting timer is used. All reels did not stop before reaching 5 seconds, but when the time counted by the time limit posting timer reached 5 seconds, the number of operations of the MAXBET switch 6 included the first operation. And less than 10 times.

  In this case, when the time counted by the time limit posting timer reaches 5 seconds, the instruction effect ends, and it is announced that the special role is not won in game 1 following the ended instruction effect. Is done. This loss notification is terminated when the game 1 is finished, but since the special role is won in the game 1, it is announced that the special role is won when the next game 2 is started. Will be. Note that even when the game 2 starts, the notice of winning the special role continues until the winning special role is won.

  In the example of FIG. 62 (d), as in the example of FIG. 62 (b), the continuous operation effect is executed when the special role is not won, but the time is measured by the time limit timer. Although all the reels did not stop before the time reached 5 seconds, when the time counted by the time limit timer reaches 5 seconds, the number of operations of the MAXBET switch 6 is the first operation. And less than 10 times.

  In this case, the instruction effect ends when the time counted by the time limit timer reaches 5 seconds, and it is announced that the special role is not won in game 1 following the ended instruction effect. Is done. This loss notification is ended when the game 1 is ended, but since no special role is won in the game 1, no notification is given when the next game 2 is started.

  Thus, in this embodiment, a continuous operation effect that suggests the possibility of winning a special role is started at the same time as the game starts. This continuous operation effect is to notify whether or not a special role is won after the instruction effect.

  The player can intervene by operating the MAXBET switch 6 while the instruction effect is being performed while notifying whether or not the special role is won in the continuous operation effect. Yes. When the player intervenes by operating the MAXBET switch 6 for this continuous operation effect (instruction effect) and operates the MAXBET switch 6 10 times within 5 seconds from the first operation, the instruction effect is displayed. At the same time, the player will be notified of the special role.

  Here, the starting point for counting whether or not the MAXBET switch 6 has been operated 10 times that the player will be notified of whether or not the special role is won following the instruction effect is first determined by the MAXBET switch 6. It is from when it was operated. Since the player can intervene in the continuous operation effect at a free timing after the start of the continuous operation effect (instruction effect), that is, a highly flexible intervention operation, it is easy for the player to intervene in the continuous operation effect As a result, the interest of the game can be improved.

  In addition, even if the player operates the MAXBET switch 6 for the first time to indicate his intention to intervene in the continuous operation effect, the player is notified as to whether or not the special role is won as it is following the instruction effect. In this case, the MAXBET switch 6 must be repeatedly operated 10 times within 5 seconds (9 times excluding the first operation). Thus, even after the player starts the intervention of the continuous operation effect, it is necessary to continue the intervention operation. Therefore, the sense of intervention in the effect is enhanced, and the interest of the game can be further improved.

  In addition, when a continuous operation effect is performed, the presence / absence of a special role is announced following the instruction effect in the game, and a total of 10 MAXBETs within 5 seconds from the first MAXBET switch 6 operation. The condition is that the switch 6 has been operated. However, if the MAXBET switch 6 is operated for the 10th time, the presence / absence of a special role is announced without waiting for the elapse of 5 seconds from the first operation of the MAXBET switch 6.

  As a result, the establishment timing of the condition for the special role winning to be executed following the instruction production is linked to the notification timing of whether or not the special role has been won, so the presence or absence of the special role has been announced. Sometimes this is easy for the player to understand. Moreover, since the presence or absence of the special role is announced at the timing linked with the player's operation (the 10th operation of the MAXBET switch 6), the player's sense of intervention for the continuous operation effect is further enhanced. Can further enhance the interest of the game.

  Even if a continuous operation effect is performed, unless the player operates the MAXBET switch 6, in any case, the presence or absence of the special role will be announced following the instruction effect in the game. There is no. Since a general player wants to know as soon as possible whether or not a special role has been won, it can prompt the player to intervene in the continuous operation effect by operating the MAXBET switch 6. It will be a thing.

  On the other hand, when the special role is won and the continuous operation effect is performed, the player does not operate the MAXBET switch 6 at all, or the game ends before the MAXBET switch 6 is operated 10 times, or the first operation Even if the MAXBET switch 6 cannot be operated 10 times within 5 seconds from the start of the game, the player will be notified of the special role when the next game is started.

  For this reason, the information that the player would like to know (that is, the user did not operate the MAXBET switch 6 while the instruction effect of the continuous operation effect was performed, or the user could not perform an appropriate operation even if operated). The information on whether or not the special role has been won) cannot be known by the player at any time, and the disadvantage of the player is not increased too much.

  By the way, in the present embodiment, the rotation of the reels 2L, 2C, and 2L is stopped when the player performs a stop operation. However, if the player does not perform the stop operation, the reels 2L, 2C, and 2L continue to rotate indefinitely. However, even if the instruction effect is started simultaneously with the start of the game, it is not necessary to determine whether or not to win the special role unless the player operates the MAXBET switch 6. For this reason, it is not necessary to increase the control load when the reels 2L, 2C, and 2L are left in a rotating state.

  Further, when the instruction effect is being executed, it may be considered that all or a part of the reels 2L, 2C, and 2R is left rotating while the MAXBET switch 6 is operated. However, it is only necessary to determine whether or not to win a special role or notify of a loss after the instruction effect in the game for only 5 seconds after the first operation of the MAXBET switch 6. For this reason, the control load does not become too large.

  In the present embodiment, the sub CPU 91a specifies the detection state of the MAXBET switch 6 based on the ON / OFF state of the operation switch specified by the operation detection command transmitted from the main CPU 41a, and performs the above-described continuous operation. Production is to be executed.

  On the other hand, in the continuous operation effect, since the winning of the special role is not notified unless the MAXBET switch 6 is operated 10 times including the first operation within 5 seconds from the first operation of the MAXBET switch 6, the sub CPU 91a performs the operation detection command. If the player misses out, it may not be announced that the special role will be won even though the player has operated the MAXBET switch 6 10 times within 5 seconds. In the present embodiment, as described above, the main CPU 41a operates as a single BET regardless of whether the single BET switch 5, the MAX BET switch 6, the start switch 7, or the stop switches 8L, 8C, 8R is operated. Switch 5, MAXBET switch 6, start switch 7, stop switch 8L, 8C, 8R respectively The sub CPU 91a can periodically specify the ON / OFF state of these operation switches by periodically transmitting an operation detection command that can specify the ON / OFF state of the operation detection command. If the player performs an operation that satisfies the notification condition, the latest detection state is acquired from the operation control information transmitted next time and it is determined whether or not the notification condition is satisfied. , It is possible to prevent the winning of the special role from being notified by missing the operation detection command.

  In the present embodiment, when a continuous operation effect is performed, if the MAXBET switch 6 is not operated ten times in total within 5 seconds from the first operation of the MAXBET switch 6, the indication effect ends and the loss occurs. In such a case, it is possible to end only the instruction effect without notifying anything. If the special combination is won, the special combination may be announced when a BET operation is performed in the next game or when a start operation is performed.

  In addition, when a continuous operation effect is performed, a special operation is continued following the instruction effect during the game on the condition that the MAXBET switch 6 is operated 10 times in total within 5 seconds from the first operation of the MAXBET switch 6. Whether or not the winning combination has been announced to the player, either one or both of the time condition of 5 seconds and the operation condition of 10 times, for example, a continuous operation effect is executed. It may be variable by lottery performed every time.

  For example, one selected from the conditions of 2 seconds 4 times and 3 seconds 6 times or one selected from the conditions of 3 seconds 3 times and 3 seconds 6 times may be used. In these cases, there will be a change in the timing at which the presence or absence of the special role will be announced following the instruction production, or there will be a change in the difficulty level of the operation required for that, so there will be a change to the continuous operation production. This will further increase the interest of the intervention.

  Further, the continuous operation effect is started from the start of the game, but may be started under other conditions and timing. For example, the continuous operation effect may be started from the timing when all the reels are stopped.

  As described above, in the continuous operation effect that is started after the game is finished, the stop switches 8L, 8C, and 8R are not involved in the progress control of the game when the instruction effect is being executed. , 8C, 8R can be applied instead of the MAXBET switch 6.

  Further, in the present embodiment, when the instruction effect is being executed, the first operation of the MAXBET switch 6 that is not involved in the progress control of the game is an operation that becomes an intention display to start intervention in the continuous operation effect. Time counting by the time limit posting timer is started, and the operation of the MAXBET switch 6 is an operation for intervening in the continuous operation effect after the intention of intervention is displayed.

  On the other hand, the operation which becomes the intention display of the intervention for starting the time counting by the time limit posting timer may be an operation related to the progress control of the game. For example, the operation of the stop switch (first stop operation) during rotation of all reels is related to the progress control of the game, but it can also be applied as an operation for indicating the intention of intervention to start timing by the timer for posting the time limit. .

  Further, in the present embodiment, when the MAXBET switch 6 is operated 10 times within 5 seconds including the first operation, the special role is elected in the game in which the continuous operation effect is performed following the instruction effect. However, the operation condition for notifying whether the special role is won or not is not limited to this. For example, the MAXBET switch 6 is set for a predetermined time. It may be operated continuously (intermittently) (3 seconds or less). Alternatively, the second and subsequent operations of the MAXBET switch 6 performed after 3 seconds have elapsed since the first operation of the MAXBET switch 6 may be continued for a predetermined time.

  Alternatively, in the case where an operation intervening in the continuous operation effect after the intention display for starting the intervention in the continuous operation effect (the first operation of the MAXBET switch 6) is an operation of a plurality of operation means, the plurality of operation means are It may be operated in a predetermined pattern. For example, after the intention display for starting the intervention to the continuous operation effect, two operation buttons, the single BET button 14 and the MAXBET switch 6 are applied as operation means for intervening in the continuous operation effect, and these are alternately performed 20 times (each It is also possible to notify the presence / absence of the special role following the instruction effect when the button is operated within 5 seconds from the first operation of the MAXBET switch 6 only 10 times.

  Further, in the present embodiment, both the operation that becomes the intention display for starting the intervention to the continuous operation effect and the operation that intervenes in the continuous operation effect after the intention display are the operations of the MAXBET switch 6. Both operations may be operations of different operation means. For example, the operation of the single BET button 14 is started as an operation to be an intention display for starting intervention in the continuous operation effect, but the operation of the MAXBET switch 6 is an operation to intervene in the continuous operation effect after the intention display. Alternatively, it may be determined whether the MAXBET switch 6 has been operated a predetermined number of times within a predetermined time from the start of timing.

  Further, in this embodiment, when a special action is won and a continuous operation effect is performed, the MAXBET switch 6 is operated, but the operation cannot be performed 10 times within 5 seconds, and there is a loss following the instruction effect. When notified, or when the MAXBET switch 6 is not operated, or when the game is ended and only the directed effect is ended before the operation of the MAXBET switch 6 has elapsed for 5 seconds or 10 times, At the start of the game (that is, at the start operation time), the winning of the special role was announced, but the timing of the special role winning notification in such a case is not limited to this. For example, when the next game ends (when the third stop button is operated), it may be the first stop or the second stop. Furthermore, it may be when a betting number setting operation for starting the next game is performed.

  Further, in the present embodiment, whether or not the special role is won is notified by the continuous operation effect, but if it is an effect to notify information advantageous to the player by the player's intervention operation Well, for example, notifying whether or not a notification state in which an operation procedure advantageous to the player is notified by the player's intervention operation is won, or notifying information for inferring the set value by the player's intervention operation It is good.

Next, the table information browsing effect among the operation effects described above will be described.
The RAM 91c of the sub-control unit 91 is allocated with a game history data storage area capable of storing game history data relating to already played games, and these game history data are based on commands sent from the main CPU 41a. Sequentially updated to the latest data. On the other hand, in the ROM 91 b of the sub-control unit 91, effect introduction data that introduces effects performed in the slot machine 1 is stored.

  The player simultaneously operates the right stop switches 8C, 8R among the stop switches 8L, 8C, 8R in the control state from the end of the game (after setting change) to the start of the game as described above. By displaying the browsing menu screen and further operating the stop switches 8L, 8C, 8R to select the menu, game history data stored in the game history data storage area of the RAM 91c (setting change to be described later) It is possible to browse game history information based on (excluding history) and effect introduction data stored in the ROM 91b.

  The game history data storage area includes an inter-bonus game number counter, an inter-bonus game number table, a total game number counter, an RB counter, a BB counter, an insertion number counter, a payout number counter, an hourly difference number table, a date-specific history table, and a setting. Consists of a value change table.

  The inter-bonus game number counter is a counter for counting the number of games since the end of the previous bonus, and is incremented by 1 every time a gaming state command is received in a state other than the bonus state, and from BB or RB to the normal gaming state. Cleared when a gaming state command indicating transition is received.

  The inter-bonus game number table stores the number of inter-bonus games together with the type of bonus (BB, RB) for each bonus, and has received a gaming state command indicating a transition from the normal gaming state to BB or RB. At this time, the type of bonus is stored, and the value of the inter-bonus game number counter is acquired and stored as the number of games between bonuses.

  The total game number counter is a counter that counts the total number of games of today, and is incremented by 1 every time a game state command is received in a state other than the bonus state.

  The RB counter is a counter that counts the number of RBs for today, and is incremented by 1 when a gaming state command indicating a transition from the normal gaming state to the RB is received.

  The BB counter is a counter that counts the number of BBs for today, and is incremented by 1 when a gaming state command indicating a transition from the normal gaming state to the BB is received.

  The inserted number counter is a counter that counts the number of pachinko balls used in the game, that is, the number of balls taken in for use in setting the number of bets, and when the internal winning command is received, it depends on the current gaming state. The number of medals required to start the game is added.

  The payout number counter is a counter that counts the number of medals paid out at the time of winning a small role, and when receiving a winning determination command indicating the win of a small role, the payout number specified by the command is added.

  The hourly difference sheet table is a table for storing a difference sheet (a value of the dispensed sheet counter−a value of the inserted sheet counter) at a predetermined interval, and the value of the dispensed sheet counter at every predetermined interval (for example, every 5 minutes). The value of the insertion number counter is acquired, and the difference number is calculated and stored.

  The date-by-date history table is a table for storing data of a bonus game number table for the past three days, a total game number counter, an RB counter, a BB counter, an insertion number counter, a payout number counter, and a time difference number table. . In the startup process (sub), the sub CPU 91a acquires date information from the clock device 97, and stores the acquired date information in the date storage area of the RAM 91c. Then, it is determined whether or not the date information newly acquired in the activation process matches the date information stored in the date storage area of the RAM 91c, and when it is determined that they do not match, that is, the date has been updated, The data stored in the area two days ago is stored in the area three days ago, the data stored in the area one day ago is stored in the area two days ago, and the data stored in the area today is 1 The data stored in the area of the previous day and the data stored in the area where the data of today is stored are cleared (initialized). That is, a process of storing each data of the inter-bonus game number table, the total game number counter, the RB counter, the BB counter, the insertion number counter, the payout number counter, and the hourly difference number table as data one day before is performed.

  In addition, as each data of the bonus game number table, total game number counter, RB counter, BB counter, insertion number counter, payout number counter, and hourly difference number table is stored in the date-specific history table, The game number table, total game number counter, RB counter, BB counter, insertion number counter, payout number counter, and hourly difference number table are cleared.

  The setting value change table is a table for storing setting value change histories for the past five times. When the game mode command is received in the state where the administrator mode is set, the time information ( The setting value indicated by the gaming state command is stored in association with the date and time. At this time, the oldest change history is cleared.

  Here, the browsing situation of game history information and effect introduction data and the control situation of the sub CPU 91a at that time will be described with reference to FIG.

  In the present embodiment, when the right stop switch 8C, 8R among the stop switches 8L, 8C, 8R is simultaneously operated in the control state from the end of the game (after the setting change) to the start of the game, the liquid crystal display The browsing menu screen shown in FIG. 63A is displayed on the device 51.

  The browsing menu screen has an explanation area for the currently selected menu, and a menu area consisting of “bonus information”, “introduction”, “bonus history”, “slump graph”, and “return”. The selection frame of the menu area is moved in accordance with the operation of the switches 8L and 8C, and the display content of the explanation area is also updated to the explanation of the currently selected menu area with this movement. Note that only the menu area corresponding to the setting state of the browsing valid flag set in the RAM 91c is displayed on the browsing menu screen, and “inter-bonus information” “direction introduction” “bonus history” “ In the “slump graph”, the menu area of the item for which the browsing valid flag is not set is not displayed. The browsing valid flag is set only for items that are set to enable browsing on the option screen described later, and for items that are not set to enable browsing on the option screen described later Cannot be browsed by the player's operation.

  If the stop switch 8R is operated in the state where the “inter-bonus information” menu area is selected on the browsing menu screen, the inter-bonus information screen shown in FIG. 63B is displayed. On the bonus information screen, a menu area consisting of “Today”, “1 day ago”, “2 days ago”, “3 days ago”, and “Return”, and a bonus information and a bonus bonus information display for each bonus are displayed. And an area. When displaying the information screen between bonuses from the browsing menu screen, the type of bonus and the number of games between bonuses are displayed in the information display area between bonuses based on data registered in the table of bonus games between today. Is displayed for each bonus. Further, when one of “1 day ago”, “2 days ago”, and “3 days ago” is selected on the inter-bonus information screen, if the stop switch 8R is operated, it is based on the data stored in the history data table by date. The type of bonus on the selected day and the number of games between bonuses are displayed in the bonus information display area for each bonus. Further, when the “return” is selected on the information screen between bonuses and the stop switch 8R is operated, the screen returns to the browsing menu screen.

  When the stop switch 8R is operated in a state where the menu area of “production introduction” is selected on the browsing menu screen, the production introduction screen shown in FIG. 63C is displayed. On the bonus information screen, a menu area corresponding to each effect and a menu area corresponding to “return” are provided. When the stop switch 8R is operated in a state where any of the menu areas corresponding to each effect is selected on the effect introduction screen, the corresponding data is extracted from the effect introduction data stored in the ROM 91b and displayed. . In addition, when the “return” is selected on the effect introduction screen and the stop switch 8R is operated, the viewing menu screen is displayed again.

  When the “bonus probability” menu area is selected on the browsing menu screen and the stop switch 8R is operated, the bonus probability screen shown in FIG. 63D is displayed. The bonus probability screen is provided with a menu area consisting of “Today”, “1 day ago”, “2 days ago”, “3 days ago”, and “Return”, and a bonus probability display area in which the probability is displayed for each bonus type. . Then, when displaying the bonus probability screen from the browsing menu screen, today's BB probability and RB probability are calculated based on the values of the total game number counter, RB counter, and BB counter of today, and are displayed in the bonus probability display area. Is displayed. Further, when the decision switch 57 is detected in a state where any one of “1 day ago”, “2 days ago”, and “3 days ago” is selected on the bonus probability screen, the selection is made based on the data stored in the history data table by date. The probability of BB and the probability of RB for the selected day are calculated and displayed in the bonus probability display area. Further, when the “return” is selected on the bonus probability screen and the stop switch 8R is operated, the browsing menu screen is displayed.

  When the stop switch 8R is operated in the state where the menu area of “slump graph” is selected on the browsing menu screen, the slump graph screen shown in FIG. 63 (e) is displayed. The slump graph screen includes a menu area including “today”, “1 day ago”, “2 days ago”, “3 days ago”, and “return”, and a graph display area in which a slump graph indicating the status of the difference ball in time series is displayed. , Is provided. When displaying the slump graph screen from the browsing menu screen, today's slump graph is generated based on today's hourly difference number table and displayed in the graph display area. In addition, if one of “1 day ago”, “2 days ago”, or “3 days ago” is selected on the slump graph screen and the stop switch 8R is operated, the selection is made based on the data stored in the history data table by date. A slump graph for the selected day is generated and displayed in the graph display area. Further, when the “return” is selected on the slump graph screen and the stop switch 8R is operated, the browsing menu screen is displayed.

  As described above, in the control state from the end of the game (after setting change) to the start of the game, the player operates the right stop switch 8C, 8R among the stop switches 8L, 8C, 8R simultaneously. A game based on game history data (excluding setting change history described later) stored in the game history data storage area of the RAM 91c by displaying the browsing menu screen and further operating the stop switches 8L, 8C, 8R. It is possible to browse history information and performance introduction data stored in the ROM 91b.

  In the present embodiment, as shown in FIG. 64, when the setting key switch 37 is activated, the main CPU 41a transmits a setting start command to the sub CPU 91a to notify the start of the setting change state and to set the setting value. Will shift to a setting change state in which can be changed. In the setting change state, the set value can be arbitrarily selected until the start switch 7 is operated. However, when the start switch 7 is operated, the set value selected at that time is fixed. Thereafter, a setting final state in which the setting value cannot be changed is entered. In this state, the setting key switch 37 is turned off to end the setting changing state, and a gaming state command is transmitted to the sub CPU 91a to change the setting changing state. Notify the end.

  On the other hand, the sub CPU 91a is notified of the start of the setting change state by the setting start command, thereby clearing the above-described game history data, setting the game history data that can be browsed by the player, and viewing the setting change history. In other words, the management mode is controlled so that the management information on the sub CPU 91a side managed by the game store can be accessed. Then, the manager mode is ended when the end of the setting change state is notified by the game state command.

  Even if the setting value is confirmed in the setting change state, no notification is sent from the main CPU 41a to the sub CPU 91a, and the sub CPU 91a changes the setting by the game state command even after the setting value is confirmed on the main CPU 41a side. Until the end of the status is notified, the administrator mode is continuously controlled. After the setting value is confirmed in the setting change state, the power is turned on again before the setting value is confirmed. The management information can be accessed without returning to the state.

  Also, as shown in FIG. 65, when the setting key switch 37 is turned on after the game is over and the setting key switch 37 is turned on as shown in FIG. 65, the main CPU 41a transmits a confirmation start command to the sub CPU 91a. And a transition to a setting confirmation state in which the setting value can be confirmed. The setting confirmation state ends when the setting key switch 37 is turned off, and the confirmation confirmation command is transmitted to the sub CPU 91a to notify the end of the setting confirmation state.

  When the start of the setting confirmation state is notified by the confirmation start command, the sub CPU 91a can manage the management information on the side of the sub CPU 91a managed by the amusement store as in the case of receiving the setting start command. Control to user mode. The administrator mode ends when the end of the setting confirmation state is notified by the confirmation end command.

  The setting key switch 37 is a switch that can be turned ON / OFF by inserting and rotating the key, but the normal key is possessed by the store clerk and can be arbitrarily set by the player. 37 cannot be operated. That is, only when the setting key switch 37 that cannot be arbitrarily operated by the player is operated, the manager mode is controlled so that the management information on the sub CPU 91a side managed by the game store can be accessed.

  As described above, in the present embodiment, not only when the main CPU 41a is controlled to the setting change state but also when the main CPU 41a is controlled to the setting confirmation state, the administrator mode is controlled. Management information can be accessed without shifting to. In particular, even if the setting change state is not entered unless the power is turned on again as in this embodiment, it is not necessary to turn off the power just to access the management information. Furthermore, even when the RAM 41c is initialized with the transition to the setting change state as in the present embodiment, it is possible to access the management information while maintaining the stored data in the RAM 41c.

  In this embodiment, when a setting start command or a confirmation start command is received from the main CPU 91a, control is performed in the administrator mode as it is. However, after the setting start command or the confirmation start command is received, For example, the configuration may be such that the administrator mode is controlled only when a certain operation is performed, for example, the MAXBET switch 6 is operated for a certain period of time or more. It is possible to prevent the administrator mode from being controlled even though there is no need to access the.

  Further, the main CPU 41a is configured to permit an interrupt before shifting to the setting change state, and periodically transmits an operation detection command while being controlled to the setting change state. While being controlled to the setting change state, the detection state of the operation switch that is not involved in the setting value change control can be sequentially specified.

  Further, interrupts are permitted even in the setting confirmation state, and since the operation detection command is periodically transmitted while being controlled to the setting confirmation state as in the setting change state, the sub CPU 91a enters the setting confirmation state. Even during the control, the detection state of the operation switch not involved in the setting value confirmation control can be sequentially specified.

  Further, as described above, the sub CPU 91a controls to the administrator mode in which the management information can be accessed during the period in which the main CPU 41a is controlled to the setting change state or the setting confirmation state. It is possible to perform an operation during the administrator mode period using the operation switch specified from the detection command, and an operation means for accessing the management information is separately provided on the production control board 90 side. However, originally, an operation for accessing the management information can be performed on the game control board 40 side using an operation switch used for controlling the progress of the game.

  Next, an operation situation when accessing the management information on the sub CPU 91a side and a control situation of the sub CPU 91a at that time will be described with reference to FIG.

  First, the sub CPU 91a controls to the administrator mode when receiving a setting start command or a confirmation start command. Accordingly, the administrator mode screen shown in FIG. 66 is displayed on the liquid crystal display 51. In this administrator mode screen, the game history data is cleared and the game history data that can be viewed by the player is displayed. The setting and setting change history can be browsed.

  Further, in the administrator mode, when a game state command or a confirmation end command is received, the stop mode is terminated and a predetermined menu area (a “return” menu area described later) displayed on the administrator mode screen is displayed on the stop switch 8L. , 8C is also ended when the stop switch 8R is operated in the state selected by 8C. In this case, it is continuously notified that the setting is being changed or the setting is being confirmed.

  The administrator mode screen is provided with an explanation area for the currently selected menu and a menu area consisting of “history data clear”, “option”, “setting change history”, and “return”, and the stop switch 8L, In response to the operation of 8C, the selection frame of the menu area is moved, and the display content of the explanation area is also updated to the explanation of the currently selected menu area with this movement.

  As shown in FIG. 66 (a), when the “history data clear” menu area is selected on the administrator mode screen and the stop switch 8R is operated, the history data clear screen shown in FIG. 67 (a) is displayed. Let The history data clear screen is provided with an explanation area for the currently selected menu and a menu area consisting of “Yes” and “No”. Then, when the stop switch 8R is operated in a state where “Yes” is selected on the history data clear screen, all of the game history data stored in the game history data storage area of the RAM 91c except for the setting change history. Is cleared, a message indicating that the history data has been cleared is displayed as shown in FIG. 67B, and the screen returns to the administrator mode screen. Note that if the decision stop switch 8R is operated in a state where “NO” is selected on the history data clear screen, the game history data is not cleared and the screen returns to the manager mode screen.

  As shown in FIG. 66 (b), when the “option” menu area is selected on the administrator mode screen and the stop switch 8R is operated, the option screen shown in FIG. 68 (a) is displayed. The option screen is provided with a menu area including “information between bonuses”, “production introduction”, “bonus history”, “slump graph”, and “return”. Then, when the stop switch 8R is operated in a state where any one of “information between bonuses”, “introduction of presentation”, “bonus history”, and “slump graph” is selected on the option screen, the display of the corresponding viewable setting column is switched. Specifically, when “ON” indicating that browsing is enabled is displayed, it is switched to “OFF” indicating that browsing is not enabled, and “ON” is displayed when “OFF” is displayed. Switch to When the “return” is selected on the option screen and the stop switch 8R is operated, the browsing valid flag is set for the item for which “ON” is displayed in the browsing setting column, while “OFF” is displayed. After clearing the viewing valid flag of the item that has been set, the screen returns to the administrator mode screen.

  As shown in FIG. 66 (c), when the stop switch 8R is operated in a state where the “setting change history” menu area is selected on the administrator mode screen, the setting change history screen shown in FIG. 68 (b) is displayed. Let The setting change history screen includes a setting change history display area for displaying the setting change history for the past five times, that is, a setting change history stored in the RAM 91c, and a menu area corresponding to “return”. Yes. When the “return” is selected on the setting change history screen and the stop switch 8R is operated, the screen returns to the administrator mode screen.

  As shown in FIG. 66 (d), when the stop switch 8R is operated in a state where the “return” menu area is selected on the administrator mode screen, the administrator mode is terminated and the setting is being changed or the setting is being confirmed. The notification screen is displayed.

  As described above, when the main CPU 41a is controlled to the setting change state or the setting confirmation state, the administrator mode screen is displayed. By operating the stop switches 8L, 8C, and 8R on the screen, the game history data is displayed. Clear, setting of game history data that can be browsed by the player, and browsing of setting change history can be performed.

  In the present embodiment, even if the game history data is cleared, the setting change history data is not cleared. For example, even if the setting change is made illegally, the evidence is surely left. The setting change history data may be cleared together with the clearing of the game history data, or the game history data and the setting change history data may be cleared by separate operations. Good.

  In the present embodiment, a setting change history as an example of management information is stored, and the setting change history can be confirmed in the game shop setting mode. For example, the front door of the slot machine 1 is opened. History (opening time and opening frequency information based on opening of front door) and error occurrence history (error occurrence time, type of error, number of errors), etc. are stored, and in the administrator mode these front doors You may be able to check the release history and error occurrence history.

  The present invention is not limited to the above-described embodiment, and various modifications and applications are possible. Hereinafter, modifications of the above-described embodiment applicable to the present invention will be described.

  (1) In the above-described embodiment, when the setting change operation is performed and the front door 1b is in a closed state and is disabled, the normal operation (opening the front door 1b, turning off the power) The example in which the immobilization is canceled when the setting key switch 37 is turned on and the power is turned on to shift to the setting change state has been described. However, the opportunity to cancel the immobilization is not limited to this, and may be a predetermined operation.

  FIG. 69 is a flowchart showing the control content of the startup process (main) in the first modification. Below, only a different part from FIG. 23 is demonstrated. Referring to FIG. 69, when it is determined in Sa27b that front door 1b is not in the open state, that is, in the closed state, processing for determining whether setting key switch 37 is in the OFF state (Sa27c ′) is performed. The process of Sa27c ′ is repeated until it is determined that the Sa27c ′ is in the OFF state, and when it is determined that the Sa27c ′ is in the OFF state, the process proceeds to Sa16. That is, after it is determined in Sa27b that the front door 1b is in the closed state, the game is disabled as long as the setting key switch 37 is in the ON state, and the setting key switch 37 is in the OFF state. Deactivation is released. This makes it impossible for a person who has committed fraud to easily release the disabled game, whereas a person who can operate the setting key switch with the front door 1b open (for example, a game hall If it is an administrator), the immobilization can be canceled easily and quickly.

  (2) In the embodiment described above, when it is determined NO in the process of Sa27b in FIG. 23, the process of Sa27b is performed, and the game is disabled according to the determination result of Sa27b. explained. However, the processing of Sa27b may be performed as long as the setting change operation is performed after the power is turned on until the setting change state is entered.

  For example, when it is determined in Sa11 that the setting key switch 37 is in the ON state, the same processing as Sa27b (hereinafter referred to as Sa27b ') is performed, and it is determined in Sa27b' that the front door 1b is in the open state. If it happens, the process proceeds to Sa24. On the other hand, when it is determined that the front door 1b is not in the open state, a process similar to Sa27c shown in FIG. 23 or a process similar to Sa27c ′ shown in FIG. 69 is performed to disable the game. After that, you may comprise so that it may transfer to Sa13.

  In such a configuration, even if the setting key switch 37 is in the ON state when the power is turned on, if it is determined in Sa27b ′ that the front door 1b is not in the open state, processing for disabling the game is performed. After that, the process proceeds to Sa13 without performing initialization 1, and then returns to the state before power interruption in Sa16. For this reason, the game can be resumed from the state before the power interruption after the disabling is released. For example, if there is a possibility that a setting change operation has been performed illegally after the power is turned off while three bets have been set before the power interruption, It is possible to return to the state in which three bets are set as the previous bet number, and the game can be resumed from the state in which three bets are set as the bet number is released after the disabling is released. That is, regardless of whether or not the setting change operation is an illegal act, the game can be resumed from the progress state of the game before the power supply is resumed.

  (3) The main control unit 41 in the above-described embodiment transmits a setting start command or an error command in principle when the setting key switch 37 is in an ON state when the power is turned on, and the sub-control unit 91 side stores the RAM 91c. In contrast to the initialization, even when the setting key switch 37 is in the ON state, when it is determined in Sa27b that the front door 1b is in the closed state, a return command is transmitted, and a process for returning on the sub side is performed. An example was described. However, when the setting key switch 37 is in the ON state when the power is turned on, the main control unit 41 initializes the RAM 91c on the sub control unit 91 side regardless of whether or not the front door 1b is in the closed state. A command for this may be transmitted. For example, when it is determined in Sa27b that the front door 1b is in the closed state, an error command indicating a setting change abnormality may be transmitted, and the RAM 91c may be initialized on the sub-control unit 91 side. As a result, for example, when power is interrupted during execution of a continuous effect that is executed over a plurality of games, information indicating that the continuous effect is being executed is backed up. When resuming, it is possible to specify that there is a possibility that the setting key switch 37 is turned on and controlled to the setting changing state because the continuous performance is not resumed.

  In the case of the configuration as described above, when the sub control unit 91 receives an error command indicating the setting change abnormality, the RAM 91c may be initialized and the setting change abnormality may be notified. . For example, a message such as “setting change error!” May be displayed on the liquid crystal display 51.

  (4) In the above-described embodiment, the bit value of the random number interrupt control data RDIC0 is set to “0”, and even if numerical data is captured in the random value register 559A serving as the random value register R1D, the interrupt is not generated. Although the configuration does not occur, the bit value of the random number interrupt control data RDIC0 is set to “1”, and the numerical value data is taken into the random value register 559A serving as the random number value register R1D. You may comprise so that it may generate | occur | produce.

  The main control unit 41 may be configured to interrupt the basic process and execute the random value latch interrupt process when a random number interrupt occurs. If another interrupt process is being executed when a random interrupt occurs, the random value latch interrupt process is executed after the end of the interrupt process being executed.

  FIG. 70 is a flowchart showing the control contents of a random value latch interrupt process executed by the main control unit 41 when a random number interrupt is generated, in a modification. Note that other interrupts are automatically prohibited during the execution period of the random value latch interrupt process.

  In the random value latch interrupt process, first, after saving the register in use to the stack area (Sk1001), the numerical data is read from the random value register 559A (Sk1002), and the value stored in the random number value storage work is The numerical data read in Sk1002 is updated (Sk1003), the register saved in the stack area is restored in Sk1001 (Sk1004), and the process before the interrupt is returned.

  In this example, a random number interrupt is generated when numerical data is taken into the random value register R1D, and the main control unit 41 interrupts the basic process and executes a random value latch interrupt process. Numerical data of the register R1D is read out. As a result, the random number latch flag is cleared, and new numerical data can be taken in. That is, every time numerical data is fetched into the random value register R1D, the random value latch interrupt processing is executed to read the numerical data in the random value register R1D, so that the numerical data is held in the random value register R1D. The state is released, and new numerical data can be taken into the random value register R1D.

  For this reason, as shown in FIG. 71, the start switch 7 is operated in a state where the start of the game is not permitted, and the numerical data is stored in the random value register R1D. Even if this state is maintained, the numerical data is latched. Since the numerical data of the random number register R1D is read out by the occurrence of an interrupt due to the occurrence of the interruption, it becomes possible to store the newly latched numerical data, so the start switch 7 before the start of the game is permitted Even if the numerical data latched by the above operation is held in the random value register R1D, it is possible to acquire the newly latched numerical data at the timing when the start switch 7 is operated after the start of the game is permitted. .

  Further, in the random value latch interrupt processing, not only the numerical data latched in the random value register R1D but also the random value storage work value in the RAM 507 is updated to the read numerical data, so that the random value register R1D Each time new numerical data is latched, the numerical data stored in the random value storage work is updated to the latest latched numerical data.

  At the start of the game, instead of the numerical data stored in the random value register R1D, the numerical data stored in the random value storage work of the RAM 507 is acquired and the internal lottery is performed, so the numerical value is stored from the random value register R1D. After the data is read, even if the numerical data changes due to noise on the signal line of the start switch, it will not affect the numerical data of the random number storage work used for internal lottery. Even in such a case, the internal lottery can be performed using the numerical data latched at the timing when the start switch 7 is operated.

  In this example, when the operation of the start switch 7 is detected, the numerical data stored in the random value storage work of the RAM 507 is set as the lottery work assigned to the RAM 507, and in the subsequent internal lottery. It is determined whether or not the winning combination has been won by performing an operation on the numerical data set in the lottery work, and the internal lottery ends when the operation of the start switch 7 is detected. Even if the numerical data stored in the random number value storage work is updated up to now, the numerical data acquired when the operation of the start switch 7 is detected will not be changed before the internal lottery ends. When the operation of the start switch 7 is detected, the numerical data stored in the random value storage work of the RAM 507 is transferred to the CPU 50. The set in the work register, may be a determination of whether the player wins a winning combination by performing an operation on numerical values set in the work register data in the subsequent internal lottery.

  Further, it may be determined whether or not the winning combination has been won by performing an operation on the numerical data stored in the random value storage work. In this case, the operation of the start switch 7 is performed. The numerical data stored in the random value storage work is newly latched, for example, by prohibiting random value interrupt processing that accompanies the generation of random number interrupts during the period from the time of detection until the end of the internal lottery. By preventing the numerical data from being updated, it is possible to prevent the numerical data acquired when the operation of the start switch 7 is detected from being changed before the internal lottery is completed.

  In this example, the numerical value data in the random value register R1D is read in the random value latch interrupt process. However, in the random value latch interrupt process, the numerical data is latched in the random value register R1D. Is set in the RAM 507, and it is determined whether the latch flag is set in the RAM 507 in basic processing such as BET processing or timer interrupt processing (main), and it is determined that the latch flag is set in the RAM 507. In such a case, the numerical data in the random value register R1D may be read. Even in such a structure, the start switch 7 is operated in a state where the start of the game is not permitted, and the numerical data is stored in the random value register R1D. Will be stored and the state will not be retained. There it is possible to obtain a new numerical data latched at the timing of the start switch 7 has been operated after being allowed.

  (5) In the above embodiment, as an example of a gaming machine, the game can be started and the display state can be changed by setting the number of bets using a medal or credit for one game. A slot machine has been described in which one game is completed when a display result is derived to a variable display device, and a winning can be generated according to the display result of the variable display device.

  However, the gaming machine that embodies the present invention is not limited to such a slot machine, and may be any gaming machine that can change the advantage to the player. As a gaming machine, for example, a game medium (for example, a pachinko ball) is driven into a predetermined game area, and the game medium that has been driven passes (wins) through a start area (for example, a start port) provided in the game area. The display state of the variable display device can be changed, and when the display result of the variable display device becomes a specific display result (for example, a combination of jackpot symbols), a specific game state (big hit state) that is advantageous to the player It may be a pachinko machine that is controlled. In this case, changing the degree of advantage means setting any one of a plurality of types of setting values determined so that the probability of being controlled to a specific gaming state (so-called jackpot) is different. In addition, the variable display condition is established when the variable passes through the start area and a random number is read out. In accordance with the probability specified from the above, it is determined whether or not the specific display result is derived using the random number.

  Here, a configuration corresponding to “opening / closing body” and “opening / closing state detecting means” when the present invention is applied to a pachinko machine will be described with reference to FIGS. 73 to 76. 73 to 76, the pachinko machine includes an outer frame 912 and a main body frame 914. The outer frame 912 is formed in a substantially rectangular shape, and is fixed to a so-called island or the like in a game arcade. As shown in FIG. 74 and FIG. 76, the main body frame 914 has a closed position in which one side is pivotally supported by the outer frame 912 and the other side is close to the outer frame 912 as shown in FIG. The other side is rotatable between an open position (open state) separated from the outer frame 912.

  On the front side of the main body frame 914, a glass door 916, a game ball tray 918, and an operation handle 920 for firing the game ball are provided. One side of the glass door 916 is pivotally supported by the main body frame 914, and as shown in FIG. 73, the other side is close to the main body frame 914 (closed state), and as shown in FIG. Is freely rotatable between an open position (open state) separated from the main body frame 914.

  Behind the glass door 916, a game board 922 for forming a game area 924 for driving a pachinko ball is arranged, and the game board 922 can be visually recognized through the glass door 916. On the game board 922, a variable display for deriving a display result by variably displaying a plurality of symbols in accordance with winning at a so-called accessory, start port, winning port, attacker, out port, game nail, windmill, starting port. A device is provided.

  Also, on the back side of the main body frame 914, a game ball tank for receiving game balls, a payout device for paying out game balls stored in the game ball tank to a tray, various control boards for controlling games and effects, protection A cover, a power supply base case 901 that houses the power supply base, and a main body frame open detection switch 925 for detecting the open state of the main body frame 914 are provided.

  On the front surface of the power supply base case 901, a power switch 939 and a setting switch 938 that are operated when the power is turned ON / OFF are provided. When changing the setting, for example, the main body frame 914 is opened, and the power switch 939 is turned on while the setting switch 938 is being pressed, so that the setting change state in the above-described embodiment is the same. Controlled by the state. In the setting change state, each time the setting switch 938 is pressed, the setting value is updated by one (when the setting switch 938 is further operated, the setting value is returned to setting 1), and a predetermined setting end operation (for example, setting switch 938) The current setting value is set by, for example, pressing 938 for 5 seconds or more, and the setting change state ends. Since the power switch 939 is temporarily turned off and the power switch 939 is turned on while pressing the setting switch 938, the operation is shifted to the setting change state. Therefore, the operations are collectively referred to as a setting change operation.

  As described above, the main body frame 914 which is a gaming machine main body is rotatably attached to the outer frame 912, and the setting change operation can be performed by opening the main body frame 914. . In such a case, it can be said that the main body frame 914 is an opening / closing body. Further, it can be said that the main body frame open detection switch 925 for detecting the open state of the main body frame 914 is an open / closed state detecting means.

  In the pachinko machine shown in FIGS. 73 to 76, for example, a power switch and a setting switch are provided so that the setting change operation can be performed by opening the glass door 916 as shown in FIG. If a glass door open detection switch for detecting the open state of the glass door 916 is provided, it can be said that the glass door 916 is an opening / closing body. Moreover, it can be said that the glass door open detection switch for detecting the open state of the glass door 916 is an open / closed state detection means.

  (6) In the above embodiment, a slot machine for setting bets using medals and credits is used. However, the present invention is not limited to this, and a game used in a pachinko gaming machine. It may be a so-called parrot that uses a ball (pachinko ball) to set a bet number, or a fully credit type slot machine that sets a bet number using only credits.

  Further, in addition to the medal insertion mechanism such as the flow path switching solenoid 30 and the insertion medal sensor 31, a ball take-in device that takes in game balls, and a take-in ball that detects game balls taken in by the ball take-in device In addition to a medal payout mechanism, such as a hopper motor 34b and a payout sensor 34c, a ball payout device for paying out game balls, a payout ball detection switch for detecting game balls payed out by the ball payout device It is possible to set the number of bets using both medals and game balls and play a game, and the present invention may be applied to a slot machine in which medals and game balls are paid out when a winning occurs.

  (7) In the above-described embodiment, as an example of the power interruption process, an example has been described in which an interrupt is executed when a voltage drop signal is input, and a return is made when the voltage drop signal is not input (FIGS. 38 and 38). 52). Below, the modification of an electrical disconnection process is demonstrated. In the startup process (main) in this modification, when a user reset signal is input, the process is started from step Sa2. That is, while starting from the security mode in which the security check process is performed only in the case of activation upon power-on, the user program stored in the ROM 506 is executed by omitting the security check process in the case of activation due to time-up of the watchdog timer It starts from the user mode to execute.

  For example, the power interruption process by the main control unit 41 may be configured as shown in FIG. FIG. 72 is a flowchart showing the control contents of the power interruption process executed by the main control unit 41 when a voltage drop signal is input.

  For example, the power interruption process by the main control unit 41 may be configured as shown in FIG. FIG. 72 is a flowchart showing the control contents of the power interruption process executed by the main control unit 41 when a voltage drop signal is input.

  In the power interruption process (main), first, all registers that may be in use are saved in the stack area (Sm1). Although the values of the I register and IY register described above are used, they are not saved here because the same fixed value is always set with the initialization at the time of startup.

  Next, destruction diagnosis data (5A (H) in this embodiment) is set (Sm4 '), and all output ports are initialized (Sm5'). Next, the RAM parity adjustment data is calculated and set so that the exclusive OR of all storage areas (including unused areas and unused stack areas) of the RAM 507 becomes 0 (Sm6 ′), and the RAM 507 is accessed. Is prohibited (Sm7 ′).

  Thereafter, the CPU 505 is stopped due to a decrease in voltage, or a user reset signal is input to restart the system. In this standby state, it is determined whether or not the random number value is latched based on the value of the random number latch flag register, that is, whether or not numerical data is taken into the random number value register 559A (Sm13), and the random number value is latched. If it is, the random number value for internal lottery is read from the random value register 559A (Sm14), and other processing is not performed. When the random number value for internal lottery is read from the random number value register 559 in the step of Sm14, the random number latch flag register is cleared, and the acquisition of new numerical data is permitted. In the step of Sm14, although the random number value for internal lottery is read, the read random number value is not used, but a dummy number is set in order to enable taking in a new random value in accordance with the operation of the start switch 7. Is read out.

  When the voltage drops in this standby state, the operation is stopped internally. Therefore, the main control unit 41 reliably stops operation when power is interrupted. Further, in this standby state, when the user reset signal is input without the voltage being lowered, the above-described activation process (main) is executed from the user mode, and if the stored data in the RAM 507 is normal, the process returns to the original process. Will be.

  As described above, the main control unit 41 according to the present embodiment does not perform any other processing after the access to the RAM 507 is permitted regardless of whether the reset is a system reset or a user reset. RAM parity of the storage area (including the unused area and the unused stack area) is calculated, and then the storage data in the RAM 507 is normal before determining whether the stored data is normal from the calculated RAM parity. Whether the data stored in the RAM 507 is normal or not is determined based on the RAM parity.

  For this reason, processing that needs to be performed in common regardless of whether the stored data in the RAM 507 is normal or not is executed separately when the stored data in the RAM 507 is determined to be normal and when it is determined to be abnormal. Since it is not necessary, the capacity of the program used for processing at the time of activation can be reduced.

  In addition, after the main control unit 41 is activated, after the access to the RAM 507 is permitted, the RAM parity is calculated before other processing is performed. Therefore, the state before any access to the RAM 507 is performed. Since it is determined whether the stored data is normal based on the calculated RAM parity, it is possible to improve the reliability of the determination of whether the data is normal.

  In the power interruption process, the RAM parity adjustment data is calculated and stored so that the RAM parity based on all the data including the unused area and the unused stack area of the RAM 507 becomes 0, and the RAM 507 is restored at the time of restoration. It is determined whether or not the data in the RAM 507 is normal by determining whether or not the RAM parity calculated based on the data stored in all areas including the unused area and the unused stack area is 0. Therefore, the determination can be performed accurately and simply, and even if an illegal program or data is stored in an unused area or an unused stack area, the illegal program or data is restored while being stored. Can be prevented.

  In addition, after calculating the RAM parity and before determining whether or not the stored data is normal from the calculated RAM parity, it is stored in the RAM 507 as a common process regardless of whether or not the stored data in the RAM 507 is normal. Each switch input data, confirmation data, edge data, that is, data indicating the detection status of each switch is cleared, and the data in the RAM 507 is normal when the main control unit 41 is started. Whether returning to the control state or not returning to the previous control state, it is possible to immediately start checking the detection state of the switch after the interruption is permitted.

  In the slot machine 1 of this modification, the main control unit 41 reads the security check program 506A stored in the ROM 506 or the like when the system reset is performed, that is, when a system reset signal is input when the power is turned on. By executing, it becomes a security mode.

  At this time, a security check process is executed as a process corresponding to the security check program 506A. Here, the security time when the main control unit 41 enters the security mode is stored in advance in the bit number [2-0] or the bit number [4-3] of the security time setting KSES stored in the program management area of the ROM 506. Depending on the bit value, a time component different from the fixed time can be included.

  For example, if the bit value in the bit number [2-0] of the security time setting KSES is a value other than “000”, it can be selected in advance in addition to the fixed time corresponding to the setting content shown in FIG. Any one of a plurality of extended times can be set as a time component included in the security time. If the bit value in the bit number [4-3] of the security time setting KSES is a value other than “00”, the system reset or power-on is performed corresponding to the short mode or the long mode shown in FIG. A variable setting time that changes in a predetermined time range each time is performed can be set as a time component included in the security time.

  Until the security time set in this way elapses, the execution of the user program stored in the ROM 506 is not started. Then, the operation of generating numerical data to be a random number value by the random number circuit 509 should not be started during the period in which the main control unit 41 is in the security mode. As a result, it becomes difficult to specify the operation start timing of the random number circuit 509 or the numerical data to be updated from the operation start timing due to system reset such as power-on, and so on. By connecting the “board” and inputting an illegal signal at a predetermined timing, it is possible to reliably prevent acts such as illegally winning a special role.

  As an example, the bit value in the bit number [2-0] of the security time setting KSES is set to a different value for each model of the slot machine 1. In this case, the extension time of the security mode can be made different for each model of the slot machine 1, and it becomes difficult to specify the operation start timing of the random number circuit 509 from the operation start timing of the slot machine 1. Further, by setting the bit value in the bit number [4-3] of the security time setting KSES to “01” or “10”, the variable setting time can be varied for each system reset. This makes it extremely difficult to specify the operation start timing of the random number circuit 509 from the operation start timing of the slot machine 1.

  In FIG. 72, an example has been described in which after Sm7 ′, the CPU 505 is stopped due to a voltage drop, or a user reset signal is input to restart the system. Thereafter, similarly to FIG. 38, when the voltage drop signal is not input, the process may be shifted to the startup process (that is, the instantaneous power failure recovery). Even in this case, Sm13 and Sm14 are executed after Sm7 'and before the instantaneous power failure recovery. In this way, when the instantaneous power failure is restored and the execution of the game control is started, numerical data is already read from the random value register in the process of step Sm14, and each random number latch flag can be set to the OFF state. Thereby, it is possible to prevent the numerical data stored in the random value register by mistake in a state where the power supply voltage is unstable when the power interruption occurs, from being acquired as a random value.

  (8) If the process of Sm9-Sm11 of FIG. 38 in embodiment mentioned above is performed at the time of a momentary stop, it will not be performed when it determines with NO in Sm8, NO in Sm2. It may be executed when it is determined.

  (9) In the above-described embodiment, the example in which the process of Sa206 is executed in FIG. 25 and the processes of Sm9 to Sm12 are executed in FIG. However, the present invention is not limited to this, and the processing of Sa206 in FIG. 25 may be executed and the processing of Sm9 to Sm12 in FIG. 38 may not be executed. In FIG. 25, the processing of Sa206 is not executed. In step S9, the processes of Sm9 to Sm12 may be executed. This also prevents the numerical data stored in the random value register by mistake with the power supply voltage being unstable as described above from being acquired as a random value.

  (10) In the above-described embodiment, the example in which the setting value for setting the advantage is a value for specifying the probability (winning rate) that it is determined that the occurrence of a winning is permitted has been described. However, the set value may be any value that varies the degree of advantage for the player. For example, an assist time (AT) for executing a navigation effect in which information corresponding to the winning situation is notified or executing the navigation effect is provided. In the slot machine that is controlled to the above, a value that specifies the probability of executing the navigation effect or the probability of controlling to the AT may be used. Further, in a slot machine that is controlled to a replay time (RT) in which the winning probability of a re-gamer is improved by a specific symbol combination, a value that specifies the probability of controlling to the RT may be used. As described above, the winning rates may be the same as long as the player's advantage differs depending on the set value.

  Further, when applied to a pachinko machine, the setting value for setting the advantage may be a value that specifies the probability of winning a big hit. In addition, in pachinko machines with multiple types of hits with different degrees of advantage for players (big hits, medium hits, and small hits), the set value is a value that specifies the probability of winning for each hit type. It may be a value that specifies the total probability of winning for any one. In a pachinko machine that controls to a probability variation state in which the probability of winning a big hit is improved, the set value may be a value that specifies the probability of controlling to the probability variation state.

  (11) In the above-described embodiment, when the power is turned on, it is determined whether or not the setting key switch 37 is in the ON state. When the setting key switch 37 is in the ON state, the front door 1b is based on the door opening detection switch 25. An example has been described in which it is determined whether or not it is in the open state, and if it is in the closed state, it is disabled without shifting to the setting change state. However, the timing for determining whether or not the front door 1b is in the open state is not limited to this. For example, the timing until it is determined whether or not the setting key switch 37 is in the ON state after the power is turned on. It may be. Specifically, it is determined whether or not the front door 1b is in an open state before the processing of Sa11 and Sa31 in FIG. 23 is performed, and when the front door 1b is in an open state, the process proceeds to Sa11 and Sa31. It may be possible to configure such that when the front door 1b is in the closed state, it is not controlled to the setting change state by not shifting to the processing of Sa11 or Sa31. This also prevents the setting change state from being controlled when a setting change operation is performed due to fraud.

  (12) In the above-described embodiment, the example in which the setting confirmation process is performed on the condition that the setting key switch 37 is in the ON state in the BET process of FIG. 30 has been described. In relation to this, in the BET process of FIG. 30, when the setting key switch 37 is in the ON state, it is determined whether or not the front door 1b is in the open state, and when the front door 1b is in the open state. It may be configured to be able to shift to the setting check process and not to shift to the setting check process when the front door 1b is in a closed state (for example, the same as when NO is determined in Se19 in FIG. 30). Further, when the front door 1b is in the closed state, in addition to not shifting to the setting confirmation process, a process for disabling (see Sa27c in FIG. 23 and Sa27c ′ in FIG. 69) may be executed. Good. As a result, when the setting key switch 37 is turned on due to an unauthorized action and a setting confirmation operation is performed, the setting confirmation process is not controlled and the setting confirmation cannot be performed.

  (13) The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  1 slot machine, 2L, 2C, 2R reel, 6 MAXBET switch, 7 start switch, 8L, 8C, 8R stop switch, 41 main control unit, 91 sub control unit, 505 CPU, 506 ROM, 507 RAM, 509 random number circuit, 559A Random value register.

(1) A gaming machine (slot machine, pachinko machine, etc.) capable of changing an advantage (for example, a set value) for a player,
An openable / closable body (front door 1b, body frame 914) provided on the front surface of the gaming machine ;
Operating means (power switch 39, setting key switch 37) that can be operated when the opening and closing body is in an open state;
Open / closed state detecting means for detecting the open / closed state of the open / close body (door open detection switch 25, body frame open detection switch 925);
A specific operation detecting means for detecting that the operating means has been specifically operated to control to a setting change state in which the advantage can be changed by selecting any one of a plurality of setting values; ,
A predetermined operation detecting means for detecting that the operating means has been operated in a predetermined manner to control the setting confirmation state for checking the set value;
When the open / close state detection means detects that the open / close body is in the open state and the specific operation detection means detects that the specific operation has been performed, the setting change state is controlled (in Sa28). Transition), when it is detected that the opening / closing body is not in an open state, the control is not changed to the setting change state (transition to Sa27c), and change state control means (Sa27b, Sa27c, Sa28, Sa29, FIG.
When the opening / closing state detecting means detects that the opening / closing body is in the open state and the predetermined operation detecting means detects that the opening / closing body has been operated, the setting confirmation state is controlled, and the opening / closing body is When it is detected that it is not in an open state, confirmation state control means that does not control to the setting confirmation state;
A set value display unit for displaying the set value,
The set value display section is provided at a position where the set value is visible when the opening / closing body is in an open state,
After the change state control means controls to the setting change state, the change state control means until the setting end condition for ending the setting change state is satisfied regardless of the detection result of the open / close state detection means in the setting change state. Maintain the setting change state.
(2) Disabling means for disabling the progress of the game when the opening / closing state detecting means detects that the opening / closing body is not in the open state.

According to such a configuration, it detects the closed state of the open closed field, when the opening-and-closing member is detected to not be open, it is not to be controlled to the setting change condition. That is, if the closing member is opened would otherwise, when a particular operation can not operate the operation unit is not performed, fraud not a closing member is opened when a specific operation is detected When there is a possibility that it has been performed, the setting change state is not controlled. Accordingly, it is possible to reliably prevent the setting change by being controlled to the setting change state by an illegal act.

Further , the open state of the opening / closing body may be detected when the operating means is specifically operated, and it is detected whether or not the operating means is specifically operated when the opening / closing body is in the closed state. It may be a thing.

( 3 ) When the progress of the game is disabled by the disabling device, the disabling device cancels the disabling operation by releasing the operating device when the operating device is released (FIG. 69). Sa27c ′).

According to such a configuration, the immobilization cannot be easily released for a person who has performed an illegal act, whereas the person who can release the operating means with the opening / closing body opened (for example, If it is a game hall manager), the immobilization can be canceled easily and quickly.

( 4 ) When the progress of the game is disabled by the disabling device, the disabling device is provided with a disabling device for canceling the disabling device by controlling the setting change state (FIG. 28). Sc14, Sc15).

According to such a configuration, the immobilization cannot be easily released for a person who has performed an illegal act, whereas the person who can release the operating means with the opening / closing body opened (for example, If it is a game hall manager), the immobilization can be canceled easily and quickly.

( 5 ) The disabling means disables the progress of the game by disabling a specific game operating means among the game operating means for detecting an operation for advancing the game (FIG. 31). Se35b).

( 6 ) Even when the progress of the game is disabled by the disabling means, the disabling is not performed until the timing at which the game progresses by operating the specific game operating means. The same game progress control is performed (see Se35b in FIG. 31).

( 7 ) Unlike the operation means, game operation means that can be operated by the player (one-sheet BET switch 5, MAXBET switch 6, start switch 7, stop switches 8L, 8C, 8R, checkout switch 10),
And means including the modified state control means performs a progress control of the game according to the operation of the game operation unit, the game control unit (main control for transmitting control information based on the progress control of the recreation (command) Part 41),
Effect control means (sub control unit 91) for controlling the effect based on the control information received from the game control means,
The game control means includes
Setting change start control information transmitting means for transmitting setting change start control information (setting start command) to the effect control means when the setting change state starts;
Participation control means for controlling a particular game operation means (stop switches 8L, 8C, 8R) of the game operation means to a participation control state (reel rotation processing) related to the progress control of the game;
Operation control information transmitting means for transmitting operation control information (operation detection command) indicating an operation state of the specific game operation means to the effect control means in a control state other than the participation control state;
Advantage change control means (such as setting change processing) for performing change control for changing the advantage in the setting change state controlled by the change state control means without being involved in the operation of the specific game operation means. And including
The operation control information transmitting means transmits the operation control information to the effect control means even in the setting change state,
The production control means includes
An operation effect executing means for executing an operation effect based on the operation control information (setting start command) received from the game control means;
On the basis of receiving the setting change start control information, an administrator state control means for controlling to an administrator state (administrator mode) accessible to management information managed by the effect control means;
Control means for managers that performs control for managers (browsing management information, changing management information) based on the operation control information received from the game control means in the manager state.

In addition, the management information, only an administrator, such as a game machine attendant of the game arcade that the gaming machine is installed is accessible information, for example, security information, such as possible door opening history viewing only by an administrator In addition, setting information indicating whether or not the player can view information such as history information and game description is applicable.

( 8 ) a variable display device (reels 2L, 2C, 2R) capable of changing the display state;
Advantageous control means for controlling to a state (bonus) advantageous to the player based on the specific display result (bonus) derived as the display result of the variable display device;
Numerical value updating means (random number sequence changing circuit 555) for updating numerical data;
When a variable display condition for performing variable display for deriving a display result after changing the display state in the variable display device is satisfied (when the start switch 7 is operated and a valid start prize is generated). Random number extraction means (random number latch selector 558A) for extracting the numerical data updated by the numerical value updating means as a random number value and storing it in a first numerical data storage area (random number value register R1D);
After the numerical data is stored in the first numerical data storage area by the random number extraction unit, new numerical data is stored by the random number extraction unit until the stored numerical data is read. And numerical data holding means for holding numerical data stored in the first numerical data storage area (prohibition of latching of new numerical data),
Numerical data storage determining means for determining whether or not numerical data is stored in the first numerical data storage area (whether or not a random number latch flag is set) at regular time intervals (approximately 2.24 ms);
When the numerical data storage determination means determines that numerical data is stored in the first numerical data storage area (a random number latch flag is set), the numerical data storage determination means stores the numerical data in the first numerical data storage area. The numeric data holding means cancels the holding of the numeric data by the numeric data holding means, and the read numeric data is stored in a second numeric data storage area (random number value) different from the first numeric data storage area. Numerical data reading means stored in the storage work),
The specified display result using the numerical data stored in the second numerical data storage area according to the probability specified from the selected setting value when starting the change of the display state in the variable display device Predetermining means (internal lottery) for determining whether or not to permit the derivation of.

( 9 ) a variable display device (reels 2L, 2C, 2R) capable of changing a display state;
Advantageous control means for controlling to a state (bonus) advantageous to the player based on the specific display result (bonus) derived as the display result of the variable display device;
Numerical value updating means (random number sequence changing circuit 555) for updating numerical data;
When a variable display condition for performing variable display for deriving a display result after changing the display state in the variable display device is satisfied (when the start switch 7 is operated and a valid start prize is generated). Random number extraction means (random number latch selector 558A) for extracting the numerical data updated by the numerical value updating means as a random number value and storing it in a first numerical data storage area (random number value register R1D);
After the numerical data is stored in the first numerical data storage area by the random number extraction unit, new numerical data is stored by the random number extraction unit until the stored numerical data is read. And numerical data holding means for holding numerical data stored in the first numerical data storage area (prohibition of latching of new numerical data),
Interrupt generating means for generating an interrupt (random number latch interrupt) when numerical data is stored in the first numerical data storage area;
In response to the occurrence of the interrupt by the interrupt generation means, reading of the numerical data stored in the first numerical data storage area releases the numerical data holding by the numerical data holding means. And numerical data reading means for storing the read numerical data in a second numerical data storage area (random value storage work) different from the first numerical data storage area;
The specified display result using the numerical data stored in the second numerical data storage area according to the probability specified from the selected setting value when starting the change of the display state in the variable display device Predetermining means (internal lottery) for determining whether or not to permit the derivation of.

( 10 ) It is provided with holding release means (Sa206, Sm9 to Sm12) for releasing the holding of numerical data by the numerical data holding means when the progress control of the game is started (when the power is turned on, when the voltage drops, etc.).

( 11 ) Power supply monitoring means for monitoring a predetermined power supply voltage generated based on power supply to the gaming machine and outputting a detection signal based on the decrease of the predetermined power supply voltage;
A start command means for performing a start command (user reset) when a predetermined time has elapsed since the detection signal was output from the power monitoring means;
The holding release unit releases holding of numerical data by the numerical data holding unit in a period of waiting for power supply to stop after the detection signal is output from the power supply monitoring unit (FIG. 72). (Refer to Modification (7)).

Claims (1)

A gaming machine capable of changing the advantage to a player,
An opening and closing body provided to be openable and closable;
Operation means that can be operated when the opening and closing body is in an open state;
An open / close state detecting means for detecting an open / close state of the open / close body;
A specific time determination unit that determines an open / closed state of the opening / closing body when the operation state of the operation unit becomes a specific operation state based on a detection result of the open / closed state detection unit;
When the open / close body is determined to be in the open state by the specific time determination means, a setting change state in which the advantage can be changed by selecting any one of a plurality of setting values. And when it is determined that the opening / closing body is not in an open state, state control means for not controlling the setting change state;
A gaming machine, comprising: a disabling device that disables the progress of a game when the open / closed body is determined not to be in an open state by the specific time determining device.

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