JP2014229207A - Multi-core system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To equalize check processing time for respective peripheral devices by respective CPUs.SOLUTION: A multi-core system has plural CPUs(Central Processing Unit), and the plural CPUs are formed of a master CPU and a slave CPU. The master CPU calculates time required for check processing of respective external peripheral devices during initialization processing, and allocates check processing to itself and the slave CPU so that difference of a total value of the check processing time becomes minimum on the basis of the calculation result.

Description

  The present invention relates to a multi-core system.

  Patent Document 1 below discloses a microcomputer and an in-vehicle system that can shorten the processing time of an initialization process executed after reset. In the in-vehicle system, when the ignition switch is turned on and the power-on reset is released, initialization processing by the CPU of each ECU, autonomous initialization by the communication controller, and establishment of a communication session are executed in parallel. The Of the initialization process by the CPU of each ECU and the establishment of the autonomous initialization / communication session by the communication controller, when the one with the longest processing time is completed, the start-up of the in-vehicle system is completed and the original function of the system is performed. Normal processing is started. Since the initialization of the communication controller is autonomously executed in parallel with the initialization process by the CPU in this way, the time required for the initialization process by the CPU and thus the initialization of the entire system can be shortened. Can be started immediately.

JP 2005-309957 A

  By the way, in the above prior art, at the time of initialization processing, check processing of each peripheral device is performed by a plurality of CPUs, but since the sharing of check processing of each peripheral device by each CPU is fixed, the check processing time of the peripheral device When a difference has occurred, the initialization processing of the entire system is not completed until the processing of the CPU having a long check processing time is completed.

  The present invention has been made in view of the above-described circumstances, and an object of the present invention is to average the check processing time of each peripheral device by each CPU and reduce the time required for initialization processing of the entire system.

  In order to achieve the above object, the present invention provides a multi-core system including a plurality of CPUs (Central Processing Units), each of which includes a master CPU and a slave CPU, and the master CPU is initialized. Calculate the time required for the check processing of each of a plurality of external peripheral devices at the time of processing, and check each peripheral device with itself and the slave CPU so that the difference in the total value of the check processing time is minimized based on the calculation result A method of allocating processing is adopted.

  In the present invention, as the second solving means, in the first solving means, the master CPU calculates a time required for the check processing of each peripheral device based on the check processing load.

  In the present invention, as the third solution means, in the first solution means, further comprising a data storage unit, the master CPU checks each peripheral device by itself and the slave CPU after the check processing of each peripheral device. The time required for processing is stored in the data storage unit, and the time required for the check processing of each peripheral device is calculated by referring to the data storage unit at the next initialization processing.

  In the present invention, as a fourth solving means, in any one of the first to third solving means, a second data storage unit is further provided, and the master CPU performs the second data storage during the initialization process. Means for storing the allocation of the check processing of each peripheral device for itself and the slave CPU in the data storage unit, and the slave CPU executes the check processing of the peripheral device with reference to the second data storage unit; adopt.

  In the present invention, as the fifth solution, in the fourth solution, the master CPU checks each peripheral device with respect to itself and the slave CPU in the second data storage unit at the start of the initialization process. Before storing the process allocation, the second data storage unit is initialized, and the slave CPU refers to the second data storage unit immediately after the initialization to check the soundness of the master CPU. Use a means of judging.

  In the present invention, as a sixth solving means, in any one of the first to fifth solving means, the master CPU judges the soundness of the slave CPU based on a peripheral device check result by the slave CPU. Adopt the means to do.

  In the present invention, as a seventh solving means, in any one of the first to sixth solving means, the slave CPU judges the soundness of the master CPU based on a peripheral device check result by the master CPU. Adopt the means to do.

  According to the present invention, the master CPU calculates the time required for the check processing of each external peripheral device at the time of the initialization process, and determines the difference in the total value of the check processing times based on the calculation result. Also, by assigning the check processing of each peripheral device to the slave CPU, the check processing time of each peripheral device by each CPU can be averaged, and the time required for the initialization processing of the entire system can be shortened.

It is a schematic block diagram of the multi-core system A which concerns on one Embodiment of this invention. It is a flowchart which shows operation | movement of the multi-core system A which concerns on one Embodiment of this invention. It is a timing chart which shows operation | movement of the multi-core system A which concerns on one Embodiment of this invention.

Embodiments of the present invention will be described below with reference to the drawings.
The multi-core system A according to the present embodiment is mounted on a moving vehicle such as an electric vehicle (EV) or a hybrid vehicle (HV: Hybrid Vehicle), and controls peripheral devices D1 to Dn that are both mounted on the moving vehicle. As shown in FIG. 1, the first arithmetic control unit E1, the second arithmetic control unit E2, and the communication bus B are provided.

As shown in FIG. 1, the first arithmetic control unit E1 includes a first ROM (Read Only Memory) 11, a first RAM (Random Access Memory) 12, and a first CPU (Central Processing Unit) 13.
The first ROM 11 is a non-volatile memory that stores various arithmetic control programs executed by the first CPU 13 and other data. The first ROM 11 is a data storage unit and a second data storage unit in the present embodiment.
The first RAM 12 is a volatile memory that is used as a working area that is a temporary storage destination of data when the first CPU 13 executes a calculation control program and performs various operations.

  The first CPU 13 is electrically connected to the first ROM 11 and the first RAM 12, and is electrically connected to the peripheral devices D1 to Dn via the communication bus B, and is based on various arithmetic control programs stored in the first ROM 11. The operation of the peripheral devices D1 to Dn is controlled by performing various arithmetic processes and communicating with each unit. Although the details will be described later, the first CPU 13 functions as a master CPU in the multi-core system A, calculates the time required for the check processing of each of the external peripheral devices D1 to Dn at the time of initialization processing, and itself based on the calculation result And the check process of each peripheral device D1-Dn is allocated to 2nd CPU23 (slave CPU) of the 2nd calculation control part E2 mentioned later.

As shown in FIG. 1, the second arithmetic control unit E <b> 2 includes a second ROM 21, a second RAM 22, and a second CPU 23.
The second ROM 21 is a non-volatile memory that stores various arithmetic control programs executed by the second CPU 23 and other data.
The second RAM 22 is a volatile memory used as a working area that is a temporary storage destination of data when the second CPU 23 executes a control program and performs various operations.

  The second CPU 23 is electrically connected to the second ROM 21 and the second RAM 22 and is electrically connected to the peripheral devices D1 to Dn via the communication bus B, and is based on various arithmetic control programs stored in the second ROM 21. The operation of the multi-core system A is controlled by performing various arithmetic processes and communicating with each unit. Although the details will be described later, the second CPU 23 functions as a slave CPU in the multi-core system A, and executes a check process of each peripheral device D1 to Dn allocated by the first CPU 13 during the initialization process.

  The communication bus B is a communication line for electrically connecting the first CPU 13, the second CPU 23 and the peripheral devices D1 to Dn. The first CPU 13, the second CPU 23, and the peripheral devices D 1 to Dn transmit and receive data via the communication bus B.

  On the other hand, the peripheral devices D1 to Dn are controllers for controlling a travel motor, a generator, a booster circuit, and the like mounted on the moving vehicle, and transmit / receive data to / from the first CPU 13 and the second CPU 23 via the communication bus B. To do. In each peripheral device D1 to Dn, whether or not writing and reading by the first CPU 13 and the second CPU 23 is set in advance. For example, in FIG. 1, “CPU13: R / W” and “CPU23: R / −” are described in the peripheral device D1. This is because the first CPU 13 can write and read data to the peripheral device D1, while the second CPU 23 cannot write data to the peripheral device D1 and can only read it. Is shown.

Next, the operation of the multi-core system A configured as described above will be described with reference to FIG.
For example, during the initial initialization process, the first CPU 13 allocates check processes for the peripheral devices D1 to Dn fixed in advance to itself and the second CPU 23, stores the allocation in the first ROM 11, and causes the second CPU 23 to perform the check process. An execution request is transmitted via the communication bus B (step S1). The first CPU 13 performs the above-described allocation based on information registered in the first ROM 11 in advance. At this time, the first CPU 13 initializes the area of the first ROM 11 in which the allocation is stored at the start of the initialization process, that is, before the above-described allocation is stored in the first ROM 11.

  Then, the first CPU 13 refers to the first ROM 11 and executes a check process for the peripheral devices D1 to Dn allocated by itself (step S2). On the other hand, when the second CPU 23 receives the execution request from the first CPU 13, the second CPU 23 refers to the first ROM 11 and executes a check process of the peripheral devices D1 to Dn allocated by the first CPU 13 (step S11).

  At this time, the first CPU 13 and the second CPU 23 measure the time required for the check processing of the peripheral devices D1 to Dn (step S3 and step S12). And 1st CPU13 receives the measurement result by 2nd CPU23, and memorize | stores the measurement result by itself and 2nd CPU23 in 1st ROM11 (step S4).

  Subsequently, the first CPU 13 determines the time required for the check processing of each peripheral device based on the time required for the check processing of the peripheral devices D1 to Dn stored in the first ROM 11 in the processing of step S4 at the next initialization processing. Calculate (step S5), allocate the check processing of each peripheral device D1 to Dn to itself and the second CPU 23 so as to minimize the difference in the total value of the check processing time based on the calculation result, and store the allocation in the first ROM 11 The execution request for the check process is transmitted to the second CPU 23 via the communication bus B (step S6).

  For example, as shown in FIG. 3, the first CPU 13 allocates the check processing of the peripheral devices D1, D2, and D3 to itself and the second CPU 23 so that the difference between the total check processing times is minimized. Note that “check” shown in FIG. 3 indicates that an actual check is being executed, and “result determination” indicates that a check result determination process based on the check is being executed. That is, “check” and “result determination” shown in FIG. 3 correspond to the processes in steps S2 and S7 shown in FIG. Further, the preprocessing includes steps S1, S5, and S6 shown in FIG. Further, the post-processing includes steps S3, S4, S8, and S9.

  Returning to FIG. 2, the first CPU 13 refers to the first ROM 11 and executes a check process for the peripheral devices D1 to Dn allocated by itself (step S7). On the other hand, when the second CPU 23 receives the execution request from the first CPU 13, the second CPU 23 refers to the first ROM 11 and executes a check process of the peripheral devices D1 to Dn allocated by the first CPU 13 (step S13).

  At this time, the first CPU 13 and the second CPU 23 measure the time required for the check processing of the peripheral devices D1 to Dn (step S8 and step S14). Then, the first CPU 13 receives the measurement result by the second CPU 23 and stores the measurement result by itself and the second CPU 23 in the first ROM 11 (step S9).

  The first CPU 13 also calculates the time required for the check processing of each peripheral device based on the time required for the check processing of the peripheral devices D1 to Dn stored in the first ROM 11 during the subsequent initialization processing, and based on the calculation result. Thus, check processing for each of the peripheral devices D1 to Dn is allocated to itself and the second CPU 23 so that the difference in the total value of the check processing times is minimized.

  According to the present embodiment as described above, the first CPU 13 calculates the time required for the check processing of each of the external peripheral devices D1 to Dn during the initialization process, and the difference in the total value of the check processing times based on the calculation result. By allocating the check processing of each peripheral device D1 to Dn to itself and the second CPU 23 so that the minimum is the minimum, the check processing time of each peripheral device D1 to Dn by each of the first CPU 13 and the second CPU 23 is averaged. Reduce the time required for initialization processing.

  In the present embodiment, the peripheral devices D1 to Dn mounted on the moving vehicle are controllers for driving the traveling motor, the generator, and the booster circuit as described above, and learning based on the operation so far. It is necessary to store a value and perform a check process based on the learned value, and the time required for the first and second check processes may change. Therefore, in this embodiment, the first CPU 13 stores the measurement result of the time required for the check processing of the peripheral devices D1 to Dn by itself and the second CPU 23 in the first ROM 11 for each initialization process, so that the peripheral devices D1 to Dn are stored. The calculation accuracy of the time required for the check process can be improved.

As mentioned above, although embodiment of this invention was described, this invention is not limited to the said embodiment, For example, the following modifications can be considered.
(1) Although the said embodiment is provided with two 1st CPU13 and 2nd CPU23, it is not limited to two, Two or more may be sufficient.
(2) Although the said embodiment is mounted in the moving vehicle, you may mount in electronic devices, such as household appliances, other than a moving vehicle.

(3) In the above embodiment, the first CPU 13 calculates the time required for the check processing of the peripheral devices D1 to Dn based on the time required for the check processing of the peripheral devices D1 to Dn stored in the first ROM 11. The invention is not limited to this. For example, the first CPU 13 may calculate the time required for the check processing of each peripheral device D1 to Dn based on the capacity (for example, the number of bytes) of the arithmetic control program used for the check processing of the peripheral devices D1 to Dn.

(4) In the above embodiment, the first CPU 13 initializes the area of the first ROM 11 that stores the allocation at the start of the initialization process, that is, before the allocation is stored in the first ROM 11, but the second CPU 23 The soundness of the first CPU 13 may be determined with reference to the first ROM 11 immediately after initialization. That is, the second CPU 23 may determine whether the first ROM 11 is correctly initialized and determine the soundness of the first CPU 13.

(5) In the above embodiment, the first CPU 13 may determine the soundness of the second CPU 23 based on the check results of the peripheral devices D1 to Dn by the second CPU 23. That is, the first CPU 13 obtains the check result of the peripheral devices D1 to Dn by the second CPU 23, and when the abnormality of the peripheral devices D1 to Dn is obtained as the check result, the first CPU 13 checks again the peripheral devices D1 to Dn in which the abnormality has occurred. If no abnormality has occurred, it is determined that there is a problem with the soundness of the second CPU 23. Similarly, the second CPU 23 may determine the soundness of the first CPU 13.

  A ... multi-core system, D1-Dn ... peripheral devices, E1 ... first calculation control unit, E2 ... second calculation control unit, B ... communication bus, 11 ... first ROM (data storage unit and second data storage unit), 12 ... 1st RAM, 13 ... 1st CPU, 21 ... 2nd ROM, 22 ... 2nd RAM, 23 ... 2nd CPU

Claims (7)

A multi-core system having a plurality of CPUs (Central Processing Units),
The plurality of CPUs are composed of a master CPU and a slave CPU.
The master CPU calculates the time required for the check processing of each of a plurality of external peripheral devices at the time of initialization processing, and the master CPU and the slave so as to minimize the difference in the total value of the check processing times based on the calculation result A multi-core system, wherein a check process for each peripheral device is assigned to a CPU.   The multi-core system according to claim 1, wherein the master CPU calculates a time required for a check process of each peripheral device based on a load of the check process. A data storage unit;
The master CPU stores the time required for the check processing of each peripheral device by itself and the slave CPU in the data storage unit after the check processing of each peripheral device, and refers to the data storage unit in the next initialization process The multi-core system according to claim 1, wherein the time required for the check processing of each peripheral device is calculated. A second data storage unit;
The master CPU stores the allocation of the check processing of each peripheral device for itself and the slave CPU in the second data storage unit during the initialization process,
The multi-core system according to any one of claims 1 to 3, wherein the slave CPU executes a peripheral device check process with reference to the second data storage unit. At the start of the initialization process, the master CPU initializes the second data storage unit before storing the allocation of the check processing of each peripheral device to itself and the slave CPU in the second data storage unit. Run
The multi-core system according to claim 4, wherein the slave CPU determines the soundness of the master CPU by referring to the second data storage unit immediately after initialization.   The multi-core system according to claim 1, wherein the master CPU determines soundness of the slave CPU based on a check result of peripheral devices by the slave CPU.   The multi-core system according to claim 1, wherein the slave CPU determines soundness of the master CPU based on a check result of peripheral devices by the master CPU.

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