JP2014220368A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a composition capable of forming a barrier metal film at an opening of an inter-electrode insulation film without disconnection.SOLUTION: According to an embodiment, a semiconductor device comprises a gate electrode which is formed on a top face of a semiconductor substrate via a gate insulation film and includes: a first conductive film which is formed on the gate insulation film and has a recess of a first opening width formed on a top face; an inter-electrode insulation film which is formed on the top face of the first conductive film and has a silicon oxide film and has an opening of a second opening width wider than the first opening width at a position of the recess of the first conductive film; a second conductive film which is formed on a top face of the inter-electrode insulation film and has an opening of a third opening width wider than the second opening width at a position of the opening; a barrier metal film which is formed on a top face of the second conductive film and a lateral face of the opening, and a top face and a lateral face of the opening of the inter-electrode insulation film, and inside the recess of the first conductive film, and which has a predetermined film thickness; and a metal film formed to cover a top face of the barrier metal film.

Description

  Embodiments described herein relate generally to a semiconductor device and a method for manufacturing the same.

  In a NAND flash memory device as a semiconductor device, for example, a memory cell transistor includes a gate electrode in which a floating gate electrode, an interelectrode insulating film, and a control gate electrode are stacked. Here, in order to lower the resistance of the control gate electrode, the control gate electrode has a barrier metal film and a metal film in a part thereof.

  On the other hand, the selection gate transistor arranged adjacent to the memory cell transistor employs a configuration in which the control gate electrode and the floating gate electrode are short-circuited. When the interelectrode insulating film is opened together with the upper polycrystalline silicon film, the post-processing post-processing may cause the interelectrode insulating film to recede from the end of the polycrystalline silicon film. For this reason, when the barrier metal film is formed by sputtering or the like, there is a case where a stepped state occurs in a portion where the interelectrode insulating film is retracted.

JP 2002-176114 A

  Accordingly, a semiconductor device and a method for manufacturing the same that can reduce the resistance of the gate electrode are provided.

  The semiconductor device of this embodiment is a semiconductor device including a gate electrode formed on the upper surface of a semiconductor substrate via a gate insulating film, and the gate electrode is formed on the gate insulating film and has a first surface on the upper surface. A first conductive film having a recess having an opening width of the first conductive film, a silicon oxide film formed on the upper surface of the first conductive film, and wider than the first opening width at the position of the recess of the first conductive film. An inter-electrode insulating film having an opening having a second opening width; and a second opening formed on the upper surface of the inter-electrode insulating film and having a third opening width wider than the second opening width at the position of the opening. A conductive film, a top surface of the second conductive film and a side surface of the opening, a top surface and a side surface of the opening of the interelectrode insulating film, and a barrier metal having a predetermined thickness formed inside the recess of the first conductive film Formed to cover the film and the upper surface of the barrier metal film Characterized by comprising a metal film.

1 is a diagram schematically illustrating an electrical configuration of a part of a memory cell region of a NAND flash memory device according to a first embodiment; An example of a schematic plan view of the memory cell region An example of a schematic longitudinal sectional view of a portion along line AA in FIG. Example of a schematic longitudinal sectional view of a portion along line AA in FIG. 2 in one stage of the manufacturing process (part 1) Example of a schematic longitudinal sectional view of a portion along line AA in FIG. 2 in one stage of the manufacturing process (part 2) Example of the schematic longitudinal cross-sectional view of the part along the AA line in FIG. 2 in one stage of a manufacturing process (the 3) Example of the schematic longitudinal cross-sectional view of the part along the AA line in FIG. 2 in one stage of a manufacturing process (the 4) Example of the schematic longitudinal cross-sectional view of the part along the AA line in FIG. 2 in one stage of a manufacturing process (the 5) Example of the schematic longitudinal cross-sectional view of the part along the AA line in FIG. 2 in one stage of a manufacturing process (the 6) (A) is an example of a schematic longitudinal sectional view of a portion along the line AA in FIG. 2 showing the second embodiment, and (b) is an enlarged view of a portion surrounded by an alternate long and short dash line in FIG. 10 (a). Example

  Hereinafter, embodiments applied to a NAND flash memory device will be described with reference to the drawings. The drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like do not necessarily match those of the actual one. Also, the vertical and horizontal directions also indicate relative directions when the circuit formation surface side of the semiconductor substrate described later is up, and do not necessarily match the direction based on the gravitational acceleration direction.

(First embodiment)
First, the configuration of the NAND flash memory device of this embodiment will be described. FIG. 1 shows an example of an electrical equivalent circuit of a part of a memory cell array formed in a memory cell region of a NAND flash memory device 1.

  The NAND flash memory device 1 includes a memory cell array, and the memory cell array includes NAND cell units SU arranged in a matrix. The NAND cell unit includes two select gate transistors Trs1 and Trs2, and a plurality (for example, 64) of memory cell transistors Trm connected in series between the select gate transistors Trs1 and Trs2. In the NAND cell unit SU, a plurality of memory cell transistors Trm share a source / drain region with adjacent ones.

  The memory cell transistors Trm arranged in the X direction (word line direction) in FIG. 1 are commonly connected by a word line WL. Further, the selection gate transistors Trs1 arranged in the X direction in FIG. 1 are commonly connected by a selection gate line SGL1, and the selection gate transistors Trs2 are commonly connected by a selection gate line SGL2. A bit line contact CB is connected to the drain region of the select gate transistor Trs1. The bit line contact CB is connected to a bit line BL extending in the Y direction (bit line direction) orthogonal to the X direction in FIG. The select gate transistor Trs2 is connected to a source line SL extending in the X direction in FIG. 1 through a source region.

  FIG. 2 is an example of a plan view of a part of the layout pattern of the memory cell region. In FIG. 2, the bit line contact CB is not shown. As shown in FIG. 2, the memory cell region of a p-type silicon substrate 2 as a semiconductor substrate has an STI (shallow trench isolation) structure in which an element isolation trench (trench) 2d formed on the surface is filled with an insulator. The element isolation region Sb is formed by extending along the Y direction in FIG. A plurality of element isolation regions Sb are formed at predetermined intervals in the X direction in FIG. Thus, the element region Sa is formed to extend along the Y direction in FIG. 2, and a plurality of element regions Sa are provided on the surface of the silicon substrate 2 separately in the X direction.

  The word line WL is arranged extending along a direction (X direction in FIG. 2) orthogonal to the element region Sa. A plurality of word lines WL are formed at predetermined intervals in the Y direction in FIG. A gate electrode MG (see FIG. 3) of the memory cell transistor Trm is formed above the element region Sa intersecting with the word line WL.

  A plurality of memory cell transistors Trm adjacent in the Y direction become a part of a NAND string (memory cell string). The select gate transistors Trs1 (Trs2) are provided adjacent to both outer sides in the Y direction of the memory cell transistors Trm at both ends of the NAND column. A plurality of selection gate transistors Trs1 are provided in the X direction, and the gate electrodes SG of the plurality of selection gate transistors Trs1 are electrically connected by a selection gate line SGL1. Note that the gate electrode SG of the selection gate transistor Trs1 is formed on the element region Sa intersecting with the selection gate line SGL1.

  Similarly, a plurality of selection gate transistors Trs2 are provided in the X direction (not shown), and the gate electrodes of the plurality of selection gate transistors Trs2 are electrically connected by a selection gate line SGL2. A gate electrode is also formed on the element region Sa intersecting with the selection gate line SGL2.

  FIG. 3 is an example of a vertical cross-sectional view of the memory cell transistor Trm and the select gate transistor Trs along the line AA in FIG. The configuration of the memory cell transistor Trm and the select gate transistor Trs in the memory cell region will be described with reference to FIG. A gate insulating film 3 is formed on the upper surface of the silicon substrate 2, and a gate electrode MG of the memory cell transistor Trm and a gate electrode SG of a select gate transistor Trs (Trs1, Trs2; hereinafter simply referred to as Trs) are formed on the upper surface. The memory cell transistor Trm includes a gate electrode MG and source / drain regions 2a formed in the silicon substrate 2 on both sides thereof. A plurality of memory cell transistors Trm are formed adjacent to each other in the Y direction. A pair of select gate transistors Trs is formed adjacent to those at the ends of the memory cell transistors Trm.

  The gate electrode MG of the memory cell transistor Trm is formed on the gate insulating film 3 with a polycrystalline silicon film (first conductive film) 4, an interelectrode insulating film 5, a polycrystalline silicon film (second conductive film) 6, tungsten nitride. A (WN) film (barrier metal film) 7, a tungsten (W) film (metal film) 8, and a silicon nitride film 9 are sequentially stacked. The interelectrode insulating film 5 is a single layer film or a film composed of a plurality of layers, and in any case includes a silicon oxide film. The interelectrode insulating film 6 is, for example, an ONO (oxide-nitride-oxide) film, a NONO (nitride-oxide-nitride-oxide) film, a NONON (nitride-oxide-nitride-oxide-nitride) film, or a NONON film. Instead of the silicon nitride film, a film using an insulating film having a high dielectric constant is used.

  Source / drain regions 2a are provided on the surface layer of the silicon substrate 2 located between the gate electrodes MG and MG and between the gate electrodes SG and MG. The source / drain region 2 a can be formed by introducing impurities into the surface layer of the silicon substrate 2.

  The gate electrode SG of the selection gate transistor Trs has substantially the same structure as the gate electrode MG of the memory cell transistor Trm, and the polycrystalline silicon film 4, the interelectrode insulating film 5, and the polycrystalline silicon film 6 are formed on the gate insulating film 3. , Tungsten nitride film 7, tungsten film 8, and silicon nitride film 9 are laminated in this order.

  In gate electrode SG, in the Y direction, recess 4a is formed along the X direction on the upper surface of polycrystalline silicon film 4, and recess 4a has a first opening width W1. An opening 5a is formed in the interelectrode insulating film 5 along the X direction above the recess 4a, and the opening 5a has a second opening width W2. In the polycrystalline silicon film 6, an opening 6a is formed in the X direction above the opening 5a of the interelectrode insulating film 5, and the opening a has a third opening width W3. Here, there is a relationship of first opening width W1 <second opening width W2 <third opening width W3. As a result, the recess 4a of the polycrystalline silicon film 4, the opening 5a of the interelectrode insulating film 5, and the opening 6a of the polycrystalline silicon film 6 are short-circuited so that the width dimension is reduced stepwise from the polycrystalline silicon film 6 side. The recess is formed.

  The tungsten nitride film 7 includes an upper surface of the polycrystalline silicon film 6, a sidewall surface of the opening 6 a, an upper surface near the opening 5 a of the interelectrode insulating film 5, a sidewall surface, an upper surface near the recess 4 a of the polycrystalline silicon film 4, and a sidewall surface. It is formed continuously along the bottom surface. The tungsten film 8 is formed so as to cover the upper surface of the tungsten nitride film 7, and the upper surface can be formed in a flat state. Further, the lower surface of the tungsten nitride film 7 is positioned lower than the lower surface of the interelectrode insulating film 5. Thus, by lowering the tungsten nitride film 7, the ratio of the metal to the gate electrode can be increased, and the resistance of the gate electrode can be reduced.

  Since the above configuration is adopted, in the memory cell transistor Trm and the selection gate transistor Trs or the peripheral circuit transistor, the configuration of the gate electrodes MG and SG is a relatively thin polycrystalline silicon film on the interelectrode insulating film 5. 6 and the tungsten film 8 can be laminated with the tungsten nitride film 7 interposed therebetween. As a result, the polycrystalline silicon film 6 as the control gate electrode can be thinned to form a so-called “polymetal” structure with a reduced aspect ratio. Further, the end of the opening 5a of the interelectrode insulating film 5 does not recede from the end of the opening 6a of the polycrystalline silicon film 6 (the third opening width W3 <the second opening width W2 is not satisfied). As a result, in the select gate electrode SG, a step-like configuration in which the tungsten nitride film 7 is not broken at the opening 5a portion of the interelectrode insulating film 5 can be obtained. Therefore, it can be set as a favorable structure also about the electrical property of the gate electrodes MG and SG.

  Next, an example of the manufacturing method of the said structure is demonstrated with reference to FIGS. In the description of the present embodiment, the description will focus on the process of forming the opening for short-circuiting the select gate electrode SG, but other processes may be added between the processes as long as they are general processes. The process can also be deleted. Further, each step may be appropriately replaced if practically possible.

  FIG. 4 shows a state before the opening 5 a is formed in the interelectrode insulating film 5. In this state, a gate insulating film 3, a polycrystalline silicon film 4, an interelectrode insulating film 5 and a polycrystalline silicon film 6 are sequentially stacked on the upper surface of the silicon substrate 2. The manufacturing process up to this state will be briefly described.

  First, a silicon oxide film having a predetermined thickness is formed as the gate insulating film 3 on the upper surface of the silicon substrate 2 by using, for example, a thermal oxidation method. Thereafter, a polycrystalline silicon film 4 is formed as a first conductive film on the upper surface of the gate insulating film 3, and a processing silicon nitride film (not shown) is formed on the upper surface. Next, an element isolation trench is formed using the processing silicon nitride film as a mask, the element isolation insulating film Sb is buried, and a planarization process and an etch back process are performed to form an element formation region Sa. Thereafter, an interelectrode insulating film 5 and a polycrystalline silicon film 6 are formed on the upper surface. The interelectrode insulating film 5 is a multilayer film having a silicon oxide film, a silicon nitride film, or the like as described above.

  In the following process, in order to electrically short-circuit the polycrystalline silicon films 4 and 6 in the select gate transistor Trs or the peripheral circuit transistor Trp, etc., the processing at the time of forming the opening 5a in the interelectrode insulating film 5 is mainly performed. explain.

  As shown in FIG. 5, a resist is patterned by photolithography to form a resist pattern for forming an opening 6a in the polycrystalline silicon film 6, and the polycrystalline silicon film 6 is etched by RIE (reactive ion etching). The upper surface of the interelectrode insulating film 5 is exposed. Thereby, an opening 6 a is formed in the polycrystalline silicon film 6. Thereafter, the resist pattern is peeled off. In this case, the opening 6a of the polycrystalline silicon film 6 is formed in a groove shape along the formation direction (X direction) of the selection gate lines SGL1 and SGL2 in which the selection gate electrode SG is formed across the element isolation region Sb. As described above, it is formed with substantially the third opening width W3.

  Subsequently, as shown in FIG. 6, a silicon oxide film 10 for forming a spacer is continuously formed on the upper surface of the polycrystalline silicon film 6 and the upper surface of the interelectrode insulating film 5 exposed on the side wall surface and the bottom surface of the opening 6a. It is formed with a film thickness d. As the silicon oxide film 10, for example, a TEOS oxide film formed at a low temperature or a TEOS oxide film formed at a room temperature can be used. This is because the etching rate of the silicon oxide film 10 in the wet treatment described later is higher than that of the silicon oxide film included in the interelectrode insulating film 5 and has a film quality that is easier to peel than the silicon oxide film included in the interelectrode insulating film 5. To get. In this case, the silicon oxide film 10 can be formed with a film thickness d of about 5 nm to 15 nm, for example, about 10 nm.

  Next, as shown in FIG. 7, the silicon oxide film 10 thus formed is subjected to spacer processing by performing an etch-back process using anisotropic etching, so that the polycrystalline silicon film 6 has openings 6a. The silicon oxide film 10 on the top surface of the interelectrode insulating film 5 on the bottom surface is removed. Further, the interelectrode insulating film 5 is etched to form an opening 5a. At this time, the silicon oxide film 10 remains on the side wall portion of the opening 6a of the polycrystalline silicon film 6 and becomes the spacer 10a. Further, the etching back process by the RIE method is performed thereafter until a part of the polycrystalline silicon film 4 exposed through the opening 5a of the interelectrode insulating film 5 is partially removed to form the recess 4a.

  In this case, both the opening 5a of the interelectrode insulating film 5 and the recess 4a of the polycrystalline silicon film 4 are formed with the same width, and the silicon oxide film 10 with respect to the opening width W3 of the opening 6a of the polycrystalline silicon film 6 is formed. The first opening width W1 is narrowed by twice the film thickness d.

  Next, as shown in FIG. 8, for example, wet treatment (chemical solution treatment) is performed using a diluted hydrofluoric acid (HF) solution as a treatment liquid, and the spacers 10 a made of the silicon oxide film 10 are removed. As described above, the silicon oxide film 10 is formed under the condition that the etching rate is higher than that of the silicon oxide film included in the interelectrode insulating film 5 with respect to this processing solution. Therefore, the silicon oxide film 10 is removed in a relatively short time. At this time, when the interelectrode insulating film 5 located under the spacer 10a is exposed, a part of the silicon oxide film contained in the interelectrode insulating film 5 is removed, and the opening width is slightly widened. The opening 5a is a second opening width. W2. However, the etching rate of the silicon oxide film included in the interelectrode insulating film 5 is lower than the etching rate of the silicon oxide film 10. As a result, the opening width W2 is smaller than the opening width W3.

  Thus, the recess 4a of the polycrystalline silicon film 4 is formed with the first opening width W1, and the opening 5a of the interelectrode insulating film 5 is formed with the second opening width W2 wider than the first opening width W1. Furthermore, the opening 6a of the polycrystalline silicon film 6 has a stepped shape formed with a third opening width W3 wider than the second opening width W2. This wet treatment can be performed in the same step as the step of removing the natural oxide film formed on the surface of the polycrystalline silicon film 4 exposed in the recess 4a. As a result, the manufacturing process can be omitted.

  Next, as shown in FIG. 9, the upper surface of the polycrystalline silicon film 6, the sidewall surface of the opening 6 a, the upper surface in the vicinity of the opening 5 a of the interelectrode insulating film 5, the sidewall surface, and the vicinity of the recess 4 a of the polycrystalline silicon film 4. A tungsten nitride (WN) film 7 is formed as a barrier metal film with a predetermined film thickness on the upper and inner surfaces of the film by sputtering. In this case, the opening 6a of the polycrystalline silicon film 6, the opening 5a of the interelectrode insulating film 5, and the concave portion 4a of the polycrystalline silicon film 4 are in a state of being exposed stepwise, so that the openings 6a, 5a and the concave portion 4a It can be formed continuously on the side wall and bottom surface of the film, without causing step breakage.

  Thereafter, a tungsten film 8 is formed on the upper surface of the tungsten nitride film 7 so as to fill the openings 6a and 5a and the recess 4a. Further, a silicon nitride film 9 is formed on the upper surface. As a result, a film configuration to be a control gate electrode is formed.

  Thereafter, as shown in FIG. 3, a mask pattern is formed and gate processing is performed by the RIE method to form the gate electrode MG of the memory cell transistor Trm and the gate electrode SG of the selection gate transistor Trs, and a peripheral area not shown. A gate electrode of a circuit transistor is formed. After the gate processing, a silicon oxide film is formed on the side wall surfaces of the gate electrodes MG and SG, and further, impurities are introduced into the surface of the silicon substrate 2 between the gate electrodes MG and between the MG-SG by ion implantation to form source / drain. A diffusion region 2a to be a region is formed.

  Thereafter, an interlayer insulating film is further formed in the configuration shown in FIG. 3 so as to cover the gate electrodes MG and SG, and the NAND flash memory device 1 is subjected to a general process such as contact formation or wiring layer formation. A chip is formed.

  According to the first embodiment, in the gate electrode SG of the select gate transistor Trs, the openings 6a of the upper and lower polycrystalline silicon films 6 and 4 and the openings of the recesses 4a with respect to the opening 5a of the interelectrode insulating film 5. The width was formed as follows. That is, the opening width W3 of the opening 6a of the upper polycrystalline silicon film 6 is made larger than the opening width W2 of the opening 5a of the interelectrode insulating film 5 (W3> W2), and the recess of the lower polycrystalline silicon film 4 is formed. The opening width W1 of 4a was narrowed (W1 <W2). Thus, the openings 6a, 5a and the recess 4a are formed in a stepped shape in which the openings become narrower as going downward. Therefore, even when the tungsten nitride film 7 is formed in the openings 6a and 5a and the recess 4a, continuous film formation without disconnection in the opening 5a can be performed even if the tungsten nitride film 7 is formed by sputtering. As a result, when the tungsten film 8 is formed on the upper surface of the tungsten nitride film 7, problems such as the tungsten film 8 being in direct contact with the polycrystalline silicon film 6 and the polycrystalline silicon film 4 can be solved.

  Further, when the opening 5a is formed in the interelectrode insulating film 5 as described above, the polycrystalline silicon film 6 is removed by etching so that the interelectrode insulating film 5 is exposed, and the opening of the polycrystalline silicon film 6 is formed. The spacer 10a is formed on the side wall surface of 6a. As a result, the interelectrode insulating film 5 and the polycrystalline silicon film 4 are etched using the spacer 10a as a mask, so that the opening 5a and the recess 4a having a narrow opening width can be formed by the self-alignment method. Furthermore, the spacer 10a is formed of a material whose etching rate in the wet process is higher than the etching rate of the silicon oxide film included in the interelectrode insulating film 5, so that the interelectrode insulating film 5 is less retracted when removed. Can be processed.

(Second Embodiment)
FIGS. 10A and 10B show the second embodiment, and only the parts different from the first embodiment will be described below. In this embodiment, an example in which a taper shape is processed by an etching process such as the RIE method when performing a processing step in the same manner as in the first embodiment is shown.

  As shown in FIGS. 10A and 10B, the opening 6b of the polycrystalline silicon film 6 is formed in a shape having an inclined surface in which the side wall surface of the opening 6b becomes narrower downward. . That is, the opening 6b of the polycrystalline silicon film 6 is formed in a so-called tapered shape. Similarly, the opening 5b of the interelectrode insulating film 5 is formed in a tapered shape so that the opening width on the lower surface side is narrowed. The recess 4b of the polycrystalline silicon film 4 is also formed in a shape having a side wall surface having a taper, that is, a side wall surface whose width becomes narrower toward the bottom surface.

  In this embodiment, the opening width W3 of the opening 6b of the polycrystalline silicon film 6 indicates the width dimension at the upper surface portion, and the width dimension (W3−ΔW3) is slightly narrower as much as it is inclined at the lower surface portion. ). Similarly, the opening width W2 of the opening 5b of the interelectrode insulating film 5 indicates the width dimension at the upper surface portion, and is slightly narrower (W2−ΔW2) by the inclination at the lower surface portion. . Further, the opening width W1 of the recess 4b of the polycrystalline silicon film 4 indicates the width dimension at the upper surface portion, and is slightly narrower (W1-ΔW1) by the amount of inclination at the bottom surface portion. FIG. 10B is an example of an enlarged view of the portion surrounded by the alternate long and short dash line in FIG. 10A, and shows the positions corresponding to the above dimensions.

  The opening width W2 of the opening 5b of the interelectrode insulating film 5 is formed to be smaller than the opening width (W3-ΔW3) at the lower surface portion of the opening 6b of the polycrystalline silicon film 6 (W3-ΔW3>). W2). The opening width W1 of the recess 4b of the polycrystalline silicon film 4 is formed to be smaller than the opening width (W2-ΔW2) at the lower surface portion of the opening 5b of the interelectrode insulating film 5 (W2-ΔW2>). W1).

  The process sequence and the manufacturing method in the manufacturing process are performed in the same manner as in the first embodiment. However, in the etching process by the RIE method shown in FIG. 5 or FIG. 7, the etching process is performed under the condition that a slight taper is formed instead of the vertical direction. Regarding the formation of the tapered shape, the openings 6b, 5b and the recess 4b are formed so that the opening width of each part satisfies the above-described conditions.

  Therefore, also by such 2nd Embodiment, the effect similar to 1st Embodiment can be acquired. Since the openings 6b and 5b and the recess 4b are inclined, the formation of the tungsten nitride film 7 and the tungsten film 8 can be performed while preventing the step breakage. A continuous film can be formed. As a result, it is possible to employ a processing process in which the aspect ratio is reduced in the gate processing with the configuration based on the control gate electrode having a polymetal structure.

(Other embodiments)
The following modifications other than those described in the above embodiment can be made.
In the above embodiment, the opening width W3 of the opening 6a of the polycrystalline silicon film 6, the opening width 5a of the opening 5a of the interelectrode insulating film 5, and the opening width 4a of the recess 4a of the polycrystalline silicon film 4 are as follows. Although the formation of W3>W2> W1 has been described, a clear step-like structure is not necessarily formed. That is, the opening widths W3 and W2 may have substantially the same dimensions as long as the magnitude relationship is maintained. Similarly, the opening widths W2 and W1 may have substantially the same dimensions as long as the magnitude relationship is maintained.

  Although applied to the NAND flash memory device 1, the present invention can also be applied to a nonvolatile semiconductor memory device such as a NOR flash memory device or an EEPROM. Further, a memory cell configured as one bit or a plurality of bits can be applied.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. For example, the material of the metal film as the gate electrode is not limited to tungsten, and may be tantalum or titanium. In this case, the material of the barrier metal film is tantalum nitride or titanium nitride, respectively. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  In the drawings, 1 is a NAND flash memory device (semiconductor device), 2 is a silicon substrate (semiconductor substrate), 3 is a gate insulating film, 4 is a polycrystalline silicon film (first conductive film), 5 is an interelectrode insulating film, 6 is a polycrystalline silicon film (second conductive film), 7 is a tungsten nitride film (barrier metal film), 8 is a tungsten film (metal film), 10 is a silicon oxide film, 10a is a spacer, Trm is a memory cell transistor, Trs is a selection gate transistor, and MG and SG are gate electrodes.

Claims (5)

A semiconductor substrate;
A gate electrode formed on the upper surface of the semiconductor substrate via a gate insulating film,
The gate electrode is
A first conductive film formed on the gate insulating film and having a recess having a first opening width formed on the upper surface;
An inter-electrode insulating film formed on an upper surface of the first conductive film and having a silicon oxide film and having an opening having a second opening width wider than the first opening width at the position of the recess of the first conductive film;
A second conductive film formed on an upper surface of the interelectrode insulating film and having an opening having a third opening width wider than the second opening width at the position of the opening;
A top surface of the second conductive film and a side surface of the opening; a top surface and a side surface of the opening of the interelectrode insulating film; a barrier metal film having a predetermined thickness formed inside the recess of the first conductive film;
And a metal film formed so as to cover an upper surface of the barrier metal film. The semiconductor device according to claim 1,
The barrier metal film is continuously formed on an upper surface of the second conductive film and a side surface of the opening, an upper surface and a side surface of the opening of the interelectrode insulating film, and the inside of the recess of the first conductive film. A semiconductor device. The semiconductor device according to claim 1 or 2,
The semiconductor device according to claim 1, wherein a lower surface of the barrier metal film is lower than a lower surface of the interelectrode insulating film. Forming a gate insulating film, a first conductive film, an interelectrode insulating film having an oxide film, and a second conductive film on a semiconductor substrate;
Forming an opening in the second conductive film to expose an upper surface of the interelectrode insulating film;
Forming an oxide film along the upper surface of the second conductive film, the side wall surface of the opening, and the exposed upper surface of the interelectrode insulating film;
Etching the oxide film into a spacer shape, opening the interelectrode insulating film and forming a recess in the first conductive film;
Selectively removing the oxide film processed into the spacer shape;
Forming a barrier metal film so as to cover the upper surface of the second conductive film and the sidewall of the opening, the upper surface and sidewall of the insulating film between the electrodes, and the recess of the first conductive film, and further forming a metal film; A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device according to claim 4,
The method of manufacturing a semiconductor device, wherein, in the oxide film removing step, the etching rate of the oxide film is higher than the etching rate of the interelectrode insulating film.

Images