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Description
本開示は、高周波信号を出力する電圧制御発振器と、出力された前記高周波信号を分周した第１の分周信号を生成する第１の注入同期型分周器と、前記第１の分周信号を分周した第２の分周信号を生成する第２の注入同期型分周器と、前記第２の分周信号を分周した第３の分周信号を生成する分周器と、前記第３の分周信号と基準信号とを比較し、位相と周波数の誤差を出力する位相周波数比較器と、出力された前記誤差を電流又は電圧に変換するチャージポンプと、変換された前記電流又は電圧に応じて前記電圧制御発振器の制御電圧を生成し、生成された前記制御電圧を前記電圧制御発振器に印加するループフィルタと、前記電圧制御発振器の発振周波数を定める発振バンドを選択し、前記第１の注入同期型分周器及び前記第２の注入同期型分周器を異なる各動作帯域において動作させる、前記第１の注入同期型分周器の第１の制御パラメータ及び前記第２の注入同期型分周器の第２の制御パラメータを調整するキャリブレーション回路と、を備え、前記キャリブレーション回路は、前記第２の制御パラメータを調整した後に、前記第１の制御パラメータを調整し、更に、前記第３の分周信号に応じて前記電圧制御発振器の発振バンドを調整する、ＰＬＬ回路である。 The present disclosure includes a voltage-controlled oscillator that outputs a high-frequency signal, a first injection-locked frequency divider that generates a first frequency-divided signal obtained by dividing the output high-frequency signal, and the first frequency division A second injection-locked frequency divider that generates a second frequency-divided signal obtained by frequency-dividing the signal; a frequency-divider that generates a third frequency-divided signal obtained by frequency-dividing the second frequency-divided signal; comparing the third divided signal and the criteria signal, a phase frequency comparator to output an error of the phase and frequency, a charge pump for converting the outputted the error current or voltage, converted the A control voltage of the voltage controlled oscillator is generated according to current or voltage, a loop filter that applies the generated control voltage to the voltage controlled oscillator, and an oscillation band that determines an oscillation frequency of the voltage controlled oscillator are selected. Same as the first injection-locked frequency divider and the second injection Calibration that adjusts the first control parameter of the first injection-locked frequency divider and the second control parameter of the second injection-locked frequency divider that causes the mold frequency divider to operate in different operating bands. And the calibration circuit adjusts the first control parameter after adjusting the second control parameter, and further adjusts the voltage controlled oscillator according to the third frequency-divided signal. This is a PLL circuit that adjusts the oscillation band of.
また、本開示は、第１の注入同期型分周器と第２の注入同期型分周器とを接続したＰＬＬ回路におけるキャリブレーション方法であって、高周波信号を出力する電圧制御発振器及び前記第１の注入同期型分周器の各動作を停止するステップと、前記第２の注入同期型分周器の第２の制御パラメータに応じて、前記第２の注入同期型分周器の出力信号を分周する分周器が出力する分周信号と基準信号との各周波数を測定するステップと、測定された前記分周信号の周波数を基に、前記第２の制御パラメータを調整するステップと、前記第１の注入同期型分周器の停止を解除するステップと、前記第１の注入同期型分周器の第１の制御パラメータに応じて、前記第１の注入同期型分周器の出力信号を前記第２の注入同期型分周器が分周し、前記第２の注入同期型分周器の出力信号を分周する前記分周器により再度出力された分周信号の周波数を測定するステップと、測定後の前記再度出力された分周信号の周波数を基に、前記第１の制御パラメータを調整するステップと、前記電圧制御発振器の停止を解除するステップと、前記電圧制御発振器の発振周波数を定める発振バンドを選択するステップと、選択された前記発振バンドに応じて前記電圧制御発振器の出力信号が前記第１の注入同期型分周器、前記第２の注入同期型分周器及び前記分周器によって分周された分周信号の周波数を基に、前記電圧制御発振器の前記発振バンドを選択するステップと、を有する、キャリブレーション方法である。 The present disclosure is also a calibration method in a PLL circuit in which a first injection-locked frequency divider and a second injection-locked frequency divider are connected, and includes a voltage-controlled oscillator that outputs a high-frequency signal, and the first An output signal of the second injection-locked frequency divider according to a step of stopping each operation of the one injection-locked frequency divider and a second control parameter of the second injection-locked frequency divider based on the steps of dividing to the frequency divider to measure each frequency of the divided signal and the criteria signal you output, the frequency of the measured pre Symbol fraction No. ShuShin, the second control parameter Adjusting the first injection locking frequency divider, releasing the stop of the first injection locking frequency divider, and the first injection locking frequency according to a first control parameter of the first injection locking frequency divider The second injection-locked frequency divider divides the output signal of the mold divider, and the second The fraction and measuring the frequency of re-outputted min ShuShin No. by dividers, peripheral minute ShuShin No. said output again after measurement for dividing an output signal of the injection-locked frequency divider Adjusting the first control parameter based on the wave number; releasing the stop of the voltage controlled oscillator; selecting an oscillation band that determines an oscillation frequency of the voltage controlled oscillator; said output signal of said voltage controlled oscillator in response to the oscillation band first injection-locked frequency divider, circumference of divides signal which is divided by the second injection-locked frequency divider and the frequency divider Selecting the oscillation band of the voltage controlled oscillator based on the wave number.
Claims (11)
出力された前記高周波信号を分周した第１の分周信号を生成する第１の注入同期型分周器と、
前記第１の分周信号を分周した第２の分周信号を生成する第２の注入同期型分周器と、
前記第２の分周信号を分周した第３の分周信号を生成する分周器と、
前記第３の分周信号と基準信号とを比較し、位相と周波数の誤差を出力する位相周波数比較器と、
出力された前記誤差を電流又は電圧に変換するチャージポンプと、
変換された前記電流又は電圧に応じて前記電圧制御発振器の制御電圧を生成し、生成された前記制御電圧を前記電圧制御発振器に印加するループフィルタと、
前記電圧制御発振器の発振周波数を定める発振バンドを選択し、前記第１の注入同期型分周器及び前記第２の注入同期型分周器を異なる各動作帯域において動作させる、前記第１の注入同期型分周器の第１の制御パラメータ及び前記第２の注入同期型分周器の第２の制御パラメータを調整するキャリブレーション回路と、を備え、
前記キャリブレーション回路は、
前記第２の制御パラメータを調整した後に、前記第１の制御パラメータを調整し、更に、前記第３の分周信号に応じて前記電圧制御発振器の発振バンドを調整する、
ＰＬＬ回路。 A voltage controlled oscillator that outputs a high frequency signal;
A first injection-locked frequency divider that generates a first frequency-divided signal obtained by dividing the output high-frequency signal;
A second injection-locked frequency divider that generates a second frequency-divided signal obtained by dividing the first frequency-divided signal;
A frequency divider for generating a third divided signal obtained by dividing the second divided signal;
Comparing the third divided signal and the criteria signal, a phase frequency comparator to output an error of the phase and frequency,
A charge pump that converts the output error into a current or voltage;
A loop filter for generating a control voltage of the voltage controlled oscillator according to the converted current or voltage, and applying the generated control voltage to the voltage controlled oscillator;
The first injection that selects an oscillation band that determines the oscillation frequency of the voltage-controlled oscillator and operates the first injection-locked frequency divider and the second injection-locked frequency divider in different operating bands. A calibration circuit for adjusting a first control parameter of the synchronous frequency divider and a second control parameter of the second injection synchronous frequency divider,
The calibration circuit includes:
Adjusting the first control parameter after adjusting the second control parameter, and further adjusting the oscillation band of the voltage controlled oscillator according to the third frequency-divided signal;
PLL circuit.
前記キャリブレーション回路は、
前記高周波信号の分周に用い、かつ、温度変動に対応した、前記第１の制御パラメータを生成する第１のバイアス生成回路、を更に有する、
ＰＬＬ回路。 The PLL circuit according to claim 1,
The calibration circuit includes:
The used frequency division of the high frequency signal, and corresponding to the temperature variations, further comprising a first bias generating circuit, for generating the first control parameter,
PLL circuit.
前記キャリブレーション回路は、前記第３の分周信号と前記基準信号との各周波数を測定するクロックカウンタと、
前記高周波信号の分周に用い、温度変動に対応し、かつ、前記測定された第３の分周信号の周波数の調整に用いる前記第１の制御パラメータを生成する第１のバイアス生成回路、
を更に有する、
ＰＬＬ回路。 The PLL circuit according to claim 1,
The calibration circuit includes a clock counter that measures each frequency of the third divided signal and the reference signal;
It used to divide the radio frequency signal, corresponding to the temperature variation, and a first bias generating for generating said first control parameter used for adjusting the frequency of the third frequency-divides signal which is the measuring circuit,
Further having
PLL circuit.
前記キャリブレーション回路は、
前記第２の制御パラメータとして、前記第１の分周信号の分周に用いる制御パラメータを生成する第２のバイアス生成回路と、
前記第２の制御パラメータとして、温度変動に対応して、前記第１の分周信号の分周に用いる制御パラメータを生成する第３のバイアス生成回路と、
前記第２のバイアス生成回路による第２の制御パラメータ又は前記第３のバイアス生成回路による第２の制御パラメータを選択するバイアス選択回路と、を更に有する、
ＰＬＬ回路。 The PLL circuit according to claim 1,
The calibration circuit includes:
A second bias generation circuit for generating a control parameter used for frequency division of the first frequency-divided signal as the second control parameter;
As the second control parameter, in response to temperature variation, and a third bias generating circuit for generating a control parameter used for dividing the first divided signal,
A bias selection circuit for selecting a second control parameter by the second bias generation circuit or a second control parameter by the third bias generation circuit;
PLL circuit.
前記キャリブレーション回路は、
前記第２の制御パラメータに応じて、前記第３の分周信号と前記基準信号との各周波数を測定するクロックカウンタと、
前記第２の制御パラメータとして、前記第１の分周信号の分周に用い、かつ、前記測定された第３の分周信号の周波数の調整に用いる制御パラメータを生成する第２のバイアス生成回路と、
前記第２の制御パラメータとして、温度変動に対応して、前記第１の分周信号の分周に用い、かつ、前記測定された第３の分周信号の周波数の調整に用いる制御パラメータを生成する第３のバイアス生成回路と、
前記第２のバイアス生成回路による第２の制御パラメータ又は前記第３のバイアス生成回路による第２の制御パラメータを選択するバイアス選択回路と、を更に有する、
ＰＬＬ回路。 The PLL circuit according to claim 1,
The calibration circuit includes:
A clock counter in response to said second control parameter, measuring each frequency between the third divided signal and the reference signal,
Wherein as the second control parameter, the first reference to the division of the divided signal and the second bias generating a control parameter used for adjusting the frequency of the third frequency-divides signal which is the measuring A generation circuit;
As the second control parameter, in response to temperature variation, using the division of the first divided signal and the control used to adjust the frequency of the third frequency-divides signal which is the measuring A third bias generation circuit for generating parameters;
A bias selection circuit for selecting a second control parameter by the second bias generation circuit or a second control parameter by the third bias generation circuit;
PLL circuit.
前記キャリブレーション回路は、
前記第１の制御パラメータの設定値として、温度変動に対応して生成された前記第１の制御パラメータの初期値と、調整後の前記第２の制御パラメータと調整前の前記第２の制御パラメータとの差分と一定係数との乗算値と、一定定数との加算結果を用いる、
ＰＬＬ回路。 A PLL circuit according to claim 3 or 4,
The calibration circuit includes:
As a setting value of the first control parameter, and the initial value of the first control parameter generated in response to temperature variation, the second control parameter after adjustment and before adjustment of the second control Use the result of adding the difference between the parameter and the constant value and the constant value,
PLL circuit.
前記キャリブレーション回路は、
前記電圧制御発振器の動作を制御するＶＣＯ制御部と、
前記第１の注入同期型分周器及び前記第２の注入同期型分周器の各動作を制御するＩＬＦＤ制御部と、を更に有し、
前記ＶＣＯ制御部は、
前記ＩＬＦＤ制御部が前記第１の制御パラメータ及び前記第２の制御パラメータを調整する場合に、前記電圧制御発振器を停止する、
ＰＬＬ回路。 A PLL circuit according to any one of claims 1 to 6,
The calibration circuit includes:
A VCO controller that controls the operation of the voltage controlled oscillator;
An ILFD controller that controls each operation of the first injection-locked frequency divider and the second injection-locked frequency divider;
The VCO control unit
Stopping the voltage controlled oscillator when the ILFD control unit adjusts the first control parameter and the second control parameter;
PLL circuit.
前記ＶＣＯ制御部は、
前記第１の制御パラメータの調整後に、前記電圧制御発振器の停止を解除し、前記電圧制御発振器の発振周波数を定める前記発振バンドを選択する、
ＰＬＬ回路。 The PLL circuit according to claim 7, wherein
The VCO control unit
After the adjustment of the first control parameter, the stop of the voltage controlled oscillator is released, and the oscillation band that determines the oscillation frequency of the voltage controlled oscillator is selected.
PLL circuit.
前記ＶＣＯ制御部は、
選択された前記発振バンドに応じて前記電圧制御発振器からの前記高周波信号が前記第１の注入同期型分周器、前記第２の注入同期型分周器及び前記分周器によって分周された分周信号と前記基準信号との各周波数差分に応じて、前記電圧制御発振器の他の前記発振バンドを選択する、
ＰＬＬ回路。 The PLL circuit according to claim 7, wherein
The VCO control unit
The high-frequency signal from the voltage controlled oscillator is divided by the first injection-locked frequency divider, the second injection-locked frequency divider, and the frequency divider according to the selected oscillation band. According to each frequency difference between the frequency-divided signal and the reference signal, the other oscillation band of the voltage-controlled oscillator is selected.
PLL circuit.
高周波信号を出力する電圧制御発振器及び前記第１の注入同期型分周器の各動作を停止するステップと、
前記第２の注入同期型分周器の第２の制御パラメータに応じて、前記第２の注入同期型分周器の出力信号を分周する分周器が出力する分周信号と基準信号との各周波数を測定するステップと、
測定された前記分周信号の周波数を基に、前記第２の制御パラメータを調整するステップと、
前記第１の注入同期型分周器の停止を解除するステップと、
前記第１の注入同期型分周器の第１の制御パラメータに応じて、前記第１の注入同期型分周器の出力信号を前記第２の注入同期型分周器が分周し、前記第２の注入同期型分周器の出力信号を分周する前記分周器により再度出力された分周信号の周波数を測定するステップと、
測定後の前記再度出力された分周信号の周波数を基に、前記第１の制御パラメータを調整するステップと、
前記電圧制御発振器の停止を解除するステップと、
前記電圧制御発振器の発振周波数を定める発振バンドを選択するステップと、
選択された前記発振バンドに応じて前記電圧制御発振器の出力信号が前記第１の注入同期型分周器、前記第２の注入同期型分周器及び前記分周器によって分周された分周信号の周波数を基に、前記電圧制御発振器の前記発振バンドを選択するステップと、を有する、
キャリブレーション方法。 A calibration method in a PLL circuit in which a first injection locked frequency divider and a second injection locked frequency divider are connected,
Stopping each operation of the voltage controlled oscillator that outputs a high frequency signal and the first injection-locked frequency divider;
The second implant in accordance with the second control parameter of a synchronous divider, the second injection the output signal of a synchronous divider dividing to divider you output divided signal and standards Measuring each frequency with the signal;
Based on the frequency of the measured pre Symbol fraction No. ShuShin, and adjusting the second control parameter,
Releasing the stop of the first injection-locked frequency divider;
In response to the first control parameter of the first injection-locked frequency divider, the second injection-locked frequency divider divides the output signal of the first injection-locked frequency divider, measuring the frequency of said frequency divider by dividing ShuShin No. outputted again for dividing an output signal of the second injection-locked frequency divider,
Based on the frequency of the minute ShuShin No. said output again after measurement, and adjusting the first control parameter,
Releasing the stop of the voltage controlled oscillator;
Selecting an oscillation band defining an oscillation frequency of the voltage controlled oscillator;
Frequency division by which the output signal of the voltage controlled oscillator is divided by the first injection locked frequency divider, the second injection locked frequency divider, and the frequency divider according to the selected oscillation band. based on the frequency of the signal, and a step of selecting the oscillation band of the voltage controlled oscillator,
Calibration method.
ベースバンドの送信信号を変調する変調部と、
前記ＰＬＬ回路が生成した第１局部信号と変調された前記送信信号とを用いて、高周波送信信号を生成する送信ミキサと、
前記ＰＬＬ回路が生成した第２局部信号と受信された高周波受信信号とを用いて、ベースバンドの受信信号を生成する受信ミキサと、
生成された前記ベースバンドの受信信号を復調する復調部と、を備える、
無線通信装置。 A PLL circuit according to any one of claims 1 to 9,
A modulation unit that modulates a baseband transmission signal;
A transmission mixer that generates a high-frequency transmission signal using the first local signal generated by the PLL circuit and the modulated transmission signal;
A reception mixer that generates a baseband reception signal using the second local signal generated by the PLL circuit and the received high-frequency reception signal;
A demodulator that demodulates the generated baseband received signal,
Wireless communication device.
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| JP2013088849A JP6252888B2 (en) | 2013-04-19 | 2013-04-19 | PLL circuit, calibration method, and wireless communication apparatus |
| PCT/JP2014/001897 WO2014171086A1 (en) | 2013-04-19 | 2014-03-31 | Pll circuit, calibration method, and wireless communication device |
| US14/409,239 US9438301B2 (en) | 2013-04-19 | 2014-03-31 | PLL circuit, calibration method, and wireless communication apparatus |
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| US7557664B1 (en) * | 2005-10-31 | 2009-07-07 | University Of Rochester | Injection-locked frequency divider |
| JP2008236557A (en) | 2007-03-22 | 2008-10-02 | Toshiba Corp | Frequency synthesizer and radio communication apparatus using same |
| US7856212B2 (en) * | 2007-08-07 | 2010-12-21 | Intel Corporation | Millimeter-wave phase-locked loop with injection-locked frequency divider using quarter-wavelength transmission line and method of calibration |
| WO2012120795A1 (en) * | 2011-03-07 | 2012-09-13 | パナソニック株式会社 | Pll circuit, calibration method and wireless communication terminal |
| US9191056B2 (en) | 2012-03-21 | 2015-11-17 | Panasonic Corporation | PLL circuit, calibration method, and wireless communication apparatus |
-
2013
- 2013-04-19 JP JP2013088849A patent/JP6252888B2/en not_active Expired - Fee Related
-
2014
- 2014-03-31 US US14/409,239 patent/US9438301B2/en not_active Expired - Fee Related
- 2014-03-31 WO PCT/JP2014/001897 patent/WO2014171086A1/en active Application Filing
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