JP2014211881A5 - - Google Patents

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Publication number
JP2014211881A5
JP2014211881A5 JP2014121814A JP2014121814A JP2014211881A5 JP 2014211881 A5 JP2014211881 A5 JP 2014211881A5 JP 2014121814 A JP2014121814 A JP 2014121814A JP 2014121814 A JP2014121814 A JP 2014121814A JP 2014211881 A5 JP2014211881 A5 JP 2014211881A5
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JP
Japan
Prior art keywords
instruction
pipeline
instructions
operable
branch instruction
Prior art date
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Application number
JP2014121814A
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English (en)
Japanese (ja)
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JP2014211881A (ja
JP6208084B2 (ja
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Publication date
Priority claimed from US11/626,443 external-priority patent/US7624254B2/en
Application filed filed Critical
Publication of JP2014211881A publication Critical patent/JP2014211881A/ja
Publication of JP2014211881A5 publication Critical patent/JP2014211881A5/ja
Application granted granted Critical
Publication of JP6208084B2 publication Critical patent/JP6208084B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2014121814A 2007-01-24 2014-06-12 誤予測された分岐のためにフラッシュするセグメント化パイプライン Expired - Fee Related JP6208084B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/626,443 2007-01-24
US11/626,443 US7624254B2 (en) 2007-01-24 2007-01-24 Segmented pipeline flushing for mispredicted branches

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP2012133878A Division JP5866259B2 (ja) 2007-01-24 2012-06-13 誤予測された分岐のためにフラッシュするセグメント化パイプライン

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2016082077A Division JP6370829B2 (ja) 2007-01-24 2016-04-15 誤予測された分岐のためにフラッシュするセグメント化パイプライン

Publications (3)

Publication Number Publication Date
JP2014211881A JP2014211881A (ja) 2014-11-13
JP2014211881A5 true JP2014211881A5 (enExample) 2015-05-21
JP6208084B2 JP6208084B2 (ja) 2017-10-04

Family

ID=39327442

Family Applications (4)

Application Number Title Priority Date Filing Date
JP2009547432A Pending JP2010517183A (ja) 2007-01-24 2008-01-24 誤予測された分岐のためにフラッシュするセグメント化パイプライン
JP2012133878A Expired - Fee Related JP5866259B2 (ja) 2007-01-24 2012-06-13 誤予測された分岐のためにフラッシュするセグメント化パイプライン
JP2014121814A Expired - Fee Related JP6208084B2 (ja) 2007-01-24 2014-06-12 誤予測された分岐のためにフラッシュするセグメント化パイプライン
JP2016082077A Expired - Fee Related JP6370829B2 (ja) 2007-01-24 2016-04-15 誤予測された分岐のためにフラッシュするセグメント化パイプライン

Family Applications Before (2)

Application Number Title Priority Date Filing Date
JP2009547432A Pending JP2010517183A (ja) 2007-01-24 2008-01-24 誤予測された分岐のためにフラッシュするセグメント化パイプライン
JP2012133878A Expired - Fee Related JP5866259B2 (ja) 2007-01-24 2012-06-13 誤予測された分岐のためにフラッシュするセグメント化パイプライン

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2016082077A Expired - Fee Related JP6370829B2 (ja) 2007-01-24 2016-04-15 誤予測された分岐のためにフラッシュするセグメント化パイプライン

Country Status (10)

Country Link
US (1) US7624254B2 (enExample)
EP (1) EP2115572B1 (enExample)
JP (4) JP2010517183A (enExample)
KR (1) KR101107812B1 (enExample)
CN (1) CN101601009B (enExample)
BR (1) BRPI0807405A2 (enExample)
CA (1) CA2674720C (enExample)
MX (1) MX2009007949A (enExample)
RU (1) RU2427889C2 (enExample)
WO (1) WO2008092045A1 (enExample)

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US7624254B2 (en) * 2007-01-24 2009-11-24 Qualcomm Incorporated Segmented pipeline flushing for mispredicted branches
US9384003B2 (en) * 2007-10-23 2016-07-05 Texas Instruments Incorporated Determining whether a branch instruction is predicted based on a capture range of a second instruction
US7877586B2 (en) * 2008-02-01 2011-01-25 International Business Machines Corporation Branch target address cache selectively applying a delayed hit
US8099586B2 (en) * 2008-12-30 2012-01-17 Oracle America, Inc. Branch misprediction recovery mechanism for microprocessors
US20110320787A1 (en) * 2010-06-28 2011-12-29 Qualcomm Incorporated Indirect Branch Hint
EP2588952A4 (en) 2010-06-29 2017-10-04 Exxonmobil Upstream Research Company Method and system for parallel simulation models
US8862861B2 (en) 2011-05-13 2014-10-14 Oracle International Corporation Suppressing branch prediction information update by branch instructions in incorrect speculative execution path
US8886920B2 (en) 2011-05-13 2014-11-11 Oracle International Corporation Associating tag to branch instruction to access array storing predicted target addresses for page crossing targets for comparison with resolved address at execution stage
CN102360282A (zh) * 2011-09-26 2012-02-22 杭州中天微系统有限公司 快速处置分支指令预测错误的流水线处理器装置
CN103974857B (zh) 2011-11-29 2017-10-27 提爱思科技股份有限公司 安装部件及安全气囊模块装备座椅
US9268569B2 (en) * 2012-02-24 2016-02-23 Apple Inc. Branch misprediction behavior suppression on zero predicate branch mispredict
CN105164637B (zh) * 2013-05-30 2017-12-19 英特尔公司 用于执行循环的方法、系统、装置和处理器以及机器可读介质
US9792252B2 (en) 2013-05-31 2017-10-17 Microsoft Technology Licensing, Llc Incorporating a spatial array into one or more programmable processor cores
US10191747B2 (en) 2015-06-26 2019-01-29 Microsoft Technology Licensing, Llc Locking operand values for groups of instructions executed atomically
US10409599B2 (en) 2015-06-26 2019-09-10 Microsoft Technology Licensing, Llc Decoding information about a group of instructions including a size of the group of instructions
US10175988B2 (en) 2015-06-26 2019-01-08 Microsoft Technology Licensing, Llc Explicit instruction scheduler state information for a processor
US9952867B2 (en) 2015-06-26 2018-04-24 Microsoft Technology Licensing, Llc Mapping instruction blocks based on block size
US10409606B2 (en) 2015-06-26 2019-09-10 Microsoft Technology Licensing, Llc Verifying branch targets
US10346168B2 (en) 2015-06-26 2019-07-09 Microsoft Technology Licensing, Llc Decoupled processor instruction window and operand buffer
US9946548B2 (en) 2015-06-26 2018-04-17 Microsoft Technology Licensing, Llc Age-based management of instruction blocks in a processor instruction window
US10169044B2 (en) 2015-06-26 2019-01-01 Microsoft Technology Licensing, Llc Processing an encoding format field to interpret header information regarding a group of instructions
US9720693B2 (en) 2015-06-26 2017-08-01 Microsoft Technology Licensing, Llc Bulk allocation of instruction blocks to a processor instruction window
US10255074B2 (en) 2015-09-11 2019-04-09 Qualcomm Incorporated Selective flushing of instructions in an instruction pipeline in a processor back to an execution-resolved target address, in response to a precise interrupt

Family Cites Families (10)

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SU1300471A1 (ru) * 1985-11-01 1987-03-30 Предприятие П/Я Г-4677 Устройство дл выполнени условных переходов в конвейерном процессоре
US5694564A (en) * 1993-01-04 1997-12-02 Motorola, Inc. Data processing system a method for performing register renaming having back-up capability
DE69425311T2 (de) * 1993-10-18 2001-03-15 National Semiconductor Corp.(N.D.Ges.D.Staates Delaware), Santa Clara Mikroprozessor mit spekulativer Befehlsausführung
ES2138051T3 (es) * 1994-01-03 2000-01-01 Intel Corp Metodo y aparato para la realizacion de un sistema de resolucion de bifurcaciones en cuatro etapas en un procesador informatico.
US5627985A (en) * 1994-01-04 1997-05-06 Intel Corporation Speculative and committed resource files in an out-of-order processor
US5586278A (en) * 1994-03-01 1996-12-17 Intel Corporation Method and apparatus for state recovery following branch misprediction in an out-of-order microprocessor
US7496734B1 (en) * 2000-04-28 2009-02-24 Stmicroelectronics, Inc. System and method for handling register dependency in a stack-based pipelined processor
JP3667703B2 (ja) * 2002-03-18 2005-07-06 エヌイーシーコンピュータテクノ株式会社 エラー訂正制御回路
US7152155B2 (en) * 2005-02-18 2006-12-19 Qualcomm Incorporated System and method of correcting a branch misprediction
US7624254B2 (en) * 2007-01-24 2009-11-24 Qualcomm Incorporated Segmented pipeline flushing for mispredicted branches

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