JP2014207319A - Semiconductor element manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor element manufacturing method which can improve characteristics of a semiconductor element using an oxide semiconductor.SOLUTION: A semiconductor element manufacturing method comprises: forming a gate electrode on a substrate; forming a gate insulation film on the gate electrode; forming an oxide semiconductor layer on the gate insulation film; performing a first heat treatment at a temperature of not less than 350°C and not more than 400°C on a laminate from the substrate to the oxide semiconductor layer; forming a source electrode and a drain electrode on the oxide semiconductor layer after the first heat treatment; and subsequently performing a second heat treatment at a temperature lower than that in the first heat treatment on a laminate from the substrate to the source electrode and the drain electrode.

Description

  The present invention relates to a method for manufacturing a semiconductor element formed by stacking thin films on a substrate.

In a semiconductor element using an oxide semiconductor for a channel layer, heat treatment is often used in order to improve characteristics of the semiconductor element.
In Patent Document 1, in a method for manufacturing a thin film transistor using an oxide semiconductor, first heat treatment at 350 ° C. to 1000 ° C. is performed after the oxide semiconductor layer is formed, and 150 ° C. or higher after the thin film transistor is formed. It is described that the second heat treatment at 500 ° C. or lower is performed.
In Patent Document 2, after an oxide semiconductor layer is formed, first heat treatment is performed at 400 ° C. to 750 ° C., and after an insulating layer containing oxygen in contact with the oxide semiconductor layer is formed, 200 ° C. to 450 ° C. It is described that a second heat treatment at a temperature of less than or equal to ° C. is performed, and a third heat treatment at a temperature of 150 to 450 ° C. is performed after an insulating layer containing hydrogen is formed.
Patent Document 3 describes that after the oxide semiconductor layer is formed, water or hydrogen contained in the oxide semiconductor layer is removed by heat treatment.

JP 2011-142111 A JP 2011-142309 A JP 2012-9844 A

However, when the temperature of the heat treatment for the oxide semiconductor is too high, desorption of oxygen in the oxide semiconductor is likely to occur. When such desorption occurs, carriers in the oxide semiconductor increase and the resistance decreases too much, thereby causing a problem that leakage current at the time of off increases.
Further, when an oxide semiconductor containing Zn such as amorphous IGZO as an oxide semiconductor is subjected to heat treatment at a high temperature, detachment of Zn is likely to occur. Similarly, even when an oxide semiconductor containing a Group 12 element (Cd, Hg, Cn) is used, the Group 12 element is likely to be detached although there is a slight temperature difference. When such desorption occurs, carriers in the oxide semiconductor increase and the resistance decreases too much, thereby causing a problem that leakage current at the time of off increases.
In particular, when heat treatment is performed on amorphous IGZO at a high temperature, IGZO is microcrystallized and the surface becomes rough, variation in characteristics within the surface, and coverage with an electrode or a protective insulating layer covering the IGZO layer decreases. There is a fear.

  An object of the present invention is to provide a method for manufacturing a semiconductor element that can reduce leakage current of a semiconductor element using an oxide semiconductor and improve characteristics (switching characteristics).

  In order to solve the above problems, the present invention is a method for manufacturing a semiconductor device, wherein a gate electrode is formed on a substrate, a gate insulating film is formed on the gate electrode, and an oxide semiconductor is formed on the gate insulating film. A first heat treatment is performed on the stacked body from the substrate to the oxide semiconductor layer at a temperature of 350 ° C to 400 ° C, and after the first heat treatment, the oxide semiconductor layer A source electrode and a drain electrode are formed thereon, and then a second heat treatment is performed on the stacked body from the substrate to the source electrode and the drain electrode at a temperature lower than the first heat treatment. Features.

  After the first heat treatment, the oxide semiconductor film is preferably etched to form an oxide semiconductor layer, and a source electrode and a drain electrode are formed over the oxide semiconductor layer.

  The oxide semiconductor layer is preferably made of IGZO (In—Ga—Zn—O).

Said composition of IGZO _{is In-Ga x -Zn y -O z} (0.8 ≦ x ≦ 1.2,0.8 ≦ y ≦ 1.2,3.2 ≦ z ≦ 4.8) Is preferred. That is, when In is 1, a composition in which Ga is 0.8 to 1.2, Zn is 0.8 to 1.2, and O is 3.2 to 4.8 is preferable.

  The first heat treatment is preferably performed in an atmosphere having an oxygen concentration of 10% to 18%.

  According to the method for manufacturing a semiconductor element of the present invention, it is possible to obtain a semiconductor element having low leakage current and good characteristics (switching characteristics).

It is a schematic perspective view which shows the structure of the semiconductor element of embodiment. It is a perspective view which shows the state which formed the gate layer on the board | substrate. It is a perspective view which shows the state which formed the gate electrode on the board | substrate. It is a perspective view which shows the state in which the gate insulating film was formed. It is a perspective view which shows the state in which the oxide semiconductor layer was formed. FIG. 10 is a perspective view illustrating a state where an oxide semiconductor film is formed. It is a perspective view which shows the state which formed the contact hole in the gate insulating film. It is a perspective view which shows the state in which the electrode layer was formed. It is a figure which shows the Id-Vg characteristic for every temperature of 1st annealing. It is a figure which shows the Id-Vg characteristic for every oxygen concentration in a 1st annealing atmosphere.

(Configuration of semiconductor element)
First, the configuration of the semiconductor element of this embodiment will be described with reference to FIG. FIG. 1 is a schematic perspective view showing an example of the semiconductor element of this embodiment. The semiconductor element 10 according to the present embodiment is formed on one surface of the substrate 1 and includes a gate electrode 11G, a gate insulating film 12, an oxide semiconductor film 14, a source electrode 15S, a drain electrode 15D, and a gate. The lead electrode 15G and the like are roughly configured. In the following description, the surface of the substrate 1 on which the semiconductor element 10 is formed is the upper surface.

Any material that is not a conductor can be used for the substrate 1. For example, a dielectric substrate such as a glass substrate, a semiconductor substrate, or the like can be used. In particular, it is preferable to use a substrate having high heat resistance.
Further, as the substrate 1, a conductor plate having an insulating layer formed on one surface may be used. In this case, the gate electrode 11G may be formed on the surface of the substrate 1 on which the insulating layer is formed.
The gate electrode 11G is formed on the substrate 1. A conductive material having a high melting point (for example, 2000 ° C. or higher) can be used for the gate electrode 11G. In particular, it is preferable to use a metal excellent in high-temperature strength, such as tungsten (W), molybdenum (Mo), molybdenum tungsten (MoW), or the like.

The gate insulating film 12 is formed on the entire surface of the substrate 1 so as to cover the gate electrode 11G. An arbitrary insulator can be used for the gate insulating film 12, for example, a metal oxide such as Al ₂ O ₃ and HfO ₂ , a metal nitride, silicon dioxide, silicon nitride, or the like can be used. In particular, it is preferable to use an insulating material having high heat resistance.
In the gate insulating film 12, a contact hole 12C is provided at a position overlapping the gate electrode 11G and spaced from the oxide semiconductor film 14, the source electrode 15S, and the drain electrode 15D. A gate extraction electrode 15G is provided on the upper surface of the gate insulating film 12 in the contact hole 12C and in the vicinity of the contact hole 12C.

The oxide semiconductor film 14 is formed on the top surface of the gate insulating film 12 so as to overlap with the gate electrode 11G. For example, an amorphous oxide semiconductor can be used for the oxide semiconductor film 14. For example, amorphous IGZO (In—Ga—Zn—O) or the like can be used. The composition of the amorphous IGZO _{is In-Ga x -Zn y -O z} (0.8 ≦ x ≦ 1.2,0.8 ≦ y ≦ 1.2,3.2 ≦ z ≦ 4.8) Is preferred. That is, when In is 1, a composition in which Ga is 0.8 to 1.2, Zn is 0.8 to 1.2, and O is 3.2 to 4.8 is preferable. With this composition, the number of carriers in the oxide semiconductor layer falls within an appropriate range, and a semiconductor element with favorable characteristics can be obtained.

The source electrode 15S and the drain electrode 15D are provided on the upper surface of the oxide semiconductor film 14 so as to sandwich the gate electrode 11 when viewed from the upper surface.
The gate lead electrode 15G, the source electrode 15S, and the drain electrode 15D can be made of any material (eg, metal) as long as it is a conductor. The conductor used for the gate extraction electrode 15G, the source electrode 15S, and the drain electrode 15D may have a lower melting point than the conductor used for the gate electrode 11G. For example, titanium (Ti), aluminum (Al), molybdenum (Mo), gold (Au), platinum (Pt), tin-doped indium oxide (ITO), or the like can be used.

(Semiconductor element manufacturing method)
Next, a method for forming the semiconductor element 10 of the present embodiment will be described with reference to FIGS.

1. Formation of Gate Electrode First, as shown in FIG. 2, a gate layer 11 is formed on the entire top surface of the substrate 1. The gate layer 11 can be formed by any vapor deposition method such as EB (Electron Beam) vapor deposition or sputtering.
Next, the gate layer 11 is patterned to form a gate electrode 11G as shown in FIG. The patterning of the gate electrode 11G can be performed by dry etching, wet etching, or the like.
Instead of forming the gate layer 11 on the entire upper surface of the substrate 1, the pattern of the gate electrode 11G may be formed directly on the upper surface of the substrate 1 by mask vapor deposition, or the gates other than the gate electrode 11G may be formed by lift-off. The layer 11 may be peeled off.

2. Formation of Gate Insulating Film Next, as shown in FIG. 4, a gate insulating film 12 covering the upper surface of the substrate 1 and the gate electrode 11G is formed. The gate insulating film 12 may be formed by any gas such as physical vapor deposition (PVD) such as sputtering, chemical vapor deposition (CVD), and atomic layer deposition (ALD). It can be formed by a phase deposition method.

3. Formation of Oxide Semiconductor Layer Next, as illustrated in FIG. 5, the oxide semiconductor layer 13 is formed over the gate insulating film 12. The oxide semiconductor layer 13 can be formed by any vapor deposition method such as CVD or vapor deposition.

4). First annealing (first heat treatment)
Next, first annealing is performed on the stacked body from the substrate 1 to the oxide semiconductor layer 13. The first annealing may be performed at 350 ° C. to 400 ° C., for example, in an atmosphere having an oxygen concentration of 10 to 18% or more, preferably 10 to 15%, and a pressure of atmospheric pressure or higher (atmospheric pressure is 101.25 hPa). Is heated to 375 ° C. to 400 ° C. and maintained for a predetermined period, for example, 5 minutes to 120 minutes, preferably 30 minutes to 80 minutes, particularly preferably 60 minutes. Accordingly, the density of the oxide semiconductor layer 13 is increased, the carrier mobility is increased, and the carrier density can be made appropriate.

Note that when the oxygen concentration is lower than 10%, desorption of oxygen in the oxide semiconductor is likely to occur. In the case where such desorption occurs, although the number of carriers in the oxide semiconductor increases and the mobility of carriers increases, there is a problem in that the resistance decreases too much and the leakage current at the time of off increases.
On the other hand, when the oxygen concentration is higher than 18%, oxygen in the oxide semiconductor is excessively increased, the number of carriers in the oxide semiconductor layer is decreased, and the resistance may be excessively increased. In addition, since the oxide semiconductor subjected to the first annealing at an oxygen concentration higher than 18% is oxygen-rich, oxygen is easily desorbed. For this reason, there is a possibility that the electrical characteristics change greatly due to the desorption of oxygen in the second annealing described later, and the reliability during operation of the device incorporating the manufactured semiconductor element may be reduced.

In order to improve the characteristics of the semiconductor element by annealing, the annealing temperature is preferably set to 350 ° C. or higher. When the annealing temperature is less than 350 ° C., there is a problem that the carrier mobility is low and the resistance is too high.
Note that when the annealing temperature exceeds 400 ° C., desorption of oxygen in the oxide semiconductor tends to occur. In the case where such desorption occurs, although the number of carriers in the oxide semiconductor increases and the mobility of carriers increases, there is a problem in that the resistance decreases too much and the leakage current at the time of off increases. For this reason, it is preferable that an annealing temperature is 400 degrees C or less.
Further, in an oxide semiconductor containing Zn such as amorphous IGZO as an oxide semiconductor, Zn is easily detached at 450 ° C. or higher. Similarly, even when an oxide semiconductor containing a Group 12 element (Cd, Hg, Cn) is used, the Group 12 element is likely to be detached although there is a slight temperature difference. In the case where such desorption occurs, although the number of carriers in the oxide semiconductor increases and the mobility of carriers increases, there is a problem in that the resistance decreases too much and the leakage current at the time of off increases.
In particular, when amorphous IGZO is used as the oxide semiconductor, if the annealing temperature is 500 ° C. or higher, IGZO is microcrystallized and the surface becomes rough. As a result, the in-plane characteristics may vary. Moreover, there is a possibility that the coverage with an electrode layer 15 and a protective insulating layer which will be described later is lowered.

5. Next, as shown in FIG. 6, the oxide semiconductor layer 13 is patterned to form an oxide semiconductor film 14. The oxide semiconductor layer 13 can be patterned by wet etching, dry etching, or the like. Note that in the case where the oxide semiconductor layer 13 is patterned after the first annealing, the oxide semiconductor 13 is stabilized by the first annealing, and a characteristic change due to moisture hardly occurs when wet etching is performed. In addition, when performing dry etching, it is difficult to be damaged by plasma, and characteristics are hardly changed. Therefore, when the first annealing is performed before the oxide semiconductor layer 13 is etched, the change in characteristics due to the etching is reduced as compared with the case where the first annealing is performed after the oxide semiconductor layer 13 is etched. There is an advantage that you can.
Next, as shown in FIG. 7, a contact hole 12 </ b> C that exposes the gate electrode 11 </ b> G is formed in the gate insulating film 12. The contact hole 12C can be formed by wet etching, dry etching, or the like.

6). Next, as shown in FIG. 8, an electrode layer 15 is formed on the entire surface so as to cover the gate electrode 11G, the gate insulating film 12, and the oxide semiconductor film 14 exposed from the contact hole 12C. Next, the electrode layer 15 is patterned to form a source electrode 15S, a drain electrode 15D, and a gate lead electrode 15G as shown in FIG. The patterning of the electrode layer 15 can be performed by dry etching, wet etching, or the like.
Instead of patterning the electrode layer 15 to form the source electrode 15S, the drain electrode 15D, and the gate extraction electrode 15G, the source electrode 15S, the drain electrode 15D, and the gate extraction electrode 15G are directly formed by mask vapor deposition. May be. Further, the electrode layer 15 other than the source electrode 15S, the drain electrode 15D, and the gate extraction electrode 15G may be peeled off by lift-off.

7). Second annealing (second heat treatment)
Next, the second annealing is performed on the stacked body from the substrate 1 to the source electrode 15S, the drain electrode 15D, and the gate extraction electrode 15G. In the second annealing, for example, in an inert gas atmosphere (for example, a nitrogen atmosphere) having an oxygen concentration of less than 10% and atmospheric pressure, the second annealing is performed at a lower temperature (for example, 200 ° C. to 300 ° C.) than the first annealing. The period is maintained, for example, 5 minutes to 2 hours, preferably 1 hour. Thus, a Schottky junction between the oxide semiconductor film 14 and the source electrode 15S and the drain electrode 15D is formed as an ohmic junction. Note that at a temperature lower than 200 ° C., the Schottky barrier does not disappear and the ohmic junction is not sufficiently formed. On the other hand, at a temperature higher than 300 ° C., diffusion of the material of the source electrode 15S and the drain electrode 15D and the oxide semiconductor film 14 occurs, and the material of the source electrode 15S and the drain electrode 15D is oxidized by oxygen in the oxide semiconductor film 14. May increase resistance.
Note that the above steps can be performed continuously in the same film forming apparatus.

  Thereafter, formation of wiring and a protective insulating layer (passivation layer), dicing, and packaging are performed as necessary. Thus, a semiconductor element is formed.

  According to the present invention, after the oxide semiconductor film is formed, the first annealing is performed at a temperature of 350 ° C. or higher and 400 ° C. or lower, thereby improving the characteristics of the oxide semiconductor film, reducing leakage current, and switching characteristics. A good semiconductor element can be obtained. In addition, after the first annealing, the electrode is formed, and then the second annealing is performed at a temperature lower than that of the first annealing, thereby forming an ohmic junction between the oxide semiconductor film and the electrode, and further, current-voltage characteristics. Can be improved.

[Example 1]
Hereinafter, examples of the present invention will be described in more detail.
A gate electrode made of Mo and a gate insulating film made of SiO ₂ were formed on a glass substrate.
Next, an oxide semiconductor layer made of IGZO was formed by sputtering. An oxide semiconductor target having a composition ratio of In: Ga: Zn: O = 1: 1: 1: 4 was used as a target, and the target was used in a mixed atmosphere of 5% oxygen and 95% rare gas at a pressure of 0.4 Pa. Sputtering was performed by applying a 13.56 MHz radio frequency (RF) 200 W to form an amorphous IGZO layer having a thickness of 60 nm.
Next, first annealing was performed for 1 hour in an atmosphere having an oxygen concentration of 10% and atmospheric pressure. The temperature was heated to 350 ° C, 375 ° C, 400 ° C, 425 ° C, or 450 ° C.
Next, the oxide semiconductor layer was patterned by etching to form a source electrode, a drain electrode, and a gate extraction electrode made of Ti.
Next, second annealing was performed at 300 ° C. for 1 hour in a nitrogen atmosphere and atmospheric pressure.
Thereafter, formation of a wiring and a protective insulating layer (passivation layer), dicing, and packaging were performed to form a semiconductor element.

[Evaluation of Id-Vg characteristics]
A voltage (Vds) of 5 V was applied between the source and drain of the manufactured semiconductor element, and a gate voltage (Vg) and a source-drain current (Id) were measured. The results are shown in FIG.

As shown in FIG. 9, in the semiconductor element in which the first annealing temperature was 450 ° C., the threshold voltage was −20 V, and the Id-Vg characteristics were not good.
In the semiconductor element in which the temperature of the first annealing was 350 ° C. to 425 ° C., the threshold voltage was 0 V or more, and the Id-Vg characteristics were good. Furthermore, in the semiconductor element in which the temperature of the first annealing was 350 ° C. to 375 ° C., the threshold voltage was 0 V to 2 V, and the Id-Vg characteristics were good.
In addition, although the Id-Vg characteristic was evaluated also about the semiconductor element which performed the 1st annealing above 475 degreeC, the favorable result was not obtained.

[Example 2]
A semiconductor element was manufactured in the same manner as in Example 1 except for the conditions for the first annealing.
In the first annealing, the first annealing was performed for 1 hour in an atmosphere having an oxygen concentration of 0%, 10%, 20%, 50%, or 100%. The temperature was heated to 375 ° C.

[Evaluation of Id-Vg characteristics]
As in Example 1, a voltage (Vds) of 5 V was applied between the source and drain of the manufactured semiconductor element, and the gate voltage (Vg) and the source-drain current (Id) were measured. The results are shown in FIG.

As shown in FIG. 10, the threshold voltage was about +8 V in the semiconductor element subjected to the first annealing in an atmosphere with an oxygen concentration of 0%, and the Id−Vg characteristics were not good. In the semiconductor element subjected to the first annealing in an atmosphere having an oxygen concentration of 10%, the threshold voltage was 0 V and the Id-Vg characteristics were good.
In each of the semiconductor elements subjected to the first annealing in an atmosphere having an oxygen concentration of 20%, 50%, and 100%, the threshold voltage was -3V and the Id-Vg characteristics were not good.

  As mentioned above, although the manufacturing method of the semiconductor element of this invention was demonstrated in detail, this invention is not limited to the said embodiment. It goes without saying that various improvements and modifications may be made without departing from the spirit of the present invention.

DESCRIPTION OF SYMBOLS 1 Substrate 10 Semiconductor element 11 Gate layer 11G Gate electrode 12 Gate insulating film 12C Contact hole 13 Oxide semiconductor layer 14 Oxide semiconductor film 15 Electrode layer 15S Source electrode 15D Drain electrode 15G Gate extraction electrode

Claims (5)

A method for manufacturing a semiconductor device, comprising:
Forming a gate electrode on the substrate;
Forming a gate insulating film on the gate electrode;
Forming an oxide semiconductor film on the gate insulating film;
A first heat treatment is performed on the stacked body from the substrate to the oxide semiconductor film at a temperature of 350 ° C. or higher and 400 ° C. or lower,
After the first heat treatment, a source electrode and a drain electrode are formed over the oxide semiconductor film,
Thereafter, a second heat treatment is performed on the stacked body from the substrate to the source electrode and the drain electrode at a temperature lower than that of the first heat treatment. After the first heat treatment, the oxide semiconductor film is etched to form an oxide semiconductor layer,
The method for manufacturing a semiconductor device according to claim 1, wherein a source electrode and a drain electrode are formed on the oxide semiconductor layer.   The method for manufacturing a semiconductor element according to claim 1, wherein the oxide semiconductor layer is made of IGZO (In—Ga—Zn—O). Said composition of IGZO _{is In-Ga x -Zn y -O z} (0.8 ≦ x ≦ 1.2,0.8 ≦ y ≦ 1.2,3.2 ≦ z ≦ 4.8) The method of manufacturing a semiconductor device according to claim 3, wherein: 5. The method of manufacturing a semiconductor element according to claim 1, wherein the first heat treatment is performed in an atmosphere having an oxygen concentration of 10% to 18%.

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