JP2014202989A - Image forming apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image forming apparatus that improves resolution in determining a change in detection values of the capacity between an image carrier and a developer carrier, so as to prevent periodic fluctuations in image density and roughening of images and thereby maintaining constant image quality.SOLUTION: An image forming apparatus includes a photoreceptor drum 1, a developing sleeve 4a, a CPU 311, an AC amplifier circuit 306. The image forming apparatus applies, to the developing sleeve 4a, a developing bias voltage forming a developing electric field between the photoreceptor drum 1 and developing sleeve 4a, with an AC high-voltage drive circuit 301, an AC transformer 302, and a DC high-voltage circuit 303; detects the capacity between the photoreceptor drum 1 and developing sleeve 4a with a p-p voltage detection circuit 304; and amplifies a change in detection signal indicating the capacity detected by the AC amplifier circuit 306. The CPU 311 changes conditions to perform image formation including development on the basis of the amplified change in the capacity detection signal.

Description

The present invention relates to an image forming apparatus that forms an image by development.

  2. Description of the Related Art Conventionally, in an image forming apparatus that forms an image using an electrophotographic method or an image forming apparatus that forms an image using an electrostatic recording method, a developer of a developing device is applied to an image carrier (photosensitive drum) that carries an electrostatic latent image. In general, development is carried out in correspondence with the carried developer carrier (developing sleeve). When developing, a developing bias voltage is applied to the developing sleeve in order to form a developing electric field between the photosensitive drum and the developing sleeve.

  As the developing bias voltage, for example, as shown in FIG. 21, a developing bias voltage in which an AC (alternating current) component is superimposed on a DC (direct current) component is used. That is, the AC component rectangular wave of the development bias voltage (also referred to as a rectangular bias voltage) conventionally has a frequency of about 2 kHz (1/2 period = 250 μsec) and a peak-to-peak voltage (Vp-p) of about 2 kV. Things are used.

  As for development using a two-component developer composed of a toner and a carrier (two-component development), for example, as shown in FIG. 16, a technique using a development bias voltage in which an AC component is intermittently superimposed on a DC component is proposed. ing. The development bias voltage (also referred to as a blank pulse bias voltage (BP bias voltage)) shown in FIG. 22 includes a pulse portion and a pause portion (blank portion).

  In the image forming apparatus, a predetermined gap (hereinafter referred to as an SD gap) is provided between the photosensitive drum and the developing sleeve. In order to maintain the SD gap, a configuration in which an abutting roller provided at an end of the developing sleeve is abutted against the surface of the photosensitive drum, or a configuration in which a spacer is fixed between the rotating shaft of the developing sleeve and the rotating shaft of the photosensitive drum Have taken.

  However, in the configuration in which the abutting roller provided at the end of the developing sleeve is abutted against the surface of the photosensitive drum, the SD gap is different for each image forming apparatus due to the variation in the diameter of the abutting roller and the variation in the size of the spacer. However, there is a problem that the average value varies statically. Originally, the nominal value of the SD gap, which is the central value in design, is very narrow, for example, 300 μm, and may vary by about ± 20% due to variations due to component tolerances. Further, the manufacturing accuracy of the abutting roller or the developer or the like adheres to the abutting roller, so that the diameter of the abutting roller partially changes, and the SD gap changes dynamically in the time period of one abutting roller. There are fluctuations.

  On the other hand, in the configuration in which the spacer is fixed between the rotating shaft of the developing sleeve and the rotating shaft of the photosensitive drum, the fluctuation of the SD gap is observed in the photosensitive drum cycle due to the eccentric component of the photosensitive drum surface with respect to the rotating shaft of the photosensitive drum. It is done. Further, in both configurations, there is also an SD gap fluctuation in one cycle of the developing sleeve due to the eccentricity or bending component of the developing sleeve.

  In the two-component development using the two-component developer composed of toner and carrier, when the SD gap is statically or dynamically narrowed, the high-voltage (hereinafter referred to as high voltage) development bias voltage becomes narrower. When applied, the electric field in the SD gap becomes very large. As a result, abnormal discharge due to conductive foreign matter mixed in the developing device is likely to occur, and a ring-like spot is formed on the image, resulting in a problem that the image quality is remarkably deteriorated. On the other hand, when the SD gap is widened, the developability is lowered, and the density of the image is reduced and the image is rough.

  On the other hand, in one-component jumping development using a one-component developer made of toner containing a magnetic material, development is performed using a phenomenon in which the developer flies by an electric field between the developing sleeve and the photosensitive drum. In the one-component jumping development, there is a problem that the image density changes as a result of the electric field being different depending on the width of the SD gap. Therefore, if there is a dynamic variation of the SD gap, the image density is low where the SD gap is wide, the image density is high where the SD gap is narrow, and band-like shading occurs in the image. There's a problem.

  As a countermeasure to these problems, a technique has been proposed in which the electrostatic capacity between the photosensitive drum and the developing sleeve that changes according to the size of the SD gap is detected, and the image forming conditions are changed (for example, patents). Reference 1). According to the proposal of Patent Document 1, an average value of the SD gap is detected as an electrostatic capacity, and an image such as a developing AC bias voltage, a developing DC bias voltage, a charging DC bias voltage, and a laser light amount is detected according to the capacitance value. Change any of the formation conditions. Further, it has been proposed to store dynamic fluctuations of the SD gap and dynamically change the image forming conditions in accordance with the fluctuations.

JP 2009-300932 A

  However, the above prior art has the following problems. When the capacitance of the SD gap is detected and the dynamic variation of the detected value is used for changing the image forming condition, the amount of change in the detected value due to the dynamic variation is very small. For this reason, the resolution when the A / D conversion circuit tries to read the change once is reduced. In addition, when the dynamic fluctuation of the detection value is directly fed back to, for example, the development DC bias voltage, it is necessary to enlarge or reduce the change of the detection signal so as to act on the output setting signal of the development DC bias voltage. Although there is no method disclosed.

  The object of the present invention is to improve the resolution when determining the change in the detected value of the capacitance between the image carrier and the developer carrier, thereby preventing periodic image density fluctuations and image roughness, An object of the present invention is to provide an image forming apparatus capable of maintaining a constant image quality.

  In order to achieve the above object, the present invention provides an image carrier that carries an electrostatic latent image, and a developer that develops the electrostatic latent image that is disposed opposite the image carrier and carried on the image carrier. An image forming apparatus for forming an image by developing the electrostatic latent image with the developer, wherein the development is performed between the image carrier and the developer carrier. An application unit that applies a developing bias voltage that forms an electric field to the developer carrier, a detection unit that detects a capacitance between the image carrier and the developer carrier, and a capacitance detected by the detection unit. Amplifying means for amplifying the change of the detection signal shown, and control means for changing the conditions for image formation including the development based on the change of the capacitance detection signal amplified by the amplifying means. To do.

  According to the present invention, the conditions for image formation including development are changed based on the change in the capacitance detection signal obtained by amplifying the change in the detection signal indicating the capacitance between the image carrier and the developer carrier. . That is, by enlarging the change in the detection signal based on the dynamic change in the capacity, it is possible to sample the change in the detection signal with high resolution and high accuracy. Then, the conditions for image formation are changed based on the dynamic change of the capacity. As a change in the conditions for image formation, for example, the development voltage is increased when the voltage of the capacitance detection signal is large, and the development voltage is decreased when the voltage of the capacitance detection signal is small. As a result, it is possible to prevent periodic fluctuations in image density and image roughness and to maintain a constant image quality.

1 is a configuration diagram illustrating a configuration of an image forming apparatus according to a first embodiment of the present invention. FIG. 3 is a configuration diagram illustrating a state where a rotating shaft of a photosensitive drum and a rotating shaft of a developing sleeve are positioned by a spacer. FIG. 2 is a block diagram illustrating configurations of a development high-voltage substrate and a control substrate of the image forming apparatus. It is a figure which shows the relationship between the magnitude | size of SD gap, and Sig3 capacity | capacitance detection DC signal. It is a figure which shows the example which the voltage of the Sig3 capacity | capacitance detection DC signal is fluctuate | varied by dynamic SD fluctuation | variation. It is a detailed circuit diagram of an AC amplifier circuit. It is a figure which shows Sig4 capacity | capacitance detection AC signal. It is a figure which shows Sig3 capacity | capacitance detection DC signal and Sig4 capacity | capacitance detection AC signal. 6 is a flowchart illustrating processing related to acquisition of an SD gap profile of the image forming apparatus. It is a figure which shows Sig3 capacity | capacitance detection DC signal and Sig4 capacity | capacitance detection AC signal. It is a figure which shows Sig4 capacity | capacitance detection AC signal profile, a latent image potential, development DC high voltage | pressure, and a drum HP signal. FIG. 10 is a configuration diagram illustrating a state where a rotating shaft of a photosensitive drum and a rotating shaft of a developing sleeve are positioned by a roller according to a second embodiment of the present invention. FIG. 2 is a block diagram illustrating configurations of a development high-voltage substrate and a control substrate of the image forming apparatus. It is a figure which shows the relationship between the magnitude | size of SD gap, and Sig3 capacity | capacitance detection DC signal. It is a detailed circuit diagram of an AC amplifier circuit. It is a figure which shows Sig3 capacity | capacitance detection DC signal and Sig4 capacity | capacitance detection AC signal. 6 is a flowchart illustrating processing related to acquisition of an average SD gap value of the image forming apparatus. It is a figure which shows Sig3 capacity | capacitance detection DC signal and Sig4 capacity | capacitance detection AC signal. It is a flowchart which shows the process which changes image formation conditions using the detected capacity | capacitance fluctuation | variation. It is a figure which shows the example by which a Sig5 development DC control signal is also changed dynamically by the fluctuation | variation of dynamic SD capacity | capacitance. It is a figure which shows the example of the developing bias voltage which superimposed the AC component on the DC component. It is a figure which shows the example of the developing bias voltage comprised from the pulse part and the rest part.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[First Embodiment]
In the first embodiment of the present invention, a dynamic variation profile of the SD gap capacity between a photosensitive drum and a developing sleeve of an image forming apparatus that forms an image by electrophotography is detected and stored in advance. A method of changing the image forming condition using the detection result at the time of image formation will be described.

  FIG. 1 is a configuration diagram showing a configuration centering on a photosensitive drum and a developing device of an image forming apparatus according to a first embodiment of the present invention.

  In FIG. 1, the image forming apparatus has a structure in which a primary charger 2, a developing device 4, a transfer charger 5, a cleaning unit 6, and a pre-exposure unit 11 are arranged around a photosensitive drum 1. The image forming apparatus performs electrophotographic image formation in which a toner image obtained by developing an electrostatic latent image formed on the photosensitive drum 1 is transferred to a sheet. The photosensitive drum 1 is an image carrier that carries an electrostatic latent image, and is driven to rotate in the direction of arrow R by a drive mechanism (not shown). In the charging step, the surface of the photosensitive drum 1 is uniformly charged by the primary charger 2. In the exposure process, laser light L corresponding to the image to be formed is exposed to the surface of the photosensitive drum 1 by a laser driving unit (not shown), and an electrostatic latent image is formed.

  The developing device 4 includes a developing sleeve 4a, a developing screw 4b, and a developing screw 4c, and stores a two-component developer containing a carrier and toner, and develops an electrostatic latent image on the surface of the photosensitive drum. The developing sleeve 4 a is a developer carrying member that carries the developer, and is disposed to face the photosensitive drum 1. In the developing process, a developing bias voltage is applied from the developing high-voltage substrate (see FIG. 3) to the developing sleeve 4a in order to form a developing electric field between the photosensitive drum 1 and the developing sleeve 4a. Accordingly, the electrostatic latent image formed on the surface of the photosensitive drum 1 is developed by the developing device 4 and visualized as a toner image. In this embodiment, the toner is charged with a negative polarity.

  In the transfer process, the toner image on the photosensitive drum is transferred by the transfer charger 5 to the paper transported by a paper transport mechanism (not shown). Transfer residual toner on the photosensitive drum is removed by a cleaning unit 6 having a cleaning blade pressed against the photosensitive drum 1. The sheet on which the toner image is transferred is conveyed to a fixing device (not shown). In the fixing process, the toner image on the paper is fixed by the fixing device. The sheet on which the toner image is fixed is discharged out of the apparatus. Thereafter, the photosensitive drum 1 is discharged by the pre-exposure unit 11 and used for image formation again.

  FIG. 2 is a configuration diagram illustrating a state in which the rotating shaft of the photosensitive drum and the rotating shaft of the developing sleeve according to the first embodiment are positioned by the spacer.

  In FIG. 2, a rotating shaft 1 a and a bearing 1 b that rotatably support the photosensitive drum 1 are provided at the center of the photosensitive drum 1. In addition, a rotation shaft 4d and a bearing 4e that rotatably support the developing sleeve 4a are provided at the center of the developing sleeve 4a. A spacer 20 is fixed between the outer periphery of the bearing 1b of the photosensitive drum 1 and the outer periphery of the bearing 4e of the developing sleeve 4a. Thus, the spacer 20 is positioned between the rotating shaft 1a of the photosensitive drum 1 and the rotating shaft 4d of the developing sleeve 4a.

  In this embodiment, the distance (SD gap: interval) between the photosensitive drum 1 positioned by the spacer 20 and the developing sleeve 4a is set to a nominal value of 300 μm. In this example, there is a possibility that the SD gap is shifted by ± 10%, that is, ± 30 μm as an average value due to tolerances, and further has a maximum fluctuation of ± 5%, that is, ± 15 μm due to the eccentricity of the photosensitive drum 1.

  A home position (hereinafter referred to as HP) flag 21 is provided at the end of the photosensitive drum 1 in the axial direction. An HP sensor 22 is disposed in the vicinity of the photosensitive drum 1. The HP sensor 22 reads the HP flag 21 and outputs an HP signal indicating that the HP of the photosensitive drum 1 has been detected to the CPU (FIG. 3).

  In the standard state, in the charging process, the surface of the photosensitive drum 1 is charged to, for example, −600 V by the primary charger 2. The potential of an electrostatic latent image (latent image portion) formed on the surface of the photosensitive drum 1 by laser light is −150V. By applying −400 V to the developing sleeve 4a as a developing DC bias voltage that is a DC component of the developing bias voltage, a contrast potential Vcont (between the latent image portion of the photosensitive drum 1 and the developing sleeve 4a) for determining the image density is applied. Potential) is 250V. Further, the fog removal potential Vback for preventing fog (a phenomenon in which toner scatters to a portion other than the latent image portion) is 200V.

  In the present embodiment, the BP bias voltage shown in FIG. 22 is used as the development bias voltage. By adding an AC component (AC bias) to a DC component (DC bias), it becomes possible to suppress the roughness of the image and to obtain a sufficient image density. When the SD gap is a nominal value, Vp-p of the pulse portion of the development AC bias voltage that is the AC component of the development bias voltage is 2 kV. When the SD gap is a nominal value, the capacitive load between the photosensitive drum 1 and the developing sleeve 4a is 350 pF.

  FIG. 3 is a block diagram illustrating the configuration of the development high-voltage substrate and the control substrate of the image forming apparatus. The configuration shown in FIG. 3 is an example for realizing the application means, detection means, control means, and amplification means of the present invention.

  In FIG. 3, the image forming apparatus is equipped with a development high-voltage substrate 300 and a control substrate 310. An AC high voltage drive circuit 301 (application unit), an AC transformer 302 (application unit), a DC high voltage circuit 303 (application unit), and a pp voltage detection circuit 304 (detection unit) are mounted on the development high voltage substrate 300. . Further, an LPF (low-pass filter) 305, an AC amplifier circuit 306 (amplifying means, limiting means, shortening means), a capacitor C1, a capacitor C2, and an output resistor are mounted on the development high-voltage substrate 300. An A / D conversion circuit 314, a D / A conversion circuit 312, a D / A conversion circuit 313, a CPU 311 (control unit), and a memory 315 are mounted on the control board 310.

  In the development high-voltage substrate 300, the AC high-voltage drive circuit 301 drives the AC transformer 302 to generate a development AC bias voltage corresponding to the Sig1Vp-p setting signal, and supplies it to the development sleeve 4a. The DC high voltage circuit 303 generates a development DC bias voltage corresponding to the Sig2 development DC setting signal and supplies the development DC bias voltage to the development sleeve 4a. As a result, a developing bias voltage that forms a developing electric field between the photosensitive drum 1 and the developing sleeve 4a is applied to the developing sleeve 4a. The pp voltage detection circuit 304 converts the peak-to-peak voltage (pp voltage) across the capacitor C2 into a DC voltage. The DC voltage is input to the LPF 305 and extracted as a Sig3 capacitance detection DC signal. Thereby, the capacity between the photosensitive drum 1 and the developing sleeve 4a is detected.

  The Sig3 capacitance detection DC signal is further input to an AC amplifier circuit 306, and the AC component is amplified and output as a Sig4 capacitance detection AC signal (capacitance detection signal). The cut-off frequency of the LPF 305 is set to, for example, about 20 Hz as a frequency at which the development AC bias voltage frequency of 2 kHz does not pass and the fluctuation of the Sig3 capacitance detection DC signal due to dynamic SD fluctuation can pass. Yes.

  In the control board 310, the A / D conversion circuit 314 is a circuit having a 10-bit resolution. The Sig3 capacity detection DC signal and the Sig4 capacity detection AC signal, which are two capacity detection signals output from the development high voltage board 300, are converted into analog signals. To digital signal. The D / A conversion circuit 312 outputs an analog voltage Sig1Vp-p setting signal for controlling the developing AC bias voltage generated by the AC high voltage driving circuit 301 driving the AC transformer 302 based on the setting of the CPU 311. The D / A conversion circuit 313 outputs an analog voltage Sig2 development DC setting signal for controlling the DC voltage output from the DC high voltage circuit 303 based on the setting of the CPU 311.

  The CPU 311 stores the detected change in the capacity between the photosensitive drum 1 and the developing sleeve 4 a in the memory 315. Also, the CPU 311 is based on the Sig3 capacity detection DC signal and the Sig4 capacity detection AC signal, in other words, on the basis of the average value of the photosensitive drum-developing sleeve capacity (development capacity) and the fluctuation profile, and the conditions for image formation including development. Change (image forming condition: image forming condition). The image forming conditions include a peak-to-peak value (p-p value) of the developing AC bias voltage, a voltage value of the developing DC bias voltage, and a charging DC bias voltage that is a DC component of the charging bias voltage for charging the photosensitive drum 1. And the amount of laser light for exposing the photosensitive drum 1.

  The operation unit 316 is used for various displays in the image forming apparatus and various settings for the image forming apparatus. The operation unit 316 is also used for displaying the capacity between the detected photosensitive drum 1 and the developing sleeve 4a, setting image forming conditions, and the like.

  The secondary side of the AC transformer 302 is a capacity voltage dividing circuit divided into a load capacity CL, which is a capacity between the photosensitive drum 1 and the developing sleeve 4a, and capacitors C1 and C2. When the load capacitance CL is a nominal value of 350 pF, the impedance of the capacitor is the reciprocal of the capacitance. Accordingly, the peak-to-peak voltage (pp voltage): Vp-p applied to both ends of the capacitor C2 in the development AC bias voltage is calculated as 2 kV × 297 pF / 0.27 uF = 2.6 V. Since the pp voltage detection circuit detects the pp voltage across the capacitor C2 with a diode, the output of the pp voltage detection circuit is reduced by two of the forward voltage Vf of the diode.

  The present applicant performed the following measurement by preparing and replacing a spacer having a different length as the spacer 20 disposed between the photosensitive drum 1 and the developing sleeve 4a. That is, when the SD gap was increased or decreased from the nominal value of 300 μm and the development AC bias voltage of 2 kVp-p was applied and the voltage of the Sig3 capacitance detection DC signal was measured, the result shown in FIG. 4 was obtained.

  FIG. 4 is a diagram showing the relationship between the size of the SD gap, which is the distance between the photosensitive drum 1 and the developing sleeve 4a, and the Sig3 capacity detection DC signal.

  FIG. 4 shows that the capacitance between the photosensitive drum and the developing sleeve changes almost in inverse proportion to the SD gap, and as a result, the voltage of the Sig3 capacitance detection DC signal decreases as the SD gap widens. That is, it is possible to detect the distance of the SD gap by the Sig3 capacitance detection DC signal.

  In the state where the photosensitive drum 1 rotates through the rotating shaft 1a and the developing sleeve 4a rotates through the rotating shaft 4d, the SD gap varies (moves) due to the eccentric components of the photosensitive drum 1 and the developing sleeve 4a. S-D fluctuation).

  FIG. 5 is a diagram illustrating an example in which the voltage of the Sig3 capacitance detection DC signal varies due to dynamic SD variation.

  In FIG. 5, the solid line is a detection waveform of the voltage of the Sig3 capacitance detection DC signal, and the black dot is a sample of the voltage of the Sig3 capacitance detection DC signal. A broken line is an average value, and a pulse waveform is an HP signal. The degree of influence on the dynamic SD fluctuation is largely due to the eccentricity of the photosensitive drum 1. Due to the eccentricity of the developing sleeve 4a, the amplitude is small and the cycle is short.

  The change width of the voltage of the Sig3 capacitance detection DC signal due to dynamic S-D fluctuation is only about 50 mV. For this reason, if this is detected by the A / D conversion circuit 314 using 3.3 V as a reference voltage, there is only a change width of 15 LSB (resolution), and the dynamic change profile cannot be read accurately. Therefore, the fluctuation component is amplified by the AC amplifier circuit 306.

  FIG. 6 is a detailed circuit diagram of the AC amplifier circuit 306 of FIG.

  6, the AC amplifier circuit 306 includes an HPF (High Pass Filter) 701, a differential amplifier circuit 702, an upper limiter 703, and a lower limiter 704. The Sig3 capacitance detection DC signal is input to the HPF 701, and DC frequency components and low frequency temperature drift components such as a pp detection circuit are removed. C701, C702, R705, and R706 are capacitors and resistors that determine the cutoff frequency of the HPF 701. Resistor R706 is DC biased to Vref2. Vref is a reference voltage for generating Vref1, 2, and 3.

  The differential amplifier circuit 702 constitutes an amplifier circuit with an amplification factor of 20 and amplifies the differential voltage between the outputs of Vref1 and HPF701. The upper limiter 703 limits the maximum voltage of the capacitor C701 to Vref3. The lower limiter 704 limits the minimum voltage of the capacitor C701 to Vref1. Vref1, 2, and 3 are 1.125V, 1.2V, and 1.275V, respectively. Since the differential amplifier circuit 702 amplifies the difference voltage between Vref2 and Vref1 in terms of DC, it outputs 1.5V, which is 20 times 0.075V. That is, the Sig4 capacitance detection AC signal is output with a waveform in which 20 times the change of the Sig3 capacitance detection DC signal is superimposed around 1.5V.

  FIG. 7 is a diagram showing a Sig4 capacitance detection AC signal obtained by amplifying the waveform of the Sig3 capacitance detection DC signal shown in FIG.

  In FIG. 7, the change width of about 50 mV is amplified to about 1 V, and becomes an AC signal of ± 0.5 V centering on 1.5 V. The voltage range of the capacitor C701 in FIG. 6 is limited by the upper limiter 703 and the lower limiter 704. The voltage of the lower limiter 704 is the same voltage as the negative voltage of the differential amplifier circuit 702. Therefore, even when a large input change is input from the Sig3 capacitance detection DC signal, the output voltage range of the Sig4 capacitance detection AC signal is limited to a range of 0V to 3.0V.

  Next, the effects of the upper limiter 703 and the lower limiter 704 described above will be described with reference to FIG.

  FIG. 8 is a diagram showing the Sig3 capacitance detection DC signal and the Sig4 capacitance detection AC signal when the development AC bias voltage is turned on while the rotation of the photosensitive drum 1 and the development sleeve 4a are stopped.

  In FIG. 8, the Sig3 capacitance detection DC signal is 0 V when the development AC bias voltage is off, but when the development AC bias voltage is turned on, it becomes a substantially constant value according to the capacity of the SD gap. The solid line of the Sig4 capacitance detection AC signal is the output from the circuit of this embodiment. When the Sig3 capacitance detection DC signal rises, the signal is swung to the plus side and the minus side, but the range is limited to a range of 0V to 3V by the action of the upper limiter 703 and the lower limiter 704, and a constant value (1.5V) The time t1 to converge to is short. That is, the time for the capacitance detection signal to converge to a constant value is shortened.

  The broken line of the Sig4 capacitance detection AC signal is a waveform when the upper limiter 703 and the lower limiter 704 are not provided. When the output of the Sig3 capacitance detection DC signal rises, the output greatly rises to the vicinity of the power supply voltage of the differential amplifier circuit 702, then swings to the negative side, sticks to 0 V for a while, and takes a very long time t2 to converge to a constant value. During the time t2, the Sig4 capacitance detection AC signal is rampant, and the signal value cannot be sampled and used. Due to the effects of the upper limiter 703 and the lower limiter 704, the time t2 is shortened to the time t1, and the waiting time until the start of sampling can be shortened.

  FIG. 9 is a flowchart illustrating processing related to acquisition of the SD gap profile of the image forming apparatus.

  In FIG. 9, the CPU 311 of the control board 310 sets the Vp-p setting of the development AC bias voltage to an initial value of 2 kV (step S101). Next, the CPU 311 turns on the output of the AC high voltage drive circuit 301 that supplies a high voltage to the developing sleeve 4a, and turns on the rotational driving of the photosensitive drum 1 and the developing sleeve 4a (step S102). Here, it waits for time t1 until the Sig4 capacitance detection AC signal is stabilized (step S103). The CPU 311 reads the Sig3 capacity detection DC signal and the Sig4 capacity detection AC signal via the A / D conversion circuit 314 in a state where the photosensitive drum 1 and the developing sleeve 4a are rotationally driven.

  The CPU 311 performs sampling of the Sig4 capacity detection AC signal for four photosensitive drums at each of eight points divided, for example, into eight equal parts per round of the photosensitive drum based on the output pulse of the drum HP sensor 22. Further, the CPU 311 performs a process of averaging the values of the sampled Sig4 capacitance detection AC signal for four points, and stores the processing result in the memory 315. In this way, the eight points per round of the photosensitive drum are averaged for the four rounds of the photosensitive drum. As a result, the CPU 311 removes minute shakes caused by other than eccentricity of the photosensitive drum 1 (for example, eccentricity of the developing sleeve 4a), and a dynamic SD fluctuation profile (SD gap). Profile is acquired (step S104).

  The CPU 311 obtains the next average value in parallel with the sampling of the Sig4 capacitance detection AC signal to acquire the dynamic SD fluctuation profile. Sampling of the Sig3 capacity detection DC signal is performed for four rotations of the photosensitive drum, and an average value of all the sampling results is obtained for this (step S104). This average value represents whether the SD gap is near static or far. Finally, the CPU 311 stores the acquired data in the memory 315 (step S105).

  FIG. 10 is a diagram illustrating examples of waveforms of the development AC bias, the Sig3 capacitance detection DC signal, and the Sig4 capacitance detection AC signal when acquiring the SD gap profile.

  In FIG. 10, a waveform obtained by amplifying the Sig3 capacitance detection DC signal by 20 times is seen in the Sig4 capacitance detection AC signal. However, since the waveform is not stable during the time t1 after the development AC bias voltage is turned on, the CPU 311 Sampling is started after elapse of t1. The image is formed by changing the image forming conditions using the static SD average value (Sig3 capacitance detection DC signal) and the dynamic SD fluctuation profile (Sig4 capacitance detection AC signal) obtained in the process of FIG. Form.

  First, when the average voltage of the Sig3 capacitance detection DC signal is larger than the voltage when the SD gap is the nominal value, the SD gap is small and the image density is high. Therefore, in order to reduce the contrast potential according to the difference from the nominal voltage, the average value of the development DC voltage is changed from the reference value of −400V to −380V, for example. As a result, the difference from the latent image potential of −150 V is changed from 250 V to 230 V. At the same time, the charging potential is set to −580 V and the fog removal potential of 200 V is maintained.

  Also, if the SD gap is small, the frequency of image defects due to ring-shaped spots formed by abnormal discharge increases. For this reason, the Vp-p voltage value of the development AC bias is reduced to, for example, 1.8 kVp-p according to the difference from the standard value of 2 kVp-p to the nominal voltage, thereby reducing the occurrence frequency of image defects. When the average voltage of the Sig3 capacitance detection DC signal is smaller than the voltage when the SD gap is the nominal value, the reverse control is performed.

  Next, as shown in FIG. 11, the following control is performed using the profile of the dynamic SD fluctuation obtained using the Sig4 capacitance detection AC signal. With reference to the signal (pulse) of the HP sensor 22 that detects the HP of the photosensitive drum 1, the development DC voltage is increased when the voltage of the Sig4 capacitance detection AC signal is large, and the development is developed when the voltage of the Sig4 capacitance detection AC signal is small. Dynamically controlled to lower the DC voltage. As a result, the contrast potential is decreased when the SD gap is close and the image density is high, and the contrast potential is increased when the SD gap is far and the image density is low. The quality of

  Sampling of the capacity between the photosensitive drum and the developing sleeve (developing capacity) may be performed when the image forming apparatus is started up (for example, at the first start-up in the morning of the day). In the sampling, when the SD gap varies depending on the temperature inside the image forming apparatus, every time the number of sheets on which the image is formed reaches a predetermined number or the operation time of the image forming apparatus is set to a predetermined time. It may be performed every time it reaches.

  In this embodiment, when controlling Vcont to stabilize the image density, the development DC bias voltage is changed in accordance with the fluctuation of the SD gap. However, the present invention is not limited to this. . There are various other methods for obtaining the effects of the present invention, such as changing the amount of laser light that exposes the photosensitive drum 1 in order to change the potential of the latent image portion of the photosensitive drum 1.

  As described above, according to the present embodiment, it is possible to sample the change in the detection signal with high resolution and high accuracy by enlarging the change in the detection signal based on the dynamic change in the capacitance between the photosensitive drum and the developing sleeve. It becomes. Then, the image forming conditions are changed based on the dynamic change of the capacity (the development DC voltage is increased when the voltage of the capacity detection signal is large, and the development DC voltage is decreased when the voltage of the capacity detection signal is small). As a result, it is possible to prevent periodic fluctuations in image density and image roughness and to maintain a constant image quality. In addition, when the change of the detection signal is directly applied to the development DC bias voltage or the like and fed back to the image forming condition, the amplitude of the dynamic change of the capacity can be changed according to the target to be applied. This makes it possible to set an appropriate feedback amount for the image forming conditions.

[Second Embodiment]
The second embodiment of the present invention differs from the first embodiment in that the developer used in the image forming apparatus is a one-component developer made of toner containing a magnetic material, and the output of a Sig4 capacitance detection AC signal. Is applied to the development DC high pressure setting in real time on the development high pressure substrate.

  Since the configuration centering on the photosensitive drum and the developing device in the second embodiment is the same as that of the first embodiment, the description thereof is omitted. The charging, development, and latent image voltage during image formation in the second embodiment are the same as in the first embodiment.

  In the standard state, the surface of the photosensitive drum 1 is charged to, for example, −600 V by the primary charger 2. The potential of an electrostatic latent image (latent image portion) formed on the surface of the photosensitive drum 1 by laser light is −150V. By applying −400 V to the developing sleeve 4a as a DC component (developing DC bias voltage) of the developing bias voltage, a contrast potential Vcont for determining the image density (between the latent image portion of the photosensitive drum 1 and the developing sleeve 4a). Potential) is 250V. Further, the fog removal potential Vback for preventing fog (a phenomenon in which toner scatters to a portion other than the latent image portion) is 200V.

  FIG. 12 is a configuration diagram illustrating a state where the rotation shaft of the photosensitive drum and the rotation shaft of the developing sleeve according to the second embodiment are positioned by rollers.

  In FIG. 12, a rotating shaft 1 a and a bearing 1 b that rotatably support the photosensitive drum 1 are provided at the center of the photosensitive drum 1. In addition, a rotation shaft 4d and a bearing 4e that rotatably support the developing sleeve 4a are provided at the center of the developing sleeve 4a. The bearing 4e is fitted in a resin roller 1201. The roller 1201 is disposed so as to be abutted against the surface of the photosensitive drum 1. Thereby, the surface of the photosensitive drum 1 and the developing sleeve 4a are positioned.

  In this embodiment, the distance (SD gap: interval) between the photosensitive drum 1 positioned by the roller 1201 and the developing sleeve 4a is set to a nominal value of 300 μm. In this example, the SD gap may be shifted by ± 10%, that is, ± 30 μm as an average value due to tolerances. Further, the SD gap is dynamically changed depending on the manufacturing accuracy of the roller 1201, adhesion of dirt to the roller 1201, bending of the developing sleeve 4a, and the like. Has a maximum variation of ± 5%, that is, ± 15 um.

  In the present embodiment, the rectangular bias voltage shown in FIG. 21 is used as the developing bias voltage. By adding the AC component (development AC bias voltage) to the DC component (development DC bias voltage), it becomes possible to suppress the image roughness and to obtain a sufficient image density. When the SD gap is a nominal value of 300 μm, the Vp-p of the pulse part of the AC component (development AC bias voltage) of the development bias voltage is 2 kV. When the SD gap is a nominal value of 300 μm, the capacitive load between the photosensitive drum 1 and the developing sleeve 4a is 350 pF.

  FIG. 13 is a block diagram illustrating the configuration of the development high-voltage board and the control board of the image forming apparatus.

  In FIG. 13, the image forming apparatus is equipped with a development high-pressure substrate 1300 and a control substrate 1310. An AC high voltage driving circuit 1301 (application means), an AC transformer 1302 (application means), a DC high voltage circuit 1303 (application means), and a current detection circuit 1304 (detection means) are mounted on the development high voltage substrate 1300. Further, an LPF (low-pass filter) 1305, an AC amplifier circuit 1306 (amplifier, limiter, shortener), an adder circuit 1307, a capacitor C1, and an output resistor are mounted on the development high-voltage substrate 1300. On the control board 1310, an A / D conversion circuit 1314, a D / A conversion circuit 1312, a D / A conversion circuit 1313, a CPU 1311 (control means), and a memory 1315 are mounted.

  In the development high-voltage substrate 1300, the AC high-voltage drive circuit 1301 drives the AC transformer 1302, generates a development AC bias voltage corresponding to the Sig1Vp-p setting signal, and supplies the development AC bias voltage to the development sleeve 4a. The adder circuit 1307 performs voltage addition of the Sig2 development DC setting signal and the Sig4 capacity detection AC signal, and outputs the result as a Sig5 development DC control signal. The DC high voltage circuit 1303 receives the Sig5 development DC control signal, generates a development DC bias voltage corresponding to the voltage of the Sig5 development DC control signal, and supplies the development DC bias voltage to the development sleeve 4a.

  The current detection circuit 1304 detects a half wave of the AC current flowing to the ground side of the AC transformer 1302 by the current detection resistor R1. A half wave of the AC current is input to the LPF 1305 and smoothed, and is extracted as a Sig3 capacitance detection DC signal. The Sig3 capacitance detection DC signal is input to the A / D conversion circuit 1314. The Sig3 capacitance detection DC signal is input to the AC amplifier circuit 1306 and the AC component thereof is amplified, and then input to the adder circuit 1307.

  In the control board 1310, the A / D conversion circuit 1314 is a circuit having a 10-bit resolution, and converts the Sig3 capacitance detection DC signal output from the development high-voltage circuit 1300 from an analog signal to a digital signal. The D / A conversion circuit 1312 outputs an analog voltage Sig1Vp-p setting signal for controlling the development AC bias voltage generated by the AC high voltage driving circuit 1301 driving the AC transformer 1302 based on the setting of the CPU 1311. The D / A conversion circuit 1313 outputs an analog voltage Sig2 development DC setting signal for controlling the DC voltage output from the DC high voltage circuit 1303 based on the setting of the CPU 1311.

  The CPU 1311 stores the detected change in the capacity between the photosensitive drum 1 and the developing sleeve 4a in the memory 1315. The CPU 1311 changes the conditions for image formation including development based on the Sig3 capacity detection DC signal, in other words, based on the average value of the photosensitive drum-developing sleeve capacity (development capacity). The image forming conditions include the peak-to-peak value (p-p value) of the developing AC bias voltage, the voltage value of the developing DC bias voltage, the voltage value of the charging DC bias voltage, and the amount of laser light that exposes the photosensitive drum 1. including.

  The operation unit 1316 is used for various displays in the image forming apparatus and various settings for the image forming apparatus. The operation unit 1316 is also used for displaying the detected capacity between the photosensitive drum 1 and the developing sleeve 4a, setting image forming conditions, and the like.

  The secondary side of the AC transformer 1302 is connected to the high-voltage side with a load capacitance CL, which is a capacitance between the photosensitive drum 1 and the developing sleeve 4a, and coupled to the ground side with a capacitor C1 and then connected to a current detection circuit 1304. ing. The current detection circuit 1304 includes a current detection resistor R1, diodes D1 and D2 for canceling half-wave current, and a resistor R2. The current flowing from the AC transformer 1302 toward the ground passes through the current detection resistor R1 and generates a voltage at both ends thereof, but the current flowing from the ground toward the AC transformer 1302 is supplied from the resistor R2 and the diode D1, It does not pass through the current detection resistor R1. That is, the current detection circuit 1304 is a circuit that detects a half-wave current.

  The current flowing through the load capacitor CL returns to the AC transformer 1302 through the current detection circuit 1304 via the ground. When the SD gap is small and the load capacitance CL is large, the current flowing through the load capacitance CL increases. However, since a half wave of the current passes through the current detection resistor R1, a large voltage is applied across the current detection resistor R1. Occurs. Conversely, when the SD gap is large and the load capacitance CL is small, the current flowing through the load capacitance CL is small, and the voltage generated at both ends of the current detection resistor R1 is also small.

  The voltage across the current detection resistor R1 is smoothed by the LPF 1305 and input to the A / D converter circuit 1314 and the AC amplifier circuit 1306 as a Sig3 capacitance detection DC signal. The cut-off frequency of the LPF 1305 is set to, for example, about 20 Hz as a frequency at which the frequency of 2 kHz of the development AC bias voltage does not pass and the fluctuation of the Sig3 capacitance detection DC signal due to dynamic SD fluctuation can pass.

  FIG. 14 is a diagram illustrating the relationship between the size of the SD gap and the Sig3 capacitance detection DC signal.

  In FIG. 14, similarly to FIG. 4 of the first embodiment, the capacitance between the photosensitive drum and the developing sleeve changes approximately in inverse proportion to the SD gap. As a result, when the SD gap widens, the Sig3 capacitance detection DC is increased. It can be seen that the signal voltage decreases. That is, it is possible to detect the distance of the SD gap by the Sig3 capacitance detection DC signal.

  FIG. 15 is a detailed circuit diagram of the AC amplifier circuit 1306 of FIG.

  15, the AC amplifier circuit 306 includes an HPF (High Pass Filter) 1701, a differential amplifier circuit 1702, and a limiter circuit 1703. The Sig3 capacitance detection DC signal is input to the HPF 1701, and the DC component and the low-frequency temperature drift component are removed. C1701 and R1701 are a capacitor and a resistor that determine the cutoff frequency of the HPF 1701. The resistor R1701 is DC biased to Vref11 (= 0.2V). Vref is a reference voltage for generating Vref11. The differential amplifier circuit 1702 constitutes a triple amplification circuit, and amplifies both the DC voltage and the AC voltage of the input signal three times. Therefore, if there is no AC component in the Sig3 capacitance detection DC signal, the Sig4 capacitance detection AC signal becomes DC 0.6V.

  The amplification factor of the AC amplifier circuit 1306 is determined so that the correction amount is appropriate when the Sig4 capacitance detection AC signal is used for image correction in a correction flow described later. The limiter circuit 1703 limits the voltage of the capacitor C1701 when the development AC bias voltage is activated. When the Sig3 capacitance detection signal rises from 0 V to a voltage corresponding to the SD gap when the development AC bias voltage is activated, the base voltage of the transistor Tr1701 exceeds the on-voltage threshold value, and the transistor Tr1701 is turned on. As a result, the voltage of the capacitor C1701 is short-circuited with the output voltage Vref11 of the IC1701. This is the same as when the resistor R1701 is short-circuited by the transistor Tr1701, and the time constant of the HPF 1701 becomes almost zero.

  Next, the effect of the limiter circuit 1703 of FIG. 15 will be described with reference to FIG.

  FIG. 16 is a diagram showing the Sig3 capacitance detection DC signal and the Sig4 capacitance detection AC signal when the development AC bias is turned on with the rotation of the photosensitive drum and the development sleeve stopped.

  In FIG. 16, the Sig3 capacitance detection DC signal is 0 V when the development AC bias voltage is off, but becomes a constant value according to the capacity of the SD gap when the development AC bias voltage is turned on. The solid line of the Sig4 capacitance detection AC signal is the output of the circuit of the present embodiment, and is shifted to the plus side and the minus side at the rise of the Sig3 capacitance detection DC signal, but the time constant of the HPF 1701 is temporarily caused by the action of the limiter circuit 1703. Shortened. Therefore, the time t1 for convergence to a constant value (0.6V) is also short.

  The broken line of the Sig4 capacitance detection AC signal is a waveform when the limiter circuit 1703 is not provided. When the Sig3 capacitance detection DC signal rises, the output t increases to the vicinity of the power supply voltage of the differential amplifier circuit 1702 and then sticks to the upper limit, and the time t2 until it converges to a constant value is very long. During this time t2, the Sig4 capacitance detection AC signal value cannot be used. That is, due to the effect of the limiter circuit 1703, the time t2 is shortened to the time t1, and the waiting time until the start of image formation in the image forming apparatus can be shortened.

  FIG. 17 is a flowchart illustrating processing related to acquisition of the average SD gap value of the image forming apparatus.

  In FIG. 17, the CPU 1311 of the control board 1310 sets the Vp-p setting of the development AC bias voltage to the initial value of 2 kV (step S201). Next, the CPU 1311 turns on the output of the AC high voltage drive circuit 1301 that supplies a high voltage to the developing sleeve 4a, and turns on the rotation of the photosensitive drum 1 and the developing sleeve 4a (step S202).

  The CPU 1311 reads the Sig3 capacity detection DC signal via the A / D conversion circuit 1314 while the photosensitive drum 1 and the developing sleeve 4a are rotationally driven (step S203). Further, the CPU 1311 performs sampling of the Sig3 capacity detection DC signal for one rotation of the photosensitive drum at each of eight points divided into, for example, eight per one rotation of the photosensitive drum, and obtains a static SD average value (step S203). This static SD average represents whether the SD gap is near or far from static. Finally, the CPU 1311 stores the acquired data (static SD average value) in the memory 1315 (step S204).

  FIG. 18 is a diagram showing the relationship between the Sig5 development DC control signal for setting the output voltage of the DC high voltage circuit 1303 and the output voltage.

  In FIG. 18, when the voltage of the Sig5 development DC control signal shown in FIG. 13 is 11V, the development DC high voltage is 0V, and when the voltage of the Sig5 development DC control signal is 1V, the development DC high voltage is −1000V. become.

  FIG. 19 is a flowchart illustrating a process of changing the image forming condition using the detected capacity variation.

  In FIG. 19, the CPU 1311 of the control board 1310 uses the static SD average value (Sig3 capacity detection DC signal) acquired in the process of FIG. 17, and first, static image forming conditions (imaging conditions). Is changed (step S301). When the average voltage of the Sig3 capacitance detection DC signal is larger than the voltage when the SD gap is the nominal value, the SD gap is small and the density is high. Therefore, in order to reduce the contrast potential according to the difference from the nominal value voltage, the average value of the development DC voltage is changed from the reference value of −400V to −380V, for example. As a result, the difference from the latent image potential of −150V is changed from 250V to 230V.

  In order to set the development DC high voltage output to −380 V, it is necessary to set the Sig5 development DC control signal to 7.2 V from FIG. 18, but the development DC control signal is supplied to the AC amplification circuit 1306 via the adder circuit 1307. DC 0.6V is added. Therefore, the CPU 1311 uses the D / A conversion circuit 1313 to set 6.6 V as the Sig2 development DC setting signal. Next, the CPU 1311 turns on the charging high voltage, the developing DC high voltage, and the AC high voltage, and starts driving the photosensitive drum 1 and the developing sleeve 4a (step S302). After the development AC high voltage is turned on, the system waits for time t1 until the Sig4 capacitance detection AC signal is stabilized (step S303). After the Sig4 capacitance detection AC signal is stabilized, image formation is started (step S304).

  Here, the Sig5 development DC control signal is obtained by adding the voltages of the Sig2 development DC setting signal and the Sig4 capacity detection AC signal. For this reason, the Sig5 development DC control signal is also dynamically changed by the dynamic fluctuation of the SD capacity. An example is shown in FIG. The Sig4 capacitance detection AC signal has an AC waveform superimposed around DC 0.6 V due to dynamic S-D capacitance variation. This AC waveform is added to 6.6V of the Sig2 development DC setting signal, and the Sig5 development DC control signal is a signal in which the AC waveform due to the fluctuation of the dynamic SD capacity is superimposed around 7.2V.

  When the SD gap between the photosensitive drum 1 and the developing sleeve 4a is close, the Sig4 capacitance detection AC signal increases. As a result, the Sig5 development DC control signal is increased and the development DC high voltage is corrected to a smaller absolute value, and the contrast potential is reduced to correct the image density increase due to the close SD gap. .

  As described above, according to the present embodiment, the fluctuation of the SD gap is taken out as a capacity detection signal, and the fluctuation of the capacity detection signal is amplified with an appropriate amplification factor to act on the development DC control signal. As a result, it is possible to perform correction so as to cancel the change in image density due to the fluctuation of the SD gap. As a result, it is possible to prevent periodic fluctuations in image density and image roughness and to maintain a constant image quality.

Other Embodiment
In the first and second embodiments, the image forming apparatus that forms an image by the electrophotographic method is taken as an example. However, the present invention is not limited to this, and an image that forms an image by the electrostatic recording method is used. The present invention can also be applied to a forming apparatus.

  In the first and second embodiments, the type of the image forming apparatus is not mentioned, but the present invention can be applied to various image forming apparatuses including a printer, a copier, and a multifunction peripheral.

  In the first and second embodiments, various specific examples have been described as described above. However, the present invention is not limited to these embodiments, and various modifications are possible within the scope of the technical idea of the present invention. Is possible.

1 Photosensitive drum 4a Developing sleeve 306, 1306 AC amplification circuit 311, 1311 CPU

However, in the structure abutting the abutting rollers provided at an end portion of the developing sleeve to the surface of the photosensitive drum, more can Baratsu diameter of abutting rollers, S-D gap statically for each image forming apparatus There is a problem that the average value varies. Originally, the nominal value of the SD gap, which is the central value in design, is very narrow, for example, 300 μm, and may vary by about ± 20% due to variations due to component tolerances. Further, the manufacturing accuracy of the abutting roller or the developer or the like adheres to the abutting roller, so that the diameter of the abutting roller partially changes, and the SD gap changes dynamically in the time period of one abutting roller. There are fluctuations.

1 is a configuration diagram illustrating a configuration of an image forming apparatus according to a first embodiment of the present invention. FIG. 3 is a configuration diagram illustrating a state where a rotating shaft of a photosensitive drum and a rotating shaft of a developing sleeve are positioned by a spacer. FIG. 2 is a block diagram illustrating configurations of a development high-voltage substrate and a control substrate of the image forming apparatus. It is a figure which shows the relationship between the magnitude | size of SD gap, and Sig3 capacity | capacitance detection DC signal. It is a figure which shows the example which the voltage of the Sig3 capacity | capacitance detection DC signal is fluctuate | varied by dynamic SD fluctuation | variation. It is a detailed circuit diagram of an AC amplifier circuit. It is a figure which shows Sig4 capacity | capacitance detection AC signal. It is a figure which shows Sig3 capacity | capacitance detection DC signal and Sig4 capacity | capacitance detection AC signal. 6 is a flowchart illustrating processing related to acquisition of an SD gap profile of the image forming apparatus. It is a figure which shows Sig3 capacity | capacitance detection DC signal and Sig4 capacity | capacitance detection AC signal. It is a figure which shows Sig4 capacity | capacitance detection AC signal profile, a latent image potential, development DC high voltage | pressure, and a drum HP signal. It is a block diagram which shows the state in which the rotating shaft of the photosensitive drum which concerns on 2nd Embodiment of this invention, and the surface of the developing sleeve are positioned with the roller. FIG. 2 is a block diagram illustrating configurations of a development high-voltage substrate and a control substrate of the image forming apparatus. It is a figure which shows the relationship between the magnitude | size of SD gap, and Sig3 capacity | capacitance detection DC signal. It is a detailed circuit diagram of an AC amplifier circuit. It is a figure which shows Sig3 capacity | capacitance detection DC signal and Sig4 capacity | capacitance detection AC signal. 6 is a flowchart illustrating processing related to acquisition of an average SD gap value of the image forming apparatus. It is a figure which shows the relationship between the Sig5 development DC control signal which sets the output voltage of DC high voltage circuit, and an output voltage . It is a flowchart which shows the process which changes image formation conditions using the detected capacity | capacitance fluctuation | variation. It is a figure which shows the example by which a Sig5 development DC control signal is also changed dynamically by the fluctuation | variation of dynamic SD capacity | capacitance. It is a figure which shows the example of the developing bias voltage which superimposed the AC component on the DC component. It is a figure which shows the example of the developing bias voltage comprised from the pulse part and the rest part.

In FIG. 7, the change width of about 50 mV is amplified to about 1 V, and becomes an AC signal of ± 0.5 V centering on 1.5 V. The voltage range of the capacitor C701 in FIG. 6 is limited by the upper limiter 703 and the lower limiter 704. The voltage of the lower limiter 704 is the same voltage as the negative voltage of the differential amplifier circuit 702. Therefore, even when a large input change is input from the Sig3 capacitance detection DC signal, the output voltage range of the Sig4 capacitance detection AC signal is limited to a range of 0V to 3.0V. The mark ♦ on the Sig4 waveform in FIG. 7 is a sampling point, and eight points obtained by dividing one circumference of the drum into eight are P1 to P8 based on HP. The handling of the values sampled at each sampling point will be described in detail later.

The CPU 311 performs Sig4 capacity detection AC signals for four photosensitive drums at eight points (sampling points P1 to P8 in FIG. 7) divided into, for example, eight equally per one rotation of the photosensitive drum based on the output pulse of the drum HP sensor 22 . Sampling. Further, the CPU 311 performs a process of averaging the values of the four rounds of each point (P1 to P8) of the sampled Sig4 capacitance detection AC signal, and stores the processing result in the memory 315 . That is, the voltage at the first sampling point P1 with respect to HP is sampled for four rounds, the average value is calculated, and stored as the average value of P1. The same applies to P2 to P8. As a result, the CPU 311 removes minute shakes caused by other than eccentricity of the photosensitive drum 1 (for example, eccentricity of the developing sleeve 4a), and a dynamic SD fluctuation profile (SD gap). Profile is acquired (step S104).

As described above, according to the present embodiment, it is possible to sample the change in the detection signal with high resolution and high accuracy by enlarging the change in the detection signal based on the dynamic change in the capacitance between the photosensitive drum and the developing sleeve. It becomes. Then, the image forming conditions are changed based on the dynamic change of the capacity (the development DC voltage is increased when the voltage of the capacity detection signal is large, and the development DC voltage is decreased when the voltage of the capacity detection signal is small). As a result, it is possible to prevent periodic fluctuations in image density and image roughness and to maintain a constant image quality .

FIG. 12 is a configuration diagram showing a state in which the rotating shaft of the photosensitive drum and the surface of the developing sleeve according to the second embodiment are positioned by rollers.

The CPU 1311 changes conditions for image formation including development based on the Sig3 capacity detection DC signal, in other words, based on the average value of the capacity between the photosensitive drum and the developing sleeve (developing capacity). The image forming conditions include the peak-to-peak value (p-p value) of the developing AC bias voltage, the voltage value of the developing DC bias voltage, the voltage value of the charging DC bias voltage, and the amount of laser light that exposes the photosensitive drum 1. including.

In Figure 15, AC amplifier circuit 306, HPF (high pass filter) 1701, amplification circuit 1702, and a limiter circuit 1703. The Sig3 capacitance detection DC signal is input to the HPF 1701, and the DC component and the low-frequency temperature drift component are removed. C1701 and R1701 are a capacitor and a resistor that determine the cutoff frequency of the HPF 1701. The resistor R1701 is DC biased to Vref11 (= 0.2V). Vref is a reference voltage for generating Vref11 . Amplification circuit 1702 constitute a 3-fold amplification circuit amplifies tripled both the DC voltage and AC voltage of the input signal. Therefore, if there is no AC component in the Sig3 capacitance detection DC signal, the Sig4 capacitance detection AC signal becomes DC 0.6V.

The broken line of the Sig4 capacitance detection AC signal is a waveform when the limiter circuit 1703 is not provided. After the output at the rising edge of the Sig3 capacitance detection DC signal rises increased to near the power supply voltage of amplifier circuit 1702, sticking to the upper limit, a very long time t2 to converge to a constant value. During this time t2, the Sig4 capacitance detection AC signal value cannot be used. That is, due to the effect of the limiter circuit 1703, the time t2 is shortened to the time t1, and the waiting time until the start of image formation in the image forming apparatus can be shortened.

CPU1311 in a state where the developing sleeve 4a was rotated and the photosensitive drum 1, Ru read the Sig3 capacitance detection DC signal via an A / D conversion circuit 1314. The CPU 1311 samples the Sig3 capacity detection DC signal for one revolution of the photosensitive drum at each of eight points divided, for example, into eight equal parts per revolution of the photosensitive drum, and obtains a static SD average value (step S203). This static SD average represents whether the SD gap is near or far from static. Finally, the CPU 1311 stores the acquired data (static SD average value) in the memory 1315 (step S204).

Claims (4)

An image carrier that carries an electrostatic latent image; and a developer carrier that carries a developer that is disposed opposite to the image carrier and that develops the electrostatic latent image carried on the image carrier. An image forming apparatus that forms an image by developing the electrostatic latent image with the developer,
Applying means for applying a developing bias voltage for forming a developing electric field between the image carrier and the developer carrier to the developer carrier;
Detection means for detecting a capacity between the image carrier and the developer carrier;
Amplifying means for amplifying a change in the detection signal indicating the capacitance detected by the detecting means;
Control means for changing a condition for image formation including the development based on a change in the capacitance detection signal amplified by the amplification means;
An image forming apparatus comprising:   The image forming apparatus according to claim 1, wherein the amplifying unit includes a limiting unit that limits input of a large change in a detection signal indicating the capacitance detected by the detecting unit.   The said amplifying means is provided with the shortening means to shorten the time when the said capacity | capacitance detection signal converges to a fixed value when the said developing bias voltage is applied to the said developer carrier. Image forming apparatus.   The image forming conditions include a peak-to-peak value of a developing AC bias voltage that is an AC component of the developing bias voltage, a voltage value of a developing DC bias voltage that is a DC component of the developing bias voltage, and the image carrier. 2. The image forming apparatus according to claim 1, further comprising: a voltage value of a charging DC bias voltage that is a DC component of a charging bias voltage to be charged; or a light amount of a laser beam that exposes the image carrier.

Images