JP2014202489A - Storage cell deterioration determination device, storage cell deterioration determination method and storage cell deterioration determination program - Google Patents

Storage cell deterioration determination device, storage cell deterioration determination method and storage cell deterioration determination program Download PDF

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JP2014202489A
JP2014202489A JP2013076048A JP2013076048A JP2014202489A JP 2014202489 A JP2014202489 A JP 2014202489A JP 2013076048 A JP2013076048 A JP 2013076048A JP 2013076048 A JP2013076048 A JP 2013076048A JP 2014202489 A JP2014202489 A JP 2014202489A
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deterioration determination
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JP6184722B2 (en
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智弘 大島
Toshihiro Oshima
智弘 大島
剛 沖
Takeshi Oki
剛 沖
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JM Energy Corp
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Abstract

PROBLEM TO BE SOLVED: To precisely determine deterioration of a storage cell on the basis of equalization control normally performed by a storage apparatus equipped with an equalization control circuit, without providing a configuration exclusively used for determining the deterioration of the storage cell.SOLUTION: A storage cell deterioration determination device comprises: an equalization control circuit that is connected to each of the storage cells in parallel; and an arithmetic processor that controls the equalization control circuit and has an equalization frequency storage unit for storing equalization control frequency. The arithmetic processor is configured to: decide an equalization control target cell requiring the equalization control, among the storage cells; apply the equalization control for an equalization control target cell to the equalization control target cell; increase equalization frequency of each storage cell, which is stored in the equalization frequency storage unit, with respect to the storage cell after the equalization control; and determine deterioration of each storage cell on the basis of the equalization frequency of each cell stored in the equalization frequency storage unit.

Description

本発明は、互いに接続された複数個のキャパシタセルやバッテリーセルなどの蓄電セルを備えた蓄電装置における、各蓄電セルの劣化状態を判定するための劣化判定装置及び劣化判定方法ならびに劣化判定プログラムに関する。   The present invention relates to a deterioration determination device, a deterioration determination method, and a deterioration determination program for determining a deterioration state of each storage cell in a storage device including storage cells such as a plurality of capacitor cells and battery cells connected to each other. .

従来、高電圧、大容量の蓄電装置として、複数個の電気二重層キャパシタやリチウムイオンキャパシタなどから構成されるキャパシタセルや、複数個のリチウムイオンバッテリーなどから構成されるバッテリーセルなどの蓄電セルが複数接続されて構成される蓄電装置が知られている。   Conventionally, as high-voltage, large-capacity power storage devices, power storage cells such as capacitor cells composed of a plurality of electric double layer capacitors and lithium ion capacitors, and battery cells composed of a plurality of lithium ion batteries, etc. A power storage device configured by connecting a plurality of devices is known.

このような蓄電装置で用いられるキャパシタセルは、経年劣化などによって特性が変化し、キャパシタセルの静電容量が徐々に減少し、内部抵抗が徐々に増加することが知られている。   It is known that the characteristics of a capacitor cell used in such a power storage device change due to deterioration over time, the capacitance of the capacitor cell gradually decreases, and the internal resistance gradually increases.

このため、複数個のキャパシタセルを備えた蓄電装置は、キャパシタセルの経年劣化に伴って、静電容量が減少してしまうことになる。
また、バッテリーセルも、経年劣化などによって電極や電解液などが劣化したり、イオンバランスが変化するなどして、バッテリーセルの放電容量が徐々に減少してしまうことが知られている。 For this reason, in a power storage device including a plurality of capacitor cells, the capacitance decreases with the aging of the capacitor cells.
In addition, it is known that the discharge capacity of the battery cell gradually decreases due to deterioration of the electrode, the electrolyte, or the like due to aging or the like, or change of the ion balance.

このような蓄電セルの劣化を検知するために、従来は、蓄電セルの放電時において、蓄電セルのセル電圧をそれぞれ監視し、セル電圧の電圧降下特性に基づいて、蓄電セルの劣化判定を行っていた。   In order to detect such deterioration of the storage cell, conventionally, when the storage cell is discharged, the cell voltage of the storage cell is monitored, and the deterioration determination of the storage cell is performed based on the voltage drop characteristic of the cell voltage. It was.

しかしながら、蓄電セルのセル電圧を監視するだけでは、蓄電セルの劣化判定を正確に行うことができなかった。
このため、特許文献１では、組電池の正極の開放電位及び負極の開放電位と、組電池に含まれるイオン量を測定し、これらに基づいて組電池の劣化判定を行う電池劣化判定装置が提案されている。 However, it is not possible to accurately determine the deterioration of the storage cell only by monitoring the cell voltage of the storage cell.
For this reason, Patent Document 1 proposes a battery deterioration determination device that measures the open potential of the positive electrode and the negative electrode of the assembled battery and the amount of ions contained in the assembled battery, and determines the deterioration of the assembled battery based on these. Has been.

このように組電池に含まれるイオン量を測定することによって、電池の劣化により生じるイオンバランスの変化を把握することができ、電池の劣化を精度よく判定することができるとしている。   Thus, by measuring the amount of ions contained in the assembled battery, it is possible to grasp the change in ion balance caused by the deterioration of the battery, and to accurately determine the deterioration of the battery.

また、特許文献２には、リチウムイオン電池の充電時において、リチウムイオン電池の推定容量Ｃeを算出するとともに、リチウムイオン電池の公称容量Ｃ0と推定容量Ｃeの比である推定比容量Ｃe／Ｃ0を算出して、この推定比容量Ｃe／Ｃ0に基づいて、リチウムイオン電池の劣化判定を行うことが開示されている。 Patent Document 2 discloses an estimated specific capacity C e which is a ratio of the nominal capacity C 0 and the estimated capacity C e of the lithium ion battery while calculating the estimated capacity C e of the lithium ion battery when charging the lithium ion battery. It is disclosed that e / C 0 is calculated and the deterioration of the lithium ion battery is determined based on the estimated specific capacity C e / C 0 .

このように、公称容量Ｃ0、すなわち、新品の状態のバッテリーの放電容量と、推定容量Ｃe、すなわち、劣化判定時のバッテリーの放電容量とを比較することによって、バッテリーの放電容量の劣化度合いを正確に把握することができる。 Thus, by comparing the nominal capacity C 0 , that is, the discharge capacity of the battery in a new state with the estimated capacity C e , that is, the discharge capacity of the battery at the time of deterioration determination, the degree of deterioration of the discharge capacity of the battery Can be grasped accurately.

特開２０１１−４０１９８号公報JP2011-40198A 特開２００１−３３２３１０号公報JP 2001-332310 A

ところで、このような複数の蓄電セルを備えた蓄電装置には、充放電を繰り返すことによってセル間の電圧にバラツキが生じた場合に、蓄電装置の使用できる電圧範囲が狭くなってしまうという問題が生じてしまう。   By the way, in such a power storage device including a plurality of power storage cells, there is a problem that the voltage range that can be used by the power storage device is narrowed when the voltage between the cells varies due to repeated charge and discharge. It will occur.

このため、蓄電セルを備えた蓄電装置には、セル間の電圧バランスを補正するために、均等化制御回路（バランス補正回路）が設けられている。
図５は、均等化制御回路１０２を備えた蓄電装置１００の回路構成図である。 For this reason, the power storage device including the power storage cells is provided with an equalization control circuit (balance correction circuit) in order to correct the voltage balance between the cells.
FIG. 5 is a circuit configuration diagram of the power storage device 100 including the equalization control circuit 102.

図５に示すように、この均等化制御回路１０２では、互いに直列接続された複数の蓄電セルＣS1〜ＣSnに対して、電荷消費用の抵抗ＲS1〜ＲSnとＦＥＴ（Field Effect Transistor：電界効果トランジスタ）を備えるスイッチＳS1〜ＳSnとがそれぞれ並列に接続されている。 As shown in FIG. 5, in the equalization control circuit 102, resistances R S1 to R Sn for charge consumption and FETs (Field Effect Transistors) are connected to a plurality of storage cells C S1 to C Sn connected in series. Switches S S1 to S Sn including field effect transistors are connected in parallel.

そして、マイコン１０４によって、蓄電セルＣS1〜ＣSnの開放電圧を測定する電圧計ＶS1〜ＶSnからの電圧信号に基づいて、各蓄電セルＣS1〜ＣSnの目標電圧値を算出するとともに、各蓄電セルＣS1〜ＣSnの電圧調整を行うためにスイッチＳS1〜ＳSnが制御されるように構成されている。 Then, the microcomputer 104, based on the voltage signal from the voltmeter V S1 ~V Sn measuring the open circuit voltage of the storage cells C S1 -C Sn, calculates a target voltage value of the storage cells C S1 -C Sn The switches S S1 to S Sn are controlled in order to adjust the voltages of the storage cells C S1 to C Sn .

このように構成された均等化制御回路１０２では、各蓄電セルＣS1〜ＣSnの電圧値が、目標電圧値となるまで、マイコン１０４によってスイッチＳS1〜ＳSnが入状態となり、蓄電セルＣS1〜ＣSnの電荷を抵抗ＲS1〜ＲSnによって消費するように制御される。 In the equalization control circuit 102 configured as described above, the switches S S1 to S Sn are turned on by the microcomputer 104 until the voltage value of each of the energy storage cells C S1 to C Sn reaches the target voltage value. It is controlled to consume the charge of S1 -C Sn by resistance R S1 to R Sn.

このように、均等化制御回路によってセル電圧を均等化することで、蓄電装置が使用出来る電圧範囲を常に最大にすることができる。このため、複数の蓄電セルを備えた蓄電装置では、均等化制御回路は重要な役割を担っている。   Thus, by equalizing the cell voltage by the equalization control circuit, the voltage range that can be used by the power storage device can always be maximized. For this reason, the equalization control circuit plays an important role in a power storage device including a plurality of power storage cells.

本発明では、蓄電セルの劣化判定を行うための専用の構成を設けずに、均等化制御回路を備えた蓄電装置が通常に行っている均等化制御に基づいて、蓄電セルの劣化判定を正確に行うことができる劣化判定装置及び劣化判定方法ならびに劣化判定プログラムを提供することを目的とする。   In the present invention, the determination of the deterioration of the storage cell is accurately performed based on the equalization control normally performed by the storage device having the equalization control circuit without providing a dedicated configuration for determining the deterioration of the storage cell. It is an object of the present invention to provide a deterioration determination device, a deterioration determination method, and a deterioration determination program that can be performed in the same manner.

本発明は、前述したような目的を達成するために発明されたものであって、本発明の蓄電セルの劣化判定装置は、複数の蓄電セルを含む蓄電装置において、蓄電セルの劣化判定を行う劣化判定装置であって、
前記複数の蓄電セルに接続された均等化制御回路と、
前記均等化制御回路を制御するとともに、均等化制御回数が記憶される均等化回数記憶部を有する演算処理装置と、を備え、
前記演算処理装置が、
前記蓄電セルのうち均等化制御が必要な均等化制御対象セルを決定し、
前記均等化制御対象セルに対して、前記均等化制御対象セルの均等化制御を行い、
均等化制御された蓄電セルについて、前記均等化回数記憶部に記憶された各蓄電セルの均等化回数を増加し、
前記均等化回数記憶部に記憶された各蓄電セルの均等化回数に基づいて、前記各蓄電セルの劣化判定を行うように構成されていることを特徴とする。 The present invention has been invented to achieve the above-described object, and the storage cell deterioration determination device of the present invention performs storage cell deterioration determination in a storage device including a plurality of storage cells. A deterioration determination device,
An equalization control circuit connected to the plurality of storage cells;
An arithmetic processing unit that controls the equalization control circuit and has an equalization number storage unit in which the equalization control number is stored;
The arithmetic processing unit is
Determine an equalization control target cell that needs equalization control among the storage cells,
Perform equalization control of the equalization control target cell for the equalization control target cell,
For the storage cells that are equalized, increase the number of equalizations of each storage cell stored in the equalization number storage unit,
The deterioration determination of each power storage cell is performed based on the number of times equalization of each power storage cell stored in the equalization number storage unit.

このように構成することによって、既存の均等化制御回路を用いて、各蓄電セルの均等化回数を均等化回数記憶部に記憶しておくだけで、容易かつ正確に、蓄電セルの劣化判定を行うことができる。   By configuring in this way, it is possible to easily and accurately determine the deterioration of the storage cell simply by storing the equalization count of each storage cell in the equalization count storage unit using the existing equalization control circuit. It can be carried out.

なお、前記均等化制御回路が、前記複数の蓄電セルに対してそれぞれ並列に接続された均等化制御用抵抗及び均等化制御用スイッチを備えていてもよい。
この場合、前記均等化制御対象セルに対して並列に接続された前記均等化制御用スイッチを入状態とすることによって、前記均等化制御対象セルから前記均等化制御用抵抗に電流を流して、前記均等化制御対象セルの均等化制御を行うように構成することができる。 The equalization control circuit may include an equalization control resistor and an equalization control switch connected in parallel to the plurality of power storage cells.
In this case, by turning on the equalization control switch connected in parallel to the equalization control target cell, a current is passed from the equalization control target cell to the equalization control resistor, The equalization control target cell can be configured to perform equalization control.

そして、前記演算処理装置において、前記均等化回数記憶部に記憶された各蓄電セルの均等化回数のうち、最も均等化回数が大きい値、すなわち均等化回数最大値Ａと、最も均等化回数が小さい値、すなわち均等化回数最小値Ｂとの差分を算出し、該差分が、所定の劣化判定値Ｊ1よりも大きい場合に、劣化した蓄電セルが存在すると判定することができる。 And in the said arithmetic processing unit, the value with the largest equalization frequency | count among the equalization frequency | count of each electrical storage cell memorize | stored in the said equalization frequency memory | storage part, ie, the equalization frequency maximum value A, and the most equalization frequency | count is the most. A difference with a small value, that is, the equalization count minimum value B is calculated, and when the difference is larger than a predetermined deterioration determination value J 1 , it can be determined that a deteriorated power storage cell exists.

また、前記演算処理装置において、前記均等化回数記憶部に記憶された各蓄電セルの均等化回数と、下記式（１）によって算出される劣化判定閾値Ｔ1とを比較し、
前記均等化回数が、前記劣化判定閾値Ｔ1以下の蓄電セルを、劣化した蓄電セルであると判定することができる。
式（１）：劣化判定閾値Ｔ1＝均等化回数最大値Ａ−劣化判定値Ｊ1 In the arithmetic processing unit, the equalization frequency of each power storage cell stored in the equalization frequency storage unit is compared with the deterioration determination threshold value T 1 calculated by the following equation (1).
A storage cell having the equalization count equal to or less than the deterioration determination threshold value T 1 can be determined as a deteriorated storage cell.
Formula (1): Deterioration determination threshold T 1 = Equalization maximum value A−Deterioration determination value J 1

また、本発明の劣化判定装置では、前記均等化制御回路が、前記複数の蓄電セルに対してそれぞれ並列に接続された補充電回路及び均等化制御用スイッチを備えていてもよい。
この場合、前記均等化制御対象セルに対して並列に接続された前記均等化制御用スイッチを入状態とすることによって、前記補充電回路から前記均等化制御対象セルに電流を流して、前記均等化制御対象セルの均等化制御を行うように構成することができる。 In the deterioration determination apparatus of the present invention, the equalization control circuit may include an auxiliary charging circuit and an equalization control switch that are connected in parallel to the plurality of power storage cells.
In this case, by turning on the equalization control switch connected in parallel to the equalization control target cell, a current is caused to flow from the auxiliary charging circuit to the equalization control target cell, and the equalization control target cell. It is possible to configure so as to perform equalization control of the equalization control target cell.

そして、前記演算処理装置において、前記均等化回数記憶部に記憶された各蓄電セルの均等化回数のうち、最も均等化回数が大きい値、すなわち均等化回数最大値Ａと、最も均等化回数が小さい値、すなわち均等化回数最小値Ｂとの差分を算出し、該差分が、所定の劣化判定値Ｊ2よりも大きい場合に、劣化した蓄電セルが存在すると判定することができる。 And in the said arithmetic processing unit, the value with the largest equalization frequency | count among the equalization frequency | count of each electrical storage cell memorize | stored in the said equalization frequency memory | storage part, ie, the equalization frequency maximum value A, and the most equalization frequency | count is the most. A difference with a small value, that is, the equalization count minimum value B is calculated, and when the difference is larger than a predetermined deterioration determination value J 2 , it can be determined that a deteriorated power storage cell exists.

また、前記演算処理装置において、前記均等化回数記憶部に記憶された各蓄電セルの均等化回数と、下記式（２）によって算出される劣化判定閾値Ｔ2とを比較し、
前記均等化回数が、前記劣化判定閾値Ｔ2以上の蓄電セルを、劣化した蓄電セルであると判定することができる。
式（２）：劣化判定閾値Ｔ2＝均等化回数最小値Ｂ＋劣化判定値Ｊ2 Further, in the arithmetic processing device, the equalization frequency of each power storage cell stored in the equalization frequency storage unit is compared with a deterioration determination threshold value T 2 calculated by the following equation (2):
A storage cell having the equalization count equal to or greater than the deterioration determination threshold T 2 can be determined as a deteriorated storage cell.
Formula (2): Degradation threshold value T 2 = Equalization count minimum value B + Degradation criterion value J 2

また、本発明の蓄電セルの劣化判定方法は、複数の蓄電セルを含む蓄電装置において、蓄電セルの劣化判定を行う劣化判定方法であって、
前記複数の蓄電セルに対して均等化制御を行う工程と、
前記各蓄電セルについて均等化制御が行われた回数を計数する工程と、
各蓄電セルの均等化回数に基づいて、前記各蓄電セルの劣化判定を行う工程と、
を有することを特徴とする。 The storage cell degradation determination method of the present invention is a degradation determination method for determining degradation of a storage cell in a storage device including a plurality of storage cells,
Performing equalization control on the plurality of power storage cells;
Counting the number of times equalization control has been performed for each of the storage cells;
Determining deterioration of each power storage cell based on the number of equalization times of each power storage cell;
It is characterized by having.

なお、前記均等化制御は、均等化制御の対象である蓄電セルの電荷を消費することによって行うことができる。
この場合、各蓄電セルの均等化回数のうち、最も均等化回数が大きい値、すなわち均等化回数最大値Ａと、最も均等化回数が小さい値、すなわち均等化回数最小値Ｂとの差分を算出し、該差分が、所定の劣化判定値Ｊ1よりも大きい場合に、劣化した蓄電セルが存在すると判定することができる。 In addition, the said equalization control can be performed by consuming the electric charge of the electrical storage cell which is the object of equalization control.
In this case, among the equalization times of each power storage cell, the difference between the value with the largest equalization number, that is, the maximum equalization number A, and the value with the smallest equalization number, ie, the minimum equalization number B is calculated. and, said difference is greater than a predetermined deterioration determination value J 1, it can be determined that the degraded storage cell is present.

また、各蓄電セルの均等化回数と、下記式（１）によって算出される劣化判定閾値Ｔ1とを比較し、
前記均等化回数が、前記劣化判定閾値Ｔ1以下の蓄電セルを、劣化した蓄電セルであると判定することができる。
式（１）：劣化判定閾値Ｔ1＝均等化回数最大値Ａ−劣化判定値Ｊ1 Also, the number of equalization times of each storage cell is compared with the deterioration determination threshold value T 1 calculated by the following equation (1),
A storage cell having the equalization count equal to or less than the deterioration determination threshold value T 1 can be determined as a deteriorated storage cell.
Formula (1): Deterioration determination threshold T 1 = Equalization maximum value A−Deterioration determination value J 1

また、本発明の劣化判定方法では、前記均等化制御を、均等化制御の対象である蓄電セルに補充電することによって行うこともできる。
この場合、各蓄電セルの均等化回数のうち、最も均等化回数が大きい値、すなわち均等化回数最大値Ａと、最も均等化回数が小さい値、すなわち均等化回数最小値Ｂとの差分を算出し、該差分が、所定の劣化判定値Ｊ2よりも大きい場合に、劣化した蓄電セルが存在すると判定することができる。 Moreover, in the deterioration determination method of this invention, the said equalization control can also be performed by carrying out supplementary charge to the electrical storage cell which is the object of equalization control.
In this case, among the equalization times of each power storage cell, the difference between the value with the largest equalization number, that is, the maximum equalization number A, and the value with the smallest equalization number, ie, the minimum equalization number B is calculated. However, when the difference is larger than the predetermined deterioration determination value J 2 , it can be determined that there is a deteriorated power storage cell.

また、各蓄電セルの均等化回数と、下記式（２）によって算出される劣化判定閾値Ｔ2とを比較し、
前記均等化回数が、前記劣化判定閾値Ｔ2以上の蓄電セルを、劣化した蓄電セルであると判定することができる。
式（２）：劣化判定閾値Ｔ2＝均等化回数最小値Ｂ＋劣化判定値Ｊ2 Also, the number of equalization times of each power storage cell is compared with the deterioration determination threshold T 2 calculated by the following equation (2),
A storage cell having the equalization count equal to or greater than the deterioration determination threshold T 2 can be determined as a deteriorated storage cell.
Formula (2): Degradation threshold value T 2 = Equalization count minimum value B + Degradation criterion value J 2

また、本発明の蓄電セルの劣化判定プログラムは、上述するいずれかの劣化判定方法を演算処理装置によって実行することができる。   In addition, the storage cell deterioration determination program of the present invention can execute any of the above-described deterioration determination methods by the arithmetic processing device.

本発明によれば、複数の蓄電セルを含む蓄電装置において、既存の均等化制御回路を用いて、各蓄電セルの均等化回数を記憶しておくだけで、容易かつ正確に、蓄電セルの劣化判定を行うことができる。   According to the present invention, in a power storage device including a plurality of power storage cells, deterioration of the power storage cell can be easily and accurately performed by simply storing the number of times of equalization of each power storage cell using an existing equalization control circuit. Judgment can be made.

このため、劣化の進んだ蓄電セルを早期に検出して、劣化した蓄電セルを交換するなどの対応を取ることができ、蓄電装置が使用中に故障するようなことを防止できる。   For this reason, it is possible to take measures such as early detection of a deteriorated power storage cell and replacement of the deteriorated power storage cell, and it is possible to prevent the power storage device from failing during use.

図１は、本実施例の劣化判定装置を備える蓄電装置の回路構成図である。FIG. 1 is a circuit configuration diagram of a power storage device including the deterioration determination device of the present embodiment. 図２は、図１の蓄電装置１０において、劣化判定装置２６を用いて蓄電セルＣ1〜Ｃnの均等化制御を行うとともに劣化判定を行う流れを示すフローチャートである。FIG. 2 is a flowchart illustrating a flow of performing deterioration determination while performing equalization control of the storage cells C 1 to C n using the deterioration determination device 26 in the power storage device 10 of FIG. 図３は、別の実施例の劣化判定装置を備える蓄電装置の回路構成図である。FIG. 3 is a circuit configuration diagram of a power storage device including a deterioration determination device according to another embodiment. 図４は、図３の蓄電装置１０において、劣化判定装置２６を用いて蓄電セルＣ1〜Ｃnの均等化制御を行うとともに劣化判定を行う流れを示すフローチャートである。FIG. 4 is a flowchart illustrating a flow of performing deterioration determination while performing equalization control of the storage cells C 1 to C n using the deterioration determination device 26 in the power storage device 10 of FIG. 図５は、従来の均等化制御回路を備えた蓄電装置の回路構成図である。FIG. 5 is a circuit configuration diagram of a power storage device including a conventional equalization control circuit.

以下、本発明の実施の形態（実施例）を、図面に基づいてより詳細に説明する。なお、本実施例の実施形態を以下に示すが、本発明はこの実施形態に限られるものではない。また、本発明に用いられる実施形態は、リチウムイオンキャパシタ、電気二重層キャパシタ、リチウムイオンバッテリーなどの蓄電セルに好適に用いることができる。   Hereinafter, embodiments (examples) of the present invention will be described in more detail based on the drawings. In addition, although embodiment of a present Example is shown below, this invention is not limited to this embodiment. In addition, the embodiment used in the present invention can be suitably used for a storage cell such as a lithium ion capacitor, an electric double layer capacitor, or a lithium ion battery.

図１は、本実施例の劣化判定装置を備える蓄電装置の回路構成図である。
本実施例の蓄電装置１０は、例えば、リチウムイオンキャパシタ、電気二重層キャパシタ、リチウムイオンバッテリーなどの蓄電セルＣ1〜Ｃnと、均等化制御回路１２とを備えている。 FIG. 1 is a circuit configuration diagram of a power storage device including the deterioration determination device of the present embodiment.
The power storage device 10 of this embodiment includes power storage cells C 1 to C n such as a lithium ion capacitor, an electric double layer capacitor, and a lithium ion battery, and an equalization control circuit 12.

均等化制御回路１２は、蓄電セルＣ1〜Ｃnに対してそれぞれ並列に接続された均等化制御用抵抗Ｒ1〜Ｒn及びＦＥＴ（Field Effect Transistor：電界効果トランジスタ）を備える均等化制御用スイッチＳ1〜Ｓnと、蓄電セルＣ1〜Ｃnのセル電圧をそれぞれ検出するためのセル電圧検出回路及び均等化制御を行う蓄電セルＣ1〜Ｃnに対して並列に接続された均等化制御用スイッチＳ1〜Ｓnを制御するための均等化セル選択回路を含む均等化ＩＣ１４と、均等化ＩＣ１４を制御するための演算処理装置１６と、蓄電セルＣ1〜Ｃnから演算処理装置１６を動作させるための電力を供給するための電源回路１８とから構成されている。 Equalization control circuit 12, storage cells C 1 -C n is connected in parallel with respect to the equalization control resistor R 1 to R n and FET: for equalization control comprising (Field Effect Transistor) a switch S 1 to S n, equally connected in parallel to the storage cells C 1 -C n to perform cell voltage detection circuit and equalization control for detecting a cell voltage of electric rechargeable cells C 1 -C n, respectively and equalization IC14 comprising equalizing cell selection circuit for controlling the reduction control switch S 1 to S n, the arithmetic processing unit 16 for controlling the equalization IC14, processing from storage cell C 1 -C n The power source circuit 18 supplies power for operating the device 16.

なお、本実施例においては、均等化制御用抵抗Ｒ1〜Ｒn及び均等化制御用スイッチＳ1〜Ｓnによって、均等化回路が構成されている。
また、本実施例では、均等化制御用スイッチＳ1〜ＳnとしてＦＥＴを用いているが、これに限定されず、ダイオードスイッチやＭＥＭＳ（Micro Electro Mechanical Systems）スイッチなどの高周波スイッチなど、均等化セル選択回路（本実施例の場合は、均等化ＩＣ１４）の出力に基づいて入切を制御できるスイッチを用いることができる。 In the present embodiment, by equalizing control resistor R 1 to R n and equalization control switch S 1 to S n, the equalization circuit is configured.
In this embodiment, FETs are used as the equalization control switches S 1 to S n , but the present invention is not limited to this, and high frequency switches such as diode switches and MEMS (Micro Electro Mechanical Systems) switches are used for equalization. A switch capable of controlling on / off based on the output of the cell selection circuit (equalization IC 14 in this embodiment) can be used.

また、本実施例では、セル電圧検出回路及び均等化セル選択回路などを含む均等化ＩＣ１４（例えば、リニアテクノロジー社製ＬＴＣ６８０２）を用いているが、セル電圧検出回路及び均等化セル選択回路をそれぞれ独立して構成してもよい。   In this embodiment, an equalization IC 14 (for example, LTC6802 manufactured by Linear Technology Co., Ltd.) including a cell voltage detection circuit and an equalization cell selection circuit is used. However, the cell voltage detection circuit and the equalization cell selection circuit are respectively used. You may comprise independently.

なお、演算処理装置１６は、ＣＰＵ（Central Processing Unit：中央演算処理装置）やＲＡＭ（Random Access Memory：ランダムアクセスメモリ）、演算処理プログラムや後述する劣化判定方法を実行するためのプログラムが記憶されたＲＯＭ（Read Only Memory：リードオンリーメモリ）などによって構成されている。   The arithmetic processing unit 16 stores a CPU (Central Processing Unit), a RAM (Random Access Memory), an arithmetic processing program, and a program for executing a later-described deterioration determination method. A ROM (Read Only Memory) is used.

また、本実施例において、演算処理装置１６には、各蓄電セルＣ1〜Ｃnの均等化制御回数が記憶される均等化回数記憶部２４を備えている。なお、本実施例では、独立した均等化回数記憶部２４を備えているが、演算処理装置１６のＲＡＭを均等化回数記憶部２４として、均等化回数を記憶するようにしてもよい。 In the present embodiment, the arithmetic processing unit 16 includes an equalization number storage unit 24 that stores the equalization control number of each of the storage cells C 1 to C n . In this embodiment, the independent equalization count storage unit 24 is provided. However, the RAM of the arithmetic processing device 16 may be used as the equalization count storage unit 24 to store the equalization count.

また、演算処理装置１６と均等化ＩＣ１４は、例えば、演算処理装置１６から均等化ＩＣ１４へ制御命令を送信したり、均等化ＩＣ１４から演算処理装置１６へセル電圧値や電流値などを送信したりするなど、双方向に通信するための通信手段２０を備えている。   Further, the arithmetic processing device 16 and the equalization IC 14 transmit, for example, a control command from the arithmetic processing device 16 to the equalization IC 14, or transmit a cell voltage value, a current value, or the like from the equalization IC 14 to the arithmetic processing device 16. For example, the communication means 20 for two-way communication is provided.

また、蓄電装置１０の蓄電部２２は、ｎ個の蓄電セルＣ1〜Ｃnが直列に接続されて構成される。
蓄電部２２の両端は電源回路１８に接続されており、蓄電部２２の電力を用いて演算処理装置１６を動作させるように構成されている。すなわち、本実施例の蓄電装置１０においては、蓄電装置１０自身の電力を用いて、蓄電セルＣ1〜Ｃnの均等化制御を行うことができる。 The power storage unit 22 of the power storage device 10 is configured by connecting n power storage cells C 1 to C n in series.
Both ends of the power storage unit 22 are connected to the power supply circuit 18, and are configured to operate the arithmetic processing device 16 using the power of the power storage unit 22. In other words, in the power storage device 10 of the present embodiment, the equalization control of the power storage cells C 1 to C n can be performed using the power of the power storage device 10 itself.

なお、本実施例では、蓄電装置１０自身の電力を用いて演算処理装置１６を動作させる電源回路１８を備えているが、蓄電装置１０の外部からの電力を用いて演算処理装置１６を動作させるように構成する場合には、電源回路１８を備えずに、演算処理装置１６を動作させるための電力を外部から直接供給するように構成することもできる。   In the present embodiment, the power supply circuit 18 that operates the arithmetic processing device 16 using the power of the power storage device 10 itself is provided. However, the arithmetic processing device 16 is operated using power from outside the power storage device 10. In such a configuration, the power supply circuit 18 is not provided, and the power for operating the arithmetic processing device 16 can be directly supplied from the outside.

なお、本実施例においては、このような演算処理装置１６及び均等化回数記憶部２４を含む均等化制御回路１２によって劣化判定装置２６が構成されている。
以下、図２に示すフローチャートに基づいて、本実施例における蓄電セルの劣化判定を行う場合の、劣化判定装置２６の動作の流れを説明する。 In the present embodiment, the deterioration determination device 26 is configured by the equalization control circuit 12 including the arithmetic processing device 16 and the equalization number storage unit 24.
Hereinafter, based on the flowchart shown in FIG. 2, the operation flow of the deterioration determination device 26 when performing deterioration determination of the storage cell in the present embodiment will be described.

図２は、図１の蓄電装置１０において、劣化判定装置２６を用いて蓄電セルＣ1〜Ｃnの均等化制御を行うとともに劣化判定を行う流れを示すフローチャートである。
均等化制御回路１２が作動すると（Ｓ１０）、まず、セル電圧検出回路（均等化ＩＣ１４）を用いて、蓄電セルＣ1〜Ｃnのセル電圧が順次測定される（Ｓ２０）。 FIG. 2 is a flowchart illustrating a flow of performing deterioration determination while performing equalization control of the storage cells C 1 to C n using the deterioration determination device 26 in the power storage device 10 of FIG.
When the equalization control circuit 12 operates (S10), first, the cell voltages of the storage cells C 1 to C n are sequentially measured using the cell voltage detection circuit (equalization IC 14) (S20).

全ての蓄電セルＣ1〜Ｃnについてセル電圧が測定されたか否かが判断され（Ｓ３０）、セル電圧が測定されていない蓄電セルがある場合には、Ｓ２０に戻って、次の蓄電セルのセル電圧が測定される。なお、測定されたセル電圧の値は、蓄電セルＣ1〜Ｃnに関連付けて演算処理装置１６のＲＡＭに記憶される。 It is determined whether or not the cell voltage has been measured for all the power storage cells C 1 to C n (S30). If there is a power storage cell for which the cell voltage has not been measured, the process returns to S20 to determine the next power storage cell. The cell voltage is measured. Note that the measured cell voltage value is stored in the RAM of the arithmetic processing unit 16 in association with the storage cells C 1 to C n .

次に、演算処理装置１６のＲＡＭに記憶された蓄電セルＣ1〜Ｃnのセル電圧値から、演算処理装置１６によって、蓄電セルＣ1〜Ｃnの均等化制御が必要か否かが判断される（Ｓ４０）。 Next, based on the cell voltage values of the storage cells C 1 to C n stored in the RAM of the arithmetic processing unit 16, the arithmetic processing unit 16 determines whether equalization control of the storage cells C 1 to C n is necessary. (S40).

蓄電セルＣ1〜Ｃnの均等化制御が必要か否かは、例えば、蓄電セルのうち最も高いセル電圧値と、最も低いセル電圧値の差が、所定の値よりも大きい場合や、蓄電セルのセル電圧値が、所定の上限電圧値よりも大きい場合などには、均等化制御が必要であると判断することができる。 Whether or not the equalization control of the power storage cells C 1 to C n is necessary depends on, for example, when the difference between the highest cell voltage value and the lowest cell voltage value among the power storage cells is larger than a predetermined value. When the cell voltage value of the cell is larger than a predetermined upper limit voltage value, it can be determined that equalization control is necessary.

均等化制御が不要と判断された場合には、Ｓ２０に戻って、再度、蓄電セルＣ1〜Ｃnのセル電圧の測定が行われる。
一方で、均等化制御が必要と判断された場合には、均等化目標電圧値ＶTを設定する（Ｓ５０）。 If it is determined that the equalization control is unnecessary, the process returns to S20 and the cell voltages of the storage cells C 1 to C n are measured again.
On the other hand, if it is determined that equalization control is necessary, the equalization target voltage value V T is set (S50).

均等化目標電圧値ＶTは、例えば、所定の電圧値とすることもできるし、蓄電セルＣ1〜Ｃnのセル電圧値の平均としたり、均等化制御の都度、ユーザーによって入力するように構成することもできる。 For example, the equalization target voltage value V T may be a predetermined voltage value, or may be an average of the cell voltage values of the storage cells C 1 to C n , or may be input by the user every time equalization control is performed. It can also be configured.

次いで、演算処理装置１６において、各蓄電セルＣ1〜Ｃnのセル電圧値と、均等化目標電圧値ＶTとを比較することによって、均等化目標電圧値ＶTよりもセル電圧値が高い蓄電セルを均等化制御対象セルＣm（ｍはセルの番号であって、１〜ｎ（ｎ≧２）の間の値）に決定する（Ｓ６０）。 Then, the arithmetic processing unit 16, by comparing the cell voltage values of the respective storage cells C 1 -C n, the equalization target voltage value V T, high cell voltage value than equalization target voltage value V T The storage cell is determined to be equalization control target cell C m (m is a cell number and is a value between 1 and n (n ≧ 2)) (S60).

そして、均等化制御対象セルＣmに対して並列に接続された均等化制御用スイッチＳmを順次入状態として、均等化制御対象セルＣmから均等化制御用抵抗Ｒmへ電流を流し、均等化制御対象セルＣmのセル電圧が均等化目標電圧値ＶTとなるまで電荷を消費させることで、均等化制御対象セルＣmの均等化制御が実行される（Ｓ７０）。 And the connected equalizing control switch S m as a sequential input states in parallel to the equalization control target cell C m, a current flows from the equalization control target cell C m to equalization control resistor R m, by cell voltage equalization control target cell C m is to consume the charge until equalization target voltage value V T, the equalization control equalization control target cell C m is performed (S70).

なお、このような均等化制御を行う場合には、均等化制御対象セルＣmのセル電圧を常時または定期的に監視することによって、均等化制御対象セルＣmのセル電圧が均等化目標電圧値ＶTとなった場合に、均等化制御用スイッチＳmを切状態として均等化制御を完了することができる。 In the case, the equalization control target cells C by the cell voltage constantly or periodically monitor the m, equalization control target cell C cell voltage equalization target voltage m performing such equalization control when a value V T, it is possible to complete the equalization control the equalization control switch S m as a switching condition.

もしくは、均等化制御開始時の均等化制御対象セルＣmのセル電圧と均等化目標電圧値ＶTとから、演算処理装置１６によって均等化制御時間を算出して、均等化制御対象セルＣmの均等化制御が開始してから、均等化制御時間が経過した時点で、均等化制御用スイッチＳmを切状態として均等化制御を完了するようにしてもよい。 Alternatively, the equalization control time is calculated by the arithmetic processing unit 16 from the cell voltage of the equalization control target cell C m at the start of the equalization control and the equalization target voltage value V T, and the equalization control target cell C m is calculated. from the start of the equalization control, at the time when the equalization control time has elapsed, it may be complete equalization control the equalization control switch S m as a switching condition.

均等化制御対象セルに決定された蓄電セル全てについて、均等化制御が行われたか否かが判断され（Ｓ８０）、均等化制御が行われていない蓄電セルがある場合には、Ｓ７０に戻って、繰り返し蓄電セルの均等化制御が行われる。   It is determined whether or not equalization control has been performed for all the storage cells determined as equalization control target cells (S80). If there is a storage cell that has not been subjected to equalization control, the process returns to S70. The equalization control of the storage cells is repeatedly performed.

均等化制御対象セルに決定された蓄電セル全てについて均等化制御が完了した場合には、均等化制御された蓄電セルについて、均等化回数記憶部２４に記憶された各蓄電セルＣ1〜Ｃnの均等化回数を増加（インクリメント）する。（Ｓ９０）。 When the equalization control is completed for all the storage cells determined as the equalization control target cells, the storage cells C 1 to C n stored in the equalization count storage unit 24 for the storage cells subjected to the equalization control. Increase (increment) the number of equalizations. (S90).

これによって、均等化制御が行われるたびに、均等化回数が１増加するため、各蓄電セルについて均等化制御が行われた回数が計数されることになる。
次いで、均等化回数記憶部２４に記憶された各蓄電セルＣ1〜Ｃnの均等化回数に基づいて、蓄電装置１０の劣化判定が行われる（Ｓ１００）。 Thus, each time equalization control is performed, the number of equalizations increases by 1. Therefore, the number of times equalization control is performed for each power storage cell is counted.
Next, the deterioration determination of the power storage device 10 is performed based on the number of equalizations of the respective power storage cells C 1 to C n stored in the equalization number storage unit 24 (S100).

蓄電装置１０の劣化判定方法としては、例えば、各蓄電セルＣ1〜Ｃnの均等化回数のうち、最も均等化回数が大きい値（均等化回数最大値Ａ）と、最も均等化回数が小さい値（均等化回数最小値Ｂ）との差分が、所定の劣化判定値Ｊ1よりも大きい場合に、劣化した蓄電セルが存在するとして、蓄電装置１０が劣化していると判定することができる。 As a method for determining the deterioration of the power storage device 10, for example, among the equalization counts of the power storage cells C 1 to C n , the value with the largest equalization count (maximum equalization count maximum value A) and the smallest equalization count are, for example. difference between the value (minimum value B equalization times) is greater than the predetermined deterioration determination value J 1, as degraded storage cell is present, it can be determined that power storage device 10 is degraded .

蓄電装置１０が劣化していないと判定された場合には、Ｓ２０に戻って、再度、均等化制御の処理が行われることになる。
一方で、蓄電装置１０が劣化していると判定された場合には、各蓄電セルの均等化回数と、下記式（１）によって算出される劣化判定閾値Ｔ1とを比較して、均等化回数が劣化判定閾値Ｔ1以下の蓄電セルを、劣化した蓄電セルであると判定する（Ｓ１１０）。
式（１）：劣化判定閾値Ｔ1＝均等化回数最大値Ａ−劣化判定値Ｊ1 If it is determined that the power storage device 10 has not deteriorated, the process returns to S20 and the equalization control process is performed again.
On the other hand, when it is determined that the power storage device 10 has deteriorated, the number of equalizations of each power storage cell is compared with the deterioration determination threshold value T 1 calculated by the following equation (1) to equalize The storage cell whose number of times is equal to or less than the deterioration determination threshold value T 1 is determined to be a deteriorated storage cell (S110).
Formula (1): Deterioration determination threshold T 1 = Equalization maximum value A−Deterioration determination value J 1

劣化した蓄電セルを含む複数の蓄電セルに対して均等化制御を行おうとすると、均等化制御が繰り返されることになり、蓄電装置１０の電圧低下が進む原因となるため、このように、蓄電セルの劣化を検出した場合には、均等化制御を中止するように構成することが好ましい。   When the equalization control is performed on a plurality of storage cells including the deteriorated storage cell, the equalization control is repeated, which causes the voltage drop of the storage device 10 to proceed. It is preferable to configure so that the equalization control is stopped when the deterioration is detected.

なお、本実施例では、所定の劣化判定値Ｊ1を用いて、蓄電装置及び蓄電セルの劣化判定を行っているが、例えば、演算処理装置１６において、各蓄電セルＣ1〜Ｃnの均等化回数のばらつきを解析し、均等化回数が極端に少ない蓄電セルを、劣化した蓄電セルであると判定することもできる。 In the present embodiment, the deterioration determination of the power storage device and the power storage cell is performed using the predetermined deterioration determination value J 1. For example, in the arithmetic processing device 16, the power storage cells C 1 to C n are equalized. By analyzing the variation in the number of times of equalization, it is possible to determine that a storage cell having an extremely small number of equalizations is a deteriorated storage cell.

図３は、別の実施例の劣化判定装置を備える蓄電装置の回路構成図である。
なお、この実施例の蓄電装置１０は、図１に示す蓄電装置１０と基本的には同様な構成であり、同一の構成部材には、同一の符号を付して、その詳細な説明を省略する。 FIG. 3 is a circuit configuration diagram of a power storage device including a deterioration determination device according to another embodiment.
The power storage device 10 of this embodiment has basically the same configuration as that of the power storage device 10 shown in FIG. 1, and the same components are denoted by the same reference numerals and detailed description thereof is omitted. To do.

図１に示す実施例の蓄電装置１０では、均等化目標電圧値ＶTよりもセル電圧の高い蓄電セルを放電することによって、均等化制御を行っているが、本実施例の蓄電装置１０では、均等化目標電圧値ＶTよりもセル電圧の低い蓄電セルに対して補充電を行うことによって均等化制御を行うように構成されている。 In the power storage device 10 of the embodiment shown in FIG. 1, equalization control is performed by discharging a power storage cell having a cell voltage higher than the equalization target voltage value V T. The equalization control is performed by performing supplementary charging on the storage cell having a cell voltage lower than the equalization target voltage value V T.

具体的には、均等化制御用抵抗Ｒ1〜Ｒnの代わりに、各蓄電セルＣ1〜Ｃnを個別に充電することができる補充電回路Ｅ1〜Ｅnを備えている。
なお、補充電回路Ｅ1〜Ｅnは、本実施例のように、電源回路１８を介して、蓄電部２２の電力を用いて動作させることもできるし、また、蓄電装置１０の外部からの電力を用いて動作させるように構成することもできる。 Specifically comprises instead of equalizing control resistor R 1 to R n, a supplemental charging circuit E 1 to E n of the respective storage cells C 1 -C n can be charged separately.
The auxiliary charging circuits E 1 to E n can be operated using the electric power of the power storage unit 22 via the power supply circuit 18 as in the present embodiment, and can also be operated from the outside of the power storage device 10. It can also be configured to operate using electric power.

本実施例においては、補充電回路Ｅ1〜Ｅn及び均等化制御用スイッチＳ1〜Ｓnによって、均等化回路が構成されている。
このように構成された蓄電装置１０では、図４に示すフローチャートに基づいて、蓄電セルの劣化判定を行うことができる。 In the present embodiment, the auxiliary charging circuit E 1 to E n and equalization control switch S 1 to S n, the equalization circuit is configured.
In the power storage device 10 configured as described above, the deterioration determination of the power storage cell can be performed based on the flowchart shown in FIG.

以下、図４に示すフローチャートに基づいて、図２に示すフローチャートとは異なる動作の流れについてのみ説明する。
本実施例においては、Ｓ５０において、均等化目標電圧値ＶTを設定した後、演算処理装置１６において、各蓄電セルＣ1〜Ｃnのセル電圧値と、均等化目標電圧値ＶTとを比較することによって、均等化目標電圧値ＶTよりもセル電圧値が低い蓄電セルを均等化制御対象セルＣm（ｍはセルの番号であって、１〜ｎ（ｎ≧２）の間の値）に決定する（Ｓ６５）。 Hereinafter, based on the flowchart shown in FIG. 4, only the flow of operations different from the flowchart shown in FIG. 2 will be described.
In this embodiment, after setting the equalization target voltage value V T in S50, the arithmetic processing unit 16 determines the cell voltage value of each of the storage cells C 1 to C n and the equalization target voltage value V T. By comparing, the storage cells having a cell voltage value lower than the equalization target voltage value V T are equalized control target cells C m (m is a cell number and is between 1 and n (n ≧ 2)). Value) (S65).

そして、均等化制御対象セルＣmに対して並列に接続された均等化制御用スイッチＳmを順次入状態として、補充電回路から均等化制御対象セルＣmへ電流を流し、均等化制御対象セルＣmのセル電圧が均等化目標電圧値ＶTとなるまで補充電することで、均等化制御対象セルＣmの均等化制御が実行される（Ｓ７５）。 Then, as a sequential input states equalization control switch S m, which is connected in parallel to the equalization control target cell C m, a current flows to the equalization control target cell C m from supplemental charge circuit, equalization control object By performing supplementary charging until the cell voltage of the cell C m reaches the equalization target voltage value V T , equalization control of the equalization control target cell C m is executed (S75).

このように、補充電による均等化制御を行う場合には、Ｓ１１５において、例えば、均等化回数が、下記式（２）によって算出される劣化判定閾値Ｔ2以上の蓄電セルを、劣化した蓄電セルであると判定することができる。
式（２）：劣化判定閾値Ｔ2＝均等化回数最小値Ｂ＋劣化判定値Ｊ2 Thus, when performing the equalization control by auxiliary charge, in S115, for example, the power storage cell equalization number, the deterioration determination threshold T 2 or more storage cells which is calculated by the following equation (2), deteriorated It can be determined that
Formula (2): Degradation threshold value T 2 = Equalization count minimum value B + Degradation criterion value J 2

以上、本発明の好ましい実施の形態を説明してきたが、本発明はこれに限定されることはなく、例えば、上記実施例では、蓄電セルＣ1〜Ｃnのセル電圧測定や均等化制御などを順次実行するように構成しているが、セル電圧測定や均等化制御を全て同時に実行するようにしてもよいなど、本発明の目的を逸脱しない範囲で種々の変更が可能である。 The preferred embodiment of the present invention has been described above, but the present invention is not limited to this. For example, in the above embodiment, cell voltage measurement and equalization control of the storage cells C 1 to C n are performed. However, various modifications can be made without departing from the object of the present invention, such as performing all cell voltage measurement and equalization control at the same time.

１０ 蓄電装置
１２ 均等化制御回路
１４ 均等化ＩＣ
１６ 演算処理装置
１８ 電源回路
２０ 通信手段
２２ 蓄電部
２４ 均等化回数記憶部
２６ 劣化判定装置
Ｃ1〜Ｃn 蓄電セル
Ｃｍ 均等化制御対象セル
Ｅ1〜Ｅn 補充電回路
Ｒ1〜Ｒn 均等化制御用抵抗
Ｒm 均等化制御用抵抗
Ｓ1〜Ｓn 均等化制御用スイッチ
Ｓｍ 均等化制御用スイッチ
１００ 蓄電装置
１０２ 均等化制御回路
１０４ マイコン
ＣS1〜ＣSn 蓄電セル
ＲS1〜ＲSn 抵抗
ＳS1〜ＳSn スイッチ
ＶS1〜ＶSn 電圧計 10 Power Storage Device 12 Equalization Control Circuit 14 Equalization IC
16 processing unit 18 power supply circuit 20 communication means 22 power storage unit 24 equalization count storage unit 26 deterioration determination device C 1 -C n storage cells Cm equalization control target cells E 1 to E n auxiliary charge circuit R 1 to R n equal of the control resistor R m equalization control resistor S 1 to S n equalization control switch Sm equalization control switch 100 power storage device 102 equalizing control circuit 104 microcomputer C S1 -C Sn storage cell R S1 to R Sn resistance S S1 to S Sn switch V S1 to V Sn voltmeter

Claims (17)

複数の蓄電セルを含む蓄電装置において、蓄電セルの劣化判定を行う劣化判定装置であって、
前記複数の蓄電セルに接続された均等化制御回路と、
前記均等化制御回路を制御するとともに、均等化制御回数が記憶される均等化回数記憶部を有する演算処理装置と、を備え、
前記演算処理装置が、
前記蓄電セルのうち均等化制御が必要な均等化制御対象セルを決定し、
前記均等化制御対象セルに対して、前記均等化制御対象セルの均等化制御を行い、
均等化制御された蓄電セルについて、前記均等化回数記憶部に記憶された各蓄電セルの均等化回数を増加し、
前記均等化回数記憶部に記憶された各蓄電セルの均等化回数に基づいて、前記各蓄電セルの劣化判定を行うように構成されていることを特徴とする劣化判定装置。 In a power storage device including a plurality of power storage cells, a deterioration determination device that performs deterioration determination of a power storage cell,
An equalization control circuit connected to the plurality of storage cells;
An arithmetic processing unit that controls the equalization control circuit and has an equalization number storage unit in which the equalization control number is stored;
The arithmetic processing unit is
Determine an equalization control target cell that needs equalization control among the storage cells,
Perform equalization control of the equalization control target cell for the equalization control target cell,
For the storage cells that are equalized, increase the number of equalizations of each storage cell stored in the equalization number storage unit,
A deterioration determination device configured to perform deterioration determination of each power storage cell based on the number of times equalization of each power storage cell stored in the equalization number storage unit. 前記均等化制御回路が、前記複数の蓄電セルに対してそれぞれ並列に接続された均等化制御用抵抗及び均等化制御用スイッチを備えることを特徴とする請求項１に記載の劣化判定装置。   The degradation determination apparatus according to claim 1, wherein the equalization control circuit includes an equalization control resistor and an equalization control switch connected in parallel to the plurality of power storage cells. 前記均等化制御対象セルに対して並列に接続された前記均等化制御用スイッチを入状態とすることによって、前記均等化制御対象セルから前記均等化制御用抵抗に電流を流して、前記均等化制御対象セルの均等化制御を行うように構成されていることを特徴とする請求項２に記載の劣化判定装置。   By turning on the equalization control switch connected in parallel to the equalization control target cell, a current is passed from the equalization control target cell to the equalization control resistor, and the equalization control target cell The deterioration determination apparatus according to claim 2, wherein the deterioration determination apparatus is configured to perform equalization control of a control target cell. 前記演算処理装置が、前記均等化回数記憶部に記憶された各蓄電セルの均等化回数のうち、最も均等化回数が大きい値、すなわち均等化回数最大値Ａと、最も均等化回数が小さい値、すなわち均等化回数最小値Ｂとの差分を算出し、該差分が、所定の劣化判定値Ｊ1よりも大きい場合に、劣化した蓄電セルが存在すると判定することを特徴とする請求項２または３に記載の劣化判定装置。 Among the equalization times of each storage cell stored in the equalization number storage unit, the arithmetic processing unit has a value with the largest equalization number, that is, a maximum equalization number A and a value with the smallest equalization number. That is, a difference from the equalization number minimum value B is calculated, and when the difference is larger than a predetermined deterioration determination value J 1 , it is determined that a deteriorated power storage cell exists. 3. The deterioration determination device according to 3. 前記演算処理装置において、前記均等化回数記憶部に記憶された各蓄電セルの均等化回数と、下記式（１）によって算出される劣化判定閾値Ｔ1とを比較し、
前記均等化回数が、前記劣化判定閾値Ｔ1以下の蓄電セルを、劣化した蓄電セルであると判定することを特徴とする請求項４に記載の劣化判定装置。
式（１）：劣化判定閾値Ｔ1＝均等化回数最大値Ａ−劣化判定値Ｊ1 In the arithmetic processing unit, the equalization frequency of each power storage cell stored in the equalization frequency storage unit is compared with the deterioration determination threshold value T 1 calculated by the following equation (1).
The deterioration determination apparatus according to claim 4, wherein a storage cell having the equalization count equal to or less than the deterioration determination threshold value T 1 is determined to be a deteriorated storage cell.
Formula (1): Deterioration determination threshold T 1 = Equalization maximum value A−Deterioration determination value J 1 前記均等化制御回路が、前記複数の蓄電セルに対してそれぞれ並列に接続された補充電回路及び均等化制御用スイッチを備えることを特徴とする請求項１に記載の劣化判定装置。   The deterioration determination apparatus according to claim 1, wherein the equalization control circuit includes an auxiliary charging circuit and an equalization control switch connected in parallel to each of the plurality of power storage cells. 前記均等化制御対象セルに対して並列に接続された前記均等化制御用スイッチを入状態とすることによって、前記補充電回路から前記均等化制御対象セルに電流を流して、前記均等化制御対象セルの均等化制御を行うように構成されていることを特徴とする請求項６に記載の劣化判定装置。   By turning on the equalization control switch connected in parallel to the equalization control target cell, a current flows from the auxiliary charging circuit to the equalization control target cell, and the equalization control target The deterioration determination apparatus according to claim 6, wherein the deterioration determination apparatus is configured to perform equalization control of cells. 前記演算処理装置が、前記均等化回数記憶部に記憶された各蓄電セルの均等化回数のうち、最も均等化回数が大きい値、すなわち均等化回数最大値Ａと、最も均等化回数が小さい値、すなわち均等化回数最小値Ｂとの差分を算出し、該差分が、所定の劣化判定値Ｊ2よりも大きい場合に、劣化した蓄電セルが存在すると判定することを特徴とする請求項６または７に記載の劣化判定装置。 Among the equalization times of each storage cell stored in the equalization number storage unit, the arithmetic processing unit has a value with the largest equalization number, that is, a maximum equalization number A and a value with the smallest equalization number. That is, a difference from the equalization number minimum value B is calculated, and when the difference is larger than a predetermined deterioration determination value J 2 , it is determined that a deteriorated power storage cell exists. 8. The deterioration determination device according to 7. 前記演算処理装置において、前記均等化回数記憶部に記憶された各蓄電セルの均等化回数と、下記式（２）によって算出される劣化判定閾値Ｔ2とを比較し、
前記均等化回数が、前記劣化判定閾値Ｔ2以上の蓄電セルを、劣化した蓄電セルであると判定することを特徴とする請求項８に記載の劣化判定装置。
式（２）：劣化判定閾値Ｔ2＝均等化回数最小値Ｂ＋劣化判定値Ｊ2 In the arithmetic processing unit, the equalization frequency of each power storage cell stored in the equalization frequency storage unit is compared with the deterioration determination threshold value T 2 calculated by the following equation (2).
The equalization times is, the deterioration determination device according to claim 8, wherein determining that the deterioration determination threshold T 2 or more storage cells, is degraded storage cells.
Formula (2): Degradation threshold value T 2 = Equalization count minimum value B + Degradation criterion value J 2 複数の蓄電セルを含む蓄電装置において、蓄電セルの劣化判定を行う劣化判定方法であって、
前記複数の蓄電セルに対して均等化制御を行う工程と、
前記各蓄電セルについて均等化制御が行われた回数を計数する工程と、
各蓄電セルの均等化回数に基づいて、前記各蓄電セルの劣化判定を行う工程と、
を有することを特徴とする劣化判定方法。 In a power storage device including a plurality of power storage cells, a deterioration determination method for determining deterioration of a power storage cell,
Performing equalization control on the plurality of power storage cells;
Counting the number of times equalization control has been performed for each of the storage cells;
Determining deterioration of each power storage cell based on the number of equalization times of each power storage cell;
A degradation determination method characterized by comprising: 前記均等化制御が、均等化制御の対象である蓄電セルの電荷を消費することによって行われることを特徴とする請求項１０に記載の劣化判定方法。   The deterioration determination method according to claim 10, wherein the equalization control is performed by consuming charge of a storage cell that is a target of equalization control. 各蓄電セルの均等化回数のうち、最も均等化回数が大きい値、すなわち均等化回数最大値Ａと、最も均等化回数が小さい値、すなわち均等化回数最小値Ｂとの差分を算出し、該差分が、所定の劣化判定値Ｊ1よりも大きい場合に、劣化した蓄電セルが存在すると判定することを特徴とする請求項１１に記載の劣化判定方法。 Of the number of equalization times of each storage cell, the difference between the value with the largest equalization number, that is, the maximum number of equalizations A, and the value with the smallest number of equalizations, that is, the minimum number of equalization times B is calculated. The deterioration determination method according to claim 11, wherein when the difference is larger than a predetermined deterioration determination value J 1 , it is determined that a deteriorated power storage cell exists. 各蓄電セルの均等化回数と、下記式（１）によって算出される劣化判定閾値Ｔ1とを比較し、
前記均等化回数が、前記劣化判定閾値以下の蓄電セルを、劣化した蓄電セルであると判定することを特徴とする請求項１２に記載の劣化判定方法。
式（１）：劣化判定閾値Ｔ1＝均等化回数最大値Ａ−劣化判定値Ｊ1 The number of equalization times of each storage cell is compared with the deterioration determination threshold value T 1 calculated by the following equation (1).
The deterioration determination method according to claim 12, wherein a storage cell having the equalization count equal to or less than the deterioration determination threshold is determined to be a deteriorated storage cell.
Formula (1): Deterioration determination threshold T 1 = Equalization maximum value A−Deterioration determination value J 1 前記均等化制御が、均等化制御の対象である蓄電セルに補充電することによって行われることを特徴とする請求項１０に記載の劣化判定方法。   The deterioration determination method according to claim 10, wherein the equalization control is performed by performing supplementary charging on a power storage cell that is a target of equalization control. 各蓄電セルの均等化回数のうち、最も均等化回数が大きい値、すなわち均等化回数最大値Ａと、最も均等化回数が小さい値、すなわち均等化回数最小値Ｂとの差分を算出し、該差分が、所定の劣化判定値Ｊ2よりも大きい場合に、劣化した蓄電セルが存在すると判定することを特徴とする請求項１４に記載の劣化判定方法。 Of the number of equalization times of each storage cell, the difference between the value with the largest equalization number, that is, the maximum number of equalizations A, and the value with the smallest number of equalizations, that is, the minimum number of equalization times B is calculated. difference is greater than a predetermined deterioration determination value J 2, deterioration determination method according to claim 14, wherein determining that degraded storage cell is present. 各蓄電セルの均等化回数と、下記式（２）によって算出される劣化判定閾値Ｔ2とを比較し、
前記均等化回数が、前記劣化判定閾値以上の蓄電セルを、劣化した蓄電セルであると判定することを特徴とする請求項１５に記載の劣化判定方法。
式（２）：劣化判定閾値Ｔ2＝均等化回数最小値Ｂ＋劣化判定値Ｊ2 The number of equalization times of each storage cell is compared with the deterioration determination threshold value T 2 calculated by the following equation (2).
The deterioration determination method according to claim 15, wherein a storage cell having the equalization count equal to or greater than the deterioration determination threshold is determined to be a deteriorated storage cell.
Formula (2): Degradation threshold value T 2 = Equalization count minimum value B + Degradation criterion value J 2 請求項１０から１６のいずれかに記載の劣化判定方法を演算処理装置によって実行するためのプログラム。   The program for performing the deterioration determination method in any one of Claim 10 to 16 by an arithmetic processing unit.
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101610923B1 (en) 2014-12-11 2016-04-08 현대오트론 주식회사 Apparatus and method for autonomous battery balancing
JP2017175705A (en) * 2016-03-22 2017-09-28 Ntn株式会社 Secondary battery deterioration suppression device and individual deterioration suppression device
WO2017163990A1 (en) * 2016-03-22 2017-09-28 日本電気株式会社 Monitoring device, monitoring system, and monitoring method
JP2017181260A (en) * 2016-03-30 2017-10-05 住友重機械工業株式会社 Deterioration assessing device for power storage devices
JP2017204947A (en) * 2016-05-12 2017-11-16 株式会社ダイヘン Unmanned transportation vehicle system
KR20220105895A (en) * 2021-01-21 2022-07-28 주식회사 미지에너텍 Apparatus and method for controlling bettery power using cell balancing

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003282155A (en) * 2002-03-25 2003-10-03 Toyota Motor Corp Abnormality detection device of battery pack and abnormality detection method therefor
JP2011067047A (en) * 2009-09-18 2011-03-31 Mitsubishi Heavy Ind Ltd Battery system
US20110210701A1 (en) * 2010-02-26 2011-09-01 Sanyo Electric Co., Ltd Battery system
JP2011530697A (en) * 2008-08-08 2011-12-22 エルジー・ケム・リミテッド Cell balance apparatus and method using voltage change behavior of battery cell
JP2012186985A (en) * 2011-02-16 2012-09-27 Iks Co Ltd Secondary battery degradation determination method and secondary battery degradation determination apparatus

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003282155A (en) * 2002-03-25 2003-10-03 Toyota Motor Corp Abnormality detection device of battery pack and abnormality detection method therefor
JP2011530697A (en) * 2008-08-08 2011-12-22 エルジー・ケム・リミテッド Cell balance apparatus and method using voltage change behavior of battery cell
JP2011067047A (en) * 2009-09-18 2011-03-31 Mitsubishi Heavy Ind Ltd Battery system
US20110210701A1 (en) * 2010-02-26 2011-09-01 Sanyo Electric Co., Ltd Battery system
JP2012186985A (en) * 2011-02-16 2012-09-27 Iks Co Ltd Secondary battery degradation determination method and secondary battery degradation determination apparatus

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101610923B1 (en) 2014-12-11 2016-04-08 현대오트론 주식회사 Apparatus and method for autonomous battery balancing
JP2017175705A (en) * 2016-03-22 2017-09-28 Ntn株式会社 Secondary battery deterioration suppression device and individual deterioration suppression device
WO2017163990A1 (en) * 2016-03-22 2017-09-28 日本電気株式会社 Monitoring device, monitoring system, and monitoring method
JP2017181260A (en) * 2016-03-30 2017-10-05 住友重機械工業株式会社 Deterioration assessing device for power storage devices
JP2017204947A (en) * 2016-05-12 2017-11-16 株式会社ダイヘン Unmanned transportation vehicle system
US10919399B2 (en) 2016-05-12 2021-02-16 Daihen Corporation Vehicle system
KR20220105895A (en) * 2021-01-21 2022-07-28 주식회사 미지에너텍 Apparatus and method for controlling bettery power using cell balancing
KR102572353B1 (en) * 2021-01-21 2023-08-30 주식회사 미지에너텍 Apparatus and method for controlling bettery power using cell balancing

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