JP2014195396A - Output control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an output control circuit capable of suppressing power loss.SOLUTION: In the output control system for photovoltaic power generation apparatus, an output controller 20 comprises: a transfer gate section 22; a state setting section 23; an input gate section 24; and an impedance monitor section 25. When an output impedance of a dye-sensitized solar cell detected by the impedance monitor section 25 is not less than a predetermined impedance, the transfer gate section 22 is set to a conduction state by the state setting section 23. When the output impedance is less than the predetermined impedance, the transfer gate section 22 is set to a cut-off state by the state setting section 23. This prevents electric energy from being consumed by electric currents rushed into the dye-sensitized solar cell with low impedance. Thus, power loss can be suppressed.

Description

  The present invention relates to an output control circuit capable of outputting, to an output side, power output from a power output device connected to the input side.

  As a technique related to the output control circuit, for example, there is “a lighting device using a dye-sensitized solar cell and a display device using the lighting device” disclosed in Patent Document 1 below. In this technique, a voltage output from a dye-sensitized solar cell (power output device) is charged in a capacitor, and the output can be supplied to a light source (output side). A diode for preventing backflow is connected in series to this dye-sensitized solar cell (Patent Document 1; paragraph 0043, FIG. 1).

  Generally, in the dye-sensitized solar cell, the open circuit voltage is determined by the difference between the Fermi level of the semiconductor electrode material and the redox level of the electrolyte solution, and the open circuit voltage is determined by the combination of the type of the semiconductor electrode material and the electrolyte solution. . In the current technical level, the output voltage of one battery cell (hereinafter referred to as “single cell”) remains around 0.5V. Therefore, in the single cell, the output voltage is lower than the voltage drop due to the backflow prevention diode (the drop voltage Vf is about 0.6 V at the silicon diode), so it is difficult to take out the output through such a diode. For example, in the disclosed technology disclosed in Patent Document 1, an output voltage exceeding the drop voltage Vf is obtained by connecting a plurality of battery cells in series to increase the electromotive force.

By the way, the equivalent circuit model of the dye-sensitized solar cell is represented as shown in FIG. 26 (Non-Patent Document 1; pages 170 to 177, analysis of internal resistance of the dye-sensitized solar cell (Naoki Koide)). ). In FIG. 26, I _ph is a constant current source representing photoexcited carriers due to light irradiation, D is a diode representing the characteristics of a pn junction, R _sh is a parallel resistance component caused by a leakage current through impurities, etc., and R _h is a main component The impedance component due to the resistance of the conductive transparent electrode (SnO ₂ etc.), R ₁ and C ₁ are the impedance components due to the redox reaction at the counter electrode interface, and R ₃ and C ₃ are the diffusion reaction of the electrolyte in the electrolyte The impedance components resulting from are shown respectively.

JP 2012-167470 A Edited by Hironori Arakawa “Latest Dye-Sensitized Solar Cell Technology II” published by CMC Publishing Co., Ltd. May 2007

  According to the equivalent circuit model of Non-Patent Document 1, the dye-sensitized solar cell acts as an electric resistance (hereinafter referred to as “resistance”) when it fails or deteriorates. It also acts as a resistance when not exposed to sunlight. Therefore, if any of the battery cells connected in series fails or deteriorates, or if it is difficult for sunlight to hit part of the battery cells due to shade, etc. The cell becomes a resistance, and not all battery cells can generate electricity satisfactorily. Therefore, in such a case, the disclosed technique disclosed in Patent Document 1 has a problem that, if there is a cell acting as a resistance among the cells connected in series, power loss may occur due to the resistance.

  Further, if a configuration is adopted in which a diode for preventing backflow is not connected to the dye-sensitized solar cell, a current in the reverse direction (the reverse direction of the current I shown in FIG. 26) can flow into the dye-sensitized solar cell. For this reason, such a current flows to the negative electrode side as a forward current or a leakage current of the diode D of the equivalent circuit model. The same applies when the dye-sensitized solar cell has failed in the short-circuit mode. Therefore, there is a problem that the electric energy stored outside is consumed by the dye-sensitized solar cell.

  SUMMARY An advantage of some aspects of the invention is that it provides an output control circuit capable of suppressing power loss.

  In order to achieve the above object, an output control circuit according to claim 1 of the claims is an output control circuit capable of outputting power output from a power output device connected to an input side to the output side. A transfer gate interposed between the input side and the output side, and when the output impedance of the power output device is greater than or equal to a predetermined impedance, the input and output of the transfer gate is controlled to be in a conductive state, and the output impedance And a control circuit that controls the input and output to be cut off when the impedance is less than the predetermined impedance. Typically, the transfer gate is configured by connecting a first conductivity type transistor (for example, an N channel MOS transistor) and a second conductivity type transistor (for example, a P channel MOS transistor) in parallel. The “predetermined impedance” refers to an impedance corresponding to the output impedance of the power output device in a state where the power output device outputs power. For example, when the power output device is a battery, it is the internal resistance (internal impedance) of the battery during normal operation.

  Further, the output control circuit according to claim 2 of the claim is the output control circuit according to claim 1, wherein the control circuit conducts the detection circuit for detecting the output impedance and the transfer gate. And a setting circuit for setting the state or the cutoff state.

  Further, the output control circuit according to claim 3 of the claims is the output control circuit according to claim 2, wherein the detection circuit includes a threshold variable circuit that varies a detection threshold of the output impedance. Is a technical feature.

  According to a fourth aspect of the present invention, in the output control circuit according to the second or third aspect, the detection circuit detects the output impedance every predetermined time. Characteristic.

  Moreover, the output control circuit according to claim 5 of the claim is the output control circuit according to any one of claims 2 to 4, wherein the detection circuit outputs the detection result other than the setting circuit. It is a technical feature that the data is also output to the outside.

  The output control circuit according to claim 6 of the claim is the output control circuit according to claim 1, wherein the control circuit detects the output impedance, and outputs from the detection circuit. Based on the detected result, it is determined whether or not the output impedance at the end of the previous operation of the power output device is greater than or equal to a predetermined impedance, or whether or not the output impedance at the end is less than the predetermined impedance And a storage circuit for storing a determination result by the determination circuit, and when the output impedance at the end is equal to or higher than the predetermined impedance based on the determination result read from the storage circuit, the transfer The output impedance at the end is controlled by controlling the connection between the input and output of the gate. Wherein in the case it is less than a predetermined impedance and technical features to control the cut-off state between the input and output.

  The output control circuit according to claim 7 of the present invention is the output control circuit according to claim 1, wherein the transfer gate has a charge storage layer and corresponds to the amount of charge stored therein. A MOS transistor that operates in a depletion mode or an enhancement mode, and the control circuit sets the operation mode of the MOS transistor to a depletion mode when the output impedance of the power output device is greater than or equal to a predetermined impedance, and the output When the impedance is less than the predetermined impedance, the setting control circuit for setting the operation mode of the MOS transistor to the enhancement mode and when the MOS transistor is in the depletion mode, the input / output of the MOS transistor is made conductive. And technical features that are provided with, an operation control circuit for controlling the cut-off state between the input and output of the MOS transistor when the MOS transistor is an enhancement mode.

  The output control circuit according to claim 8 of the present invention is the output control circuit according to claim 7, wherein the setting control circuit injects electrons into the charge storage layer at the time of initialization. An initialization circuit for accumulating charge in the charge accumulation layer to place the MOS transistor in an enhancement mode, and when the output impedance of the power output device is equal to or higher than a predetermined impedance when the mode is set, the charge accumulation layer Withdrawing electrons and transferring the charge to the outside, the operation mode of the MOS transistor is changed to the depletion mode, and when the output impedance is less than the predetermined impedance, the operation mode of the MOS transistor is maintained in the enhancement mode. And an operation mode setting circuit.

  The output control circuit according to claim 9 of the present invention is the output control circuit according to claim 2, wherein the control circuit conducts the detection circuit for detecting the output impedance and the transfer gate. A setting circuit for setting the state or the cutoff state, and the setting circuit sets the transfer gate to the conduction state or the cutoff state according to control information input from the outside.

  The output control circuit according to claim 10 of the present invention is the output control circuit according to claim 2, wherein the control circuit conducts between the detection circuit for detecting the output impedance and the transfer gate. A setting circuit for setting the state or the cutoff state, and the setting circuit stores the conduction state or the cutoff state and outputs the stored state to the outside according to control information input from the outside. Is a technical feature.

  Further, the output control circuit according to claim 11 of the claims is the output control circuit according to claim 9 or 10, wherein the control circuit receives address information for specifying the control circuit. An address determination circuit for determining whether or not the setting circuit performs a predetermined operation according to the control information when the address determination circuit determines that address information for specifying the control circuit is input. Is a technical feature. In the “predetermined operation”, the transfer gate is set to a conduction state or a cutoff state (Claim 9), and the conduction state or the cutoff state stored in the setting circuit is output to the outside according to control information input from the outside. (Claim 10).

  A power storage control circuit according to claim 12 of the claims is connected to the output side of the output control circuit according to any one of claims 1 to 11 and is output from the output control circuit. A power storage control circuit for controlling charging / discharging of a power storage device that stores electrical energy, the voltage information output circuit for detecting the voltage of the power storage device and outputting voltage information, and the output of the power storage device in a first state Conducting a control circuit to charge the power storage device, and in the second state, shutting off the power storage device from the output control circuit and conducting to an external output to store the electrical energy stored in the power storage device to the external output A transfer gate for discharging and transmitting power, and the power storage device by the transfer gate based on the voltage information output from the voltage information output circuit. A charge / discharge control circuit for controlling charge / discharge of a chair, wherein the charge / discharge control circuit controls the transfer gate when the charge voltage of the power storage device is lower than a preset output allowable voltage. The state is controlled, and when the charging voltage of the power storage device is equal to or higher than the output allowable voltage, the transfer gate is controlled to the second state.

  Further, the storage control circuit according to claim 13 of the claim is the storage control circuit according to claim 12, wherein at least the voltage information output circuit and the transfer gate are formed on the same semiconductor substrate. Is a technical feature.

  A power storage control circuit according to claim 14 of the claims is connected to the output side of the output control circuit according to any one of claims 1 to 11 and is output from the output control circuit. An electrical storage control circuit for controlling charging / discharging of an electrical storage device for storing electrical energy, the switch circuit controlling electrical continuity and interruption between the output side of the output control circuit and the electrical storage device, and the electrical storage device storing A discharge circuit for releasing the electric energy to the low potential side, and the switch circuit and the discharge circuit are controlled according to control information input from the outside.

  Further, the storage control circuit according to claim 15 of the claim is the charge control circuit according to claim 15, wherein the storage device is connected to a semiconductor substrate on which the storage control circuit is formed by an MIM (Metal -Insulator-Metal) The feature is that it is formed by the structure.

  In the invention of claim 1, the transfer gate interposed between the input side and the output side is controlled by the control circuit so that the input and output are in a conductive state when the output impedance of the power output device is equal to or higher than the predetermined impedance. When the output impedance is less than the predetermined impedance, the input / output is controlled to be cut off. Typically, the transfer gate is configured by connecting a first conductivity type transistor (for example, an N channel MOS transistor) and a second conductivity type transistor (for example, a P channel MOS transistor) in parallel. For this reason, there is almost no voltage drop by a transfer gate. For example, in the case of a power output device whose output impedance decreases as the output voltage decreases, such as a dye-sensitized solar cell, when the output impedance is less than a predetermined impedance, the input and output between the transfer gates are Controlled to shut off state. For this reason, electric current is prevented from flowing into the power output device having a low impedance to consume electric energy. Therefore, power loss can be suppressed.

  According to a second aspect of the present invention, the control circuit includes a detection circuit that detects the output impedance, and a setting circuit that sets the transfer gate to a conductive state or a cut-off state. As a result, when the output impedance detected by the detection circuit is equal to or higher than the predetermined impedance, the transfer gate is set to the conductive state by the setting circuit, and when the output impedance is lower than the predetermined impedance, the transfer gate is set to the cutoff state by the setting circuit. Is done.

  According to a third aspect of the present invention, the detection circuit includes a threshold variable circuit that varies the detection threshold of the output impedance. As a result, it becomes possible to change the detection threshold of the output impedance, that is, the threshold for determining whether the output impedance is equal to or higher than the predetermined impedance, so that the output impedance of the power output device fluctuates or the power output Even if the output impedance varies from device to device, the detection threshold can be set to an optimum value. Therefore, power loss can be further suppressed.

  In the invention according to claim 4, the detection circuit detects the output impedance every predetermined time. Thereby, compared with the case where the detection circuit always detects the output impedance, the operation time of the detection circuit is reduced, so that the power consumption by the detection circuit can be reduced. In particular, when the active element of the control circuit is composed of MOS transistors, much of the drive power is consumed when the state changes, so that intermittent operation of the detection circuit in this way greatly increases the power consumption by the control circuit. Can be reduced.

  In the invention of claim 5, the detection circuit outputs the detection result to the outside other than the setting circuit. Thereby, the apparatus etc. which were provided outside for the said detection result are acquirable.

  In the invention of claim 6, the control circuit detects the output impedance, and based on the detection result output from the detection circuit, the output impedance at the end of the previous operation of the power output device is equal to or higher than the predetermined impedance And a determination circuit that determines whether or not the output impedance at the time of termination is less than a predetermined impedance, and a storage circuit that stores a determination result by the determination circuit. If the output impedance at the end is greater than or equal to a predetermined impedance based on the determination result read from the memory circuit, the input / output of the transfer gate is controlled to be conductive, and the output impedance at the end is less than the predetermined impedance. Controls the input and output to be disconnected. Thereby, for example, in the case of a power output device whose output impedance decreases as the output voltage decreases, such as a dye-sensitized solar cell, the output impedance at the end of the previous operation of the power output device is less than a predetermined impedance. Sometimes, the control circuit controls the input and output of the transfer gate to be in a disconnected state, thereby preventing current from flowing into the power output device having low impedance and consuming electrical energy. Also, at the time of restarting, the control circuit controls the transfer gate to the conductive state or the cut-off state based on the determination result stored in the storage circuit, so it is necessary to re-detect the output impedance by the detection circuit or the determination circuit, etc. In addition, the processing speed can be increased. Therefore, if the response is fast, the power loss can be further suppressed.

  According to a seventh aspect of the present invention, the transfer gate is a MOS transistor that has a charge storage layer and operates in a depletion mode or an enhancement mode according to the amount of charge stored in the charge storage layer, and the control circuit outputs the output of the power output device. A setting control circuit that sets the operation mode of the MOS transistor to the depletion mode when the impedance is equal to or higher than the predetermined impedance, and sets the operation mode of the MOS transistor to the enhancement mode when the output impedance is less than the predetermined impedance; When the transistor is in the depletion mode, the operation is controlled between the input and output of the MOS transistor, and when the MOS transistor is in the enhancement mode, the operation is controlled between the input and output of the MOS transistor. And a circuit. That is, according to the present invention, the MOS transistor functions as a transfer gate, and the MOS transistor is set to the depletion mode or the enhancement mode according to the output impedance, and the MOS transistor is connected between the input and output of the depletion mode. In the enhancement mode, the MOS transistor is controlled so as to be in a cut-off state. Thereby, since the transfer gate itself memorizes the state according to the output impedance of the power output device, it is not necessary to provide a separate memory circuit or the like. Therefore, the circuit configuration can be simplified.

  According to an eighth aspect of the present invention, the setting control circuit includes an initialization circuit that injects electrons into the charge storage layer and stores charges in the charge storage layer to set the MOS transistor in the enhancement mode at the time of initialization, and at the time of mode setting. When the output impedance of the power output device is equal to or higher than the predetermined impedance, the electrons are extracted from the charge storage layer and transferred to the outside to change the operation mode of the MOS transistor to the depletion mode. And an operation mode setting circuit for maintaining the operation mode of the MOS transistor in the enhancement mode. As a result, when the MOS transistor that has been set to the enhancement mode by the initialization circuit at the time of initialization is set to the depletion mode by the operation mode setting circuit when the output impedance of the power output device is equal to or higher than the predetermined impedance at the time of mode setting. If it is changed and the impedance is less than the predetermined impedance, the operation mode is maintained as it is in the enhancement mode by the operation mode setting circuit.

  According to a ninth aspect of the present invention, the control circuit includes a detection circuit that detects the output impedance, and a setting circuit that sets the transfer gate to a conductive state or a cut-off state. Then, the setting circuit sets the transfer gate to a conductive state or a cut-off state according to control information input from the outside. As a result, when the output impedance detected by the detection circuit is equal to or higher than the predetermined impedance, the transfer gate is set to the conductive state by the setting circuit, and when the output impedance is lower than the predetermined impedance, the transfer gate is set to the cutoff state by the setting circuit. Is done. In addition, regardless of the output impedance detected by the detection circuit, the transfer gate is forcibly set to a conductive state or a cut-off state according to control information input from the outside. Therefore, for example, since the failed power output device can be forcibly electrically disconnected from the output side, the power loss can be further suppressed by preventing power consumption by the failed power output device.

  According to a tenth aspect of the present invention, the control circuit includes a detection circuit that detects the output impedance and a setting circuit that sets the transfer gate to a conductive state or a cut-off state, and the setting circuit stores the conductive state or the cut-off state. At the same time, these stored states are output to the outside in accordance with control information input from the outside. As a result, when the output impedance detected by the detection circuit is equal to or higher than the predetermined impedance, the transfer gate is set to the conductive state by the setting circuit, and when the output impedance is lower than the predetermined impedance, the transfer gate is set to the cutoff state by the setting circuit. Is done. In addition, transfer gate conduction / shut-off state information set by the setting circuit is output to the outside in accordance with control information input from the outside. Therefore, it is possible to easily confirm the power generation state of the power output device by reading information on the state of conduction or cutoff of the transfer gate from the outside.

  In the eleventh aspect of the present invention, the control circuit further includes an address determination circuit that determines whether or not address information that specifies the control circuit is input, and the setting circuit receives address information that specifies the control circuit. If the address determination circuit determines that this is the case, a predetermined operation according to the control information is performed. Thereby, when the address information specifying the control circuit is not input, the control circuit does not perform the predetermined operation without following the control information. For example, when the predetermined operation according to the control information is to set the transfer gate to a conductive state or a cut-off state (Claim 9), the address information specifying the control circuit is input to the operation. Only done sometimes. Also, for example, when the predetermined operation according to the control information is to output the transfer gate conduction / shut-off state information stored in the setting circuit to the outside (Claim 10), the operation is performed by the control information. This is performed only when address information specifying a circuit is input. Therefore, when there are a plurality of output control circuits, a specific output control circuit can be designated by the address information to perform these predetermined operations.

  According to a twelfth aspect of the present invention, a voltage information output circuit, a transfer gate, and a charge / discharge control circuit are provided, and the charge / discharge control circuit sets the transfer gate when the charge voltage of the power storage device is less than a preset output allowable voltage. The storage device is controlled to the first state to conduct the storage device to the output control circuit to charge the storage device. When the charging voltage of the storage device is equal to or higher than the allowable output voltage, the transfer gate is controlled to the second state. Accordingly, the power storage control circuit connected to the output side of the output control circuit according to any one of claims 1 to 5 is configured such that when the charging voltage of the power storage device is equal to or higher than a preset output allowable voltage, the power storage device The electric energy stored in the battery is discharged to the external output via the transfer gate and transmitted, so that an external device or the like can receive power supply from the power storage control circuit.

  According to the thirteenth aspect of the present invention, at least the voltage information output circuit and the transfer gate are formed on the same semiconductor substrate. Therefore, it is possible to configure the both in a compact and low cost compared to the case where both are formed on separate semiconductor substrates. become. In addition, when the charge / discharge control circuit is formed on the same semiconductor substrate together with these, it can be configured more compactly and at low cost.

  The invention of claim 14 includes a switch circuit and a discharge circuit. The switch circuit controls electrical continuity and interruption between the output side of the output control circuit and the power storage device according to control information input from the outside, and the discharge circuit reduces the electrical energy stored in the power storage device. Escape to the potential side. As a result, normally, the power output from the power output apparatus can be stored in the power storage device by electrically connecting the output side of the output control circuit and the power storage device with the switch circuit in a conductive state. Further, the output side of the output control circuit and the power storage device are electrically disconnected by turning off the switch circuit, and the electrical energy of the power storage device is released to the low potential side by the discharge circuit. Thereby, the electrical energy stored in the electricity storage device can be made substantially zero. For example, the discharge characteristics of the electricity storage device can be confirmed by performing such an operation during maintenance. In addition, the charging characteristics of the power storage device can be confirmed by setting the switch circuit in a conductive state and electrically connecting the output side of the output control circuit to the power storage device that has released electrical energy to the low potential side.

  According to a fifteenth aspect of the present invention, the power storage device is formed with a MIM structure on a semiconductor substrate on which the power storage control circuit is configured. This enables the storage device to be manufactured as an MIM capacitor in the semiconductor manufacturing process that forms the storage control circuit, thereby reducing resistance loss and improving storage efficiency compared to the case where the storage device is configured separately. Can be made.

It is a block diagram which shows the structure outline | summary of the said system in 1st Embodiment which applied the output control circuit of this invention to the output control system of the solar power generation device. It is a circuit diagram which shows the structural example of the output control apparatus shown in FIG. It is a circuit diagram which shows the structural example of the electrical storage control apparatus shown in FIG. It is a timing chart which shows the example of control by the controller shown in FIG. 1, and is an example at the time of a dye-sensitized solar cell changing from a shade state to a sunshine state. It is a timing chart which shows the example of control by the controller shown in FIG. 1, and is an example at the time of a dye-sensitized solar cell changing from a sunshine state to a shade state. FIG. 6 is a circuit diagram showing a configuration when the threshold value by the impedance monitor unit is made variable as another configuration example of the output control device shown in FIG. 1. FIG. 7 is a circuit diagram showing a configuration when the impedance monitor unit includes a current mirror circuit as another configuration example of the output control device shown in FIG. 1. FIG. 5 is a circuit diagram showing a configuration when an impedance monitor unit is configured by an operational amplifier as another configuration example of the output control device illustrated in FIG. 1. FIG. 6 is a circuit diagram showing a configuration when a load element is added to the input side of the impedance monitor unit as another configuration example of the output control device shown in FIG. 1. It is a block diagram which shows the modification of the output control system shown in FIG. It is a circuit diagram which shows the structural example of the output control apparatus shown in FIG. It is a block diagram which shows the structure outline | summary of the said system in 2nd Embodiment which applied the output control circuit of this invention to the output control system of the solar power generation device. It is a circuit diagram which shows the structural example of the output control apparatus shown in FIG. It is a block diagram which shows the structure outline | summary of the said system in 3rd Embodiment which applied the output control circuit of this invention to the output control system of the solar power generation device. It is a circuit diagram which shows the structural example of the output control apparatus shown in FIG. It is a block diagram which shows the structure outline | summary of the said system in 4th Embodiment which applied the output control circuit of this invention to the output control system of the solar power generation device. FIG. 17 is a circuit diagram illustrating a configuration example of the output control device illustrated in FIG. 16, illustrating a circuit example of a power transfer unit and a cell state detection / holding unit. FIG. 17 is a circuit diagram illustrating a configuration example of the output control device illustrated in FIG. 16, and illustrates a circuit example of an R / W control unit. It is a circuit diagram which shows the structural example of the electrical storage control apparatus shown in FIG. FIG. 17 is a timing chart showing an example of normal control by the controller shown in FIG. 16, in which the dye-sensitized solar cell is changed from a sunshine state to a shade state. It is a timing chart which shows the example of control at the time of the maintenance by the controller shown in FIG. 16, and is an example at the time of forcibly setting a power transfer part to a conduction | electrical_connection state as a test function. FIG. 17 is a timing chart showing an example of control at the time of maintenance by the controller shown in FIG. 16, and is an example in the case where DSSC pass / fail information is read from the cell state detection / holding unit as a test function. It is typical sectional drawing of the semiconductor device which shows the structural example of the capacitor | condenser by a MIM (Metal-Insulator-Metal) structure. It is a typical sectional view of a semiconductor device showing other examples of composition of an N channel MOS transistor which functions as a transfer gate. FIG. 25A is an explanatory diagram illustrating a layout example when the output control system of the photovoltaic power generation apparatus is formed into a chip as a system LSI, and FIG. 25B is a dashed-dotted line α illustrating a layout example of the output control apparatus. FIG. 25C is an enlarged view showing an example of a comparison layout with respect to the layout example of FIG. 25B. It is explanatory drawing which shows the equivalent circuit model of a dye-sensitized solar cell.

  Hereinafter, a first embodiment to a fourth embodiment in which the output control circuit of the present invention is applied to an output control system (hereinafter referred to as “the present system”) of a solar power generation device will be described with reference to the drawings.

[First Embodiment]
First, a configuration outline of the present system will be described with reference to FIG. FIG. 1 is a block diagram showing an outline of the configuration of the present system. As shown in FIG. 1, this system mainly includes an output control device 20, a power storage control device 150, and a controller 170. In this system, generated power output from the plurality of DSSCs 10 is collected in the charge unit 190 of the power storage control device 150 via the output control device 20 and output as supply power.

  In the first embodiment, the output control device 20 is provided with an output control device 20 corresponding to each of the plurality of DSSCs 10. Therefore, as shown in FIG. 1, for convenience, “a”, “b”... “N”, etc. are added to the end of the reference numerals of the DSSC 10 and the output control device 20. The same configuration as the DSSC 10 and the output control device 20 is performed.

  DSSC 10 (10a, 10b, 10c, 10d,..., 10m, 10n) is a dye-sensitized solar cell that converts light energy into electrical energy. A typical example of the DSSC 10 is a Gretzel type. For example, a transparent electrode (one electrode (negative electrode)) in which titanium dioxide powder is baked to adsorb a pigment, and a counter electrode provided at a predetermined distance from the transparent electrode. (The other electrode (positive electrode)) and an iodine electrolyte solution (electrolyte solution) held between these electrodes.

  The principle of DSSC power generation is described in detail in Non-Patent Document 1 (edited by Hironori Arakawa, “Latest Dye-Sensitized Solar Cell II”), so please refer to that for details. In the first embodiment, the DSSC 10 is composed of a single cell, that is, one battery cell. Therefore, the output voltage of the DSSC 10 alone is around 0.5 V, and the obtained power remains in the milliwatt order. In the first embodiment, for example, the generated power is collected from several tens of cells to several hundreds of cells of DSSC 10 and stored in the charge unit 190 of the power storage control device 150 for output.

  The output control device 20 (20a, 20b, 20c, 20d,..., 20m, 20n) is mainly composed of a power transfer unit 21, an input gate unit 24, an impedance monitor unit 25, and the like, via a control bus CB. Connected to the controller 170. The output control device 20 is provided in a one-to-one relationship with the DSSC 10, and the DSSC 10 is connected to the power input terminal PI of the output control device 20 so that the generated power of the DSSC 10 can be input. Further, the output control device 20 receives a control command from the controller 170, and when the DSSC 10 receives sunlight to generate power, the output control device 20 transfers the generated power input from the DSSC 10 to the power line PL, and the DSSC 10 generates power. If not, each control such as electrically disconnecting between the DSSC 10 and the power line PL is performed. 2 is a circuit diagram showing a configuration example of the output control device 20, and will be described below with reference to FIG.

  As shown in FIG. 2, the output control device 20 includes a power transfer unit 21 including a transfer gate unit 22 and a state setting unit 23. The power transfer unit 21 has a function of outputting generated power input from the DSSC 10 to the power output terminal TO via an input gate unit 24 described later.

  The transfer gate unit 22 is, for example, a transfer gate configured by connecting an N-channel MOS transistor (hereinafter referred to as “NMOS”) and a P-channel MOS transistor (hereinafter referred to as “PMOS”) in parallel. That is, the transfer gate unit 22 is a bidirectional analog switch configured by connecting the drain of the NMOS 22a and the source of the PMOS 22b as an input node, and connecting the source of the NMOS 22a and the drain of the PMOS 22b as an output node. It is also called “gate” or “CMOS switch”.

  In the transfer gate unit 22, when an H level voltage is applied to the gate of the NMOS 22a and an L level voltage is applied to the gate of the PMOS 22b, both the MOSs 22a and 22b are turned on. Conduction (conduction state). On the other hand, when an L level voltage is applied to the gate of the NMOS 22a and an H level voltage is applied to the gate of the PMOS 22b, both the MOSs 22a and 22b are turned off. Blocked (blocked state). The transfer gate unit 22 may correspond to a “transfer gate” recited in the claims.

  The state setting unit 23 includes a flip-flop circuit composed of PMOS 23a, NMOS 23b, PMOS 23c, NMOS 23d, NMOS 23e, NMOS 23f and NMOS 23g, and an inverter circuit composed of PMOS 23h, NMOS 23i and NMOS 23k.

  This flip-flop circuit is configured in substantially the same manner as an SRAM storage cell in which one inverter circuit composed of PMOS 23a and NMOS 23b and the other inverter circuit composed of PMOS 23c and NMOS 23d are cross-connected. The SRAM is different from the SRAM storage cell in that each output node is connected to the gates of the NMOS 22a and PMOS 22b of the transfer gate unit 22 described above and a reset circuit using the NMOS 23g.

  That is, the output node of one inverter circuit (the connection node between the drain of the PMOS 23a whose source is connected to the positive power supply Vdd and the drain of the NMOS 23b whose source is connected to the negative power supply Vss) is connected to the input node (plus The gate is connected to the gate of the PMOS 23c whose source is connected to the power source Vdd and the gate of the NMOS 23d whose source is connected to the negative power source Vss), and is also connected to the gate of the NMOS 22a of the transfer gate unit 22.

  Similarly, the output node of the other inverter circuit (the connection node between the drain of the PMOS 23c whose source is connected to the positive power supply Vdd and the drain of the NMOS 23d whose source is connected to the negative power supply Vss) is connected to the input node ( The gate of the PMOS 23a having a source connected to the positive power source Vdd and the gate of the NMOS 23b having a source connected to the negative power source Vss) are also connected to the gate of the PMOS 22b of the transfer gate portion 22.

  The sources of the data loading NMOSs 23e and 23f are connected to the input / output node of the one inverter circuit and the input / output node of the other inverter circuit, respectively. The drain of the data loading NMOS 23e is connected to the input node of the inverter circuit composed of the PMOS 23h, NMOS 23i and NMOS 23k, and the drain of the data loading NMOS 23f is connected to the output node of the inverter circuit. The gates of the data loading NMOSs 23e and 23f are connected to a load terminal Ld to which a load signal is input from the outside.

  Further, the drain of the reset NMOS 23g having the source connected to the negative power source Vss is connected to the output node of the one inverter circuit and the input node of the other inverter circuit. The gate of the reset NMOS 23g is connected to a transfer gate reset terminal T_Rst to which a transfer gate reset signal is input from the outside.

  On the other hand, in the inverter circuit composed of the PMOS 23h, the NMOS 23i, and the NMOS 23k, the source of the PMOS 23h is connected to the positive power source Vdd, and the source of the NMOS 23i is connected to the negative power source Vss. Are connected in series. The NMOS 23k is a control gate that controls whether or not the inverter circuit can output, and the gate of the NMOS 23k is connected to a monitor enable terminal Mon_En to which an enable signal is input from the outside. The input node of the inverter circuit is a connection node between the gates of the MOSs 23h and 23i, and is connected to the drain of the NMOS 23e for data loading of the flip-flop circuit and the output node of the impedance monitor unit 25. The output node of the inverter circuit is a connection node between the drains of the PMOS 23h and the NMOS 23k and is connected to the drain of the NMOS 23f for data loading.

  Thus, when an H level voltage is applied to the transfer gate reset terminal T_Rst, the reset NMOS 23g is turned on, so that the gates of the NMOS 22a, PMOS 23c, and NMOS 23d become the voltage (L level) of the negative power source Vss. Therefore, only the PMOS 23c is turned on. As a result, the gates of the PMOS 22b, PMOS 23a, and NMOS 23b become the voltage (H level) of the positive power supply Vdd, so that only the NMOS 23b is turned on, and the flip-flop circuit is set to the reset state. On the other hand, when an H level voltage is applied to the load terminal Ld when the transfer gate reset terminal T_Rst is at the L level, both the NMOS 23e and the NMOS 23f are turned on, and the input nodes of the flip-flop circuit are The voltage level (H level or L level) input exclusively from the drains of the MOSs 23e and 23f is set. That is, when an H level voltage is input from the impedance monitor unit 25 to the state setting unit 23, the transfer gate unit 22 is set to a conductive state, and when an L level voltage is input, the transfer gate unit. 22 is set to the cut-off state.

  The input gate unit 24 is a gate circuit provided in front of the power transfer unit 21 and includes an NMOS 24a, a PMOS 24b, and an inverter 24c. This gate circuit is also a transfer gate. The input gate unit 24 connects the drain of the NMOS 24a and the source of the PMOS 24b as an input node, and connects the source of the NMOS 24a and the drain of the PMOS 24b as an output node. The gate of the NMOS 24a and the gate of the PMOS 24b are connected via an inverter 24c. The inverter 24c is interposed between the gate of the PMOS 24b and the gate of the NMOS 24a. As a result, in the transfer gate, when an L level voltage is applied to a control node that is a connection node between the input node of the inverter 24c and the drain of the PMOS 24b, the input gate portion 24 becomes conductive between the input and output (conduction state). ) When an H level voltage is applied to the control node, the input / output of the input gate unit 24 is blocked (blocked state). This control node is connected to the monitor enable terminal Mon_En. Therefore, when the L level voltage is applied to the monitor enable terminal Mon_En, the input gate portion 24 becomes conductive, and when the H level voltage is applied to the terminal Mon_En, the input gate portion 24 is cut off. It becomes a state.

  The impedance monitor unit 25 is a monitoring circuit provided in the preceding stage of the state setting unit 23, and includes a detection circuit including a PMOS 25a, an NMOS 25b, and an NMOS 25e, and an inverter circuit including a PMOS 25c, an NMOS 25d, and an NMOS 25f. . In this detection circuit, the source is connected to the positive power source Vdd, the gate and the drain are connected to draw a current from the positive power source Vdd, the gate is connected to the power input terminal PI, and the source is connected to the negative power source Vss. An NMOS 25e is connected in series between the connected NMOS 25b. The NMOS 25e is a control gate that controls whether or not the output of the detection circuit is possible, and the gate of the NMOS 25e is connected to the monitor enable terminal Mon_En.

  On the other hand, in the inverter circuit composed of the PMOS 25c, NMOS 25d and NMOS 25f, the source of the PMOS 25c is connected to the positive power source Vdd, and the source of the NMOS 25d is connected to the negative power source Vss. Are connected in series. The NMOS 25f is a control gate for controlling the output of the inverter circuit, and the gate of the NMOS 25f is connected to a monitor enable terminal Mon_En to which an enable signal is input from the outside. An input node of the inverter circuit is a connection node between the gates of the MOSs 25c and 25d, and a connection node between the PMOS 25a and the NMOS 25e of the detection circuit described above is connected thereto.

  As a result, when an H level voltage is applied to the monitor enable terminal Mon_En and a voltage is input to the power input terminal PI, that is, when the DSSC 10 is generating power, both the NMOS 25b and the NMOS 25e are turned on. Therefore, the output node of the detection circuit (input node of the inverter circuit), that is, each gate of the PMOS 25c and the NMOS 25d becomes the voltage (L level) of the negative power supply Vss. Therefore, since an inverted H level voltage is output from the output node of the inverter circuit, the H level voltage is input to the state setting unit 23 to set the transfer gate unit 22 to a conductive state.

  On the contrary, when no voltage is input to the power input terminal PI, that is, when the DSSC 10 is not generating power, the NMOS 25b is turned off, so that the output node of the detection circuit and the input node ( The gates of the PMOS 25c and NMOS 25d) become the voltage (H level) of the positive power supply Vdd. For this reason, since an inverted L level voltage is output from the output node of the inverter circuit, the L level voltage is input to the state setting unit 23 to set the transfer gate unit 22 to the cutoff state.

  In the output control device 20, the power generated by the DSSC 10 input to the power input terminal PI is received by the gate of the NMOS 25b. Therefore, when the gate voltage of the NMOS 25b exceeds the threshold voltage of the NMOS 25b, when the output impedance of the DSSC 10 is equal to or higher than the predetermined impedance, an L level voltage is output to the input node of the inverter circuit. That is, the case where the input voltage due to the generated power of the DSSC 10 exceeds the threshold voltage of the NMOS 25b is “the output impedance of the DSSC 10 is equal to or higher than a predetermined impedance (the output impedance of the DSSC 10 in the power generation state)”. However, in actuality, the output impedance of the DSSC 10 during power generation varies in value and varies widely. There are also variations in the output voltage during power generation. For this reason, the impedance monitor unit 26 (FIG. 6), which will be described later, solves these problems by adopting a configuration in which the threshold voltage threshold by the detection circuit is made variable.

  Further, when an H level voltage is applied to the monitor enable terminal Mon_En and the impedance monitor unit 25 performs such an operation, the control node of the input gate unit 24 also has an H level voltage from the monitor enable terminal Mon_En. Since the voltage is applied, the input gate unit 24 is cut off as described above. Thereby, in a state where the generated power of the DSSC 10 input from the power input terminal PI is monitored by the impedance monitor unit 25, the generated power of the DSSC 10 is output to the transfer gate unit 22 via the input gate unit 24. Without being exclusively input to the impedance monitor unit 25. Therefore, the output state of the DSSC 10 can be accurately monitored by the impedance monitor unit 25.

  On the other hand, when the generated power of the DSSC 10 input from the power input terminal PI is output to the transfer gate unit 22 via the input gate unit 24, a voltage of L level is applied to the monitor enable terminal Mon_En. Since the voltage is applied, the NMOS 25e and 25f of the impedance monitor unit 25 are turned off. For this reason, the PMOS 25a and the NMOS 25b are disconnected from each other, so that the current does not flow from the PMOS 25a to the NMOS 25b, and the impedance monitor unit 25 enters a sleep state. Therefore, all the generated power of the DSSC 10 can be output to the transfer gate unit 22 without loss.

  The control of each terminal (monitor enable terminal Mon_En, load terminal Ld, transfer gate reset terminal T_Rst) of the output control device 20 is performed by the controller 170 via the control bus CB. The controller 170 is typically a microcomputer, which corresponds to a control one-board microcomputer, a one-chip microcomputer, a general-purpose personal computer, or the like. A control example of the output control device 20 by the controller 170 will be described with reference to FIGS. 4 and 5 after describing the configuration of the power storage control device 150 and the like.

  Next, based on FIG. 1 and FIG. 3, the structure of the electrical storage control apparatus 150 etc. are demonstrated. 3 is a circuit diagram illustrating a configuration example of the power storage control device 150.

  As shown in FIG. 1, the power storage control device 150 is mainly configured by an input / output gate unit 151, a charge monitor unit 153, and the like, and each output control device 20 (20a, 20b, 20c, 20d, ..., 20m, 20n). The power storage control device 150 is also connected to the controller 170, receives the control command from the controller 170, and stores the generated power of each DSSC 10 sent from each output control device 20 through the power line PL in the charge unit 190. And control such as transferring the electric power (charge) stored in the charge unit 190 to the outside via the power output terminal PO. Note that FIG. 3 is a circuit diagram showing a configuration example of the power storage control device 150, which will be described below with reference to FIG.

  As shown in FIG. 3, the input / output gate unit 151 includes a front-stage transfer gate (151a, 151b), a rear-stage transfer gate (151c, 151d) and an inverter 151e in which the control of conduction and cutoff is reversed.

  Similar to the transfer gate of the transfer gate unit 22 described above, the pre-stage transfer gate is configured by connecting an NMOS 151a and a PMOS 151b in parallel. The transfer gate control terminal T_Cnt is connected to the gate of the NMOS 151a, and the output side of the inverter 151e is connected to the gate of the PMOS 151b. The storage control input terminal CI is connected to the input node of the front transfer gate, and the charge unit terminal Crg and the input node of the rear transfer gate are connected to the output node. The charge unit 190 is connected to the charge unit terminal Crg. The charge unit 190 may be an electric storage device that can store electric energy (charge), and is, for example, a large-capacity capacitor such as an electric double layer capacitor, a storage battery, or the like.

  Similarly, the post-stage transfer gate is configured by connecting the NMOS 151c and the PMOS 151d in parallel. The transfer gate control terminal T_Cnt is connected to the gate of the PMOS 151d, and the output side of the inverter 151e is connected to the gate of the NMOS 151c. Yes. The output node of the preceding transfer gate and the charge unit terminal Crg are connected to the input node of the latter transfer gate, and the power output terminal PO is connected to the output node. The input side of the inverter 151e is connected to the transfer gate control terminal T_Cnt.

  As a result, when an H level voltage is applied to the transfer gate control terminal T_Cnt, the input / output of the preceding transfer gate is turned on and the input / output of the subsequent transfer gate is cut off. On the other hand, when an L level voltage is applied to the transfer gate control terminal T_Cnt, the input / output of the front transfer gate is cut off and the input / output of the rear transfer gate is turned on. When the transfer gate control terminal T_Cnt is set to the H level by such exclusive operation of the two transfer gates, the charge unit 190 connected to the charge unit terminal Crg is the power input to the power storage control input terminal CI. When the transfer gate control terminal T_Cnt is set to the L level, the power (charge) stored in the charge unit 190 can be taken out (transferred) from the transfer gate control terminal T_Cnt.

  The charge monitor unit 153 is a circuit that monitors the storage state of the charge unit 190 connected to the charge unit terminal Crg, and is configured by a flip-flop circuit. Since the charge monitor unit 153 is substantially the same as the flip-flop circuit of the state setting unit 23 described above, the charge monitor unit 153 will be described here in comparison with the flip-flop circuit of the state setting unit 23, and will be described with reference to FIG. .

  As shown in FIGS. 2 and 3, a flip-flop circuit of the charge monitor unit 153 is configured for each of the MOS transistors 23a, 23b, 23c, 23d, 23e, and 23f that configure the flip-flop circuit of the state setting unit 23. The MOS transistors 153a, 153b, 153c, 153d, 153e, and 153f correspond to each other. However, as shown in FIG. 3, the sources of the NMOSs 153b, 153d, 153e, and 153f are all connected to the negative power source Vss, the gate of the NMOS 153e is connected to the charge unit terminal Crg, and the gate of the NMOS 153f is status. The point connected to the reset terminal S_Rst is different from the flip-flop circuit of the state setting unit 23 shown in FIG.

  The charge monitor unit 153 is set to an initial state (indicating that sufficient electric power (charge) is not stored in the charge unit 190) by inputting an H level voltage to the status reset terminal S_Rst, and is set to the L level. Is output from the status terminal Sts. When an L level voltage is input to the gate of the NMOS 153f, the NMOS 153f is turned on. Then, the drain of the NMOS 153f, the gates of the PMOS 153a and the NMOS 153b, and the status terminal Sts become the voltage (L level) of the negative power source Vss. As a result, the status terminal Sts becomes L level and the PMOS 153a is turned on, so that the gates of the PMOS 153c and NMOS 153d become the voltage (H level) of the positive power supply Vdd. For this reason, the NMOS 153d is turned on, the state of the flip-flop circuit is stabilized, and the status terminal Sts is maintained at the L level.

  On the other hand, when the charge unit 190 connected to the charge unit terminal Crg is charged and its voltage rises and a voltage corresponding to the H level is input to the gate of the NMOS 153e, the NMOS 153e is turned on. Then, the drain of the NMOS 153e, the gate of the PMOS 153c, and the gate of the NMOS 153d become the voltage (L level) of the negative power supply Vss, so that the PMOS 153c is turned on. As a result, the gates of the PMOS 153a and the NMOS 153b and further the status terminal Sts become the voltage (H level) of the positive power supply Vdd, so that the NMOS 153b is turned on and the state of the flip-flop circuit is stabilized. That is, the status terminal Sts informs that the charge unit 190 has been sufficiently charged by changing the state from the L level to the H level. The status terminal Sts returns to the L level by inputting the H level voltage to the status reset terminal S_Rst again. Here, the threshold voltage at which the NMOS 153e shifts from the off state to the on state is set as the determination threshold value of the output allowable voltage of the charge unit 190.

  The input / output gate unit 151 and the charge monitor unit 153 of the power storage control device 150 configured as described above are both configured by MOS transistors. Therefore, by forming the input / output gate unit 151 and the charge monitor unit 153 on the same semiconductor substrate, for example, it is possible to configure the input / output gate unit 151 and the charge monitor unit 153 more compactly and at a lower cost than the case where they are formed on different semiconductor substrates. In addition, when the core chip and peripheral circuit chip of the microcomputer, which is the controller 170 that controls the input / output gate unit 151 and the charge monitor unit 153, are formed on the same semiconductor substrate, the configuration is made more compact and low cost. be able to.

  The control of the controller 170 according to the present system configured as described above will be described with reference to FIGS. 4 and 5 are timing charts showing examples of control by the controller 170. FIG. 4 shows an example when the DSSC 10 changes from the shaded state to the sunshine state, and FIG. 5 shows the DSSC 10 from the sunshine state to the shaded state. It is an example when it changes to.

  As shown in FIG. 4, the controller 170 first displaces the transfer gate reset terminal T_Rst and the status reset terminal S_Rst from the L level to the H level, and then returns to the L level. As a result, the transfer gate unit 22 of the output control device 20 is set to the cut-off state, and the front-stage transfer gates (151a, 151b) of the input / output gate unit 151 of the power storage control device 150 are set to the conductive state. The transfer gates (151c, 151d) are set in the cutoff state. At the same time, the status terminal Sts of the charge monitor unit 153 of the power storage control device 150 is set to L level.

  Next, the controller 170 displaces the monitor enable terminal Mon_En of the output control device 20 from the L level to the H level. Then, since the input gate unit 24 of the output control device 20 transitions to the cut-off state, the generated power is not transferred to the power storage control device 150 by the transfer gate unit 22, and the rising edge timing (1 ) Gradually increases the voltage at the power input terminal PI. At this time, since the impedance monitor unit 25 is activated, monitoring by the impedance monitor unit 25 is performed.

  While the monitor enable terminal Mon_En is at the H level, the controller 170 displaces the load terminal Ld of the output control device 20 from the L level to the H level ((2) shown in FIG. 4). Thereby, voltage information of the power input terminal PI is set from the impedance monitor unit 25 to the flip-flop circuit of the state setting unit 23. In the example shown in FIG. 4, since each DSSC 10 is generating electric power ((3) shown in FIG. 4), the transfer gate unit 22 becomes conductive at the timing (2).

  Then, when the controller 170 shifts the monitor enable terminal Mon_En from the H level to the L level, the impedance monitor unit 25 is stopped and the input gate unit 24 is changed to the conductive state at the timing (3) of the falling edge. For this reason, the generated power input to the power input terminal PI is output to the output control output terminal TO of the output control device 20 via the input gate unit 24 and the transfer gate unit 22, so that the power input shown in FIG. The voltage at the terminal PI temporarily decreases at timing (3). On the other hand, since the generated power is transferred from the output control device 20 to the power storage control device 150 via the power supply line PL, the voltage of the charge unit 190 slightly increases ((3 ′) shown in FIG. 4).

  The controller 170 repeats such control every predetermined time (for example, every 1 minute, 3 minutes, 10 minutes, 30 minutes, etc.). As a result, the same control as described above is performed at a series of timings (4), (5), (6), and (6 ′) shown in FIG. When the charge unit 190 reaches the output allowable voltage determination threshold value Vth ((7) shown in FIG. 4), the status terminal Sts of the power storage control device 150 is displaced from the L level to the H level. 170 shifts the transfer gate control terminal T_Cnt from the H level to the L level.

  Then, the front transfer gate (151a, 151b) of the power storage control device 150 that has been in the conductive state transitions to the cutoff state, and the rear stage transfer gate (151c, 151d) that has been in the cutoff state transitions to the conductive state. . Therefore, the electric power (charge) stored in the charge unit 190 is output to the power output terminal PO through the rear transfer gates (151c, 151d). As a result, the voltage of the charge unit 190 starts to decrease (timing (8) shown in FIG. 4), and the voltage of the power output terminal PO rapidly increases ((8 ′) shown in FIG. 4). In addition, since the pre-stage transfer gates (151a and 151b) are cut off, the voltage at the power input terminal PI starts to rise ((8 ") shown in FIG. 4).

  Based on the voltage information of the power output terminal PO from the voltage sensor (not shown), the controller 170 triggers the voltage of the power output terminal PO to be almost zero volts and changes the transfer gate control terminal T_Cnt from the L level to the H level. Displace. That is, when it is confirmed that the electric power (charge) stored in the charge unit 190 is almost transferred, the input / output gate unit 151 is restored. That is, the front transfer gates (151a and 151b) are turned on, and the rear transfer gates (151c and 151d) are turned off. As a result, as shown in FIG. 4, when each DSSC 10 continues to generate power, the voltage of the charge unit 190 begins to gradually increase at timing (9), and the voltage of the power input terminal PI also increases ( Shown in FIG. 4 (9 ')).

  The controller 170 shifts the transfer gate reset terminal T_Rst from the L level to the H level, so that the transfer gate unit 22 of the output control device 20 transitions to the cutoff state. Therefore, since the transfer of the generated power to the power storage control device 150 is interrupted, the voltage at the charge unit terminal Crg temporarily stops increasing from the timing (10). However, by performing the same control as (4), (5), (6), (6 ') shown in FIG. 4 ((11), (12), (13) shown in FIG. 4), the monitor enable When the terminal Mon_En shifts from the H level to the L level, the charge unit 190 in which the transfer of the electric power (charge) is resumed starts again ((13 ′) shown in FIG. 4).

  As shown in FIG. 5, when the DSSC 10 changes from the sunshine state to the shaded state, the control by the controller 170 is different from the middle. That is, as shown in FIG. 5, when each DSSC 10 that has been receiving sunshine until now becomes shaded from the timing (20), when the charge unit 190 has not reached the judgment threshold Vth of the output allowable voltage, the status terminal Sts Does not transition from L level to H level. Therefore, the controller 170 does not displace the input / output gate unit 151 of the power storage control device 150 from the H level to the L level. Therefore, after the timing (20) (the arrow shown in FIG. 4), the charge unit 190 The voltage of is kept at a constant value or decreases slightly.

  In this case, after the timing (21), the controller 170 also performs a series of controls ((1), (2), (3), (3 ′), (4), (5), (6), (6 ′), etc.), but the power generation input from the DSSC 10 to the power input terminal PI takes zero volts or a value close thereto. Therefore, even if the voltage information of the power input terminal PI is set from the impedance monitor unit 25 of the output control device 20 to the flip-flop circuit of the state setting unit 23, the transfer gate unit 22 maintains the cutoff state, so the output control device 20 Is not transferred to the power storage control device 150.

  That is, when the DSSC 10 is not generating power, the controller 170 cuts off the electrical connection with the power storage control device 150 by the transfer gate unit 22 of the output control device 20. Therefore, the electric power (charge) stored in the charge unit 190 does not flow backward in the direction of the output control device 20 and is not consumed by the DSSC 10 acting as a resistor. Therefore, power loss can be suppressed.

  As described above, in the control by the controller 170, the impedance monitor unit 25 is not always operated, but is intermittently operated every predetermined time, for example, every 1 minute, 3 minutes, 10 minutes, or 30 minutes. The output impedance is detected. Thereby, compared with the case where the impedance monitor unit 25 always detects the output impedance, the operation time of the impedance monitor unit 25 is reduced, so that the power consumption by the impedance monitor unit 25 can be reduced. As shown in FIG. 2, since all of the impedance monitor unit 25 is composed of MOS transistors, when the NMOSs 25e and 25f are in an off state, a direct current is applied to the PMOSs 25a and 25c and the NMOSs 25b and 25d. Not flowing. Therefore, by intermittently operating the detection circuit in this way, the power consumption by the output control device 20 can be greatly reduced.

  4 and 5 have been described assuming that all DSSCs 10a to 10n are exposed to sunlight or shade. However, as shown in FIG. 1, the output control devices 20 (20a to 20n) are connected to the respective DSSCs 10a to 10n. Are individually connected corresponding to ˜10n. Therefore, in the case where the sunlight hits the DSSCs 10a to 10n individually, the control as shown in FIGS. 4 and 5 is performed individually for each output controller 20a to 20n corresponding to each DSSC 10a to 10n. To do.

  In the control example of the controller 170 described above, the impedance monitor unit 25 is intermittently operated, for example, every 1 minute, 3 minutes, 10 minutes, 30 minutes, etc., and the output impedance is detected every predetermined time. Although configured, the impedance monitor 25 may be operated almost continuously. Thereby, since the impedance monitor unit 25 can detect substantially continuous impedance, the accuracy of monitoring the DSSC 10 can be improved.

  Here, another configuration example of the output control device 20 will be described with reference to FIGS. First, the configuration example shown in FIG. 6 will be described. The output control device 120 according to this configuration example is different from the output control device 20 described above in that the impedance monitor unit 25 is changed to the impedance monitor unit 26. Since the other configuration is substantially the same as that of the output control device 20, the same components are denoted by the same reference numerals and description thereof is omitted.

  The output control device 120 illustrated in FIG. 6 includes an impedance monitor unit 26 instead of the impedance monitor unit 25 of the output control device 20. The impedance monitor unit 26 employs a configuration in which the NMOS 25b of the impedance monitor unit 25 is substantially changed to the flash element 26b2. Therefore, the PMOSs 26a and 26c and the NMOSs 26d, 26e, and 26f of the output control device 120 correspond to the PMOSs 25a and 25c, and the NMOSs 25d, 25e, and 25f of the output control device 20, respectively.

  The flash element 26b2 is usually a semiconductor device for constituting a flash memory. However, it functions not as a memory device but as an NMOS transistor in which the threshold voltage for on-off control between the drain and source is made variable depending on the amount of charge stored in the floating gate of the flash element 26b2. Note that the NMOSs 26b1 and 26b3 are used for control at the time of writing to the flash element 26b2, and a gate voltage is applied to the gate control terminals Cga and Cgb so as to maintain the ON state in normal times.

  The threshold setting for the flash element 26b2 is performed by the controller 170 in the following procedure. First, for the output control devices 120a to 120n (corresponding to the output control devices 20a to 20n shown in FIG. 1), an L level voltage is applied to the respective gate control terminals Cga and Cgb, and both NMOSs 26b1 sandwiching the flash element 26b2 are sandwiched. , 26b3 are set to the off state. Next, after setting the power input terminal PI to zero volts (for example, connecting the power input terminal PI to GND), for example, 20 volts is applied to the sub-board terminal Sub for 1 to 100 milliseconds. As a result, electrons stored in the floating gate are pulled out to the sub-substrate terminal Sub and the threshold voltage becomes a negative voltage, so that the flash element 26b2 is in a depletion state (this state is called an erase state in the flash memory).

  Next, individual threshold voltages are set for the DSSCs 10 (10a to 10n) connected to the power input terminals PI of the output control devices 20 (20a to 20n). This setting is performed for each DSSC 10a connected to each output control device 20a. After applying an L level voltage to the gate control terminals Cga and Cgb to turn off the NMOSs 26b1 and 26b3, -20 volts, for example, is applied to the sub-substrate terminal Sub for several microseconds. Thereafter, an H level voltage is applied to the gate control terminals Cga and Cgb to turn on the NMOSs 26b1 and 26b3, and then the current flowing through the control voltage terminal Vcn is measured. Since this current fluctuates in accordance with the input voltage at the power input terminal PI, the input current at the power input terminal PI is changed, the application of −20 volts and measurement are repeated until the desired current value is reached. Is measured, the setting of the threshold voltage is finished.

  The current flowing through the control voltage terminal Vcn is current information that is detected based on a voltage drop caused by a current sensor or a resistor and is output to the controller 170, and varies depending on the impedance of the DSSC 10 connected to the power input terminal PI. Therefore, the controller 170 obtains a predetermined impedance corresponding to each DSSC 10 (the output impedance of the DSSC 10 in the power generation state, specifically, different for each DSSC 10) from such current information, and corresponds to the predetermined impedance. When the current value is reached, the output control device 20 is controlled so that the setting of the threshold voltage is completed. Note that FIG. 6 does not show a current sensor or the like. If the voltage generated by the DSSC 10 at a predetermined impedance is known in advance, the known voltage may be applied to the power input terminal PI to set the threshold voltage of the flash element 26b2. This eliminates the need to measure the voltage flowing through the control voltage terminal Vcn such as a current sensor, thereby simplifying the configuration.

  Note that the voltage values of the power input terminal PI and the sub board terminal Sub may be changed as long as the relative voltage relationship between the power input terminal PI and the sub board terminal Sub is maintained as described above. For example, the sub board terminal Sub may be set to zero volts, and −20 V may be applied to the power input terminal PI. In the previous procedure, the controller 170 first sets the flash element 26b2 to the negative threshold voltage state (erased state) for all the output control devices 120a to 120n, and then sets the threshold voltage. For example, the flash element 26b2 may be set to a positive high threshold voltage state first, and then individually set to a specific threshold voltage.

  Since the impedance monitor unit 26 is configured to receive the power input terminal PI at the gate of the flash element 26b2 that can change the threshold voltage (detection threshold) in this way, the detection threshold of the output impedance of the DSSC 10, that is, the output impedance is equal to or higher than a predetermined impedance It is possible to change the threshold value for determining whether the value is less than or less than. Therefore, by setting the threshold voltage of the flash element 26b2 for each DSSC 10, the detection threshold can be set to the optimum value even if the output impedance of the DSSC 10 varies. Therefore, power loss can be further suppressed.

  Next, a configuration example shown in FIG. 7 will be described. The output control device 220 according to this configuration example is different from the output control device 20 described above in that the impedance monitor unit 25 is changed to the impedance monitor unit 27. Since the other configuration is substantially the same as that of the output control device 20, the same components are denoted by the same reference numerals and description thereof is omitted.

  The output control device 220 illustrated in FIG. 7 includes an impedance monitor unit 27 instead of the impedance monitor unit 25 of the output control device 20. The impedance monitor unit 27 employs a configuration in which the PMOS 25a of the impedance monitor unit 25 is substantially changed to a current mirror circuit composed of a PMOS 27a, an NMOS 27b, a PMOS 27c, and NMOSs 27d and 27h. Therefore, the NMOS 27d, PMOS 27e, NMOS 27f, 27h, and 27i of the output control device 220 have no difference in configuration and function corresponding to the NMOS 25b, PMOS 25c, NMOS 25d, 25e, and 25f of the output control device 20, respectively. The NMOSs 27d and 27h also contribute to the configuration of the current mirror circuit.

  The current mirror circuit constituting the impedance monitor unit 27 shown in FIG. 7 includes a PMOS 27a having a source connected to the positive power source Vdd and a gate-drain connected to draw current from the positive power source Vdd, and a gate having a comparison voltage terminal Vrf. The NMOS 27g is connected in series with the NMOS 27b whose source is connected to the negative power source Vss. The NMOS 27g is a control gate that controls whether or not the current mirror circuit can operate, and the gate of the NMOS 27g is connected to the monitor enable terminal Mon_En. The current flowing through the PMOS 27a, NMOS 27b, and 27g is copied as the current flowing through the PMOS 27c, NMOS 27d, and 27h. Therefore, the gate of the PMOS 27c is connected to the gate of the PMOS 27a. The comparison voltage terminal Vrf receives a threshold voltage (comparison reference voltage) that determines whether or not detection by the impedance monitor unit 27 is possible according to the input voltage of the power input terminal PI. This voltage is a voltage generated by the DSSC 10 at a predetermined impedance.

  As a result, the PMOS 27c and the NMOS 27h connected in series to the NMOS 27d that receives the power input terminal PI do not constitute a MOS diode having a gate-drain connection like the PMOS 25a. Therefore, since the current flowing through the PMOS 27c, NMOS 27h, and 27d can be minimized, the loss of the generated power by the DSSC 10 input from the power input terminal PI can be reduced as compared with the configuration of the impedance monitor unit 25 of the output control device 20. Further suppression can be achieved. Further, the threshold voltage can be easily changed by the comparison reference voltage input to the comparison voltage terminal Vrf, and it is possible to flexibly cope with individual impedances during power generation that differ depending on the DSSCs 10a to 10n.

  Next, a configuration example shown in FIG. 8 will be described. The output control device 320 according to this configuration example is different from the output control device 20 described above in that the impedance monitor unit 25 is changed to the impedance monitor unit 28. Since the other configuration is substantially the same as that of the output control device 20, the same components are denoted by the same reference numerals and description thereof is omitted.

  An output control device 320 illustrated in FIG. 8 includes an impedance monitor unit 28 instead of the impedance monitor unit 25 of the output control device 20. The impedance monitor unit 28 employs a configuration in which the power input terminal PI is received by the operational amplifier 28a. That is, in this configuration example, the power input terminal PI is connected to one (non-inverting input) of the differential input of the operational amplifier 28a, and the output control output terminal TO is connected to the other (inverting input). The output side of the operational amplifier 28a is connected to the gates of the NMOS 23h and NMOS 23i constituting the inverter circuit of the state setting unit 23. The operational amplifier 28a has a differential input stage composed of MOS transistors. The operational amplifier 28a is a positive and negative power source type, and is supplied with power from each of a positive power source + V and a negative power source -V.

  Note that + V is supplied through the NMOS 28b, so that the operational amplifier 28a operates when a voltage of H level is applied to the gate of the NMOS 28b. In the first embodiment, since the gate of the NMOS 28b is connected to the monitor enable terminal Mon_En, as in the impedance monitor unit 25 and the like described so far, when the monitor enable terminal Mon_En becomes H level, the impedance monitor unit 27 is activated. Operates and pauses at L level.

  By configuring the impedance monitor unit 28 with the operational amplifier 28a as described above, the power input terminal PI is received at the differential input stage of the operational amplifier 28a, so that the input impedance to the power input terminal PI can be increased. Therefore, compared to the configuration of the impedance monitor unit 25 of the output control device 20, it is possible to suppress the loss of generated power by the DSSC 10 that is input from the power input terminal PI.

  Next, the output control device 420 shown in FIG. 9 connects the load element 29 to the power input terminal PI of the output control device 20, and when there is input of generated power from the DSSC 10 to the power input terminal PI, this load element 29. Is supplied to the DSSC 10 as a load, and when there is no input of generated power, the impedance monitor 25 detects a voltage generated by passing a current from the load element 29 to the DSSC 10. Therefore, since the other configuration is substantially the same as that of the output control device 20, the same components are denoted by the same reference numerals and description thereof is omitted.

  As shown in FIG. 9, the load element 29 includes a flash element 29a and NMOSs 29b and 29c connected in series across the flash element 29a. The load element 29 can change the impedance as the load element 29 by setting the threshold voltage of the flash element 29a, and can be individually adjusted according to the DSSCs 10a to 10n.

  When setting the threshold voltage of the flash element 29a of the load element 29, an L level voltage is applied to the gate control terminal Cga so that the NMOS 29b whose drain is connected to the power input terminal PI is turned off. Thereby, the flash element 29a and the NMOS 29c are electrically disconnected from the power input terminal PI. Further, when setting the threshold voltage of the flash element 29a, a threshold corresponding voltage corresponding to the threshold voltage to be set is applied to the gate of the NMOS 29c from the gate control terminal Cgb, and L is applied to the control voltage terminal Vcn connected to the source. Set to level (zero volts). In this state, by applying 20 volts to the floating gate control terminal Cgf of the flash element 29a, the threshold voltage of the flash element 29a is increased and set to a predetermined threshold voltage. When the sub substrate terminal Sub is connected to the sub substrate of the flash element 29a, the sub substrate terminal Sub may be set to L level (zero volts) instead of the control voltage terminal Vcn.

  On the other hand, when the threshold voltage of the flash element 29a is lowered, the voltage applied to the floating gate control terminal Cgf and the voltage applied to the control voltage terminal Vcn or the sub substrate terminal Sub are set in reverse. That is, the floating gate control terminal Cgf is set to L level (zero volts), and 20 volts is applied to the control voltage terminal Vcn or the sub-substrate terminal Sub. Further, a threshold corresponding voltage corresponding to the threshold voltage to be lowered is applied to the gate of the NMOS 29c from the gate control terminal Cgb. As a result, the threshold voltage of the flash element 29a decreases, and is set to a predetermined threshold voltage.

  By configuring the load element 29 and its peripheral circuits in this way, when the load element 29 is used as a load of the DSSC 10 during power generation, the H level voltage is gated so that both the NMOS 29b and 29c are turned on. Applied to the control terminals Cga and Cgb. Further, the control voltage terminal Vcn of the NMOS 29c is connected to GND (ground or reference potential). Thereby, since a current flows from the power input terminal PI to the load element 29, the impedance generated by the impedance monitor unit 25 can be detected indirectly by detecting the voltage generated by the impedance monitor unit 25.

  On the other hand, even when a current is passed from the load element 29 to the DSSC 10 that is not generating power, an H level voltage is applied to the gate control terminals Cga and Cgb so that both the NMOSs 29b and 29c are turned on. The control voltage terminal Vcn of the NMOS 29c is connected to the positive power source Vdd. As a result, since the current flows from the load element 29 to the DSSC 10 that is not generating power, the impedance monitor 25 detects the voltage generated at the power input terminal PI, thereby reducing the impedance of the DSSC 10 that acts as a resistance during non-power generation. It can be detected directly.

  In addition, as a modification example of the above-described system, a configuration example provided with an external monitor terminal that can output a detection result by the impedance monitor unit to the outside will be described with reference to FIGS. As shown in FIG. 10, in this modified example, the output control device 20 ′ has an impedance monitor unit 25 ′ having an external monitor terminal Ex_Mon, and the output control devices 20′a, 20′b, 20′c, Monitor information output from 20′d,..., 20′m, 20′n can be collected by the controller 170 via the monitor bus MB.

  FIG. 11 shows an example of the configuration of the output control device 20 ′, which will now be described with reference to FIG. 11. The output control device 20 ′ according to this configuration example is different from the above-described output control device 20 in that the impedance monitor unit 25 is changed to the impedance monitor unit 25 ′, and other configurations are substantially the same as the output control device 20. Are identical. Therefore, the same components as those of the output control device 20 are denoted by the same reference numerals and description thereof is omitted.

  As shown in FIG. 11, the impedance monitor unit 25 'includes an NMOS 25g having a gate connected to the gate of the NMOS 25b among the PMOS 25a, NMOS 25b, and NMOS 25e constituting the detection circuit. The NMOS 25g has a gate connected to the power input terminal PI, a source connected to the negative power source Vss, and a drain connected to the external monitor terminal Ex_Mon as an open drain.

  As a result, an external device connected to the drain of the NMOS 25g via the external monitor terminal Ex_Mon can generate power generated by the DSSC 10 from the power input terminal PI by connecting a pull-up resistor or the like to the external monitor terminal Ex_Mon, for example. When input, the NMOS 25g as well as the NMOS 25b shift from the off state to the on state, so that the power generation state of the DSSC 10 can be detected from the outside.

  Further, since the NMOS 25g is connected to the external monitor terminal Ex_Mon through an open drain, as shown in FIG. 10, a plurality of output control devices 20′a, 20′b, 20′c, 20′d,. External monitor terminals Ex_Mon provided at 20′m and 20′n can be directly connected to each other to be combined into one monitor bus MB. Then, by measuring the impedance of the monitor bus MB, the impedance of the monitor bus MB decreases as the number of DSSCs 10 generating power increases. Therefore, the number of DSSCs 10 that are generating power can also be calculated from the impedance value of the monitor bus MB.

  In addition, by interposing a MOS switch or the like between the external monitor terminal Ex_Mon and the monitor bus MB so that the connection between the two can be controlled from the outside, the on / off state of the NMOS 25g of each output control device 20 is detected from the outside. Therefore, it is possible to identify the output control device 20 to which the DSSC 10 that is not generating power due to a failure or the like is connected. In addition, by the individual control of the output control device 20 by the controller 170, the output control device 20 to which the DSSC 10 not generating power due to a failure or the like is connected can be electrically disconnected from the power line PL. That is, as described with reference to FIG. 2, by setting the transfer gate reset terminal T_Rst to the H level, the transfer gate unit 22 of the output control device 20 shifts to the cut-off state, so that this state is maintained. Thus, the output control device 20 can be electrically disconnected from the power line PL.

  As described above, according to the system according to the first embodiment, the output control device 20 includes the transfer gate unit 22, the state setting unit 23, the input gate unit 24, and the impedance monitor unit 25, and is detected by the impedance monitor unit 25. When the output impedance of the DSSC 10 is equal to or higher than the predetermined impedance, the transfer gate unit 22 is set to the conductive state by the state setting unit 23, and when the output impedance is less than the predetermined impedance, the transfer gate unit 22 is cut off by the state setting unit 23. Set to state. This prevents current from flowing into the DSSC 10 having a low impedance and consuming electrical energy. Therefore, power loss can be suppressed.

[Second Embodiment]
Next, a second embodiment of the present system will be described with reference to FIG. 12 and FIG. As shown in FIG. 12, the second embodiment is characterized in that the output control device 620 includes a power transfer unit 61 and a state storage unit 63 associated therewith, and this point is the output control device 20 of the first embodiment. And different. Therefore, other than these, substantially the same components as those in the first embodiment are denoted by the same reference numerals and description thereof is omitted.

  As shown in FIG. 12, also in the second embodiment, the output control device 620 is provided with an output control device 620 corresponding to each of the plurality of DSSCs 10. Therefore, as shown in FIG. 12, for convenience, “a”, “b”... “N”, etc. are added to the end of each symbol of the DSSC 10 and the output control device 620, both of which will be described below. The configuration is the same as the DSSC 10 and the output control device 620. The state storage unit 63 of the output control device 620 is connected to the controller 170 via the control bus CB, receives a control command from the controller 170, and receives power from the DSSC 10 when receiving power from the DSSC 10. The input generated power is transferred to the power line PL, and when the DSSC 10 is not generating power, various controls such as electrically disconnecting between the DSSC 10 and the power line PL are performed.

  As illustrated in FIG. 13, the output control device 620 includes a power transfer unit 61, a state storage unit 63, an input gate unit 24, and an impedance monitor unit 25. Among these, the input gate unit 24 and the impedance monitor unit 25 are the same as those described in the first embodiment.

  The power transfer unit 61 is a transfer gate composed of only the NMOS 61a and is not a complementary type here. However, the power transfer unit 61 may be configured by connecting the NMOS 22a and the PMOS 22b in parallel like the transfer gate unit 22 described in the first embodiment. Good. However, when the complementary type is configured, it is necessary to provide a state storage unit 63 described below for each of the NMOS and the PMOS. The output side of the input gate unit 24 is connected to the drain of the NMOS 61a, and the output control output terminal TO is connected to the source of the NMOS 61a. The gate of the NMOS 61a is controlled by being connected to the state storage unit 63.

  The state storage unit 63 has a function of storing the detection result of the DSSC 10 output from the impedance monitor unit 25 and controlling the power transfer unit 61 based on the detection result. NMOS 63a and 63c, a flash element 63b connected in series between them, an NMOS 63g that connects the gate and drain and draws current from the positive power supply Vdd to the gate of the NMOS 63a, and NMOS 63d and 63f, The flash device 63e connected in series, the NMOS 63h connecting the gate and the drain to draw current from the positive power source Vdd to the gate of the NMOS 63d, the NMOS 63p having the drain connected to the power transfer unit 61, and an inverter circuit A PMOS 63k and NMOSs 63m and 63n are included.

  The PMOS 63k and NMOSs 63m and 63n that are connected in series to constitute the inverter circuit have the source of the PMOS 63k connected to the positive power source Vdd and the source of the NMOS 63n connected to the negative power source Vss. An NMOS 63m connected between the PMOS 63k and the NMOS 63n is a control gate that controls whether or not the inverter circuit can operate. The gate of the NMOS 63m is connected to a monitor enable terminal Mon_En to which an enable signal is input from the outside. The input node of the inverter circuit is a node where both gates of the PMOS 63k and the NMOS 63n are connected to which the gate of the NMOS 63a is connected. On the other hand, the output node of the inverter circuit is a node in which the drain of the PMOS 63k and the source of the NMOS 63m are connected to which the gate of the NMOS 63d is connected. The flash element 63b and the flash element 63e are configured such that their gates are connected to each other, and a gate control terminal Cg2 is connected to the flash element 63b and the flash element 63e so that they can be controlled from the outside. These flash elements 63b and 63e are electrically connected to each other's sub-boards, and a sub-board terminal Sub is connected to them in common. Further, the gates of the NMOS 63c and the NMOS 63f are also connected to each other, and the gate control terminal Cg1 is connected to the NMOS 63c and the NMOS 63f so that they can be controlled from the outside. The NMOS 63p whose drain is connected to the gate of the NMOS 61a of the power transfer unit 61 has its source connected to the negative power source Vss and its gate connected to the write control terminal Cw.

  By configuring the state storage unit 63 in this way, the controller 170 controls the output control device 620 according to the following procedure. First, a voltage of 20 volts is applied to the sub-substrate terminal Sub, and an L level voltage is applied to the gate control terminals Cg1 and Cg2 and the write control terminal Cw. As a result, electrons are emitted from the floating gates of the flash elements 63b and 63e to the sub-substrate terminal Sub, and the flash elements 63b and 63e are set to normally-on because the threshold voltage decreases.

  Next, the controller 170 controls the output control device 620 so as to apply an H level voltage to the monitor enable terminal Mon_En. As a result, the input gate unit 24 is cut off, and the impedance monitor unit 25 outputs a detection result to the state storage unit 63 when a voltage is input from the power input terminal PI.

  Subsequently, GND is applied to the sub-substrate terminal Sub, L level voltage is applied to the gate control terminal Cg1, 20 volts is applied to the gate control terminal Cg2, and H level voltage is applied to the write control terminal Cw. As a result, electrons are injected into the floating gate of the flash element connected to the NMOS 63a or NMOS 63d whose gate potential is at the H level, and the threshold voltage rises. That is, normally off is set.

  For example, when the voltage generated by the DSSC 10 is input to the power input terminal PI, the gate of the NMOS 63a becomes H level and the gate of the NMOS 63d becomes L level, so that the NMOS 63a is turned on and the NMOS 63d is turned off. Become. At this time, since the gate of the NMOS 63p is at the L level, the NMOS 63p is turned on, and electrons are injected from the negative power supply Vss side into the floating gate of the flash element 63b via the NMOS 63a in the on state. On the other hand, since the NMOS 63d is in the off state, electrons are not injected into the flash element 63e from the negative power source Vss side. As a result, the threshold voltage of the flash element 63b rises and is set to normally off. The flash element 63e maintains normally on.

  On the other hand, when no voltage is input from the DSSC 10 to the power input terminal PI, the gate of the NMOS 63a becomes L level and the gate of the NMOS 63d becomes H level, so that the NMOS 63a is turned off and the NMOS 63d is turned on. As a result, electrons are injected into the floating gate of the flash element 63e from the negative power source Vss side through the NMOS 63p and NMOS 63d in the ON state. In this case, electrons are not injected into the flash element 63a. As a result, the threshold voltage of the flash element 63e rises and is set to normally off. The flash element 63b maintains normally on.

  When the threshold voltages of the flash elements 63b and 63e are thus set according to the detection result by the impedance monitor unit 25, the monitor enable terminal Mon_En is returned to the L level and then the normal operation is performed. In normal operation, the sub-substrate terminal Sub and the gate control terminal Cg2 are applied with GND, the gate control terminal Cg1 with the H level, and the write control terminal Cw with the L level. As a result, the NMOSs 63c and 63f are both turned on, so that the normally-on voltage level of the flash elements 63b and 63e is applied to the gate of the NMOS 61a of the power transfer unit 61.

  For example, when the voltage generated by the power generated by the DSSC 10 is input to the power input terminal PI, since the flash element 63e is normally on, the voltage level of the positive power supply Vdd, that is, the H level is applied to the gate of the NMOS 61a. Thus, the power transfer unit 61 is controlled to be in a conductive state. On the other hand, when no voltage is input from the DSSC 10 to the power input terminal PI, since the flash element 63b is normally on, the voltage level of the negative power source Vss, that is, the L level is applied to the gate of the NMOS 61a to transfer power. The unit 61 is controlled to be in a shut-off state.

  Such a series of control of the state storage unit 63 by the controller 170 is performed once a day in accordance with, for example, a time zone with good sunshine conditions, two hours before the sunset time, or when the operation of the system ends. Done at a frequency. Thereby, for example, it is not necessary to perform detection by the impedance monitor unit or control the transfer gate unit based on the result every time the system is started.

  As described above, in the second embodiment, based on the impedance monitor unit 25 that detects the output impedance and the detection result output from the impedance monitor unit 25, the output impedance at the end of the previous operation of the DSSC 10 is greater than or equal to the predetermined impedance. A state storage unit 63 that determines whether or not the output impedance at the time of termination is less than a predetermined impedance, and flash elements 63b and 63e that store the determination result by the state storage unit 63. If the output impedance at the end is greater than or equal to a predetermined impedance based on the determination results read from the flash elements 63b and 63e, the input / output of the power transfer unit 61 is controlled to be in a conductive state, and the output impedance at the end is the predetermined impedance. If it is less, the input / output is controlled to be cut off.

  Thereby, for example, in the case of a power output device whose output impedance decreases as the output voltage decreases, such as DSSC, when the output impedance at the end of the previous operation of the DSSC 10 is less than a predetermined impedance, the state storage unit 63 As a result, the input and output of the power transfer unit 61 are controlled to be in a cut-off state, so that current is prevented from flowing into the DSSC 10 having a low impedance and consuming electrical energy. Further, at the time of restart, since the state storage unit 63 controls the power transfer unit 61 to be in a conductive state or a cut-off state based on the determination result stored in the flash elements 63b and 63e, the output impedance of the impedance monitor unit 25 is restored. There is no need to perform detection or the like, and the processing speed can be increased. Therefore, if the response is fast, the power loss can be further suppressed.

[Third Embodiment]
Next, a third embodiment of the present system will be described with reference to FIG. 14 and FIG. As shown in FIG. 14, the third embodiment is characterized in that the output control device 720 includes a power transfer unit 71 and a flash element control unit 73 associated therewith, and this point is the output control device of the first embodiment. Different from 20. Therefore, other than these, substantially the same components as those in the first embodiment are denoted by the same reference numerals and description thereof is omitted.

  As shown in FIG. 14, also in the third embodiment, the output control device 720 is provided with an output control device 720 corresponding to each of the plurality of DSSCs 10. For this reason, as shown in FIG. 14, “a”, “b”... “N”, etc. are added to the end of the reference numerals of the DSSC 10 and the output control device 720 for convenience. The configuration is the same as the DSSC 10 and the output control device 620. The flash element control unit 73 of the output control device 720 is connected to the controller 170 via the control bus CB, receives a control command from the controller 170, and when the DSSC 10 receives sunlight to generate power, the DSSC 10 Is transferred to the power line PL. When the DSSC 10 is not generating power, each control such as electrically disconnecting the DSSC 10 and the power line PL is performed.

  As shown in FIG. 15, the output control device 720 includes a power transfer unit 71 and a flash element control unit 73. In the power transfer unit 71, the flash element 71a is used as a transfer gate, and an NMOS 73a is connected in series with the preceding stage of the flash element 71a, and an NMOS 73b is connected in series with the subsequent stage. A floating gate control terminal Cgf is connected to the floating gate of the flash element 71a, and a sub substrate terminal Sub is connected to the sub substrate. The NMOSs 73a and 73b are not transfer gates but switching elements used when setting the threshold voltage of the flash element 71a. Therefore, these are included in the flash element control unit 73.

  The flash element control unit 73 includes NMOSs 73a and 73b, an NMOS 73c, and a resistor 73d. The gate of the NMOS 73a is connected to the gate control terminal Cga, and the gate of the NMOS 73b is connected to the gate control terminal Cgb. The NMOS 73c has a drain connected to the power input terminal PI and a source connected to the positive power source Vdd via the resistor 73d. The gate of the NMOS 73c is connected to the selection control terminal Csl.

  By configuring the flash element control unit 73 in this way, the controller 170 controls the output control device 720 according to the following procedure. First, an L level voltage is applied to the gate control terminals Cga and Cgb, and 20 volts is applied to the floating gate control terminal Cgf (initialization). As a result, electrons are injected into the floating gate of the flash element 71a, so that the threshold voltage is increased and normally off. That is, the enhancement mode is set.

  Next, an H level is applied to the gate control terminal Cga, an L level is applied to the gate control terminal Cgb, an H level is applied to the selection control terminal Csl, and a voltage of −20 volts is applied to the floating gate control terminal Cgf (mode setting). As a result, when the DSSC 10 is generating power, the DSSC 10 itself has a high impedance. When the NMOS 73c is turned on, the drain voltage of the NMOS 73a rises, and is stored in the floating gate of the flash element 71a. Electrons are extracted to the positive power supply Vdd side via the NMOSs 73a and 73c. Therefore, the flash element 71a is in a depletion mode and is set to ON, that is, normally ON without applying a voltage to the gate.

  On the other hand, when the DSSC 10 is not generating power, the DSSC 10 itself has a low impedance. Therefore, even when the NMOS 73c is turned on, the current of the positive power source Vdd flows into the low-impedance DSSC 10 side. Accordingly, the drain voltage of the NMOS 73a does not increase, and electrons stored in the floating gate of the flash element 71a are not drawn out to the positive power supply Vdd side, and the flash element 71a maintains the off state. That is, it remains normally off.

  When the threshold voltage of the flash element 71a is set by the flash element control unit 73 in this manner, the normal operation is started. In normal operation, the H level is applied to the gate control terminal Cga, the H level is applied to the gate control terminal Cgb, and the intermediate potential voltage of the H level and L level is applied to the floating gate control terminal Cgf. As a result, when the DSSC 10 is generating power, the flash element 71a is normally on, so that the power generated by the DSSC 10 is output from the NMOS 73b to the output control output terminal TO. On the other hand, when the DSSC 10 is not generating power, since the flash element 71a is normally off, there is no output from the NMOS 73b.

  Such a series of control of the flash element control unit 73 by the controller 170 is performed each time monitoring is performed, for example. The NMOS 73c and the resistor 73d are not necessary when the output voltage of the DSSC 10 has a margin.

  As described above, in the third embodiment, the flash element 71a functions as a transfer gate, and the flash element 71a is set to the depletion mode or the enhancement mode according to the output impedance, and the input / output of the flash element 71a is connected to the depletion mode. The flash element 71a is controlled so as to be in a conductive state when it is and in a cutoff state when it is in the enhancement mode. Thus, since the flash element 71a itself stores a state corresponding to the output impedance of the DSSC 10, it is not necessary to separately provide a storage circuit or the like. Therefore, the circuit configuration can be simplified.

  Further, by collecting the selection control terminals Csl of each output control device 720 connected to one bus, a plurality of output control devices 720 can be selected at a time, and the control by the controller 170 described above is completed at once. Can be made. As a result, the control processing by the controller 170 becomes very simple, and the processing speed can be increased.

[Fourth Embodiment]
Next, a fourth embodiment of the present system will be described with reference to FIGS. As shown in FIG. 16, in the fourth embodiment, the output control device 820 includes the cell state detection / holding unit 82 and the R / W control unit 85, but does not include the input gate unit, The output control device 820 is characterized in that each can be specified by a unique address assigned individually. Also, the configuration of the power storage control device 250 is characterized in that the configuration is simple, unlike the power storage control device 150 of the first to third embodiments. Therefore, other than these, substantially the same components as in the first embodiment and the like are denoted by the same reference numerals and description thereof is omitted.

  As shown in FIG. 16, also in the fourth embodiment, the output control device 820 is provided with an output control device 820 corresponding to each of the plurality of DSSCs 10. Therefore, as shown in FIG. 16, for convenience, “a”, “b”... “N”, etc. are added to the end of the reference numerals of the DSSC 10 and the output control device 820. The configuration is the same as the DSSC 10 and the output control device 820. The R / W control unit 85 of the output control device 820 is connected to the controller 170 via the system bus SB. When the output control device 820 receives a control command from the controller 170 and the DSSC 10 receives sunlight to generate power, the output control device 820 transfers the generated power input from the DSSC 10 to the power line PL, or the DSSC 10 does not generate power. In such a case, various controls such as electrically disconnecting between the DSSC 10 and the power line PL and checking (testing) the operation state of the DSSC 10 by arbitrarily controlling the power transfer unit 81 are performed.

  The system bus SB includes, for example, a data bus for exchanging control information such as a reset signal, a load signal, an enable signal and a status signal, and an address bus to which address data (address information) is sent. ing.

  As shown in FIG. 17, the output control device 820 includes a power transfer unit 81, a cell state detection / holding unit 82, and an R / W control unit 85, and is provided in the first embodiment and the second embodiment. The input gate section 24 (see FIGS. 1, 10, and 12) is not provided. Therefore, in the output control device 820, power loss can be reduced compared to the output control devices 20, 20 ', 120, 220, 320, 420, and 620 of the first and second embodiments. A circuit diagram of the R / W control unit 85 is shown in FIG. Therefore, the R / W control unit 85 will be described with reference to FIG.

<< Power Transfer Unit 81 >>
The power transfer unit 81 is a transfer gate including only the NMOS 81a, and is not a complementary type transfer gate connecting the PMOS and NMOS described in the first embodiment or the like in parallel. Therefore, the semiconductor chip area allocated for the power transfer unit 81 and the area occupied by the discrete components can be minimized. The drain of the NMOS 81a is connected to the power input terminal PI, and the source of the NMOS 81a is connected to the output control output terminal TO. The gate is connected to the cell state detection / holding unit 82, and the NMOS 81a is turned on / off. In other words, the NMOS 81a is controlled to be cut off when an L level voltage is input to its gate, and is controlled to be conductive when an H level voltage is input. The reason why the PMOS is not used as the transfer gate is that the output voltage of the DSSC 10 alone is around 0.5 V as described above, as can be seen from the general transfer characteristics (input / output voltage characteristics) of the CMOS switch. This is because a PMOS which is suitable for switching a high voltage instead of such a low voltage is not necessarily required.

<< Cell State Detection / Holding Unit 82 >>
The cell state detection / holding unit 82 includes a cell state detection unit 83 and a cell state holding unit 84. That is, the cell state detection / holding unit 82 holds (stores) the detection result indicating the power generation state of the DSSC 10 detected by the cell state detection unit 83 by the cell state holding unit 84 and controls the power transfer unit 81 based on the detection result. Or has a function of outputting to the outside via the R / W control unit 85.

<< Cell state detection unit 83 >>
The cell state detection unit 83 detects the output voltage of the DSSC 10, detects that the output impedance of the DSSC 10 is equal to or higher than the predetermined impedance when the predetermined threshold voltage is exceeded, and outputs the DSSC 10 when it is equal to or lower than the predetermined threshold voltage. Detect that the impedance is less than a predetermined impedance. That is, as the detection result indicating the power generation state of the DSSC 10, the pass / fail information of the DSSC 10 including two values of “good” and “no” is obtained. The pass / fail information of the DSSC 10 is also information indicating the on / off state of the power transfer unit 81 (transfer gate NMOS 81a), as will be described later. The predetermined threshold voltage is input from the outside or the like and set to an arbitrary voltage. The cell state detection unit 83 is mainly composed of a current mirror circuit and an inverter circuit.

  That is, the current mirror circuit includes PMOSs 83a and 83c whose both sources are connected to the positive power supply Vdd, NMOS 83b whose drain is connected to one of the PMOSs 83a (the drain thereof) and connected in series to the PMOS 83a, and the other PMOS 83c (the drain) of which has a drain and a gate connected to each other and an NMOS 83d which is also connected to the gate of the NMOS 83b. The gate of the PMOS 83a is connected to the power input terminal PI, and the gate of the NMOS 83c is connected to the comparison voltage terminal Vrf. Both sources of the NMOS 83b and the NMOS 83d are connected to each other and connected to the drain of the NMOS 83g that functions as a control gate. The comparison voltage terminal Vrf receives a threshold voltage (comparison reference voltage) that determines whether or not detection by the cell state detection unit 83 is possible according to the input voltage of the power input terminal PI. The threshold voltage may be input from an external power source provided outside the output control device 820, or may be supplied from a constant voltage source or the like provided inside the output control device 820. Further, the threshold voltage value may be variable from the outside.

  In contrast, the inverter circuit includes a PMOS 83e whose source is connected to the positive power supply Vdd and an NMOS 83f whose source is connected to the drain of the NMOS 83g. In the PMOS 83e and NMOS 83f, the gates are connected to form an input node, and the drains are connected to form an output node. The input node is connected to the output side of the current mirror circuit (the drains of the PMOS 83a and NMOS 83b), and the output node is connected to the input of the cell state holding unit 84 as the output of the cell state detection unit 83. The NMOS 83g functioning as a control gate is a switching element that is turned on when an enable signal input from the outside is at an H level and turned off when the enable signal is at an L level. Therefore, the gate of the NMOS 83g is connected to the monitor enable terminal Mon_En to which an enable signal is input from the outside, and the source is connected to the negative power source Vss.

  By configuring the cell state detection unit 83 in this way, the current flowing through the PMOS 83c and the NMOS 83d configuring the current mirror circuit can flow through the PMOS 83a and the NMOS 83b. As a result, when an enable signal (H level) is input from the outside to the NMOS 83g of the control gate, an input voltage exceeding the comparison reference voltage (predetermined threshold voltage) input to the comparison voltage terminal Vrf is applied to the power input terminal PI. When input, an L level voltage is output from the current mirror circuit, and when it is input to the inverter circuit (PMOS 83e, NMOS 83f), an H level voltage is output from the inverter circuit. That is, when an input voltage exceeding the comparison reference voltage (predetermined threshold voltage) is input to the power input terminal PI, the cell state detection unit 83 has an H level corresponding to “good” as a detection result indicating the power generation state of the DSSC 10. Is output from the cell state detection unit 83. On the contrary, when an input voltage equal to or lower than the comparison reference voltage is input to the power input terminal PI, the cell state detection unit 83 outputs an L level voltage corresponding to “No” as a detection result indicating the power generation state of the DSSC 10. Output.

<Cell state holding unit 84>
On the other hand, the cell state holding unit 84 mainly includes a flip-flop circuit and an inverter circuit. The cell state holding unit 84 controls on / off of the power transfer unit 81 based on the pass / fail information of the DSSC 10 output from the cell state detection unit 83 and the DSSC 10 It has a function to hold (store) pass / fail information and output it to the R / W control unit 85. The flip-flop circuit is configured in substantially the same manner as an SRAM memory cell in which one inverter circuit composed of PMOS 84a and NMOS 84b and the other inverter circuit composed of PMOS 84c and NMOS 84d are cross-connected. However, the input node of one of the inverter circuits (PMOS 84a, NMOS 84b) is connected to the inverter 84h, and is input to the R / W control unit 85 as the output of the cell state holding unit 84 and eventually the cell state detection / holding unit 82. Is also connected. The input node is also connected to the drain of the NMOS 84e of the two NMOSs 84e and 84g connected in series. The gate of the NMOS 84e is connected as an input of the cell state holding unit 84 to the output of the cell state detection unit 83 (the drains of the PMOS 83e and the NMOS 83f).

  The NMOS 84g is a control gate for data loading, the drain is connected to the source of the NMOS 84e, the source is connected to the negative power source Vss, and the gate is connected to the load terminal Ld to which a load signal is input from the outside. . On the other hand, the drain of the NMOS 84f is connected to the input node of the other inverter circuit (PMOS 84c, NMOS 84d). The NMOS 84f is a control gate for reset control, the source is connected to the negative power source Vss, and the gate is connected to the reset terminal Rst to which a reset signal is input from the outside.

  The inverter 84h is an inverting circuit interposed between the flip-flop circuit and the power transfer unit 81. As described above, the input node is an input node of one inverter circuit (PMOS 84a, NMOS 84b), in other words, the other one. It is connected to the output node of the inverter circuit (PMOS 84c, NMOS 84d). The input node of the inverter 84h is also connected to the input side (R / W node) of the R / W control unit 85. The output node of the inverter 84h is connected to the power transfer unit 81 (the gate of the NMOS 81a thereof) as the output of the cell state holding unit 84, and hence the cell state detection / holding unit 82.

  As a result, when the H level voltage (corresponding to the power generation state “good”) is input from the cell state detection unit 83 at the timing when the load signal (H level) is input from the load terminal Ld, the cell state The holding unit 84 outputs an L level voltage from the flip-flop circuit and outputs an H level voltage that turns on the NMOS 81 a to the power transfer unit 81. On the other hand, when an L level voltage (corresponding to the power generation state “No”) is input from the cell state detection unit 83 at the input timing of the load signal (H level), the cell state holding unit 84 An H level voltage is output from the flip-flop circuit, and an L level voltage that turns off the NMOS 81 a is output to the power transfer unit 81. In other words, the pass / fail information of the DSSC 10 is information indicating the on / off state of the NMOS 81a.

  When a reset signal (H level) is input from the reset terminal Rst, the NMOS 84f is turned on. Therefore, regardless of the input of the cell state detection unit 83, the cell state holding unit 84 outputs an H level voltage from the flip-flop circuit and outputs an L level voltage to the power transfer unit 81 to turn off the NMOS 81a. Set to. That is, the cell state holding unit 84 performs a reset operation for forcibly turning off the NMOS 81a serving as the transfer gate by the input of the reset signal (H level). Also, the pass / fail information of the DSSC 10 input from the cell state detection unit 83 is output by the cell state holding unit 84 with the H level and L level voltages inverted. That is, when the power generation state is “good”, the L level voltage is output from the cell state holding unit 84 to the R / W control unit 85, and when the power generation state is “No”, the H level voltage is output to the cell state holding unit. 84 to the R / W control unit 85. Thus, when the reset signal (H level) is input to the reset terminal Rst, the power transfer unit 81 is forcibly cut off. For example, the failed DSSC 10 is forcibly electrically disconnected from the power line PL. Can do. Therefore, power loss stored in the charge unit 190 can be suppressed by preventing power consumption by the failed DSSC 10.

<< R / W control unit 85 >>
As shown in FIG. 18, the R / W control unit 85 connected to the cell state detection / holding unit 82 includes an R / W gate unit 86 and an address decoding unit 87. The R / W control unit 85 performs a write operation and a read operation on the cell state detection / holding unit 82 when address data matching a preset unique address is input from the outside via the address input terminal Adr_In. It has a function to perform. Since this unique address is assigned to each of the plurality of output control devices 820, a specific output control device 820 can be selected. The write operation is an operation of setting the NMOS 81a, that is, the transfer gate to the on state without depending on the power generation state of the DSSC 10. That is, the write operation is to forcibly turn on the NMOS 81a as the transfer gate, and corresponds to the reverse operation of the reset operation. On the other hand, the read operation is an operation of reading the pass / fail information of the DSSC 10 set in the cell state holding unit 84 at that timing.

<< R / W gate part 86 >>
The R / W gate unit 86 includes an inverter circuit composed of a PMOS 86a and an NMOS 86b, two control gates NMOS 86c and 86d connected in series, a transfer gate connected to an output node of the inverter circuit, and the like. . The inverter circuit includes a PMOS 86a whose source is connected to the positive power source Vdd and an NMOS 86b whose source is connected to the negative power source Vss. In the PMOS 86a and NMOS 86b, the gates are connected to form an input node, and the drains are connected to form an output node. The input node is connected to the output side of the flip-flop circuit of the cell state holding unit 84 that constitutes the cell state detection / holding unit 82 as the R / W node of the R / W control unit 85. It should be noted that this R / W node is described as “R / W_Nod” in FIGS.

  The drain of the control gate NMOS 86c is connected to the input node of the inverter circuit, that is, the R / W node, and the gate is connected to the write enable terminal Wrt_En. The write enable terminal Wrt_En receives an enable signal for controlling each operation of writing and reading. That is, an H level voltage is input during a write operation, and an L level voltage is input during a read operation. The other control gate NMOS 86d has its drain connected to the source of the NMOS 86c and its source connected to the negative power supply Vss. The gate of the NMOS 86 d is connected to the output of the inverter 86 g that receives the output of the address decoding unit 87.

  The transfer gate is formed by connecting a PMOS 86e and an NMOS 86f in parallel, an input is connected to an output node of the inverter circuit (PMOS 86a, NMOS 86b), and an output is connected to the status terminal Sts_Out. The gate of the PMOS 86e is connected to the output of the address decoding unit 87, and the gate of the NMOS 86f is connected to the output of the inverter 87g. As a result, when an L level voltage is output from the address decode unit 87, the input and output of the transfer gate become conductive, and when an H level voltage is output from the address decode unit 87, the transfer gate is turned on. The output is cut off. That is, it controls whether or not the output from the inverter circuit (PMOS 86a, NMOS 86b) is output to the status terminal Sts_Out. From the status terminal Sts_Out, the pass / fail information of the DSSC 10 is output during the read operation.

<Address decoding unit 87>
The address decoding unit 87 includes a NAND gate 87a having an input corresponding to the number of bits of the unique address. The input of the NAND gate 87a is connected to the address bus of the system bus SB. In this embodiment, the address bus is composed of eight address lines, and eight lines corresponding to A0, / A0, A1, / A1, A2, / A2, A3, / A3 with respect to a 4-bit unique address. (/ An indicates that An is provided with an overbar). Therefore, the NAND gate 87a having four inputs is connected to the eight address lines of the address bus in correspondence with the unique address uniquely assigned to the output control device 820.

  For example, as shown in FIG. 18, eight address lines are arranged in the order of A3, / A3, A2, / A2, A1, / A1, A0, / A0 from the left side of the page, of which / A3 Four lines corresponding to / A2, A1, and A0 are connected to the input of the NAND gate 87a. Therefore, it can be seen that this NAND gate 87a is given "0011" in binary notation, that is, "3" in decimal notation as a unique address.

  By configuring the R / W control unit 85 in this way, when address data that matches the unique address set in the address decoding unit 87 is input from the address bus via the address input terminal Adr_In, the address decoding unit 87. To output an L level voltage. Therefore, since the control gate NMOS 86d that receives the output of the inverter 86g is turned on, when the control gate NMOS 86c whose gate is connected to the write enable terminal Wrt_En is turned on, the voltage of the R / W node is changed from the H level to the L level. Transition to level.

  That is, while the address data matching the unique address is being input to the address decoding unit 87, the write enable terminal Wrt_En becomes an H level voltage, so that the cell state holding unit 84 constituting the cell state detection / holding unit 82. Since the L level voltage is input to the input node of the inverter 84h, the H level voltage is output from the output node of the inverter 84h to the gate of the NMOS 81a of the power transfer unit 81, so that the transfer gate is in a conductive state. become. That is, the write operation by the R / W control unit 85 is performed, and the transfer gate (NMOS 81a) is forced to be turned on.

  When the L-level voltage is output from the address decoding unit 87 due to the coincidence of the unique addresses, the transfer gate composed of the PMOS 86e and the NMOS 86f becomes conductive, and the quality of the DSSC 10 input from the cell state detection / holding unit 82 is good or bad. Information is inverted by an inverter circuit composed of a PMOS 86a and an NMOS 86b and output to the status terminal Sts_Out.

  That is, while the address data matching the unique address is being input to the address decoding unit 87 via the address input terminal Adr_In, the L level voltage is input to the write enable terminal Wrt_En, thereby detecting / holding the cell state. The pass / fail information of the DSSC 10 held (stored) by the unit 82 is output to the status terminal Sts_Out via the inverter circuit (PMOS 86a, NMOS 86b) and the transfer gate (PMOS 86e, NMOS 86f). Thus, when the power generation state is “good”, an H level voltage is output from the status terminal Sts_Out, and when the power generation state is “not”, an L level voltage is output from the status terminal Sts_Out. That is, the read / write information of the DSSC 10 by the R / W control unit 85 is performed.

<< Power storage control device 250 >>
Next, the configuration of the power storage control device 250 will be described with reference to FIG. FIG. 19 is a circuit diagram illustrating a configuration example of the power storage control device 250. The power storage control device 250 is mainly configured by a charge control unit 251 and a discharge control unit 253, and is connected to each output control device 820 via the power line PL. The power storage control device 250 is also connected to the controller 170, receives the control command from the controller 170, and stores the generated power of each DSSC 10 sent from each output control device 820 via the power line PL in the charge unit 190. And control such as discharging the electric power (charge) stored in the charge unit 190 is performed. The power storage control device 250 directly connects (directly connects) both terminals without being interposed between the power storage control input terminal CI and the power output terminal PO. Thereby, compared with the power storage control device 150 described in the first embodiment or the like, it is possible to reduce power loss due to the input / output gate unit 151 being interposed.

  The charge control unit 251 is configured by an NMOS 251a. The NMOS 251a has a drain connected to the power line directly connecting the power storage control input terminal CI and the power output terminal PO, and a charge unit terminal Crg connected to the source. A charge unit 190 is connected to the charge unit terminal Crg. The gate of the NMOS 251a is connected to the charge enable terminal Crg_En. Thus, when an H level voltage is input to the charge enable terminal Crg_En, the NMOS 251a is turned on, and the power input from the power storage control input terminal CI is stored in the charge unit 190 connected to the charge unit terminal Crg. be able to.

  The discharge control unit 253 is configured by an NMOS 253a. The drain of the NMOS 253a is connected to the source of the NMOS 251a, and the negative power source Vss is connected to the source. A discharge terminal Discrg is connected to the gate of the NMOS 253a. While the L level voltage is input to the charge enable terminal Crg_En, the NMOS 251a is turned off, and the charge unit 190 is electrically disconnected from the power storage control input terminal CI and the power output terminal PO. When a level voltage is input, the electric energy (charge) stored in the charge unit 190 is discharged (discharged) to the negative power source Vss side via the NMOS 253a.

  As a result, it is possible to quickly release (discharge) the electric energy (charge) charged in the charge unit 190 to almost zero, so that, for example, such a discharge operation is performed during the maintenance. By performing the process according to H.253, the discharge characteristics of the charge unit 190 can be monitored. In addition, the charge characteristic of the charge unit 190 is monitored by turning on the NMOS 251a of the charge control unit 251 (the NMOS 253a of the discharge control unit 253 is off) with respect to the charge unit 190 whose electric energy is almost zero. can do.

  Note that a plurality of output control devices 820 (output control output terminals TO) are connected to a power line directly connecting the power storage control input terminal CI and the power output terminal PO. Therefore, in order to monitor the charging characteristics of the charge unit 190 without being affected by other than the output control device 820 that is the object of the maintenance work, as described above, an H level voltage is input to the reset terminal Rst and power is supplied. It is necessary to shift the transfer unit 81 to the cutoff state and electrically disconnect each DSSC 10 from the power line PL.

  Control of the controller 170 by the system according to the fourth embodiment configured as described above will be described with reference to FIGS. FIG. 20 is a timing chart showing an example of normal control by the controller 170, and is an example when the DSSC 10 changes from the sunshine state to the shaded state. FIGS. 21 and 22 are timing charts showing examples of control during maintenance by the controller 170. As an example of a test function, the power transfer unit 81 is forcibly set to a conductive state (FIG. 21). As an example of the test function, an example (FIG. 22) in the case of reading DSSC quality information from the cell state detection / holding unit 82 is shown. Note that in FIGS. 20 to 22, the power transfer unit 81 is shown in place of “TG_81”.

<Normal control>
First, control when the DSSC 10 is generating power, that is, control during normal time will be described with reference to FIG. As shown in FIG. 20, the controller 170 shifts the reset terminal Rst from the L level to the H level, and then returns it to the L level. As a result, the power transfer unit 81 of the output control device 820 is set to the cut-off state (in FIG. 20, since the power transfer unit 81 is in the cut-off state from the beginning, there is no displacement in that state). Next, the controller 170 displaces the monitor enable terminal Mon_En of the output control device 820 from the L level to the H level, and further displaces the load terminal Ld of the output control device 820 from the L level to the H level (shown in FIG. 20). (41)). As a result, the pass / fail information of the DSSC 10 is set from the cell state detection unit 83 of the cell state detection / holding unit 82 to the flip-flop circuit of the cell state holding unit 84. In the example shown in FIG. 20, since the DSSC 10 generates power at a voltage exceeding the threshold voltage Vth, the power transfer unit 81 becomes conductive at the timing (42) based on the information corresponding to the power generation state “good”. .

  Since the charge enable terminal Crg_En is set to the H level from the beginning, the charge unit 190 is electrically connected to the power line PL via the charge control unit 251. Therefore, the generated power input to the power input terminal PI is output to the output control output terminal TO of the output control device 820 via the power transfer unit 81 at the timing (42) when the power transfer unit 81 shifts to the conductive state. Therefore, while the voltage at the power input terminal PI shown in FIG. 20 temporarily decreases, the voltage at the charge unit terminal Crg and the power output terminal PO starts to rise at that timing ((43), ( 43 ')). The controller 170 repeats such control every predetermined time (for example, every 1 minute, 3 minutes, 10 minutes, 30 minutes, etc.). As a result, the controller 170 performs the same control as described above at each of the timings (44), (45), (46), and (46 ′) shown in FIG.

  On the other hand, when the sunshine state changes to the shaded state and the generated voltage of the DSSC 10 reaches the threshold voltage Vth or less, the controller 170 performs the following control to shut off the power transfer unit 81. That is, when the DSSC 10 is not generating power at a voltage exceeding the threshold voltage Vth at the timing when the load terminal Ld is displaced from the L level to the H level ((47) shown in FIG. 20), the cell of the cell state detection / holding unit 82 Information corresponding to the power generation state “NO” (DSSC 10 pass / fail information) is set from the state detection unit 83 to the flip-flop circuit of the cell state holding unit 84. For this reason, as shown in FIG. 20, the electric power transfer part 81 transfers to the interruption | blocking state ((48) shown in FIG. 20). Further, the voltages of the charge unit 190 and the power output terminal PO thereafter are gradually decreased or maintained ((49) and (49 ′) shown in FIG. 20).

<Control during maintenance>
Next, the control when the operation state of the DSSC 10 is confirmed, that is, the control at the time of maintenance will be described with reference to FIG. 21 and FIG. As described above, the control at the time of maintenance includes the continuity control of the power transfer unit 81 by the write operation and the read control of the pass / fail information of the DSSC 10 by the read operation. First, forcible conduction control of the power transfer unit 81 by a write operation will be described with reference to FIG.

  As shown in FIG. 21, the controller 170 shifts the reset terminal Rst from the L level to the H level, and then returns it to the L level. As a result, the power transfer unit 81 of the output control device 820 is set to the cut-off state as in the above-described normal control ((52) shown in FIG. 21). 21 corresponds to the voltage of the R / W node shown in FIGS. 17 and 18, and is a voltage input to the inverter 84h that controls on / off of the power transfer unit 81. Therefore, the voltage is displaced before the state transition in the power transfer unit 81 ((51) shown in FIG. 21). When the power transfer unit 81 shifts to the cut-off state, the voltage at the output control output terminal TO, which has been outputting the same voltage as the power input terminal PI so far, is cut off ((53) shown in FIG. 21). For this reason, the output control output terminal TO has a high impedance, so the voltage cannot be determined (indefinite interval shown in FIG. 21).

  Next, when the address data Adr_Dat that matches the unique address assigned to the output control device 820 is input from the address bus via the address input terminal Adr_In, the output of the address decoding unit 87 is shifted from H level to L level. ((54) shown in FIG. 21). Further, in response to the output displacement of the address decode unit 87, the transfer gates (PMOS 86e, NMOS 86f) of the R / W gate unit 86 shift from the cutoff state to the conductive state, so that the status terminal Sts_Out shifts from the H level to the L level ( Shown in FIG. 21 (55)). While the L level voltage is output from the address decoding unit 87, the controller 170 shifts the write enable terminal Wrt_En from the L level to the H level, so that the voltage at the R / W node is shifted from the H level to the L level. For this reason ((56) shown in FIG. 21), the power transfer unit 81 shifts to the conductive state ((57) shown in FIG. 21), and the voltage is output again to the output control output terminal TO (shown in FIG. 21). (58)). At substantially the same time, the status terminal Sts_Out is displaced from the L level to the H level ((58 ′) shown in FIG. 21).

  As described above, when the address data Adr_Dat matching the unique address is input to the output control device 820, the write enable terminal Wrt_En is displaced to the H level so that the generated voltage is equal to or lower than the threshold voltage Vth. The power generation voltage of the DSSC 10 input to the power input terminal PI can be output from the output control output terminal TO. At this time, by setting the charge control unit 251 of the power storage control device 250 to the off state, the generated voltage of the DSSC 10 can be monitored without being affected by the charge unit 190 (good or bad of the DSSC 10 shown in FIG. 23). (See Information readout control). In addition, by adopting a configuration in which the address data Adr_Dat input to each output control device 820 is sequentially changed corresponding to the unique address for each output control device 820 while the write enable terminal Wrt_En is displaced to the H level. It is possible to monitor the generated voltage of the DSSC 10 so that each output control device 820 is scanned.

  Subsequently, read / write control of the DSSC 10 by the read operation will be described with reference to FIG. As shown in FIGS. 22A and 22B, the controller 170 sets all of the reset terminal Rst, the charge enable terminal Crg_En, and the write enable terminal Wrt_En to the L level. Although not shown in FIG. 22, the monitor enable terminal Mon_En and the load terminal Ld are shifted from the L level to the H level in accordance with the timing at which the state of the DSSC 10 is to be acquired, as in the normal control. Revert. Thereby, the voltage of the R / W node is determined, and the state of the power transfer unit 81 is determined. That is, when the power generation voltage of the DSSC 10 exceeds the threshold voltage Vth, the voltage at the R / W node becomes L level, and the power transfer unit 81 becomes conductive (FIG. 22 (A)). On the contrary, when the generated voltage of the DSSC 10 is equal to or lower than the threshold voltage Vth, the voltage of the R / W node becomes H level, and the power transfer unit 81 is cut off (FIG. 22B).

  For this reason, when the address data Adr_Dat matching the unique address assigned to the output control device 820 is input from the address bus, the output of the address decoding unit 87 is shifted from the H level to the L level (FIG. 22A). (61) shown in FIG. 22B (71) shown in FIG. 22B), the transfer gates (PMOS 86e, NMOS 86f) of the R / W gate unit 86 shift from the cutoff state to the conductive state. Therefore, when the power generation voltage of the DSSC 10 exceeds the threshold voltage Vth, the status terminal Sts_Out shifts from the H level to the L level ((62) shown in FIG. 22). The terminal Sts_Out remains at the L level ((72) shown in FIG. 22). The output of the address decoding unit 87 returns to the H level when the address data Adr_Dat does not match ((63) shown in FIG. 22 (A), (73) shown in FIG. 22 (B)). Sts_Out also returns to the original voltage level ((64) shown in FIG. 22 (A), (74) shown in FIG. 22 (B)).

  When the address data Adr_Dat matching the unique address is input to the output control device 820 as described above, the pass / fail information of the DSSC 10 is transferred to the cell state detection / holding unit by displacing the write enable terminal Wrt_En to the L level. 82 can be read out from the cell state holding unit 84 via the status terminal Sts_Out. Further, since the charge enable terminal Crg_En is set at the L level, the charge control unit 251 of the power storage control device 250 is set to the off state and is electrically disconnected from the power line PL from the charge unit 190. Therefore, the power generation state of the DSSC 10 that is not affected by the charge unit 190 can be read as pass / fail information. In addition, by adopting a configuration in which the address data Adr_Dat input to each output control device 820 is sequentially changed corresponding to the unique address for each output control device 820 while the write enable terminal Wrt_En is displaced to the H level. It is possible to read the pass / fail information of the DSSC 10 so that each output control device 820 is scanned.

  As described above, according to the system of the fourth embodiment, the output control apparatus 820 includes the cell state detection unit 83, the cell state holding unit 84, and the R / W control unit 85, and includes the cell state holding unit 84 and the R The / W control unit 85 sets the power transfer unit 81 to a conductive state or a cut-off state according to control information input from the outside. As a result, when the output impedance detected by the cell state detection unit 83 is equal to or higher than the predetermined impedance, the cell state holding unit 84 and the R / W control unit 85 set the power transfer unit 81 to the conductive state, which is less than the predetermined impedance. In this case, the power transfer unit 81 is set to the cutoff state by the cell state holding unit 84 and the R / W control unit 85. Regardless of the output impedance detected by the cell state detection unit 83, the power transfer unit 81 is forcibly set to a conduction state or a cutoff state according to control information input from the outside. Therefore, for example, since the failed DSSC 10 can be forcibly electrically disconnected from the power line PL, power loss can be further suppressed by preventing power consumption by the failed DSSC 10.

  Further, according to the present system according to the fourth embodiment, the state information of the conduction or cutoff of the power transfer unit 81 set by the cell state holding unit 84 and the R / W control unit 85 is externally applied according to the control information input from the outside. Is output. Therefore, it is possible to easily confirm the power generation state of the DSSC 10 by reading out such conduction / cutoff state information of the power transfer unit 81 from the outside.

  Furthermore, according to the present system according to the fourth embodiment, the output control device 820 further includes an address decoding unit 87 that determines whether or not the address data Adr_Dat specifying the output control device 820 is input, and maintains the cell state. When the address decoding unit 87 determines that the address data Adr_Dat specifying the output control device 820 is input, the unit 84 and the R / W control unit 85 perform a predetermined operation according to the control information. Thereby, for example, when the predetermined operation according to the control information is to set the power transfer unit 81 to the conductive state or the cut-off state, this operation is performed by the address data Adr_Dat specifying the output control device 820. Only done when entered. Further, when the predetermined operation is to output the information on the state of conduction or interruption of the power transfer unit 81 stored in the cell state holding unit 84 to the outside, the operation is an address for specifying the output control device 820. This is performed only when data Adr_Dat is input. Therefore, when there are a plurality of output control devices 820, a specific output control device 820 can be designated by the address data Adr_Dat and these predetermined operations can be performed. Can be identified. Further, by providing a plurality of output control devices 820 specified by the address data Adr_Dat, the sum of the respective output voltages can be obtained from the power line PL for a plurality of DSSCs 10 connected thereto.

  In the fourth embodiment, a configuration is adopted in which a unique address that is uniquely set for each of the plurality of output control devices 820 is adopted, and a specific address is specified by address data input via an address bus that constitutes the system bus SB. Although the above-described control is performed by designating the output control device 820, the output control device 820 may be configured without giving the output control device 820 the concept of such an address. In this case, each control described above is executed for all the output control devices 820 at the same time. However, during maintenance, the output control device 820 and the DSSC 10 that are not to be tested are appropriately electrically connected to the power line PL. By separating from the above, control during maintenance similar to the above can be performed.

  Next, an example in which an MIM capacitor (capacitor) as the charge unit 190 is configured with an MIM (Metal-Insulator-Metal) structure will be described with reference to FIG. When the systems according to the first to fourth embodiments described above are formed on a semiconductor substrate, the charge unit 190 is formed in the substrate by the MIM structure. As a result, the charge unit 190 is manufactured as an MIM capacitor in a semiconductor manufacturing process for forming a semiconductor circuit such as NMOS or PMOS constituting the system, so that the charge unit 190 is configured with a separate super capacitor, for example. The resistance loss is suppressed compared to the case where it is done. Therefore, the power storage efficiency of the charge unit 190 can be improved. Moreover, since it can be accommodated in the same semiconductor substrate, it contributes to a compact system LSI.

  In addition, the code | symbol shown in FIG. 23 is as follows. 1000 denotes a semiconductor device constituting this system, 1010 denotes a silicon substrate (P-type region), 1020 denotes an element isolation region, 1030 denotes a diffusion region in the source region (N-type region), and 1040 denotes a diffusion layer in the drain region. (N-type region) 1050 indicates a gate electrode, and 1060 indicates a gate insulating film. As a result, an NMOS is formed.

  Reference numerals 1070, 1110, and 1210 denote interlayer insulating films, and 1080 and 1090 denote contacts (W plugs). Reference numerals 1120, 1130, 1220, and 1230 denote wiring layers, 1150 and 1260 denote via holes, 1240 denotes a capacitor electrode, and 1310 and 1320 denote copper wiring or aluminum wiring. The MIM capacitor (charge unit 190) includes a part of the wiring layer 1230 and the capacitor electrode 1240. Note that a dielectric having a high dielectric constant may be disposed instead of the interlayer insulating film 1210 located between them. Thereby, the electrostatic capacitance of the charge unit 190 is increased.

  Further, for example, a transfer gate such as NMOS 81a constituting the power transfer unit 81 described in the fourth embodiment may be manufactured using a double well process in a semiconductor process. That is, an N well region 2020 is formed in the silicon substrate 1010 so as to surround the P type region of the silicon substrate 1010 constituting the NMOS structure of the semiconductor device 1000 described with reference to FIG. Thereby, the P well region 2010 located in the N well region 2020 is separated from the silicon substrate 1010 by the N well region 2020. Therefore, even if the silicon substrate 1010 is connected to the ground or the like, A voltage different from the substrate potential can be applied to 2010.

  For this reason, by applying a forward bias to the P well region 2010, the potential of the P well region 2010 can be made higher than the voltage of the source region 1030. Therefore, the threshold voltage of the NMOS formed in the silicon substrate 1010 is lowered. Can be made. That is, an increase in the NMOS threshold voltage due to the substrate effect is suppressed. As a result, a transfer gate (NMOS) that suppresses power loss as much as possible can be configured even with a low voltage of about 0.5 V, such as the output voltage of the DSSC 10 alone. In the present embodiment, the bias voltage applied to the P well region 2010 is set to about 0.1 V, for example. Further, the P well region 2010 surrounded by the N well region 2020 may not be electrically connected to the silicon substrate 1010. Therefore, for example, a floating structure that electrically floats the P well region 2010 may be employed.

  Furthermore, when the system according to the first to fourth embodiments described above is formed on a semiconductor substrate, for example, as shown in FIG. 25, the output control devices 20, 20a, 120, 220, 320, 420, 620. , 720, 820 (collectively referred to as “output control device x20” in the present paragraph and the next paragraph), and storage control devices 150, 250 (referred to as “storage control device x50” in the present paragraph and the next paragraph). The controller 170, the charge unit 190, and the like may be arranged. FIG. 25A is an explanatory diagram showing a layout example when the present system is formed as a chip as a system LSI, and FIG. 25B shows a layout example of the output control device x20. An enlarged view in the alternate long and short dash line α and an enlarged view showing an example of the comparison layout are shown in FIG. 25C.

  As shown in FIG. 25 (A), when the present system is an LSI, it is necessary to reduce the power loss input from the DSSC 10 as much as possible. It is desirable that the output control device x20 provided in a one-to-one relationship is disposed in the vicinity of the pad Pad. Therefore, for example, when the circuit area block constituting the output control device x20 has a strip shape, the length Bh in the short direction of the circuit area block is set to the arrangement pitch of the pads Pad as shown in FIG. Set to be equal to Pp (BL = Pp). As a result, the wiring Wa that connects the circuit area block and the pad Pad can be formed in a straight line. Therefore, a comparative example in which the wiring Wb as shown in FIG. 25C is formed in a bowl shape (Ch> Bh, The wiring length of the wiring Wa is shorter than that of Pp), and power loss due to wiring resistance can be suppressed. The pads Pad arranged around the semiconductor chip Die are provided for wire bonding the semiconductor chip Die die-bonded to the lead frame to each lead of the lead frame.

  In addition, “external” such as “output to the outside” and “input from the outside” in the description of each embodiment described above refers to the control bus CB, the monitor bus MB, or the system bus SB applied to each embodiment. Note that it means. In addition, the “minus power supply Vss” in the description in each of the above-described embodiments is generally connected to the ground or the ground potential GND.

  In each of the above-described embodiments, the DSSC (dye-sensitized solar cell) 10 has been described as an example of the power output device. However, the present invention is not limited to this, and any device capable of outputting power can be used. It may be a silicon-based solar cell or an organic semiconductor solar cell based on crystalline or polycrystalline silicon, a solar cell by other methods, or the like. In addition, it is not limited to a power generation device caused by excitation energy by light, for example, a power generation device caused by a living body that generates power by converting biochemical energy of an enzyme or a microorganism into electric energy. Also good. That is, if the generated voltage is higher than the voltage drop due to the NMOS type transfer gate and lower than the voltage drop Vf (about 0.6 V) due to the silicon diode, for example, a piezoelectric element due to the piezoelectric effect, a Peltier element, etc. It may be a power generation device such as a thermoelectric element by the Seebeck effect.

  In each of the above-described embodiments, the flash element is exemplified as having a floating gate (charge storage layer). However, the flash element is not limited to this as long as it is a layer capable of storing charges (charge storage layer). For example, it may have silicon nitride.

  Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications or alterations of the specific examples illustrated above. In addition, the technical elements described in the present specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology illustrated in this specification or the drawings achieves a plurality of objects at the same time, and has technical usefulness by achieving one of the objects. Note that the description in parentheses in the [Explanation of Symbols] clearly shows the correspondence between the terms used in the above-described embodiments and the terms described in the claims.

10 ... DSSC (Power Output Device)
20, 20 ′, 120, 220, 320, 420, 620, 720, 820... Output control device (output control circuit)
21 ... Power transfer unit 22 ... Transfer gate unit (transfer gate)
23: State setting section (control circuit, setting circuit)
25, 25 ', 27, 28 ... Impedance monitor section (control circuit, detection circuit)
26: Impedance monitor (control circuit, detection circuit, threshold variable circuit)
29 ... Load element (detection circuit, threshold variable circuit)
61 ... Power transfer part (transfer gate)
63... State storage unit (determination circuit)
63b, 63e... Flash element (memory circuit)
71 ... Power transfer unit (transfer gate)
71a: Flash element (MOS transistor)
73 ... Flash element control unit (setting control circuit, operation control circuit)
73a, 73b ... NMOS (initialization circuit, operation mode setting circuit)
73c ... NMOS (operation mode setting circuit)
73d ... resistance (operation mode setting circuit)
81 ... Electric power transfer unit (transfer gate)
82 ... Cell state detection / holding unit (detection circuit, setting circuit)
83 ... Cell state detection unit (detection circuit)
84: Cell state holding unit (setting circuit)
85 ... R / W control unit (setting circuit, address determination circuit)
86 ... R / W gate (setting circuit)
87: Address decoding unit (address determination circuit)
150, 250 ... Power storage control device (power storage control circuit)
151 ... Input / output gate (transfer gate)
153 ... Charge monitor (voltage information output circuit)
170 ... Controller (setting circuit, setting control circuit, operation control circuit, charge / discharge control circuit)
190 ... Charge unit (electric storage device)
251 ... Charge control unit (switch circuit)
253 ... Discharge control unit (discharge circuit)
1000, 2000: Semiconductor device Adr_Dat: Address data (address information)
TO: Output control output terminal (output side)
PI: Power input terminal (input side)

Claims (15)

An output control circuit capable of outputting to the output side the power output by the power output device connected to the input side,
A transfer gate interposed between the input side and the output side;
When the output impedance of the power output device is equal to or higher than a predetermined impedance, the input / output of the transfer gate is controlled to be in a conductive state, and when the output impedance is less than the predetermined impedance, the input / output is disconnected. A control circuit for controlling
An output control circuit comprising:   The output control circuit according to claim 1, wherein the control circuit includes a detection circuit that detects the output impedance, and a setting circuit that sets the transfer gate to a conductive state or a cutoff state.   The output control circuit according to claim 2, wherein the detection circuit includes a threshold variable circuit that varies a detection threshold of the output impedance.   The output control circuit according to claim 2, wherein the detection circuit detects the output impedance every predetermined time.   5. The output control circuit according to claim 2, wherein the detection circuit outputs the detection result to an outside other than the setting circuit. 6. The control circuit detects whether the output impedance at the end of the previous operation of the power output device is equal to or higher than a predetermined impedance based on a detection circuit that detects the output impedance and a detection result output from the detection circuit. Or a determination circuit that determines whether or not the output impedance at the time of termination is less than the predetermined impedance, and a storage circuit that stores a determination result by the determination circuit,
Based on the determination result read from the storage circuit, when the output impedance at the end is equal to or higher than the predetermined impedance, the input / output of the transfer gate is controlled to be in a conductive state, and the output impedance at the end is the predetermined impedance. 2. The output control circuit according to claim 1, wherein the output control circuit controls the input / output state to be in a cut-off state when the input / output value is less than the input value. The transfer gate is a MOS transistor having a charge storage layer and operating in a depletion mode or an enhancement mode depending on the amount of charge stored in the charge storage layer.
The control circuit sets the operation mode of the MOS transistor to a depletion mode when the output impedance of the power output device is equal to or higher than a predetermined impedance, and the MOS transistor when the output impedance is lower than the predetermined impedance. A setting control circuit for setting the operation mode to enhancement mode;
An operation control circuit for controlling between the input and output of the MOS transistor when the MOS transistor is in the depletion mode, and for controlling the input and output between the MOS transistors to be cut off when the MOS transistor is in the enhancement mode;
The output control circuit according to claim 1, further comprising: The setting control circuit includes:
An initialization circuit that injects electrons into the charge storage layer and stores the charge in the charge storage layer to place the MOS transistor in an enhancement mode at the time of initialization;
At the time of mode setting, if the output impedance of the power output device is equal to or higher than a predetermined impedance, the electrons are extracted from the charge storage layer and transferred to the outside to change the operation mode of the MOS transistor to the depletion mode. An operation mode setting circuit for maintaining the operation mode of the MOS transistor in an enhancement mode when the output impedance is less than the predetermined impedance;
The output control circuit according to claim 7, further comprising: The control circuit includes a detection circuit that detects the output impedance, and a setting circuit that sets the transfer gate to a conductive state or a cutoff state.
3. The output control circuit according to claim 2, wherein the setting circuit sets the transfer gate to the conductive state or the cut-off state according to control information input from the outside. The control circuit includes a detection circuit that detects the output impedance, and a setting circuit that sets the transfer gate to a conductive state or a cutoff state.
The output control circuit according to claim 2, wherein the setting circuit stores the conduction state or the cutoff state and outputs the stored state to the outside according to control information input from the outside. The control circuit further includes an address determination circuit that determines whether address information specifying the control circuit is input,
11. The setting circuit according to claim 9, wherein the setting circuit performs a predetermined operation according to the control information when the address determination circuit determines that address information specifying the control circuit is input. Output control circuit. A storage control circuit that controls charging / discharging of a storage device that is connected to the output side of the output control circuit according to any one of claims 1 to 11 and stores electrical energy output from the output control circuit,
A voltage information output circuit for detecting voltage of the power storage device and outputting voltage information;
In the first state, the power storage device is conducted to the output control circuit to charge the power storage device, and in the second state, the power storage device is disconnected from the output control circuit and conducted to an external output to conduct the power storage device. A transfer gate for discharging and transmitting the electrical energy stored in the external output to the external output;
A charge / discharge control circuit for controlling charge / discharge of the power storage device by the transfer gate based on the voltage information output from the voltage information output circuit,
The charge / discharge control circuit controls the transfer gate to the first state when a charge voltage of the power storage device is less than a preset output allowable voltage, and the charge voltage of the power storage device is set to the output allowable voltage. In the above-described case, the storage control circuit controls the transfer gate to the second state.   The power storage control circuit according to claim 12, wherein at least the voltage information output circuit and the transfer gate are formed on the same semiconductor substrate. A storage control circuit that controls charging / discharging of a storage device that is connected to the output side of the output control circuit according to any one of claims 1 to 11 and stores electrical energy output from the output control circuit,
A switch circuit that controls electrical conduction and interruption between the output side of the output control circuit and the power storage device;
A discharge circuit that releases the electrical energy stored in the power storage device to the low potential side, and
The power storage control circuit, wherein the switch circuit and the discharge circuit are controlled according to control information input from outside.   The power storage control according to any one of claims 12 to 14, wherein the power storage device is formed on a semiconductor substrate in which the power storage control circuit is configured with an MIM (Metal-Insulator-Metal) structure. circuit.