JP2014192374A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently perform an electrical testing process of a semiconductor wafer.SOLUTION: In a process of performing electrical testing of a semiconductor integrated circuit by bringing tips of a plurality of contact terminals held by a probe card into contact with a plurality of chip electrodes of a wafer WH, electrical testing is sequentially performed on each of a plurality of testing ranges 10t by moving relative positions of the probe card and the wafer WH on a principal surface 12a of the wafer WH divided into the plurality of testing ranges 10t. And regarding a testing order of the plurality of testing ranges 10t, when the principal surface 12a of the wafer WH is divided into a semicircle HM1 and a semicircle HM2 which do not overlap each other, a part of testing of the plurality of testing ranges 10t in the semicircle HM2 is performed before testing of the plurality of testing ranges 10t in the semicircle HM1 is completed.

Description

  The present invention relates to a semiconductor device manufacturing technique, and is effective when applied to, for example, a semiconductor device manufacturing method including a step of performing an electrical inspection for confirming the electrical characteristics of an integrated circuit formed on a semiconductor wafer in a high-temperature environment. Regarding technology.

  Japanese Patent Laying-Open No. 2009-21397 (Patent Document 1) describes a method of performing electrical inspection by bringing a plurality of probe needles into contact with a plurality of circuit elements formed on a semiconductor wafer (wafer) at a time. Yes. Patent Document 1 describes a method of correcting a positional deviation that occurs between a probe card (multi-card) in which a plurality of probe needles are formed and a semiconductor wafer.

  Japanese Patent Laid-Open No. 2009-99693 (Patent Document 2) has an object to prevent the probe of the probe card from being cooled even when the probe of the probe card partially protrudes from the wafer chuck at the time of high temperature inspection by the probe card. Thus, an inspection apparatus is described in which a heating body for heating the probe card is provided around the wafer chuck.

JP 2009-21397 A JP 2009-99693 A

  When performing an electrical inspection to confirm the electrical characteristics of a semiconductor chip, it is necessary to confirm the electrical characteristics in the temperature range required for the inspection target product. For example, the electrical inspection is performed in a high temperature environment exceeding 100 ° C. A physical inspection may be performed. Also, as a method of electrical inspection, a method of electrically connecting an inspection circuit and a circuit formed on the inspection target product by bringing a plurality of probe needles into contact with a plurality of electrodes of the inspection target product collectively There is.

  However, when the above-described electrical inspection is performed in a high-temperature environment, the length of the probe needles may expand and contract due to thermal effects, and the plurality of probe needles may not be correctly brought into contact with the plurality of electrodes. In this case, since electrical inspection is performed again, manufacturing efficiency is reduced. Further, if the planar size of the heater for heating the probe needles is increased in order to keep the temperature of the plurality of probe needles constant, the inspection apparatus will be enlarged. In addition, due to the integration of probe needles, it is difficult to perform an electrical inspection for the entire range of a single semiconductor wafer at a time. It is divided into two and it carries out sequentially. For this reason, when the probe needle is reheated every time the inspection of each inspection range is completed, the inspection time increases and the manufacturing efficiency decreases.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to an embodiment of the present invention, there is provided a method of manufacturing a semiconductor device in which a plurality of contact terminals held on a first card are brought into contact with a plurality of chip electrodes of a semiconductor wafer while the semiconductor wafer is heated. A step of performing an electrical inspection. Further, in the step of performing the electrical inspection, the main surface of the semiconductor wafer divided into a plurality of inspection ranges is moved for each of the plurality of inspection ranges while moving the relative positions of the first card and the semiconductor wafer. Electrical inspections are performed in sequence. Further, the inspection order of the plurality of inspection ranges is that when the main surface of the semiconductor wafer is divided into a first semicircle and a second semicircle that do not overlap each other, the plurality of inspection ranges in the first semicircle Before the inspection is completed, a part of the plurality of inspection ranges in the second semicircle is inspected.

  According to the one embodiment, the electrical inspection process can be efficiently performed.

It is explanatory drawing which shows the outline | summary of the manufacturing flow of the semiconductor device which is one embodiment. It is a top view which shows the main surface side of the semiconductor wafer prepared at the wafer preparation process shown in FIG. FIG. 3 is an enlarged sectional view of a part of the semiconductor wafer shown in FIG. 2. It is a top view which shows one main surface side among the several semiconductor chips acquired by the individualization process shown in FIG. It is explanatory drawing which shows typically schematic structure of the test | inspection apparatus used by the probe test process shown in FIG. It is sectional drawing which shows the structure of the probe card shown in FIG. 5 typically. FIG. 6 is a plan view schematically showing a surface (main surface) facing the wafer of the probe card shown in FIG. 5. 6 is an enlarged cross-sectional view showing a state in which the probe card shown in FIG. 6 and the semiconductor wafer shown in FIG. 2 are arranged to face each other in the inspection apparatus shown in FIG. It is a top view which shows the example which divided the main surface of the semiconductor wafer shown in FIG. 2 into the some test | inspection range. FIG. 10 is an enlarged cross-sectional view illustrating a state in which an electrical inspection is performed on the inspection range of the peripheral portion of the main surface of the semiconductor wafer among the plurality of inspection ranges illustrated in FIG. 9. FIG. 10 is an enlarged plan view showing a state in which the main surface of the semiconductor wafer shown in FIG. 9 is partitioned into a plurality of inspection regions each having a plurality of inspection ranges. FIG. 2 is a plan view showing an inspection sequence immediately after the start of inspection in the electrical inspection step shown in FIG. 1. It is a top view which shows the protrusion part of the probe card shown in FIG. 10 from the viewpoint from the contact terminal arrangement | positioning surface side of a probe card. FIG. 13 is a plan view showing an inspection sequence following FIG. 12. It is a top view which shows the protrusion part of a probe card in the completion of the test | inspection order shown in FIG. 14 from the viewpoint from the contact terminal arrangement | positioning surface side of a probe card. FIG. 15 is a plan view showing an inspection sequence following FIG. 14. FIG. 17 is a plan view showing an inspection sequence following FIG. 16. FIG. 18 is a plan view showing an inspection sequence following FIG. 17. FIG. 19 is a plan view showing an inspection sequence following FIG. 18. FIG. 20 is a plan view showing an inspection sequence following FIG. 19. FIG. 21 is a plan view showing an inspection sequence following FIG. 20. It is a top view which shows collectively the test | inspection order shown in FIGS. It is a top view which shows the modification with respect to FIG. It is a top view which shows the other modification with respect to FIG. It is a top view which shows the other modification with respect to FIG. It is a top view which shows the test | inspection order in the electrical test process which is a comparative example with respect to embodiment. It is a top view which shows the test | inspection order in the electrical test process which is another comparative example with respect to embodiment.

(Description of description format in this application)
In the present application, the description of the embodiment will be divided into a plurality of sections for convenience, if necessary, but these are not independent from each other unless otherwise specified. Regardless of the front and rear, each part of a single example, one is a part of the other, or a part or all of the modifications. In principle, repeated description of similar parts is omitted.

  In addition, each component in the embodiment is not indispensable unless specifically stated otherwise, unless it is theoretically limited to the number, and obviously not in context. Moreover, in each figure of embodiment, the same or similar part is shown with the same or similar symbol or reference number, and description is not repeated in principle.

  In the accompanying drawings, hatching or the like may be omitted even in a cross section when it becomes complicated or when the distinction from the gap is clear. In relation to this, when it is clear from the description etc., the contour line of the background may be omitted even if the hole is planarly closed. Furthermore, even if it is not a cross section, hatching or a dot pattern may be added in order to clearly indicate that it is not a void or to clearly indicate the boundary of a region.

<Method for Manufacturing Semiconductor Device>
First, the overall flow of the semiconductor device manufacturing method of the present embodiment will be described with reference to FIGS. FIG. 1 is an explanatory diagram showing an outline of the manufacturing flow of the semiconductor device of the present embodiment. 2 is a plan view showing the main surface side of the semiconductor wafer prepared in the wafer preparation step shown in FIG. 1, FIG. 3 is an enlarged sectional view of a part of the semiconductor wafer shown in FIG. 2, and FIG. It is a top view which shows one main surface side among the several semiconductor chips acquired by the individualization process shown in FIG.

  First, as a wafer preparation step shown in FIG. 1, as shown in FIG. 2, a wafer (semiconductor wafer) WH partitioned into a plurality of chip regions 10a is prepared. The wafer WH has a substantially circular planar shape (specifically, a notch such as a notch or an oriental flat is formed in order to recognize the crystal orientation at the periphery). In the example shown in FIG. 2, the diameter of the main surface of the wafer WH is, for example, 300 mm.

  Further, on the main surface of the wafer WH, chip regions 10a each corresponding to one semiconductor chip are provided. In FIG. 2, the plane size of the chip region 10a is shown to be large for the sake of clarity, so 44 chip regions 10a are provided. However, when the number of chip regions 10a is larger than that shown in FIG. Is also applicable. The number of chip regions 10a included in one wafer WH varies depending on the planar size of the chip region 10a. For example, the number of chip regions 10a may be approximately 1,000 to 2,000. . A semiconductor integrated circuit is formed in each of the plurality of chip regions 10a of the wafer WH, and a plurality of pads (electrodes, chip electrodes, electrode pads) 11 that are electrically connected to the semiconductor integrated circuit on the main surface (see FIG. 4). Is formed.

  An example of a method for forming the wafer WH shown in FIG. 2 will be briefly described with reference to FIG. 3. For example, the wafer WH is formed as follows. First, in the semiconductor substrate preparation step (see FIG. 1), the semiconductor substrate 12 having the main surface (device forming surface) 12a is prepared. Thereafter, in a semiconductor element formation step (see FIG. 1), a plurality of semiconductor elements (not shown) such as transistors and diodes are formed on the main surface 12a of the semiconductor substrate 12. Thereafter, the wiring layer 13 is laminated on the main surface 12a of the semiconductor substrate 12 in a chip wiring layer forming step (see FIG. 1). In FIG. 3, the example which laminated | stacked the several wiring layer 13 on the main surface 12a is shown.

  In this chip wiring layer forming step, a plurality of pads 11 are formed in the uppermost layer, and each pad 11 is electrically connected to a plurality of semiconductor elements on the main surface 12a via a plurality of wirings 13a provided in the wiring layer 13. . The plurality of wirings 13 a are insulated by an insulating film 13 b provided in the wiring layer 13. Through these steps, a plurality of semiconductor integrated circuits are formed on the main surface 12a side of the wafer WH. Thereafter, in a protective film forming step (see FIG. 1), a protective film (passivation film, insulating film) 14 is formed so as to cover the wiring layer 13 and the pad 11. Then, an opening 14 a is formed in a part of the protective film 14, and the pad 11 is exposed from the protective film 14 in the opening 14 a.

  Through the above steps, an integrated circuit corresponding to the semiconductor chip 10 shown in FIG. 4 and a plurality of pads 11 are formed in each of the plurality of chip regions 10a of the wafer WH, and the wafer WH shown in FIG. 2 is obtained. The protective film (passivation film, insulating film) 14 is formed of, for example, a silicon nitride film, a silicon oxide film, or a laminated film of a silicon nitride film and a silicon oxide film. As shown in FIG. 4, in the present embodiment, a plurality of pads 11 are arranged along each side of the semiconductor chip 10 (chip region 10a) that forms a quadrangle in plan view.

  In the example shown in FIG. 4, an embodiment is shown in which a plurality of pads 11 are arranged in a row along each side of the semiconductor chip 10. Can be applied. For example, the pads 11 can be arranged in a plurality of rows along each side of the semiconductor chip 10. Further, for example, the present invention can be applied to an embodiment in which the pad 11 is arranged in the central portion inside the peripheral portion in addition to the peripheral portion of the semiconductor chip 10.

  Next, as a probe inspection process shown in FIG. 1, an electrical inspection of the wafer WH shown in FIG. 2 is performed. As shown in FIG. 1, the probe inspection process includes a probe card preparation process and an electrical inspection process. In FIG. 1, for convenience of explanation, the wafer preparation process and the probe inspection process are shown separately, but the wafer preparation process may be included in the probe inspection process. Details of the probe inspection process will be described later.

  Next, as the singulation process shown in FIG. 1, the wafer WH shown in FIG. 2 is divided for each chip region 10a to obtain a plurality of semiconductor chips (semiconductor devices) 10 shown in FIG. In this step, for example, the wafer WH is cut along the scribe regions 10b arranged between each of the plurality of chip regions 10a shown in FIG. 2 and separated into individual chip regions 10a. Through the above steps, the semiconductor chip 10 which is the semiconductor device of the present embodiment is obtained. The above describes the outline of the main steps among the steps of manufacturing a semiconductor chip, and various modifications can be applied.

<Inspection device>
Next, an outline of an inspection apparatus used in the probe inspection process shown in FIG. 1 will be described. FIG. 5 is an explanatory view schematically showing a schematic configuration of the inspection apparatus used in the probe inspection step shown in FIG. 1, and FIG. 6 is a cross-sectional view schematically showing the structure of the probe card shown in FIG. FIG. 7 is a plan view schematically showing the surface (main surface) facing the wafer of the probe card shown in FIG. In the example shown in FIGS. 6 and 7, the number of probe needles 2 is reduced for ease of viewing. However, since the probe needles 2 are provided in correspondence with the number of pads 11 to be inspected at a time in the electrical inspection process shown in FIG. 1, the number of probe needles 2 is larger than that shown in FIGS.

  As shown in FIG. 5, the prober (inspection apparatus) PR of the first embodiment includes a probe card PRC, a tester head THD, an interface ring IFR, a card holder CHD, a wafer stage WST, and a wafer chuck (wafer holding table) WCH. It is formed from. The tester head THD and the interface ring IFR, and the interface ring IFR and the probe card PRC are electrically connected to each other via a plurality of wirings IFw, whereby the tester head THD and the probe card PRC are connected. Are electrically connected. As the plurality of wirings IFw, for example, a conductive member called a pogo pin (POGO pin) or a spring probe can be used. Pogo pins and spring probes have a structure in which a contact pin (plunger (contact needle)) is pressed against an electrode (terminal) by the elastic force of a spring (coil spring), and electrical connection to the electrode is performed as necessary. In this contact needle, for example, a spring arranged in a metal tube (holding member) transmits the elastic force to the contact pin via the metal ball. The tester head THD is electrically connected to the tester T, and a voltage and a signal current necessary for probe inspection are supplied from the tester T.

  The card holder CHD mechanically connects the probe card PRC to the prober PR, and has a mechanical strength that prevents the probe card PRC from being warped due to pressure during electrical inspection. In addition, wafer stage WST is disposed in the housing of prober PR, and wafer chuck WCH, which is a wafer holding table, is disposed and fixed on wafer stage WST.

  The wafer WH to be inspected is held by the wafer chuck WCH with the main surface 12a (see FIG. 3) side on which the plurality of pads 11 (see FIG. 4) are formed facing the probe card PRC. The wafer chuck WCH can hold the wafer WH by, for example, an adsorption method. Further, the wafer chuck WCH has a built-in heater HT as a heating source, and the wafer chuck WCH can be heated by causing the heater HT to generate heat. In the electrical inspection process shown in FIG. 1, the electrical characteristics of the wafer WH are inspected while the wafer WH is heated via the wafer chuck WCH.

  Further, as described above, since many chip regions 10a (see FIG. 2) are formed on the wafer WH, it is difficult to inspect all the chip regions 10a at once. Therefore, in the electrical inspection process shown in FIG. 1, the main surface of the wafer WH is partitioned into a plurality of inspection ranges, and the electrical positions of the plurality of inspection ranges are electrically moved while moving the relative positions of the probe card PRC and the wafer WH. Conduct an inspection.

  As a method of moving the relative positions of the probe card PRC and the wafer WH, there is a method of moving one or both of the probe card PRC and the wafer WH. In the example of the present embodiment, the wafer chuck WCH that fixes the wafer WH by operating a driving unit (not shown) attached to the wafer stage WST, together with the wafer stage WST, is in a planar direction (shown in FIG. 5). The structure operates in the (XY plane direction). From the viewpoint of suppressing the occurrence of deviation by moving the probe card PRC, a structure for moving the wafer chuck WCH as in the present embodiment is preferable.

  Note that the above-described inspection range is not necessarily limited to one chip region 10a. For example, a plurality of chip regions 10a may be included in one inspection range. In the above, the embodiment in which wafer stage WST moves together with wafer chuck WCH has been described. However, as a modification, wafer stage WST does not move, and wafer chuck WCH moves independently from wafer stage WST. It can also be.

  Next, the structure of the probe card PRC shown in FIG. 5 will be described. As shown in FIG. 6, the probe card PRC has an upper surface 1a, a lower surface 1b located on the opposite side of the upper surface 1a, and a wiring having a plurality of wirings 1w formed so as to electrically connect the upper surface 1a and the lower surface 1b. A substrate 1 is provided. The lower surface 1b of the wiring board 1 is a contact terminal arrangement surface of the probe card PRC, and a central portion of the lower surface 1b is a contact terminal for making contact with each of the plurality of pads 11 (see FIG. 4). A plurality of probe needles (contact terminals, contactors) 2 are formed. Moreover, the upper surface 1a of the wiring board 1 is a back surface located on the opposite side to the contact terminal arrangement surface of the probe card PRC.

  The plurality of wirings 1 w formed on the wiring board 1 are electrically connected to the plurality of probe needles 2 on the lower surface 1 b side of the wiring board 1. On the other hand, a plurality of terminals 1d, which are terminals electrically connected to the plurality of wirings IFw shown in FIG. 5, are formed on the upper surface 1a of the wiring board 1, and are electrically connected to the plurality of wirings 1w. . The terminal 1d is a terminal connected to a wiring IFw (see FIG. 5) for inputting or outputting a signal between the tester head THD (see FIG. 5) and the probe card PRC. That is, the terminal 1d is an external terminal of the probe card PRC, and each of the plurality of probe needles 2 shown in FIG. 6 is connected to the tester head shown in FIG. 5 via the plurality of wirings 1w formed on the wiring board 1. It is electrically connected to a circuit for electrical inspection (not shown) formed in the THD.

  As shown in FIG. 7, a needle pressing portion (contact terminal fixing portion) 3 that fixes the root portions of the plurality of probe needles 2 is provided at the center portion of the lower surface 1 b of the wiring board 1. The needle pressing portion 3 is a member made of, for example, resin, and a part of the probe needle 2 is sealed by the needle pressing portion 3 as shown in FIG. Specifically, the wiring connection portion 2a provided at one end of the probe needle 2 is connected to the wiring 1w, and the contact portion (contact portion, tip portion) 2c provided at the other end is a needle pressing portion. 3 is exposed. The probe needle 2 has a bent portion 2b between the wiring connecting portion 2a and the contact portion 2c, and is bent so that the extending direction of the contact portion 2c faces the wafer WH shown in FIG. Yes. The needle pressing portion 3 has a function of preventing the tip end position of the contact portion 2c from shifting by sealing the bent portion 2b of the probe needle 2. In the electrical inspection process shown in FIG. 1, the probe needle 2 and the pad 11 are electrically connected by bringing the contact portion 2c, which is the tip of the probe needle 2, into contact with the pad 11 shown in FIG.

<Details of electrical inspection process>
Next, details of the electrical inspection process shown in FIG. 1 performed using the prober PR shown in FIG. 5 will be described. 8 is an enlarged cross-sectional view showing a state in which the probe card shown in FIG. 6 and the semiconductor wafer shown in FIG. 2 are arranged to face each other in the inspection apparatus shown in FIG. FIG. 9 is a plan view showing an example in which the main surface of the semiconductor wafer shown in FIG. 2 is partitioned into a plurality of inspection ranges. FIG. 10 is an enlarged cross-sectional view showing a state in which an electrical inspection is being performed on the inspection range of the peripheral portion of the main surface of the semiconductor wafer among the plurality of inspection ranges shown in FIG. FIG. 26 is a plan view showing an inspection sequence in an electrical inspection process which is a comparative example with respect to the present embodiment. FIG. 27 is a plan view showing an inspection sequence in an electrical inspection process which is another comparative example with respect to the present embodiment.

  In the electrical inspection process shown in FIG. 1, as shown in FIG. 8, the wafer WH described with reference to FIGS. 2 to 4 is fixed on the wafer chuck WCH. Wafer chuck WCH has an adsorption function, and adsorbs and holds wafer WH in a state where back surface 12b located on the opposite side of main surface 12a of wafer WH faces wafer holding surface WCHa of wafer chuck WCH.

  In the electrical inspection process shown in FIG. 1, as shown in FIG. 8, the probe card PRC described with reference to FIGS. 6 and 7 is disposed so that the lower surface 1b faces the main surface 12a of the wafer WH. In the example shown in FIG. 8, the probe card PRC is held with the lower surface 1b facing the wafer WH by fixing the card holder CHD of the prober PR and the probe card PRC, for example, with screws.

  The order of the step of fixing wafer WH on wafer chuck WCH and the step of holding probe card PRC on card holder CHD is not particularly limited. For example, when the wafers WH are sequentially replaced and the electrical inspection is continuously performed, the probe card PRC replaces the wafers WH while being held by the card holder CHD.

  Next, a plurality of probe needles 2 and a plurality of pads 11 in a state where the lower surface 1b which is a contact terminal arrangement surface of the probe card PRC and the main surface 12a side of the wafer WH which is an object to be inspected are arranged to face each other. (See FIG. 4) is contacted to inspect the electrical characteristics of the integrated circuit formed on the wafer WH. In this embodiment, in this process, in order to inspect the electrical characteristics of the wafer WH in a high temperature environment, the inspection is performed in a state where the wafer WH is heated by the heater HT incorporated in the wafer chuck WCH. The set temperature of the wafer WH varies depending on the product, but is heated to a temperature exceeding 100 ° C., for example. In the present embodiment, the electrical inspection is performed by heating the wafer WH so that the temperature is in a temperature range of, for example, about 140 ° C. to 160 ° C.

  Here, from the viewpoint of shortening the time required for the electrical inspection process, it is preferable to collectively inspect a plurality of chip regions 10a (see FIG. 2) formed on the main surface 12a side of the wafer WH. However, considering the routing space of the wiring 1w electrically connected to the plurality of probe needles 2, it is difficult to inspect all the chip regions 10a formed on one wafer WH collectively. For this reason, in the electrical inspection process, as shown in FIG. 9, the main surface 12a of the wafer WH is partitioned into a plurality of inspection ranges 10t, and the relative positions of the probe card PRC and the wafer WH shown in FIG. 8 are moved. Then, electrical inspection is performed in order for each of the plurality of inspection ranges 10t shown in FIG.

  Here, when the relative position of the probe card PRC and the wafer WH shown in FIG. 8 is moved, from the viewpoint of inspection efficiency, or from the viewpoint of improving the reliability of inspection by suppressing the occurrence of positional deviation, It is preferable to make the total moving distance of the relative position as small as possible from the start to the completion of the inspection of the wafer WH.

  For example, as shown in an inspection sequence TFH1 schematically shown with arrows in FIG. 26, a method of moving spirally from the central portion on the main surface 12a toward the peripheral portion, or an inspection sequence TFH2 shown in FIG. In addition, if the method is to move spirally from the peripheral edge on the main surface 12a toward the center, the movement distance of the relative position can be minimized.

  However, the inventor of the present application applies the inspection sequence TFH1 shown in FIG. 26 or the inspection sequence TFH2 shown in FIG. 27 in the electrical inspection performed in a state where the wafer WH is heated, in other words, in a high temperature environment. As a result, it was found that a correct inspection result could not be obtained in a part of the inspection range 10t. In other words, when an electrical test is performed by applying the test sequence TFH1 shown in FIG. 26 or the test sequence TFH2 shown in FIG. 27 in a high temperature environment, a measurement error is likely to occur and the reliability of the electrical test is reduced. I found out that

  For example, in a part of the inspection range 10t, a so-called open defect has occurred in which the probe needle 2 (see FIG. 6) and the pad 11 (see FIG. 4) do not contact each other. Further, if the setting is changed so as to reduce the distance between the probe card PRC and the wafer WH shown in FIG. 8 in order to suppress the open defect, the probe needle 2 in the inspection range 10t different from the above-described partial inspection range. The contact pressure between the pad 11 (see FIG. 6) and the pad 11 (see FIG. 4) increased. If the contact pressure between the probe needle 2 and the pad 11 becomes excessively large, the pad 11 may be damaged. Further, when the contact pressure becomes excessively large, a positional deviation between the probe needle 2 and the pad 11 occurs.

  Further, according to the study by the present inventor, it has been found that the above-described measurement error is particularly likely to occur when a test is performed in a high temperature environment. After the electrical inspection is performed in a high temperature environment, when the contact traces remaining on the plurality of pads 11 formed on the wafer WH are confirmed, the peripheral surface of the main surface 12a in the plurality of inspection ranges 10t shown in FIG. In the inspection range 10 to, there are many pads 11 with shallow contact marks, and there are also pads 11 for which no contact marks can be confirmed. On the other hand, in the main surface 12a, in the inspection range 10ti existing inside the inspection range 10to, there are many pads 11 with deep contact marks.

  From the above examination results, when an electrical inspection is performed in a high temperature environment, the length of the probe needle 2 shown in FIG. 6 changes due to thermal expansion or contraction, and the height of the tip of the contact portion 2c changes. Is considered to be the cause.

  Specifically, in the case of performing an electrical inspection of the inspection range 10ti arranged at the center of the main surface 12a shown in FIG. 9, as shown in FIG. 8, almost the entire probe card PRC is connected to the wafer chuck WCH as a heat source. It overlaps in the thickness direction (Z direction shown in FIG. 8). The wafer chuck WCH is a heat source for heating the wafer WH. However, when the electrical inspection is performed, the distance between the wafer chuck WCH and the probe card PRC is short, so that the probe card PRC is also heated. Therefore, if almost the entire probe card PRC overlaps the wafer chuck WCH in the thickness direction, the temperatures of the plurality of probe needles 2 formed on the probe card PRC are stabilized. In other words, the length of the probe needle 2 is maintained in a thermally expanded state.

  However, when an electrical inspection is performed in the inspection range 10 to that is arranged at the peripheral portion of the main surface 12a shown in FIG. 9, as shown in FIG. 10, the portion PRCf that is a part of the probe card PRC is a wafer chuck that is a heat source. It does not overlap with WCH in the thickness direction (Z direction shown in FIG. 10). In other words, when an electrical inspection is performed in the inspection range 10 to that is arranged at the peripheral edge, the portion PRCf that is a part of the probe card PRC protrudes from the wafer chuck WCH in plan view. Therefore, the temperature of the portion PRCf of the probe card PRC is lower than that of other portions of the probe card PRC.

  At this time, a wiring 1w that is electrically connected to the probe needle 2 is formed in the portion PRCf of the probe card PRC as shown in FIG. For this reason, if the temperature of the partial PRCf decreases, the heat of the probe needle 2 is easily transmitted to the outside via the wiring 1w of the partial PRCf, and therefore the temperature of the probe needle 2 is likely to decrease. Further, when the probe needle 2 is formed on the portion PRCf of the probe card PRC, the temperature of the probe needle 2 is particularly likely to decrease.

  That is, when an electrical inspection is performed in the inspection range 10 to that is arranged at the peripheral portion of the main surface 12a shown in FIG. 9, a temperature drop is likely to occur in some of the plurality of probe needles 2 (see FIG. 8). Become. For this reason, it is considered that the probe needle 2 whose temperature has decreased is subject to thermal contraction, and the height of the tip of the contact portion 2c (see FIG. 6) has increased (closer to the lower surface 1b side of the wiring board 1).

  The inventor of the present application further studied a technique capable of suppressing the temperature drop of the probe needle 2 in an electrical test under a high temperature environment based on the above examination results.

  First, the inventor of the present application increases the plane area of the surface of the wafer chuck WCH facing the probe card PRC shown in FIG. 8 so that the probe card PRC can be inspected anywhere in the plurality of inspection ranges 10t shown in FIG. An embodiment was examined in which almost the entire surface of the wafer overlaps with the wafer chuck WCH in the thickness direction. However, when the plane area of the wafer chuck WCH is increased, the size of the apparatus is increased. In particular, when a method of moving the wafer chuck WCH is applied as a method of moving the relative position between the probe card PRC and the wafer WH, the entire apparatus becomes very large because it is necessary to drive the enlarged wafer chuck WCH. . Further, from the viewpoint of energy efficiency, a portion of the wafer mounting surface of the wafer chuck WCH that does not overlap the wafer WH needs to be heated, resulting in a large loss of heating energy.

  Next, the inventor of the present application completes the inspection of each inspection range 10 to when the inspection range 10 to is arranged in the peripheral portion of the main surface 12 a among the plurality of inspection ranges 10 t illustrated in FIG. 9. Each time the probe card PRC was moved to a position where it overlapped with the wafer chuck WCH, the probe needle 2 was reheated. In this case, since the probe needle 2 can be stably heated, the depth of the contact mark can be stabilized.

  However, since it takes time to reheat the probe needle 2, the inspection time increases and the manufacturing efficiency decreases. In addition, since the total movement distance of the relative position is greatly increased as compared with the inspection order TFH1 shown in FIG. 26 and the inspection order TFH2 shown in FIG. 27, there is an increased possibility that the probe card PRC and the wafer WH are displaced. To do.

  Next, the inventor of the present application attaches the probe card PRC by the wafer chuck WCH before the electrical inspection or before the inspection of the next wafer WH after the electrical inspection of one wafer WH is finished. The method of heating was examined. However, as described above, the phenomenon in which a correct test result cannot be obtained in a part of the test range 10t shown in FIG. 9 changes in length due to thermal expansion or contraction of the probe needle 2 shown in FIG. This is considered to be caused by the change in the height of the tip of the contact portion 2c. Therefore, it was found that if the time for heating the probe card PRC by the wafer chuck WCH is extended, the number of measurement errors is reduced, but it is not sufficient.

  Next, the inventor of the present application performs the inspection of the inspection range 10to arranged at the peripheral portion of the main surface 12a among the plurality of inspection ranges 10t shown in FIG. The height of the tip of each was confirmed, and an embodiment for adjusting the height was examined. However, since it takes time to adjust the height of the probe needle 2, the inspection time increases and the manufacturing efficiency decreases. Further, when the temperature of the plurality of probe needles 2 varies, it is difficult to cope with the height adjustment.

  Therefore, the inventor of the present application has further studied a technique for efficiently performing the electrical inspection process, and has found a technique described in this embodiment. That is, when the electrical inspection is performed, as shown in FIG. 10, when the portion PRCf of the probe card PRC protrudes from the wafer chuck WCH, a measurement error due to a temperature drop of the portion PRCf occurs. Before this, the portion PRCf moves to a position where it overlaps the wafer chuck WCH in the thickness direction, and the electrical inspection is continued.

  According to the study by the present inventor, when the portion PRCf of the probe card PRC protrudes from the wafer chuck WCH, a measurement error does not immediately occur. For example, when the heating set temperature of the wafer WH is set to about 140 ° C. to 160 ° C., when the portion PRCf of the probe card PRC protrudes from the wafer chuck WCH for about 2 hours or more, the above measurement error is likely to occur. I found out that

  Therefore, if the portion PRCf shifts from the wafer chuck WCH to an electrical inspection within the inspection range 10t (see FIG. 9) in which the portion PRCf is disposed at a position where the portion PRCf overlaps the wafer chuck WCH within two hours. The occurrence of measurement errors can be suppressed.

  At this time, even if a part other than the part PRCf protrudes from the wafer chuck WCH, an electrical inspection of the inspection range 10t in which the part overlaps the wafer chuck WCH within two hours. If it shifts to, generation | occurrence | production of a measurement error can be suppressed.

  The inspection sequence of the above-described embodiment will be described below with reference to the drawings. In the present embodiment, in order to easily explain the inspection sequence in the electrical inspection process, as shown in FIG. 11, the main surface 12a of the wafer WH is a plurality of virtual regions each having a plurality of inspection ranges 10t. A description will be given by dividing into inspection areas. FIG. 11 is an enlarged plan view showing a state in which the main surface of the semiconductor wafer shown in FIG. 9 is partitioned into a plurality of inspection regions each having a plurality of inspection ranges. FIG. 12 is a plan view showing the inspection sequence immediately after the start of inspection in the electrical inspection step shown in FIG. FIG. 13 is a plan view showing a protruding portion of the probe card shown in FIG. 10 from a viewpoint from the contact terminal arrangement surface side of the probe card. FIG. 14 is a plan view showing the inspection sequence following FIG. FIG. 15 is a plan view showing the protruding portion of the probe card as seen from the contact terminal arrangement surface side of the probe card when the inspection sequence shown in FIG. 14 is completed. FIG. 16 is a plan view showing the inspection sequence following FIG. FIG. 17 is a plan view showing the inspection sequence following FIG. FIG. 18 is a plan view showing the inspection sequence following FIG. FIG. 19 is a plan view showing the inspection sequence following FIG. FIG. 20 is a plan view showing the inspection sequence following FIG. FIG. 21 is a plan view showing the inspection sequence following FIG. FIG. 22 is a plan view collectively showing the inspection sequence shown in FIGS.

  11, FIG. 12, FIG. 14, and FIG. 16 to FIG. 22 are plan views, but are different for each of the inspection regions TR1, TR2, TR3, TR4, and TR5 in order to clearly show the range of the inspection region. It is shown with a pattern. Further, in FIGS. 13 and 15, in order to clarify the range of the portion PRCf protruding from the wafer chuck WCH in the probe card PRC, the portion PRCf is shown with a dot pattern.

  First, the definition of the section of the main surface 12a of the wafer WH will be described in detail with reference to FIG. As shown in FIG. 11, the main surface 12a of the wafer WH is divided into a semicircle HM1 and a semicircle HM2, which are virtual areas that do not overlap each other. In addition to the division of the semicircles HM1 and HM2, the main surface 12a of the wafer WH is divided into a plurality of inspection areas each having a plurality of inspection ranges 10t. In addition to the example shown in FIG. 11, the number of inspection areas includes many variations. In the example shown in FIG. 11, the inspection area is divided into five inspection areas TR1, TR2, TR3, TR4, and TR5. Is shown.

  The inspection area TR1 shown in FIG. 11 is an inspection area that includes the center of the main surface 12a, and is a virtual area that does not include the peripheral portion of the main surface 12a. In other words, another inspection range 10t is arranged around a plurality (four in FIG. 11) of inspection ranges 10t included in the inspection region TR1. Furthermore, in other words, the plurality of inspection ranges 10t included in the inspection region TR1 are all inspection ranges 10ti arranged in the central portion of the main surface 12a. The inspection region TR1 is arranged so as to straddle the boundary between the semicircle HM1 and the semicircle HM2.

  Also, the inspection region TR2 shown in FIG. 11 is a virtual region that is a part of the semicircle HM1, does not overlap the semicircle HM2, and includes the peripheral edge of the main surface 12a. The inspection region TR2 has a plurality of (four in FIG. 11) inspection ranges 10t along the peripheral edge of the main surface 12a. Of the plurality of inspection ranges 10t arranged in the inspection region TR2, the inspection range 10t1 is arranged at one end of the inspection region TR2. Further, among the plurality of inspection ranges 10t arranged in the inspection region TR2, the inspection range 10t2 is arranged at the end opposite to the inspection range 10t1.

  Further, the inspection region TR3 shown in FIG. 11 is a virtual region that is a part of the semicircle HM2, does not overlap with the inspection region TR1 and the inspection region TR2, and includes the peripheral portion of the main surface 12a. is there. In the example shown in FIG. 11, the inspection region TR3 is disposed adjacent to the inspection region TR1, the inspection region TR2, and the inspection region TR5. As shown in FIG. 11, each of the plurality of inspection ranges 10t has a quadrangular shape in plan view, and therefore a part of the inspection range 10t arranged at the end of the inspection region TR3 (in FIG. 11, the inspection range 10t4 May be arranged so as to straddle the boundary between the semicircle HM1 and the semicircle HM2. However, most of the inspection region TR3 (for example, half or more) is included in the semicircle HM2.

  The inspection region TR3 has a plurality of (three in FIG. 11) inspection ranges 10t along the peripheral edge of the main surface 12a. Among the plurality of inspection ranges 10t arranged in the inspection region TR3, the inspection range 10t3 is arranged at one end of the inspection region TR3. Further, among the plurality of inspection ranges 10t arranged in the inspection region TR3, the inspection range 10t4 is arranged at the end opposite to the inspection range 10t3.

  Further, the inspection region TR4 shown in FIG. 11 is a part of the semicircle HM1, does not overlap the inspection region TR1, the inspection region TR2, and the inspection region TR3, and includes the peripheral portion of the main surface 12a. This is a virtual area. In the example shown in FIG. 11, the inspection region TR4 is disposed adjacent to the inspection region TR1, the inspection region TR2, and the inspection region TR5. In the example shown in FIG. 11, the inspection region TR4 is provided on the opposite side of the inspection region TR3 with the inspection region TR1 interposed therebetween.

  As shown in FIG. 11, each of the plurality of inspection ranges 10t has a quadrangular shape in plan view, and therefore a part of the inspection range 10t disposed at the end of the inspection region TR4 (in FIG. 11, the inspection range 10t5 May be arranged so as to straddle the boundary between the semicircle HM1 and the semicircle HM2. However, most of the inspection region TR4 (for example, half or more) is included in the semicircle HM1. The inspection region TR4 has a plurality of (three in FIG. 11) inspection ranges 10t along the peripheral edge of the main surface 12a.

  Among the plurality of inspection ranges 10t arranged in the inspection region TR4, the inspection range 10t5 is arranged at one end of the inspection region TR4. Further, among the plurality of inspection ranges 10t arranged in the inspection region TR4, the inspection range 10t6 is arranged at the end opposite to the inspection range 10t5.

  Further, the inspection region TR5 shown in FIG. 11 is a part of the semicircle HM2, does not overlap the inspection region TR1, the inspection region TR2, the inspection region TR3, and the inspection region TR4, and the peripheral edge of the main surface 12a. This is a virtual area including a part. In the example shown in FIG. 11, the inspection region TR5 is disposed adjacent to the inspection region TR1, the inspection region TR3, and the inspection region TR4. In the example shown in FIG. 11, the inspection region TR5 is provided on the opposite side of the inspection region TR2 across the inspection region TR1.

  In the example shown in FIG. 11, the inspection range 10t included in the inspection region TR5 is arranged at a position that does not overlap with the semicircle HM1. However, as a modified example, like the inspection range 10t4 and the inspection range 10t5 described above, a part of the inspection range 10t arranged at the end of the inspection region TR5 crosses the boundary between the semicircle HM1 and the semicircle HM2. There is also a case where it is arranged. However, most of the inspection region TR5 (for example, half or more) is included in the semicircle HM2.

  The inspection region TR5 has a plurality of (four in FIG. 11) inspection ranges 10t along the peripheral edge of the main surface 12a. Among a plurality of inspection ranges 10t arranged in the inspection region TR5, an inspection range 10t7 is arranged at one end of the inspection region TR5. In addition, the inspection range 10t8 is disposed at the end opposite to the inspection range 10t7 among the plurality of inspection ranges 10t disposed in the inspection region TR5.

  If it demonstrates using the division of the main surface 12a of the wafer WH defined as mentioned above, the electrical process of this Embodiment includes the following processes.

  First, the wafer WH and the probe card shown in FIG. 8 are moved from the inspection region TR1 toward the inspection range 10t1 located at the end of the inspection region TR2 as in the inspection sequence TF1 schematically shown with arrows in FIG. While moving the relative position of the PRC, each of the plurality of inspection ranges 10t included in the inspection region TR1 is inspected in order.

  In this step, the electrical inspection can be started from the inspection range 10t provided at the end of the inspection region TR1, but in the example shown in FIG. 12, it is adjacent to the center of the main surface 12a (or the main surface The electrical inspection is started from the inspection range 10t (including the center of the surface 12a). When performing an electrical inspection near the center of the main surface 12a, as shown in FIG. 8, the entire probe card PRC overlaps the wafer chuck WCH in the thickness direction. Therefore, from the viewpoint of starting the electric liquid inspection after aligning the temperature of the entire probe card PRC, as shown in the example shown in FIG. 12, it is adjacent to the center of the main surface 12a (or includes the center of the main surface 12a). It is preferable to start the electrical inspection from the inspection range 10t.

  In this case, a part of the inspection range 10t included in the inspection region TR1 may remain in an uninspected state in this process. However, as will be described later, since the inspection region TR1 is disposed at the center of the main surface 12a, it can be inspected even after this step.

  Further, in this process, when the inspection of the inspection range 10t1 shown in FIG. 12 is performed, as shown in FIG. 10, the portion PRCf which is a part of the probe card PRC is connected to the wafer chuck WCH which is a heat source and the thickness direction ( It will be in the state which does not overlap in the Z direction shown in FIG. In other words, when the inspection of the inspection range 10t1 shown in FIG. 12 is performed, as shown in FIG. 13, a portion PRCf (a portion with a dot pattern in FIG. 13) that is a part of the probe card PRC in plan view. Will protrude from the wafer chuck WCH. Therefore, the temperature of the portion PRCf of the probe card PRC starts to be lower than that of other portions of the probe card PRC. However, even if the partial PRCf starts to decrease in temperature as described above, a measurement error does not immediately occur.

  Next, the relative position of the wafer WH and the probe card PRC shown in FIG. 8 from the inspection range 10t1 of the inspection region TR2 toward the inspection range 10t2 as in the inspection sequence TF2 schematically shown with arrows in FIG. Each of the plurality of inspection ranges 10t included in the inspection region TR1 is inspected in turn. In this step, as shown in FIG. 14, the relative position is moved along the outer periphery of the main surface 12a.

  At this time, since the inspection region TR2 is a part rather than the entire semicircle HM1, when the inspection of the inspection range 10t2 is completed, the inspection range 10t in an uninspected state remains at the peripheral portion of the semicircle HM1. Yes. For example, in the example shown in FIG. 14, the inspection range 10t6 of the inspection region TR4 corresponds to the uninspected inspection range 10t.

  Further, the portion PRCf of the probe card PRC that protrudes from the wafer chuck WCH in the state shown in FIG. 13 continues to protrude from the wafer chuck WCH until the inspection of the inspection range 10t2 shown in FIG. 14 is completed. This is the partial PRCf1 shown in FIG. The portion PRCf1 is considered to have a lower temperature than other portions, and the probe needle 2 (see FIG. 6) is electrically connected to the wiring 1w (see FIG. 6) formed in the portion PRCf1. It is considered that the temperature of (see) has also decreased.

  For this reason, after the inspection of the inspection range 10t2 is completed, if the relative position is continuously moved along the outer periphery of the main surface 12a, the temperature decrease of the portion PRCf1 of the probe card PRC further proceeds and a measurement error occurs. become. On the other hand, in the present embodiment, after the inspection range 10t2 completes the inspection, the inspection range 10t6 adjacent to the inspection range 10t2 is not inspected, and as shown in FIG. 16, toward the inspection range 10t3 in the inspection region TR3. Move. At this time, the portion PRCf1 shown in FIG. 15 overlaps the wafer chuck WCH in the thickness direction, so that at least the temperature drop of the portion PRCf1 can be stopped.

  As described above, according to the study by the present inventor, it has been found that the measurement error described above is likely to occur after about two hours or more have passed from the wafer chuck WCH. Therefore, from the viewpoint of preventing measurement errors, it is preferable that the time from the start of the inspection of the inspection range 10t1 shown in FIG. 14 to the completion of the inspection of the inspection range 10t2 is within 2 hours. In other words, it is preferable to complete the inspection of all the inspection ranges 10t included in the inspection region TR2 shown in FIG. 14 within 2 hours.

  The inspection time required for inspecting one inspection range 10t and the movement time of the relative position can be easily measured. Therefore, by calculating the number of inspection ranges 10t included in the inspection region TR2 from the inspection time required to inspect one inspection range 10t and the movement time of the relative position, the inspection region TR2 shown in FIG. The inspection of all the included inspection ranges 10t can be completed within 2 hours.

  Next, relative to the wafer WH and the probe card PRC shown in FIG. 8 from the inspection range 10t2 toward the inspection range 10t3 of the inspection region TR3 as in the inspection sequence TF3 schematically shown with arrows in FIG. Move position. At this time, the relative position is moved so that the entire portion PRCf1 of the probe card PRC shown in FIG. 15 overlaps the wafer chuck WCH. For example, each of the plurality of probe needles 2 of the probe card PRC shown in FIG. 8 moves the relative position so as to straddle the inspection region TR1 shown in FIG. 16, so that the portion PRCf1 of the probe card PRC shown in FIG. It can be overlapped with the wafer chuck WCH in the thickness direction.

  In this step, if there is an uninspected inspection range 10t in the path from the inspection range 10t2 to the inspection range 10t3 shown in FIG. 16, the relative position is moved while performing the inspection of the uninspected inspection range 10t in order. Can be made. In this case, since the electrical inspection is performed in the middle of the inspection sequence TF3, the movement time becomes longer, and accordingly, the heating time of the portion PRCf1 of the probe card PRC shown in FIG. 15 becomes longer. That is, the temperature of the part PRCf1 is likely to rise.

  As shown in FIG. 16, when there is no unexamined inspection range 10t in the path from the inspection range 10t2 to the inspection range 10t3, each of the probe needles 2 of the probe card PRC shown in FIG. It may be simply moved so as to pass through the inspection region TR1 shown in FIG. Even in this case, the temperature drop of the partial PRCf1 can be stopped.

  When the contact portions 2c (see FIG. 6) of the plurality of probe needles 2 are arranged at positions facing the inspection range 10t3 shown in FIG. 16, most of the portion PRCf1 of the probe card PRC shown in FIG. It overlaps with chuck WCH. Of the portion PRCf1 of the probe card PRC, a portion near the boundary with the wafer chuck WCH may not overlap the wafer chuck WCH when the inspection range 10t3 shown in FIG. 16 is inspected. However, this portion is a slight range of the portion PRCf1 and is disposed in the vicinity of the boundary with the wafer chuck WCH. Therefore, in the inspection sequence TF3 shown in FIG. 16, if the entire part PRCf1 overlaps the entire wafer chuck WCH, the temperature drop of the part PRCf1 can be stopped.

  Next, the relative position of the wafer WH and the probe card PRC shown in FIG. 8 from the inspection range 10t3 of the inspection region TR3 toward the inspection range 10t4 as in the inspection order TF4 schematically shown with arrows in FIG. Each of the plurality of inspection ranges 10t included in the inspection region TR3 is inspected in turn. In this step, as shown in FIG. 17, the relative position is moved along the outer periphery of the main surface 12a.

  At this time, since the inspection region TR3 is a part rather than the whole of the semicircle HM2, when the inspection of the inspection range 10t2 is completed, the inspection range 10t in an uninspected state remains at the periphery of the semicircle HM2. Yes. For example, in the example shown in FIG. 17, the inspection range 10t8 and the inspection range 10t7 in the inspection region TR5 correspond to the uninspected inspection range 10t.

  Although not shown, when the inspection range 10t3 is inspected, the inspection range 10t4 shown in FIG. 17 is inspected from the portion of the probe card PRC (see FIG. 8) that protrudes from the wafer chuck WCH (see FIG. 8). Until the completion, there is a portion continuously protruding from the wafer chuck WCH. Therefore, from the viewpoint of preventing measurement errors, it is preferable that the time from the start of the inspection of the inspection range 10t3 shown in FIG. 17 to the completion of the inspection of the inspection range 10t4 is within 2 hours. In other words, it is preferable to complete the inspection of all the inspection ranges 10t included in the inspection region TR3 shown in FIG. 17 within 2 hours.

  Next, relative to the wafer WH and the probe card PRC shown in FIG. 8 from the inspection range 10t4 toward the inspection range 10t5 in the inspection region TR4 as in the inspection order TF5 schematically shown with arrows in FIG. Move position. In this step, the relative position is moved so that the entire portion that has continuously protruded from the wafer chuck WCH (see FIG. 8) when inspecting the inspection region TR3 overlaps the wafer chuck WCH. For example, each of the plurality of probe needles 2 of the probe card PRC shown in FIG. 8 moves continuously when the inspection region TR3 is inspected by moving the relative position so as to straddle the inspection region TR1 shown in FIG. In addition, the portion protruding from the wafer chuck WCH can be overlapped with the wafer chuck WCH in the thickness direction.

  In this step, if there is an uninspected inspection range 10t in the path from the inspection range 10t4 to the inspection range 10t5 shown in FIG. 18, the relative position is moved while performing the inspection of the uninspected inspection range 10t in order. Can be made. Further, when there is no uninspected inspection range 10t in the path from the inspection range 10t4 to the inspection range 10t5, each of the plurality of probe needles 2 of the probe card PRC shown in FIG. 8 has the inspection region TR1 shown in FIG. You can just move it to pass. Further, even when the uninspected inspection range 10t exists in the path from the inspection range 10t4 to the inspection range 10t5 shown in FIG. 18, the inspection is not performed in this step, and the plurality of probe needles 2 of the probe card PRC shown in FIG. Each of these may be simply moved so as to pass through the inspection region TR1 shown in FIG.

  Next, the relative position of the wafer WH and the probe card PRC shown in FIG. 8 from the inspection range 10t5 to the inspection range 10t6 in the inspection region TR4 as in the inspection sequence TF6 schematically shown with arrows in FIG. Each of the plurality of inspection ranges 10t included in the inspection region TR4 is inspected in turn. In this step, as shown in FIG. 19, the relative position is moved along the outer periphery of the main surface 12a.

  At this time, since the inspection region TR4 is a part rather than the whole of the semicircle HM1, in this step, among the plurality of inspection ranges 10t included in the semicircle HM1, the inspection range 10t not included in the inspection region TR2 is inspected. To implement. Therefore, in this step, the inspection of the inspection range 10t included in the inspection region TR2 is not performed.

  Although not shown, when the inspection range 10t5 is inspected, the inspection range 10t6 shown in FIG. 19 is inspected from the portion of the probe card PRC (see FIG. 8) that protrudes from the wafer chuck WCH (see FIG. 8). Until the completion, there is a portion continuously protruding from the wafer chuck WCH. Therefore, from the viewpoint of preventing measurement errors, it is preferable that the time from the start of the inspection range 10t5 shown in FIG. 19 to the completion of the inspection range 10t6 is within two hours. In other words, it is preferable to complete the inspection of all the inspection ranges 10t included in the inspection region TR4 shown in FIG. 19 within 2 hours.

  Next, relative to the wafer WH and the probe card PRC shown in FIG. 8 from the inspection range 10t6 toward the inspection range 10t7 in the inspection region TR5 as in the inspection sequence TF7 schematically shown with arrows in FIG. Move position. In this step, the relative position is moved so that the entire portion that has continuously protruded from the wafer chuck WCH (see FIG. 8) when inspecting the inspection region TR4 overlaps the wafer chuck WCH. For example, each of the plurality of probe needles 2 of the probe card PRC shown in FIG. 8 moves continuously when the inspection region TR4 is inspected by moving the relative position so as to straddle the inspection region TR1 shown in FIG. In addition, the portion protruding from the wafer chuck WCH can be overlapped with the wafer chuck WCH in the thickness direction.

  In this step, if there is an uninspected inspection range 10t in the path from the inspection range 10t6 to the inspection range 10t7 shown in FIG. 20, the relative position is moved while performing the inspection of the uninspected inspection range 10t in order. Can be made. The example shown in FIG. 20 shows an example in which a part of a plurality of inspection ranges 10ti included in the inspection region TR1 is inspected. Further, when there is no uninspected inspection range 10t in the path from the inspection range 10t6 to the inspection range 10t7, each of the plurality of probe needles 2 of the probe card PRC shown in FIG. 8 has the inspection region TR1 shown in FIG. You can just move it to pass. For example, in the inspection sequence TF5 described with reference to FIG. 18, when the inspection of a plurality of inspection ranges 10ti included in the inspection region TR1 is completed, the inspection is omitted in this step.

  Next, the relative position of the wafer WH and the probe card PRC shown in FIG. 8 from the inspection range 10t7 of the inspection region TR5 toward the inspection range 10t8 as in the inspection sequence TF8 schematically shown with arrows in FIG. Each of the plurality of inspection ranges 10t included in the inspection region TR5 is inspected in turn. In this step, as shown in FIG. 21, the relative position is moved along the outer periphery of the main surface 12a.

  At this time, since the inspection region TR5 is a part rather than the whole of the semicircle HM2, in this step, the inspection range 10t not included in the inspection region TR3 is inspected among the plurality of inspection ranges 10t included in the semicircle HM2. To implement. Accordingly, in this step, the inspection of the inspection range 10t included in the inspection region TR3 is not performed.

  Although not shown, when the inspection range 10t7 is inspected, the inspection range 10t8 shown in FIG. 21 is inspected from the portion of the probe card PRC (see FIG. 8) that protrudes from the wafer chuck WCH (see FIG. 8). Until the completion, there is a portion continuously protruding from the wafer chuck WCH. Therefore, from the viewpoint of preventing measurement errors, it is preferable that the time from the start of the inspection in the inspection range 10t7 shown in FIG. 21 to the completion of the inspection in the inspection range 10t8 is within 2 hours. In other words, it is preferable to complete the inspection of all the inspection ranges 10t included in the inspection region TR5 shown in FIG. 21 within 2 hours.

  FIG. 22 shows an inspection order TFa according to the present embodiment, which is a combination of the inspection order TF1 to the inspection order TF8 described in order with reference to FIGS. As shown in FIG. 22, in the case of the inspection order TFa, when the inspection of the inspection range 10t included in the inspection region TR5 is completed, the electrical inspection of all the inspection ranges of the wafer WH is completed. Therefore, after the inspection of the inspection range 10t8 is completed, no measurement error occurs even if the temperature of the probe card PRC drops.

  However, from the viewpoint of shortening the time until the electrical inspection of the next wafer (not shown) of the wafer WH is started, after the inspection of the inspection range 10t8 is completed, as shown in FIG. It is preferable to stabilize the temperature of the probe card PRC by moving the relative position to a position where the whole overlaps with the wafer chuck WCH.

  As described above, according to the electrical inspection process of the present embodiment, when the temperature of the probe card PRC is reduced by protruding from the wafer chuck WCH, it protrudes before a measurement error due to the temperature decrease occurs. The wafer chuck WCH is moved so that the portion overlaps the wafer chuck WCH. Thereby, shrinkage | contraction of the probe needle 2 resulting from the temperature fall of the probe card PRC can be suppressed. As a result, the occurrence of measurement errors can be suppressed and the reliability of electrical inspection can be improved.

  Further, according to the present embodiment, the movement order for moving the relative positions of the wafer chuck WCH (see FIG. 8) and the probe card PRC (see FIG. 8) is devised as in the inspection order TFa shown in FIG. As a result, the occurrence of measurement errors can be suppressed, and the increase in size of the inspection apparatus can be suppressed.

  In addition, according to the present embodiment, since the cold portion of the probe card PRC is heated while being inspected, the inspection time is greatly reduced as compared with the method in which the probe card PRC is reheated every 10 t of the inspection range. can do. Although there are processes that do not contribute to the electrical inspection, such as the inspection order TF3 and the inspection order TF5 shown in FIG. 22, even in this case, the total inspection time can be shortened.

<Modification>
Although the invention made by the inventors of the present application has been specifically described above based on the embodiments, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

(Modification 1)
For example, the position of the inspection range 10t3 may be a region arranged next to the inspection range 10t1 in the inspection order TF3 as in the inspection order TFb of the modification shown in FIG. FIG. 23 is a plan view showing a modification to FIG. In the inspection order TFb shown in FIG. 23, the positions of the inspection range 10t3 and the inspection range 10t4 included in the inspection region TR3 are opposite to the inspection order TFa shown in FIG. In the case of the inspection order TFb, the inspection range 10t3 that is the inspection start position of the inspection order TF4 is arranged adjacent to the inspection range 10t1 of the inspection region TR2. In the case of the inspection order TFb, since the inspection range 10t3 is arranged adjacent to the inspection range 10t1, in the inspection order TF4, the inspection is sequentially performed in a direction away from the inspection region TR1.

  However, when the inspection range 10t3 that is the inspection start position is arranged adjacent to the inspection range 10t1, the exposed area of the partial PRCf1 shown in FIG. 15 becomes large at the start of the inspection sequence TF4. Therefore, from the viewpoint of reducing the exposed area of the portion PRCf1 and suppressing the temperature drop of the probe card PRC (see FIG. 15), the inspection range 10t3 and the inspection range 10t1 are adjacent to each other as in the inspection order TFa shown in FIG. It is preferred that they do not match. Further, like the inspection order TFa, in the inspection order TF4, it is preferable to perform the inspection in order in the direction approaching the inspection region TR2. The modification shown in FIG. 23 is the same as the inspection order TFa shown in FIG.

(Modification 2)
Further, for example, like the inspection order TFc of the modification shown in FIG. 24, in the inspection order TF3, the inspection range 10t3 adjacent to the boundary between the inspection region TR3 and the inspection region TR5 is adjacent to the boundary between the inspection region TR3 and the inspection region TR4. Alternatively, the inspection may be sequentially performed toward the inspection range 10t4. FIG. 24 is a plan view showing another modification to FIG. In the inspection order TFc shown in FIG. 24, the positions of the inspection region TR3 and the inspection region TR5 included in the semicircle HM2 are opposite to the inspection order TFa shown in FIG. In other words, the inspection region TR3 and the inspection region TR2 are not adjacent to each other.

  In this case, as shown in FIG. 24, the inspection order TF3 and the inspection order TF7 are moved across the centers of the semicircles HM1 and HM2. Therefore, it is particularly preferable from the viewpoint of reducing the exposed area of the portion PRCf1 shown in FIG. 15 and suppressing the temperature drop of the probe card PRC (see FIG. 15). The modification shown in FIG. 24 is the same as the inspection order TFa shown in FIG.

(Modification 3)
Further, for example, as in the inspection sequence TFd of the modification shown in FIG. 25, the inspection range 10t5 located at the end of the inspection region TR4 is provided in a position that does not overlap the semicircle HM1 within the semicircle HM2. May be. FIG. 25 is a plan view showing another modification of FIG. As shown in FIG. 25, when the inspection range 10t5 is provided in the semicircle HM2, the inspection range 10t6 is preferably provided on the semicircle HM1 side and moved toward the semicircle HM1. The modification shown in FIG. 25 is the same as the inspection order TFa shown in FIG.

(Modification 4)
Further, for example, in the above embodiment, the embodiment has been described in which the peripheral portion of the main surface 12a of the wafer WH is divided into four inspection regions TR2, TR3, TR4, and TR5, and inspection is performed. Various modifications can be applied to the number of inspection areas to be divided according to the inspection time required for inspecting one inspection range 10t and the movement time of the relative position. For example, when the number of inspection ranges 10t is small, the peripheral portion of the main surface 12a of the wafer WH can be divided into three inspection regions.

  When the number of inspection ranges 10t increases and the time required for the inspection of the peripheral inspection range 10to increases, the peripheral portion of the main surface 12a of the wafer WH is divided into more than four inspection regions. An inspection may be performed.

(Modification 5)
Furthermore, the modified examples can be applied in combination within a range not departing from the gist of the technical idea described in the above embodiment.

1 Wiring board 1a Upper surface 1b Lower surface 1d Terminal 1w Wiring 2 Probe needle (contact terminal, contactor)
2a wiring connection part 2b bent part 2c contact part (contact part, tip part)
3 Needle presser (contact terminal fixing part)
10 Semiconductor chip (semiconductor device)
10a Chip area 10b Scribe area 10t, 10t1, 10t2, 10t3, 10t4, 10t5, 10t6, 10t7, 10t8, 10ti, 10to Inspection range 11 Pad (electrode, chip electrode, electrode pad)
12 Semiconductor substrate 12a Main surface (device formation surface)
12b Back surface 13 Wiring layer 13a Wiring 13b Insulating film 14 Protective film (passivation film, insulating film)
14a Opening part CHD Card holder HM1, HM2 Semicircle HT Heater IFR Interface ring IFw Wiring PR prober (inspection device)
PRC probe card PRCf, PRCf1 Partial T tester TF1, TF2, TF3, TF4, TF5, TF6, TF7, TF8, TFa, TFb, TFc, TFd, TFH1, TFH2 Inspection sequence THD tester head TR1, TR2, TR3, TR4, TR5 Inspection area WCH Wafer chuck (wafer holder)
WCHa Wafer holding surface WH Wafer (semiconductor wafer)
WST wafer stage

Claims (19)

(A) A main surface including a plurality of chip regions, a semiconductor integrated circuit formed in each of the plurality of chip regions, and formed in each of the plurality of chip regions and electrically connected to the semiconductor integrated circuit. Fixing a semiconductor wafer having a plurality of chip electrodes on a wafer holder;
(B) A wiring board on which a plurality of first wirings are formed, a plurality of contact terminals for contacting the plurality of chip electrodes, a contact terminal arrangement surface holding the plurality of contact terminals, and the contact terminal arrangement surface Arranging the first card having a back surface located on the opposite side of the semiconductor wafer such that the contact terminal arrangement surface faces the main surface of the semiconductor wafer;
(C) conducting the electrical inspection of the semiconductor integrated circuit by bringing tips of the plurality of contact terminals of the first card into contact with the plurality of chip electrodes of the semiconductor wafer while the semiconductor wafer is heated;
Including
In the step (c), the electrical surface of each of the plurality of inspection ranges is moved on the main surface of the semiconductor wafer divided into a plurality of inspection ranges while moving the relative positions of the first card and the semiconductor wafer. Inspections are performed in order,
When the main surface of the semiconductor wafer is partitioned into a first semicircle and a second semicircle that do not overlap each other,
In the step (c),
(C1) From the first inspection region including the center of the main surface, part of the first semicircle, does not overlap with the second semicircle, and includes a peripheral portion of the main surface. A step of sequentially inspecting each of the plurality of inspection ranges while moving the relative position toward the first inspection range located at an end of the second inspection region,
(C2) After the step (c1), from the first inspection range of the second inspection region toward the second inspection range of the second inspection region located on the opposite side of the first inspection range, A step of sequentially inspecting each of the plurality of inspection ranges in the second inspection region while moving the relative position along the outer periphery of the main surface;
(C3) After the step (c2), from the second inspection range, it is a part of the second semicircle, does not overlap the first and second inspection regions, and the main surface Moving the relative position toward a third inspection range of a third inspection region including a peripheral edge;
(C4) After the step (c3), from the third inspection area of the third inspection area toward the fourth inspection area of the third inspection area located on the opposite side of the third inspection area. A step of sequentially inspecting each of the plurality of inspection ranges in the third inspection region while moving the relative position along the outer periphery of the surface;
A method for manufacturing a semiconductor device, comprising: In claim 1,
In the step (c), the heat source for heating the semiconductor wafer is the wafer holder,
In the step (c2), in plan view, the first portion that is a part of the first card does not overlap the wafer holding table,
In the step (c3), the first portion of the first card overlaps the wafer holder in plan view. In claim 2,
In the step (c),
(C5) After the step (c4), the fourth inspection range does not overlap with the first, second, and third inspection regions, and includes a peripheral portion of the main surface. Moving the relative position toward the fifth inspection range of the inspection region;
(C6) After the step (c5), from the fifth inspection area of the fourth inspection area toward the sixth inspection area of the fourth inspection area located on the opposite side of the fifth inspection area. A step of sequentially inspecting each of the plurality of inspection ranges in the fourth inspection region while moving the relative position along the outer periphery of the surface;
A method for manufacturing a semiconductor device, comprising: In claim 3,
In the step (c),
(C7) After the step (c6), from the sixth inspection range, the first, second, third, and fourth inspection regions do not overlap and include the peripheral portion of the main surface. Moving the relative position toward the seventh inspection range of the fifth inspection region,
(C8) After the step (c7), from the seventh inspection range of the fifth inspection region toward the eighth inspection range of the fifth inspection region located on the opposite side of the seventh inspection range. A step of sequentially inspecting each of the plurality of inspection ranges in the fifth inspection region while moving the relative position along the outer periphery of the surface;
A method for manufacturing a semiconductor device, comprising: In claim 1,
The method for manufacturing a semiconductor device, wherein the third inspection range and the first inspection range are not adjacent to each other. In claim 1,
The method of manufacturing a semiconductor device, wherein the third inspection region and the second inspection region are not adjacent to each other. In claim 1,
In the step (c2), the inspection of the inspection range included in the second inspection area is completed within 2 hours,
In the step (c4), the method of manufacturing a semiconductor device, wherein the inspection of the inspection range included in the third inspection region is completed within 2 hours. In claim 1,
In the step (c3), the relative position of each of the plurality of contact terminals of the first card is moved so as to straddle the first inspection range. In claim 1,
In the step (c3), the uninspected inspection range between the second inspection range and the third inspection range is sequentially inspected while moving from the second inspection range toward the third inspection range. A method for manufacturing a semiconductor device. In claim 1,
In the step (c), the relative position is moved by driving the wafer holding table. (A) A semiconductor wafer having a main surface including a plurality of chip regions is prepared and electrically connected to the semiconductor integrated circuit and the semiconductor integrated circuit on each main surface of the plurality of chip regions. Forming a plurality of chip electrodes;
(B) A wiring board on which a plurality of first wirings are formed, a plurality of contact terminals for contacting the plurality of chip electrodes, a contact terminal arrangement surface holding the plurality of contact terminals, and the contact terminal arrangement surface Preparing a first card having a back surface located on the opposite side of
(C) conducting the electrical inspection of the semiconductor integrated circuit by bringing tips of the plurality of contact terminals of the first card into contact with the plurality of chip electrodes of the semiconductor wafer while the semiconductor wafer is heated;
Including
In the step (c), the electrical surface of each of the plurality of inspection ranges is moved on the main surface of the semiconductor wafer divided into a plurality of inspection ranges while moving the relative positions of the first card and the semiconductor wafer. Inspections are performed in order,
When the main surface of the semiconductor wafer is partitioned into a first semicircle and a second semicircle that do not overlap each other,
In the step (c),
(C1) From the first inspection region including the center of the main surface, part of the first semicircle, does not overlap with the second semicircle, and includes a peripheral portion of the main surface. A step of sequentially inspecting each of the plurality of inspection ranges while moving the relative position toward the first inspection range located at an end of the second inspection region,
(C2) After the step (c1), from the first inspection range of the second inspection region toward the second inspection range of the second inspection region located on the opposite side of the first inspection range, A step of sequentially inspecting each of the plurality of inspection ranges in the second inspection region while moving the relative position along the outer periphery of the main surface;
(C3) After the step (c2), from the second inspection range, it is a part of the second semicircle, does not overlap the first and second inspection regions, and the main surface Moving the relative position toward a third inspection range of a third inspection region including a peripheral edge;
(C4) After the step (c3), from the third inspection area of the third inspection area toward the fourth inspection area of the third inspection area located on the opposite side of the third inspection area. A step of sequentially inspecting each of the plurality of inspection ranges in the third inspection region while moving the relative position along the outer periphery of the surface;
A method for manufacturing a semiconductor device, comprising: In claim 11,
In the step (c), the heat source for heating the semiconductor wafer is a wafer holder on which the semiconductor wafer is fixed,
In the step (c2), in plan view, the first portion that is a part of the first card does not overlap the wafer holding table,
In the step (c3), the first portion of the first card overlaps the wafer holder in plan view. In claim 12,
In the step (c),
(C5) After the step (c4), the fourth inspection range does not overlap with the first, second, and third inspection regions, and includes a peripheral portion of the main surface. Moving the relative position toward the fifth inspection range of the inspection region;
(C6) After the step (c5), from the fifth inspection area of the fourth inspection area toward the sixth inspection area of the fourth inspection area located on the opposite side of the fifth inspection area. A step of sequentially inspecting each of the plurality of inspection ranges in the fourth inspection region while moving the relative position along the outer periphery of the surface;
A method for manufacturing a semiconductor device, comprising: In claim 13,
In the step (c),
(C7) After the step (c6), from the sixth inspection range, the first, second, third, and fourth inspection regions do not overlap and include the peripheral portion of the main surface. Moving the relative position toward the seventh inspection range of the fifth inspection region,
(C8) After the step (c7), from the seventh inspection range of the fifth inspection region toward the eighth inspection range of the fifth inspection region located on the opposite side of the seventh inspection range. A step of sequentially inspecting each of the plurality of inspection ranges in the fifth inspection region while moving the relative position along the outer periphery of the surface;
A method for manufacturing a semiconductor device, comprising: In claim 11,
The method for manufacturing a semiconductor device, wherein the third inspection range and the first inspection range are not adjacent to each other. In claim 11,
The method of manufacturing a semiconductor device, wherein the third inspection region and the second inspection region are not adjacent to each other. In claim 11,
In the step (c2), the inspection of the inspection range included in the second inspection area is completed within 2 hours,
In the step (c4), the method of manufacturing a semiconductor device, wherein the inspection of the inspection range included in the third inspection region is completed within 2 hours. In claim 11,
In the step (c3), the relative position of each of the plurality of contact terminals of the first card is moved so as to straddle the first inspection range. In claim 11,
In the step (c3), the uninspected inspection range between the second inspection range and the third inspection range is sequentially inspected while moving from the second inspection range toward the third inspection range. A method for manufacturing a semiconductor device.

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