JP2014187416A - Differential amplifier and data output circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a differential amplifier and a data output circuit that reduce current consumption by suppressing a tail current.SOLUTION: A first transistor N103 is connected between a first constant current source CI1 and a first current mirror type differential amplifier CDA1 and is supplied with a first input signal at a gate electrode. A second transistor P103 is connected between a second current mirror type differential amplifier and a second constant current source CI2 and is supplied with the first input signal at a gate electrode.

Description

  Embodiments described herein relate generally to a current mirror type differential amplifier and a data output circuit applied to a semiconductor device.

  A current mirror type differential amplifier applied to a semiconductor device is a differential pair even when an output signal is determined from a transition state of signals supplied to gate electrodes of two transistors constituting the differential pair. A tail current always flows through the connected constant current source. For this reason, the current mirror type differential amplifier has a problem that current consumption is large.

JP 2007-184688 A JP-A-11-150427

  The present embodiment provides a differential amplifier and a data output circuit capable of suppressing tail current and reducing current consumption.

  The differential amplifier according to this embodiment includes a first conductivity type first current to which an inverted signal of a first input signal and an inverted signal of a second input signal complementary to the first input signal are supplied. A mirror type differential amplifier, a first constant current source, and the first constant current source and the first current mirror type differential amplifier are connected between the first input signal and the gate electrode. The supplied first transistor of the second conductivity type, the inverted signal of the first input signal, and the inverted signal of the second input signal are supplied, and the output terminal is the first current mirror type differential. Second conductivity type second current mirror type differential amplifier connected to output terminal of amplifier, second constant current source, second constant current source and second current mirror type differential amplifier Connected to the gate electrode, and the first input signal is supplied to the gate electrode. Characterized by comprising the transistor, the.

1 is a circuit diagram showing a differential amplifier according to a first embodiment. FIG. 2 is a timing chart showing the operation of FIG. 1. The circuit diagram which shows the differential amplifier which concerns on 2nd Embodiment. The circuit diagram which concerns on 3rd Embodiment and shows the modification of 2nd Embodiment. The circuit diagram which shows the example of the data output circuit to which 3rd Embodiment is applied.

  Hereinafter, embodiments will be described with reference to the drawings.

(First embodiment)
FIG. 1 shows a differential amplifier according to the first embodiment. This differential amplifier is a differential amplifier in which a through current is suppressed.

  In FIG. 1, the differential amplifier 13 includes first and second differential amplifiers CDA1 and CDA2 of current mirror type. For example, PMOS transistors P101 to P105, NMOS transistors N101 to N105, inverter circuits I101 and I103, , Constant current sources CI1 and CI2.

  In the first differential amplifier CDA1, one end of the current path of the PMOS transistors P101 and P102 constituting the current mirror circuit is connected to a node to which the power supply VDD is supplied. The gate electrodes of the PMOS transistors P101 and P102 are connected to the other end of the current path of the PMOS transistor P101. The other ends of the flow paths of the PMOS transistors P101 and P102 are connected to one ends of the current paths of the NMOS transistors N101 and N102, respectively. The other ends of the current paths of the NMOS transistors N101 and N102 are grounded via the NMOS transistor N103 and the constant current source CI1.

  The first input signal (eg, clock signal REOLATe) is supplied to the gate electrode (inverting input terminal BIN) of the NMOS transistor N101 via the inverter circuit I101, and the second input signal (eg, clock signal REOLATo) is supplied from the inverter circuit. The voltage is supplied to the gate electrode (input terminal IN) of the NMOS transistor N102 via I103.

  Further, the first input signal is supplied to the gate electrode of the NMOS transistor N103.

  On the other hand, in the second differential amplifier CDA2, one end of the constant current source CI2 is connected to the supply node of the power supply VDD, and the other end is connected to one end of the current path of the PMOS transistor P102. The other end of the current path of the PMOS transistor P102 is connected to one end of the current path of the PMOS transistors P104 and P105. The other ends of the current paths of the PMOS transistors P104 and P105 are connected to one end of the current paths of the NMOS transistors N104 and N105 constituting the current mirror circuit. The gate electrodes of the current paths of the NMOS transistors N104 and N105 are connected to one end of the current path of the NMOS transistor N104. The other ends of the current paths of the NMOS transistors N104 and N105 are grounded.

  A first input signal (eg, clock signal REOLATe) is supplied to the gate electrode of the PMOS transistor P103.

  The gate electrode of the PMOS transistor P104 is connected to the inverting input terminal BIN, and the gate electrode of the PMOS transistor P105 is connected to the input terminal IN.

  A connection node between the PMPS transistor P102 and the NMOS transistor N102 and a connection node between the PMPS transistor P105 and the NMOS transistor N105 are connected to the output terminal OUT.

  In the differential amplifier 13 having the above-described configuration, the first and second differential amplifiers CDA1 and CDA2 have the first and second input signals REOLATe and REOLATo transition from high level to low level and from low level to high level. It sometimes stops and stops in the state where the transition of the first and second input signals REOLATe and REOLATo is completed.

  As shown in FIG. 2A, at the time t1, for example, when the first input signal REOLATe changes from high level to low level and the second input signal REOLATo changes from low level to high level, the first differential amplifier CDA1. Since the NMOS transistor N103 is turned off, the first constant current source CI1 is stopped, and the PMOS transistor P103 of the second differential amplifier CDA2 is turned on, so that the second constant current source CI2 is in the operating state. Become. The PMOS transistor P105 is turned on, and the output terminal OUT is at a high level. At this time, since the inverting input BIN is at a high level, the PMOS transistor P104 is in an off state, and the connection node between the PMOS transistor P104 and the NMOS transistor N104 connected to the gate electrodes of the NMOS transistors N104 and N105 is connected to the NMOS transistor N104. It is held at a potential equal to the threshold voltage. As a result, the NMOS transistors N104 and N105 are turned off, and the second differential amplifier CDA2 is also prevented from passing through.

  On the other hand, at time t2, for example, when the first input signal REOLATe changes from low level to high level and the second input signal REOLATo changes from high level to low level, the NMOS transistor N103 of the first differential amplifier CDA1 is turned on. Therefore, the first constant current source CI1 is in an operating state, and the PMOS transistor P103 of the second differential amplifier CDA2 is turned off, so that the second constant current source CI2 is in a stopped state. At this time, since the inverting input terminal BIN is at a low level and the non-inverting input terminal IN is at a high level, the NMPS transistor N101 is turned off, the N102 is turned on, and the PMOS transistor P105 is turned on. Becomes a low-level bell. At this time, since the inverting input BIN is at a low level, the NMOS transistor N101 is in an off state, and the connection node between the PMOS transistor P101 and the NMOS transistor N101 connected to the gate electrodes of the PMOS transistors P101 and P102 is connected to the PMOS from the power supply VDD. The potential is kept lower by the threshold voltage of the transistor P101. Therefore, the PMOS transistors P101 and P102 are turned off, and the through current of the first differential amplifier CDA1 can be prevented.

  In addition, as shown in FIG. 2B, even when the rise time and fall time of the first and second input signals REOLATe and REOLATo are different, the first and second input signals REOLATe and REOLATo When the levels match, the output potential of the first differential amplifier CDA1 or the second differential amplifier CDA2 is determined.

  For this reason, the first and second differential amplifiers CDA1 and CDA2 have a potential difference between the first and second input signals REOLATe and REOLATo at the transition of the first and second input signals REOLATe and REOLATo. Sometimes a through current flows and is blocked in a steady state (high impedance state).

  According to the first embodiment, the first and second differential amplifiers CDA1 and CDA2 include the NMOS transistor N103 and the PMOS transistor P103 connected in series to the first and second constant current sources CI1 and CI2. The NMOS transistor N103 and the PMOS transistor P103 are controlled by the first input signal REOLATe. Therefore, the first and second constant current sources CI1 and CI2 operate simultaneously when the first input signal REOLATE transitions from the low level to the high level, or from the high level to the low level, and the first input signal When REOLATe becomes high level or low level, one of the first and second constant current sources CI1 and CI2 is stopped. The other of the first and second constant current sources CI1 and CI2 is operable, but the NMOS transistors N101 and N102 or the PMOS transistors P104 and P105 that constitute the differential pair are turned off. The tail current does not flow to the other of the first and second constant current sources CI1 and CI2. Therefore, the differential amplifier 13 consumes current when the first input signal REOLATe transitions from low level to high level, or from high level to low level, and can reduce current consumption in a steady state.

(Second Embodiment)
FIG. 3 shows a second embodiment. In the second embodiment, the same parts as those in the first embodiment are denoted by the same reference numerals, and different parts will be described.

  In FIG. 3, an NMOS transistor N106 is connected in parallel to the NMOS transistor N103, and a PMOS transistor P106 is connected in parallel to the PMOS transistor P103. An inverter circuit I102 is connected to the output terminal OUT, and an output signal of the inverter circuit I102 is supplied to the gate electrode of the NMOS transistor N106 and the gate electrode of the PMOS transistor P106.

  According to the second embodiment, by feeding back the output signal to the NMOS transistor N106 and the PMOS transistor P106, when the first input signal REOLATE transitions from the low level to the high level, the NMOS transistors N103 and N106 The current driving capability of the first constant current source CI1 can be increased. For this reason, it is possible to improve the balance when the output signal transitions from the low level to the high level or from the high level to the low level.

  Further, when the first input signal REOLATe transitions from a high level to a low level, the current driving capability of the second constant current source CI2 can be increased by the PMOS transistors P103 and P106. For this reason, it is possible to improve the balance when the output signal transitions from the high level to the low level or from the low level to the high level.

  Therefore, it is possible to improve the speed balance when the output signal transitions from the high level to the low level, or when the output signal transitions from the low level to the high level.

(Third embodiment)
FIG. 4 shows a third embodiment. The third embodiment is a modification of the second embodiment. The differential amplifier shown in the second embodiment has a variable current drive capability and is applied to a control circuit in front of an OCD (Off chip Driver) circuit. An example is shown. In FIG. 4, the same parts as those of the second embodiment are denoted by the same reference numerals, and only different parts will be described.

  The control circuit shown in FIG. 4 includes current mirror type first to fourth differential amplifiers CDA1 to CDA4. Since the third and fourth differential amplifiers CDA3 and CDA4 are the same as the first and second differential amplifiers CDA1 and CDA2 except for the control signal, the first and second differential amplifiers CDA1 and CDA2 are The configuration will be described, and only differences between the third and fourth differential amplifiers CDA3 and CDA4 from the first and second differential amplifiers CDA1 and CDA2 will be described.

  The third embodiment is different from the second embodiment in that each of the first and second current mirror type differential amplifiers CDA1 and CDA2 has three constant current sources, and two of these constant currents. The source is selectable by a switch.

  That is, in the first differential amplifier CDA1, between the NMOS transistors N103 and N106 and the ground, the NMOS transistor N111, the constant current source CI11, the series circuit of the NMOS transistor N112 and the constant current source CI12, the NMOS transistor N113, A series circuit of a constant current source CI13 is connected.

  A control signal ByPn is supplied to the gate electrode of the NMOS transistor N111, a control signal SWPn1 is supplied to the gate electrode of the NMOS transistor N112, and a control signal SWPn2 is supplied to the gate electrode of the NMOS transistor N113.

  In the second differential amplifier CDA2, a series circuit of a PMOS transistor P111, a constant current source CI21, a constant current source CI22, and a PMOS transistor P112 is provided between the supply node of the power supply VDD and the PMOS transistors P103 and P105. The constant current source CI23 and the series circuit of the PMOS transistor P113 are connected.

  A control signal ByPp is supplied to the gate electrode of the PMOS transistor P111, a control signal SWPp1 is supplied to the gate electrode of the PMOS transistor P112, and a control signal SWPp2 is supplied to the gate electrode of the PMOS transistor P113.

  The third and fourth differential amplifiers CDA3 and CDA4 are different in control signal from the first and second differential amplifiers CDA1 and CDA2.

  That is, in the third differential amplifier CDA3, the control signal ByNn is supplied to the gate electrode of the NMOS transistor N111, the control signal SWNn1 is supplied to the gate electrode of the NMOS transistor N112, and the control electrode is supplied to the gate electrode of the NMOS transistor N113. Signal SWNn2 is supplied.

  In the fourth differential amplifier CDA4, the control signal ByNp is supplied to the gate electrode of the PMOS transistor P111, the control signal SWNp1 is supplied to the gate electrode of the PMOS transistor P112, and the gate electrode of the PMOS transistor P113 is supplied. Is supplied with a control signal SWNp2.

  The first input signal B and the second input signal A are complementary signals, for example, and the first input signal B is supplied to the first to fourth differential amplifiers CDA1 to CDA4 via the inverter circuit I113. Is done. The second input signal A is supplied to the first to fourth differential amplifiers CDA1 to CDA4 via the inverter circuits I111 and I112. Between the inverter circuit I111 and the inverter circuit I112, the gate electrodes of the NMOS transistor N115 and the PMOS transistor P115 constituting the MOS capacitor are connected. This MOS capacitor delays the second input signal A by the same time as the delay time of the first input signal B.

  Further, the output signals of the first and second differential amplifiers CDA1 and CDA2 are supplied to the PMOS drive transistor (not shown) via the inverter circuit I114, and the output signals of the third and fourth differential amplifiers CDA3 and CDA4. Is supplied to an NMOS drive transistor (not shown) via an inverter circuit I114.

(Function)
In the above configuration, in the first to fourth differential amplifiers CDA1 to CDA4, in operation, the NMOS transistors N111 and N111 and the PMOS transistors P111 and P111 are set to the off state by the control signals ByPn, ByPp, ByNn, and ByNp. . For this reason, the constant current circuits CI11, CI11, CI21, CI21 are operated.

  In this state, the output signals OUT_P and OUT_N output an inverted signal of the input signal A.

  For example, when the control signals SWPn1, SWPn2, SWPp1, SWPp2, SWNn1, SWNn2, SWNp1, and SWNp2 are controlled by a command, the current driving capabilities of the first to fourth differential amplifiers CDA1 to CDA4 are adjusted. Therefore, the rise time, fall time, and high impedance period of the output signals OUT_P and OUT_N can be adjusted, and the duty ratio of the output signals OUT_P and OUT_N can be adjusted.

  According to the third embodiment, similarly to the first and second embodiments, in the steady state of the input signal, it is possible to cut off the tail current and reduce the current consumption.

  In addition, according to the third embodiment, the control signals SWPn1, SWPn2, SWPp1, SWPp2, SWNn1, SWNn2, SWNp1, and SWNp2 are used to control the number of drives of the constant current sources CI11 to CI13 and CI21 to CI23. The total current drive capability of the fourth differential amplifiers CDA1 to CDA4 can be adjusted. Therefore, the rise time, fall time, and high impedance period of the output signals OUT_P and OUT_N can be adjusted, and the duty ratio of the output signals OUT_P and OUT_N can be adjusted.

  Furthermore, according to the third embodiment, since the duty ratio can be set to 50% (approaching), a sufficient effective data time for latching data can be secured. Therefore, when the third embodiment is applied to, for example, a DDR (Double Data Rate) data output circuit, it is possible to perform a reliable operation at high speed.

(Example of data output circuit)
FIG. 5 shows an example of a DDR data output circuit.

  This data output circuit includes first and second differential amplifiers 11 and 12, third and fourth differential amplifiers 13 and 14, a level converter 15, a multiplexer 16, and a fifth differential amplifier 17.

  For the third and fourth differential amplifiers 13 and 14, for example, the current mirror type differential amplifier shown in the first or second embodiment is used, and for the fifth differential amplifier 17, the third embodiment is used. The OCD circuit shown in FIG.

  The third and fourth differential amplifiers 13 and 14 receive clock signals REOLATe and REOLATo as complementary signals. The clock signals REOLATe and REOLATo are signals of a first voltage, for example, VDD level.

  The third differential amplifier 13 generates a clock signal from the clock signals REOLATe and REOLATo. This clock signal is supplied to the first differential amplifier 11 through the inverter circuits 21, 22 and 23 as a clock signal clked at the VDD level.

  The fourth differential amplifier 14 generates a clock signal from the clock signals REOLATe and REOLATo. This clock signal is supplied to the second differential amplifier 12 via the inverter circuits 24, 25, and 26 as a VDD level clock signal clkod.

  The clock signal clked and the clock signal clkod are complementary signals.

(Level converter)
Output terminals of the inverter circuits 21 and 24 are connected to a level converter (LS) 15. The level converter 15 converts the VDD level clock signal into a second voltage higher than VDD, for example, a VCCQ level clock signal.

  The level converter 15 includes a plurality of P channel MOS transistors (hereinafter referred to as PMOS transistors) P1 to P6 and a plurality of N channel MOS transistors (hereinafter referred to as NMOS transistors) N1 and N2.

  The clock signal clkeq and the clock signal clkoq as output signals of the level converter 15 are complementary signals.

(First differential amplifier)
The first differential amplifier 11 includes PMOS transistors P11 to P21 and NMOS transistors N11 to N15. The PMOS transistors P11 to P21 constitute a precharge circuit for the output terminals OUTe and BOUTe.

  In the first differential amplifier 11, the clock signal clkeq is supplied to the gate electrodes of the PMOS transistors P14, P17, and P20. The clock signal clked is supplied to the gate electrode of the NMOS transistor N15. Data DTe is supplied to the gate electrode of NMOS transistor N12, and data BDTe is supplied to the gate electrode of NMOS transistor N14.

(Second differential amplifier)
Since the second differential amplifier 12 has the same configuration as the first differential amplifier 11, the same reference numerals are given to the same parts.

  In the second differential amplifier 12, the clock signal clkoq is supplied to the gate electrodes of the PMOS transistors P14, P17, and P20. The clock signal clkod is supplied to the gate electrode of the NMOS transistor N15. Data DTo is supplied to the gate electrode of NMOS transistor N14, and data BDTo is supplied to the gate electrode of NMOS transistor N12.

(Multiplexer)
The multiplexer 16 includes PMOS transistors P41 to P46, NMOS transistors N41 to N46, inverter circuits I11 to I14, and a latch circuit LT.

  The PMOS transistor P41 and the NMOS transistor N46 are controlled by the clock signal clkod, and the PMOS transistor P44 and the NMOS transistor N43 are controlled by the clock signal clked.

  The PMOS transistors P42 and P43 and the NMOS transistors N41 and N42 are controlled by the output signals of the output terminals OUTe and BOUTe of the first differential amplifier 11, and the PMOS transistors P46 and P45 and the NMOS transistors N45 and N44 have the second difference. It is controlled by output signals from the output terminals OUTo and BOUTo of the dynamic amplifier 12.

  The latch circuit LT is connected to the first and second output terminals A and B of the multiplexer 16. The first and second output terminals A and B of the multiplexer 16 are connected to a pair of input terminals of the differential amplifier 17. The output terminal of the differential amplifier 17 is connected to a PMOS drive transistor and an NMOS drive transistor (not shown).

  The first differential amplifier 11 stops charging the output terminals OUTe and BOUTe at the rising edge of the clock signal clkeq, receives the even-numbered complementary data DTe and BDTe at the rising edge of the clock signal clked, and receives the second differential amplifier. 12 stops charging of the output terminals OUTo and BOUTo at the rise of the clock signal clkoq, and receives odd-numbered complementary data DTo and BDTo at the rise of the clock signal clkod.

  In this way, the first and second differential amplifiers 11 and 12 receive the even-numbered and odd-numbered complementary data at the rising edges of the clock signals clked and clkod, respectively, thereby suppressing the phase difference between the complementary data. The phase difference between even-numbered data and odd-numbered data can also be suppressed.

  In addition, the data output circuit shown in FIG. 5 uses the differential amplifiers of the first and second embodiments as the differential amplifiers 13 and 14 and uses the OCD circuit of the third embodiment as the differential amplifier 17. Therefore, the effects of the first to third embodiments can be obtained.

  In the first and second embodiments, the current driving capability of the first and second constant current sources CI1 and CI2 can be adjusted by a control signal as in the third embodiment. is there.

  In addition, the present invention is not limited to the above-described embodiments as they are, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. Moreover, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the above embodiments. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

  11 ... Differential amplifier, CDA1, CDA2, CDA3, CDA4 ... Current mirror type first to fourth differential amplifiers, N101, N102, N103, N106 ... NMOS transistors, P101, P102, P103, P106 ... PMOS transistors, CI1, CI2, CI11 to CI13, CI21 to CI23... Constant current source, REOLATe, REOLATo... First and second input signals.

Claims (7)

A first current mirror circuit comprising a first conductivity type transistor;
First and second transistors of a second conductivity type connected to the first current mirror circuit and constituting a differential pair;
A second transistor of the second conductivity type connected to the first and second transistors;
A first constant current source connected to the third transistor;
An output terminal connected to a connection node of the first current mirror circuit and the second transistor;
An inverted first input signal is supplied to the gate electrode of the first transistor, and a second input signal as an inverted signal of the first input signal is supplied to the gate electrode of the second transistor, A first differential amplifier in which the first input signal is supplied to a gate electrode of the third transistor;
Fourth and fifth transistors of the first conductivity type constituting a differential pair;
A second current mirror circuit connected to the fourth and fifth transistors and comprising a second conductivity type transistor;
A second constant current source;
A sixth transistor of a first conductivity type connected between the second constant current source and the fourth and fifth transistors;
Have
The inverted first input signal is supplied to the gate electrode of the fourth transistor, and the inverted second input signal is supplied to the gate electrode of the fifth transistor,
The first input signal is supplied to a gate electrode of the sixth transistor;
A second differential amplifier in which a connection node of the fifth transistor and the second current mirror circuit is connected to the output terminal;
A differential amplifier comprising: A first conductivity type first current mirror type differential amplifier to which an inverted signal of the first input signal and an inverted signal of the second input signal complementary to the first input signal are supplied;
A first constant current source;
A first transistor of a second conductivity type connected between the first constant current source and the first current mirror type differential amplifier and having the gate electrode supplied with the first input signal;
An inverted signal of the first input signal and an inverted signal of the second input signal are supplied, and an output terminal is connected to an output terminal of the first current mirror type differential amplifier. Two current mirror type differential amplifiers;
A second constant current source;
A second transistor of a first conductivity type connected between the second constant current source and the second current mirror type differential amplifier, wherein the first input signal is supplied to a gate electrode;
A differential amplifier comprising: A third transistor of a second conductivity type connected in parallel to the first transistor and supplied by inverting the output signal of the output terminal to the gate electrode;
A fourth transistor of the first conductivity type connected in parallel to the second transistor and supplied by inverting the output signal of the output terminal to the gate electrode;
The differential amplifier according to claim 2, further comprising:   4. The differential amplifier according to claim 1, wherein the first and second constant current sources have current driving capabilities adjusted by a control signal. 5. A first input signal and a second input signal complementary to the first input signal are supplied, and first and second differential amplifiers are provided to output inverted signals of the second input signal, respectively. A differential amplifier,
The first differential amplifier includes:
A first conductivity type first current mirror type differential amplifier which is supplied with the first and second input signals and has a first output end;
A first transistor of a second conductivity type connected to the first current mirror type differential amplifier and supplied with the first input signal inverted to a gate electrode;
A plurality of first constant current sources;
A plurality of second transistors of a second conductivity type connected between the first transistor and the plurality of first constant current sources and selected by a first control signal;
A plurality of second constant current sources;
A second current mirror type differential amplifier of a second conductivity type, supplied with the first and second input signals and having an output terminal connected to the first output terminal;
A third transistor of a first conductivity type connected to the second current mirror type differential amplifier and supplied with the inverted first input signal to the gate electrode;
A plurality of fourth transistors of a first conductivity type connected between the third transistor and the plurality of second constant current sources, and selected by a second control signal;
Comprising
The second differential amplifier is:
A first conductivity type third current mirror type differential amplifier which is supplied with the first and second input signals and has a second output end;
A fifth transistor of a second conductivity type connected to the third current mirror type differential amplifier and supplied with the inverted first input signal to the gate electrode;
A plurality of third constant current sources;
A plurality of sixth transistors of a second conductivity type connected between the fifth transistor and the plurality of third constant current sources, and selected by a third control signal;
A plurality of fourth constant current sources;
A fourth conductivity mirror type differential amplifier of a second conductivity type supplied with the first and second input signals and having an output terminal connected to the second output terminal;
A seventh transistor of a first conductivity type connected to the fourth current mirror type differential amplifier and supplied with the first input signal inverted to the gate electrode;
A plurality of eighth transistors of a first conductivity type connected between the seventh transistor and the plurality of fourth constant current sources and selected by a fourth control signal;
A differential amplifier comprising: A first differential amplifier that receives complementary first and second clock signals and outputs a third clock signal;
A second differential amplifier that receives the first and second clock signals and outputs a fourth clock signal complementary to the third clock signal;
Based on the third clock signal, first and second data receiving complementary at the first level, and outputting third and fourth complementary data at a second level different from the first level. 3 differential amplifiers;
A fourth differential amplifier for receiving complementary fifth and sixth data at a first level and outputting complementary seventh and eighth data at the second level based on the fourth clock signal; ,
A selection circuit that alternately selects the third and fourth data output from the third differential amplifier and the seventh and eighth data output from the fourth differential amplifier;
A fifth differential amplifier connected to the selection circuit;
The data output circuit according to claim 2, wherein the first and second differential amplifiers are the differential amplifiers according to claim 2. A first differential amplifier that receives complementary first and second clock signals and outputs a third clock signal;
A second differential amplifier that receives the first and second clock signals and outputs a fourth clock signal complementary to the third clock signal;
Based on the third clock signal, the first level and the second level of complementary data are received, and the third level and the fourth level of the second level higher than the first level are output. Differential amplifier,
A fourth differential amplifier for receiving complementary fifth and sixth data at a first level and outputting complementary seventh and eighth data at the second level based on the fourth clock signal; ,
A selection circuit that alternately selects the third and fourth data output from the third differential amplifier and the seventh and eighth data output from the fourth differential amplifier;
A fifth differential amplifier connected to the selection circuit;
The data output circuit according to claim 5, wherein the fifth differential amplifier is a differential amplifier according to claim 5.

Images