JP2014183287A - Pattern formation method on wafer, mask, exposure method and exposure device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the number of semiconductor elements per one wafer.SOLUTION: A pattern formation method on a wafer comprises: exposing a plurality of semiconductor chip patterns on a wafer by using a mask on which a semiconductor chip pattern and an exposure accuracy measurement pattern are formed and a reduction projection aligner and exposing the exposure accuracy measurement pattern only on a region of the wafer, outside a region of the wafer, where the semiconductor chip patterns are exposed; forming a first layer including the plurality of semiconductor chip patterns and the exposure accuracy measurement pattern by performing processing based on the exposed patterns in the exposure process; and similarly performing exposure by using the mask and the reduction projection aligner and forming a second layer based on the exposed pattern in the exposure process.

Description

  The present invention relates to a pattern forming method, a mask, an exposure method, and an exposure apparatus on a wafer.

  When a semiconductor chip pattern is formed on a wafer, the semiconductor chip pattern formed on a mask (also called a reticle) is exposed on the wafer (more specifically, on a photosensitive resist applied to the wafer) and exposed. Based on the formed pattern, processing such as development, etching, and resist removal is performed. The exposure of the semiconductor chip pattern onto the wafer is performed, for example, by repeating the reduction and baking of the semiconductor chip pattern formed on the mask while moving the wafer relative to the mask. Conventionally, an exposure accuracy measurement pattern is exposed and formed around each semiconductor chip pattern exposed and formed on a wafer, and exposure accuracy (single layer position accuracy and multiple A technique is known in which the overlay accuracy between layers) is measured and exposure conditions are corrected based on the measurement results (see, for example, Patent Documents 1 and 2).

JP 2002-134397 A JP 11-317340 A

  In the above conventional technique, since an exposure accuracy measurement pattern is exposed and formed around each semiconductor chip pattern, the area that can be used for exposure and formation of the semiconductor chip pattern on the wafer is reduced, and one wafer is obtained. There was a problem that the number of semiconductor elements per unit was reduced.

  The present invention has been made to solve the above-described problems, and can be realized as the following forms.

(1) According to one aspect of the present invention, a method for forming a pattern on a wafer is provided. In this method, at least one mask on which a semiconductor chip pattern and an exposure accuracy measurement pattern capable of measuring the positional accuracy of a single layer formed on the wafer and the overlay accuracy between a plurality of layers are formed. A plurality of semiconductor chip patterns are exposed on the wafer using a single mask and a reduced projection type exposure apparatus, and a region of the semiconductor chip pattern on the wafer to be exposed is exposed. By performing processing based on the pattern exposed on the wafer in the exposure process for the first layer that exposes the exposure accuracy measurement pattern only in the outer region, and the exposure process for the first layer, Forming the first layer including a plurality of the semiconductor chip patterns and the exposure accuracy measurement pattern on the wafer; A plurality of the semiconductor chip patterns are exposed on the wafer by using one mask and a reduction projection type exposure apparatus, and only in an area outside the area where the semiconductor chip patterns are exposed on the wafer. An exposure process for the second layer that exposes the pattern for measuring the exposure accuracy, and a process based on the pattern exposed on the wafer in the exposure process for the second layer, thereby performing a plurality of processes on the wafer. Forming the second layer including the semiconductor chip pattern and the exposure accuracy measurement pattern. According to the method of this aspect, with respect to the first layer and the second layer, the exposure accuracy measurement pattern is exposed and formed only in the region outside the region where the semiconductor chip pattern is exposed and formed on the wafer. Compared to the case where an exposure accuracy measurement pattern is exposed and formed in a region sandwiched between regions where each semiconductor chip pattern is exposed and formed, the semiconductor chip pattern on the wafer is exposed and formed. The usable area can be widened, and the number of semiconductor elements per wafer can be increased while improving the exposure accuracy by feedback of the exposure accuracy measurement result.

(2) In the method of the above aspect, the exposure process for the first layer and the exposure process for the second layer are performed without performing unloading of the mask and the wafer, respectively. It may be a step of exposing the chip pattern and the exposure accuracy measurement pattern. According to the method of this embodiment, since the semiconductor chip pattern and the exposure accuracy measurement pattern are continuously exposed without sandwiching the unloading of the mask or wafer, the position accuracy of the exposure accuracy measurement pattern with respect to the semiconductor chip pattern is increased. Even if the exposure accuracy measurement pattern is exposed only to the area outside the area where the semiconductor chip pattern is exposed on the wafer, a single layer can be formed using the formed exposure accuracy measurement pattern. Position accuracy can be measured with high accuracy.

(3) In the method of the above aspect, the exposure process for the first layer and the exposure process for the second layer each include a position of each vertex of a rectangle having at least the center of the wafer as an intersection of diagonal lines It may be a step of exposing the exposure accuracy measurement pattern. According to the method of this embodiment, it is possible to accurately measure the position accuracy of a single layer and the overlay accuracy between a plurality of layers using the formed exposure accuracy measurement pattern.

(4) In the method of the above aspect, the exposure accuracy measurement pattern may be at least one of a cross-shaped pattern and a rectangular pattern. According to the method of this aspect, the exposure accuracy measurement pattern can measure the position accuracy of a single layer and the overlay accuracy between a plurality of layers.

(5) In the method of the above aspect, each of the exposure process for the first layer and the exposure process for the second layer has a reduction projection exposure magnification of 1/2. The shortest distance between the center of the exposure accuracy measurement pattern formed on the mask and the outer edge of the semiconductor chip pattern may be 2.125 mm or more. According to this method, the exposure accuracy measurement pattern can be accurately exposed with a shot different from the shot for exposing the semiconductor chip pattern.

(6) In the method of the above aspect, each of the exposure process for the first layer and the exposure process for the second layer is a reduction projection exposure magnification of 1/4 as the reduction projection exposure apparatus. The shortest distance between the center of the exposure accuracy measurement pattern formed on the mask and executed by using a certain stepper and the outer edge of the semiconductor chip pattern may be 1.58 mm or more. According to this method, the exposure accuracy measurement pattern can be accurately exposed with a shot different from the shot for exposing the semiconductor chip pattern.

(7) In the method of the above aspect, each of the exposure process for the first layer and the exposure process for the second layer is a reduction projection exposure magnification of 1/5 as the reduction projection exposure apparatus. The shortest distance between the center of the exposure accuracy measurement pattern formed on the mask and executed by using a certain stepper and the outer edge of the semiconductor chip pattern may be 1.6 mm or more. According to this method, the exposure accuracy measurement pattern can be accurately exposed with a shot different from the shot for exposing the semiconductor chip pattern.

(8) In the method of the above aspect, the exposure accuracy measurement pattern may be a pattern capable of measuring the accuracy of a pattern dimension. According to this method, it is possible to increase the number of semiconductor elements per wafer while realizing improvement in pattern dimension accuracy by feedback of exposure accuracy measurement results.

  A plurality of constituent elements of each aspect of the present invention described above are not indispensable, and some or all of the effects described in the present specification are to be solved to solve part or all of the above-described problems. In order to achieve the above, it is possible to appropriately change, delete, replace with another new component, and partially delete the limited contents of some of the plurality of components. In order to solve part or all of the above-described problems or to achieve part or all of the effects described in this specification, technical features included in one embodiment of the present invention described above. A part or all of the technical features included in the other aspects of the present invention described above may be combined to form an independent form of the present invention.

  The present invention can be implemented in various forms other than the method of forming a pattern on a wafer. For example, it can be realized in the form of a mask used for exposure, a method of exposing a pattern on a wafer, an exposure apparatus, a semiconductor chip manufacturing apparatus, a semiconductor chip manufacturing method, and the like.

  According to the present invention, with respect to the first layer and the second layer, the exposure accuracy measurement pattern is exposed and formed only in the area outside the area where the semiconductor chip pattern is exposed and formed on the wafer. Compared to the case where an exposure accuracy measurement pattern is exposed and formed in a region sandwiched between regions where each semiconductor chip pattern is exposed and formed, it can be used to expose and form a semiconductor chip pattern on a wafer. The area can be widened, and the number of semiconductor elements per wafer can be increased while improving the exposure accuracy by feedback of the exposure accuracy measurement result.

It is explanatory drawing which shows typically the structure of the exposure apparatus 10 in embodiment of this invention. It is explanatory drawing which shows schematically the structure of the mask 20 used in the exposure apparatus 10 of this embodiment. 4 is an explanatory diagram showing a detailed configuration of an exposure accuracy measurement pattern 220 in a mask 20. FIG. It is a flowchart which shows the flow of the semiconductor chip manufacturing process in this embodiment. It is a flowchart which shows the flow of an exposure process. FIG. 6 is an explanatory diagram showing a state in which a semiconductor chip pattern 210 is exposed on a wafer W. It is explanatory drawing which shows a mode that the pattern 220 for exposure accuracy measurement was exposed on the wafer W. FIG. It is explanatory drawing which shows the outline | summary of the measuring method of the positional accuracy of a single layer. It is explanatory drawing which shows the outline | summary of the measuring method of the overlay precision between several layers. It is explanatory drawing which shows the structure of the pattern 220 for exposure accuracy measurement in a modification.

A. Embodiment:
A-1. Configuration of exposure apparatus:
FIG. 1 is an explanatory view schematically showing a configuration of an exposure apparatus 10 in the embodiment of the present invention. The exposure apparatus 10 of the present embodiment reduces a pattern formed on a mask 20 (also called a reticle) and prints it on a wafer W (more specifically, on a photosensitive resist applied to the wafer W). Exposure apparatus. More specifically, the exposure apparatus 10 is an exposure apparatus called a stepper having a reduced projection exposure magnification of 1 / 2.5. As shown in FIG. 1, the exposure apparatus 10 includes an illumination optical system 110, a mask stage 130, a reduction projection optical system 140, and a wafer stage 150.

  The mask stage 130 is a table for mounting the mask 20, and the wafer stage 150 is a table for mounting the wafer W. The illumination optical system 110 has a light source that emits predetermined light (eg, g-line, i-line, KrF, ArF, etc.), converts light emitted from the light source into illumination light suitable for exposure, and a mask stage 130. Output to. The reduction projection optical system 140 has a plurality of lenses, reduces the illumination light transmitted through the mask 20, and irradiates the wafer W on the wafer stage 150. As a result, the pattern formed on the mask 20 is reduced and baked onto the wafer W.

  The wafer stage 150 is movable along a horizontal plane that is substantially orthogonal to the optical axis of the reduction projection optical system 140. By moving the wafer stage 150 along the horizontal plane, the relative position of the wafer W with respect to the mask 20 along the horizontal plane can be changed. When the exposure of one shot on the wafer W is completed, the exposure apparatus 10 moves the wafer stage 150 along the horizontal plane to change the relative position of the wafer W with respect to the mask 20 and performs the next shot exposure. Run repeatedly. Thereby, the pattern formed on the mask 20 can be exposed to each region on the wafer W.

A-2. Mask configuration:
FIG. 2 is an explanatory view schematically showing the configuration of the mask 20 used in the exposure apparatus 10 of the present embodiment. As shown in FIG. 2, a semiconductor chip pattern 210 and an exposure accuracy measurement pattern 220 are formed on the mask 20 of the present embodiment. In FIG. 2, the outer shape of the semiconductor chip pattern 210 is indicated by a simple white rectangle, and the actual pattern configuration inside the semiconductor chip pattern 210 is not shown. A region other than the semiconductor chip pattern 210 and the exposure accuracy measurement pattern 220 in the mask 20 is a shielding region 230 that shields light.

  FIG. 3 is an explanatory diagram showing a detailed configuration of the exposure accuracy measurement pattern 220 in the mask 20. FIG. 3 shows an enlarged X portion of the mask 20 shown in FIG. As shown in FIG. 3, the exposure accuracy measurement pattern 220 is a pattern in which a cross-shaped shielding region 222 is arranged in a rectangular transmission region having a size of L1 × L1. As shown in FIGS. 2 and 3, a shielding region 230 having a width Lm exists around the exposure accuracy measurement pattern 220.

  Here, the exposure apparatus 10 of the present embodiment is a stepper having a reduced projection exposure magnification of 1 / 2.5, and the minimum shot size in terms of apparatus performance is 0.25 mm × 0.25 mm. Further, in this stepper, if there is no shielding area of at least 2 mm around the pattern, the exposure accuracy of the pattern may be lowered. The outer size (L1 × L1) of the exposure accuracy measurement pattern 220 is equal to 0.25 mm × 0.25 mm, which is the minimum shot size of the exposure apparatus 10, and the width of the shielding region 230 around the exposure accuracy measurement pattern 220 When (Lm) is 2 mm, the shortest distance (L1 / 2 + Lm) between the center of the exposure accuracy measurement pattern 220 and the outer edge of the semiconductor chip pattern 210 is 2.125 mm. Therefore, the mask 20 used in this embodiment is designed and manufactured so that the shortest distance between the center of the exposure accuracy measurement pattern 220 and the outer edge of the semiconductor chip pattern 210 is 2.125 mm or more. In this way, even when the exposure accuracy measurement pattern 220 is exposed alone, a decrease in the exposure accuracy of the pattern can be suppressed.

A-3. Semiconductor chip manufacturing process:
FIG. 4 is a flowchart showing the flow of the semiconductor chip manufacturing process in the present embodiment. The semiconductor chip manufacturing process is a process for forming a plurality of semiconductor chips on the wafer W. In the following description, the formed semiconductor chip is assumed to be composed of two layers.

  First, an exposure process for the first layer of the semiconductor chip is executed (step S110). FIG. 5 is a flowchart showing the flow of exposure processing. In the exposure process, first, the mask 20 is loaded (installed) on the mask stage 130 (step S210), and the position of the mask shielding plate is set (step S220). At this time, the position of the mask shielding plate is set so that the region of the semiconductor chip pattern 210 to be exposed is exposed in the region on the mask 20 and the remaining region is shielded. Next, the wafer W is loaded (installed) on the wafer stage 150 (step S230). The loading order of the mask 20 and the shield plate position setting and the loading of the wafer W may be executed in reverse order or simultaneously.

  Next, the semiconductor chip pattern 210 is exposed on the wafer W (step S240). In the exposure of the semiconductor chip pattern 210, the illumination light emitted from the illumination optical system 110 and transmitted through the semiconductor chip pattern 210 on the mask 20 is reduced by the reduction projection optical system 140 and irradiated onto the wafer W on the wafer stage 150. This is performed by repeating the movement of the wafer W relative to the mask 20 along the horizontal plane. FIG. 6 is an explanatory view showing a state in which the semiconductor chip pattern 210 is exposed on the wafer W. FIG. Hereinafter, the semiconductor chip pattern 210 exposed (or formed) on the wafer W is also referred to as a semiconductor chip pattern 310. As shown in FIG. 6, a plurality of semiconductor chip patterns 310 are continuously exposed on the wafer W.

  When the exposure of the semiconductor chip pattern 210 is completed, the position of the mask shielding plate is changed (step S250 in FIG. 5). At this time, the position of the mask shielding plate is changed so that the area of the exposure accuracy measurement pattern 220 in the area on the mask 20 is exposed and the remaining area is shielded. At this time, the mask 20 and the wafer W are not unloaded from the mask stage 130 and the wafer stage 150.

  Next, the exposure accuracy measurement pattern 220 is exposed on the wafer W (step S260). In exposure of the exposure accuracy measurement pattern 220, the illumination light emitted from the illumination optical system 110 and transmitted through the exposure accuracy measurement pattern 220 on the mask 20 is reduced by the reduction projection optical system 140, and the wafer W on the wafer stage 150 is reduced. Is repeated by moving the wafer W relative to the mask 20 along the horizontal plane. FIG. 7 is an explanatory view showing a state in which the exposure accuracy measurement pattern 220 is exposed on the wafer W. FIG. Hereinafter, the exposure accuracy measurement pattern 220 exposed (or formed) on the wafer W is also referred to as an exposure accuracy measurement pattern 320. In the present embodiment, four exposure accuracy measurement patterns 320 (exposure accuracy measurement patterns 320a, 320b, 320c, and 320d) are exposed in a region outside the region where the semiconductor chip pattern 310 on the wafer W is exposed. . Each exposure accuracy measurement pattern 320 is not exposed in a region sandwiched between regions where each semiconductor chip pattern 310 is exposed on the wafer W. That is, the exposure accuracy measurement pattern 320 is exposed only in the area outside the area where the semiconductor chip pattern 310 is exposed on the wafer W. In the present embodiment, the four exposure accuracy measurement patterns 320 are exposed at the positions of the vertices of a rectangle (more specifically, a square) having the center of the wafer W as an intersection of diagonal lines. The exposure accuracy measurement patterns 320a and 320b have a relationship to be aligned along the X direction, and the exposure accuracy measurement patterns 320a and 320c have a relationship to be aligned along the Y direction orthogonal to the X direction. The patterns 320a and 320d have a relationship that should be located on the diagonal line of the rectangle.

  When the exposure of the exposure accuracy measurement pattern 220 is completed, the wafer W is unloaded from the wafer stage 150 and transferred to the next process apparatus (step S270).

  When the exposure process for the first layer of the semiconductor chip (step S110 in FIG. 4) is completed, the patterning process for the first layer is executed (step S120). In the patterning process, processing such as development, etching, resist removal, and film formation is performed based on the pattern exposed on the wafer W in the exposure process, and a pattern (semiconductor chip pattern 310 and exposure accuracy measurement pattern 320 is formed on the wafer W. ). The pattern formed in the first layer may be a concave pattern by etching or a convex pattern by film formation.

  When the patterning process for the first layer is completed, the measurement process for the first layer of the semiconductor chip is executed (step S130). In this measurement process, the position accuracy (pitch and orthogonality) and pattern dimension accuracy of a single layer (first layer) are measured. In the present embodiment, the measurement process is executed using an image recognition type exposure accuracy measurement apparatus that uses pattern recognition based on an image. This makes it necessary to use an image recognition type exposure accuracy measurement device that uses pattern recognition by laser scanning, in which the pattern of the pattern needs to be enlarged due to the structure of the device and the pattern shape is restricted to a linear shape. Compared to the above, the exposure accuracy measurement pattern 320 can be formed by effectively utilizing the limited area on the wafer W. However, pattern recognition by laser scanning may be used.

  FIG. 8 is an explanatory diagram showing an outline of a method for measuring the position accuracy and pattern dimension accuracy of a single layer. 8A shows the actual positions of the four exposure accuracy measurement patterns 320 (320a, 320b, 320c, 320d) formed on the wafer W, and the corresponding design positions 420 (420a, 420b). , 420c, 420d). FIG. 8B shows an enlarged exposure accuracy measurement pattern 320 (320a).

In the measurement process, the coordinates of a predetermined point (for example, a cross-shaped center point) on each exposure accuracy measurement pattern 320 as viewed from the center O of the wafer W are measured. Also, the coordinates of the design position 420 of the predetermined point of each exposure accuracy measurement pattern 320 are determined in advance. Therefore, for each exposure accuracy measurement pattern 320, X-direction deviations Xa, Xb, Xc, Xd and Y-direction deviations Ya, Yb, Yc, Yd with respect to the designed position 420 are calculated. Based on these, the positional deviation X-Pitch in the X direction, the positional deviation Y-Pitch in the Y direction, and the rotational deviation Rot in a single layer are calculated by the following equations (1) to (3), respectively. That is, as apparent from the equation (1), the X-direction positional deviation X-Pitch is each combination of the two exposure accuracy measurement patterns 320 (a combination of 320a and 320b and a combination of 320c and 320d). Is the average of the positional deviations (Xa + Xb) and (Xc + Xd) in the X direction calculated from The Y-direction positional deviation Y-Pitch is a Y-direction positional deviation calculated from each combination of the two exposure accuracy measurement patterns 320 (a combination of 320a and 320c and a combination of 320b and 320d). The average of (Ya + Yc) and (Yb + Yd). Further, the rotational deviation Rot is a rotational deviation (Xa−Xc) and (Xb−) calculated from each combination of the two exposure accuracy measurement patterns 320 (a combination of 320a and 320c and a combination of 320b and 320d). Xd) is the average.
X-Pitch = ((Xa + Xb) + (Xc + Xd)) / 2 (1)
Y-Pitch = ((Ya + Yc) + (Yb + Yd)) / 2 (2)
Rot = ((Xa−Xc) + (Xb−Xd)) / 2 (3)

  In the measurement process, the dimensions Lx and Ly of each exposure accuracy measurement pattern 320 are measured, and the pattern dimension accuracy is measured by comparison with the design dimensions.

  After the measurement process (step S130 in FIG. 4) of the first layer of the semiconductor chip is completed, an exposure process (step S140) for the second layer and a patterning process (step S150) for the second layer are executed. Since the exposure process for the second layer is executed in the same manner as the exposure process for the first layer described above, description thereof is omitted. The patterning process for the second layer is a process for forming a pattern on the wafer W by performing processing such as development, etching, resist removal, and film formation based on the pattern exposed on the wafer W in the exposure process. It is. The pattern formed on the second layer may be a concave pattern formed by etching or a convex pattern formed by film formation. Further, the pattern formed on the first layer and the pattern formed on the second layer may both be a concave pattern by etching or a convex pattern by film formation. Alternatively, the pattern formed in the first layer may be a concave pattern formed by etching, and the pattern formed in the second layer may be a convex pattern formed by film formation, and conversely, the pattern formed in the first layer May be a convex pattern formed by film formation, or the pattern formed in the second layer may be a concave pattern formed by etching.

  Next, the measurement process of the second layer of the semiconductor chip is executed (step S160). In the measurement process of the second layer, similarly to the measurement process of the first layer described above, the positional accuracy of the second layer (single layer) (specifically, the positional deviation X-Pitch in the X direction in the single layer, The positional deviation Y-Pitch in the Y direction and the rotational deviation Rot) and the pattern dimension accuracy are measured.

  Furthermore, in the measurement process of the second layer, the overlay accuracy between the first layer and the second layer is measured. FIG. 9 is an explanatory diagram showing an outline of a method for measuring overlay accuracy between a plurality of layers. FIG. 9 shows the exposure of the second layer derived from the actual position of the exposure accuracy measurement pattern 320a of the first layer formed on the wafer W and the actual position of the exposure accuracy measurement pattern 320a of the first layer. The design position 620 (620a) of the accuracy measurement pattern and the actual position of the exposure accuracy measurement pattern 520 (520a) of the second layer are shown. As for the overlay displacement amount between the first layer and the second layer, the displacement amount in the X direction is EXa shown in FIG. 9, and the displacement amount in the Y direction is EYa shown in FIG.

  When the second layer measurement process (step S160 in FIG. 4) is completed, an exposure correction process is executed (step S170). The exposure correction process is performed based on the positional deviation and rotational deviation in the single layer measured in the measurement process of the first layer and the positional deviation between the plurality of layers measured in the measurement process of the second layer. The setting of the exposure apparatus 10 is corrected so as to be reduced.

  Thereafter, it is determined whether or not the process for the next wafer W is to be executed (step S180). If it is determined that the process is to be executed, the processes after the exposure process for the first layer (step S110) described above are executed. Is done. At this time, since the setting of the exposure apparatus 10 is corrected in the exposure correction process (step S160) in the previous loop, the accuracy of the exposure process is improved as compared with the previous time. If it is determined that the process for the next wafer W is not executed, the process is terminated. In addition, after the process shown in FIG. 4, each semiconductor chip is manufactured through a predetermined process (for example, dicing, bonding, molding, etc.).

  As described above, in the semiconductor chip manufacturing process of the present embodiment, the mask 20 on which the semiconductor chip pattern 210 and the exposure accuracy measurement pattern 220 are formed is prepared. The exposure accuracy measurement pattern 220 is a pattern capable of measuring the position accuracy of a single layer formed on the wafer W and the overlay accuracy between a plurality of layers. In the exposure process using the exposure apparatus 10, a plurality of semiconductor chip patterns 210 formed on the mask 20 are exposed on the wafer W, and the exposure accuracy measurement pattern 220 formed on the mask 20 is exposed on the wafer W. The semiconductor chip pattern 210 is exposed only to the area outside the area to be exposed. Therefore, in the present embodiment, the semiconductor chip on the wafer W is compared with the case where the exposure accuracy measurement pattern 220 is exposed in a region sandwiched between regions where the semiconductor chip patterns 210 on the wafer W are exposed. The area that can be used for exposing and forming the pattern 210 can be widened, and the number of semiconductor elements per wafer W can be increased while improving the exposure accuracy by feedback of the exposure accuracy measurement result.

  In the present embodiment, the semiconductor chip pattern 210 and the exposure accuracy measurement pattern 220 are continuously exposed without performing unloading of the mask 20 and the wafer W during the exposure process. The position accuracy of the exposure accuracy measurement pattern 220 with respect to the chip pattern 210 can be kept high. As described above, the exposure accuracy measurement pattern 220 is applied only to the region outside the region on the wafer W where the semiconductor chip pattern 210 is exposed. Even if it exposes, the position accuracy of a single layer can be measured accurately.

  In the present embodiment, the exposure accuracy measurement pattern 220 is exposed and formed at the position of each vertex of a rectangle having the center of the wafer W as an intersection of diagonal lines. Therefore, the exposure accuracy measurement pattern 220 is used to form a single layer. It is possible to accurately measure the position accuracy and the overlay accuracy between a plurality of layers.

  In the present embodiment, a stepper having a reduced projection exposure magnification of 1 / 2.5 is used as the exposure apparatus 10, and the shortest distance between the center of the exposure accuracy measurement pattern 220 and the outer edge of the semiconductor chip pattern 210 is 2. Since the mask 20 having a thickness of 125 mm or more is used, the exposure accuracy measurement pattern 220 can be accurately exposed with a shot different from the shot for exposing the semiconductor chip pattern 210. As a result, the exposure accuracy measurement pattern 220 can be accurately exposed and formed only in the region outside the region where the semiconductor chip pattern 210 is exposed and formed on the wafer W.

  In the present embodiment, the exposure accuracy measurement pattern 220 is a pattern that can also measure the accuracy of pattern dimensions. Therefore, in this embodiment, the number of semiconductor elements per wafer W can be increased while realizing improvement in pattern dimension accuracy by feedback of the exposure accuracy measurement result.

B. Variations:
The present invention is not limited to the above-described embodiment, and can be implemented in various modes without departing from the gist thereof. For example, the following modifications are possible.

  The configuration of the exposure accuracy measurement pattern 220 in the above embodiment is merely an example, and various modifications can be made. FIG. 10 is an explanatory diagram showing the configuration of the exposure accuracy measurement pattern 220 in the modification. FIG. 10A shows the exposure accuracy measurement pattern 220 of the above embodiment in which a cross-shaped shielding region 222 is arranged in a rectangular transmission region. As shown in FIG. 10B, the exposure accuracy measurement pattern may be a pattern 240 in which a cross-shaped transmission region 242 is arranged in a rectangular shielding region. Further, as shown in FIG. 10C, the exposure accuracy measurement pattern may be a pattern 250 in which a rectangular shielding region 252 is arranged in a rectangular transmission region, or as shown in FIG. As described above, the pattern 260 may be a rectangular transmission region 262 arranged in a rectangular shielding region. When the pattern shown in FIG. 10C or FIG. 10D is used as the exposure accuracy measurement pattern, a predetermined point (for example, a rectangular center point) on the exposure accuracy measurement pattern is used during the measurement process. ) Is measured, and the deviation from the designed position is calculated. As the exposure accuracy measurement pattern, any known pattern other than the pattern shown in FIG. 10 can be used as long as the position (coordinates) of a certain point on the wafer W can be measured. Further, the exposure accuracy measurement pattern 220 is not necessarily a pattern that can also measure the accuracy of the pattern dimension.

  The configuration of the mask 20 in the above embodiment is merely an example, and various modifications can be made. For example, the number of exposure accuracy measurement patterns 220 formed on the mask 20 may be plural, and the number of semiconductor chip patterns 210 formed on the mask 20 may be one. Further, the exposure accuracy measurement pattern 220 formed on the mask 20 may be a positive type or a negative type, or both may be formed on the mask 20.

  Moreover, in the said embodiment, although the semiconductor chip is comprised from two layers (layer), this invention is generally applicable when a semiconductor chip is comprised from a some layer. For example, when the semiconductor chip is composed of three layers, the second layer and the third layer are formed using the semiconductor chip pattern 210 as in the overlay accuracy measurement between the first layer and the second layer described above. Measurement of overlay accuracy between layers can be performed.

  In the above embodiment, the exposure of the exposure accuracy measurement pattern 220 is performed after the exposure of the semiconductor chip pattern 210 is completed. Conversely, the exposure of the exposure accuracy measurement pattern 220 is completed after the exposure of the exposure accuracy measurement pattern 220 is completed. The exposure 210 may be executed. Alternatively, the exposure of the semiconductor chip pattern 210 and the exposure of the exposure accuracy measurement pattern 220 may be executed alternately so that the wafer stage 150 is efficiently moved, instead of being executed separately. .

  In the above embodiment, the four exposure accuracy measurement patterns 320 are exposed and formed at the positions of the respective vertices of the square with the center of the wafer W as the intersection of the diagonal lines, but these positions are strictly square. There is no need to be at the position of each vertex, and any position in the vicinity of each vertex of the square may be used. Further, the four exposure accuracy measurement patterns 320 may be exposed and formed at the positions (near the vertices) of the respective rectangles having the center of the wafer W as the intersection of the diagonal lines. Further, the number of exposure accuracy measurement patterns 320 exposed and formed is not limited to four and may be any number of two or more. It is preferable that the number of exposure accuracy measurement patterns 320 exposed and formed be four or more because the exposure accuracy can be measured with high accuracy.

  In the above embodiment, the exposure apparatus 10 is a stepper having a reduced projection exposure magnification of 1 / 2.5, but instead is a stepper having a reduced projection exposure magnification of 1/4. Also good. In this case, if the size of the exposure accuracy measurement pattern 220 exposed and formed on the wafer W is 0.04 mm × 0.04 mm, the minimum shot size is 0.16 mm × 0.16 mm. Further, in this stepper, if there is no shielding area of at least 1.5 mm around the pattern, the exposure accuracy of the pattern may be lowered. The external size (L1 × L1) of the exposure accuracy measurement pattern 220 is equal to 0.16 mm × 0.16 mm which is the minimum shot size of the exposure apparatus 10, and the width of the shielding region 230 around the exposure accuracy measurement pattern 220 is When (Lm) is 1.5 mm, the shortest distance (L1 / 2 + Lm) between the center of the exposure accuracy measurement pattern 220 and the outer edge of the semiconductor chip pattern 210 is 1.58 mm. Therefore, in this case, if the mask 20 is designed and manufactured so that the shortest distance between the center of the exposure accuracy measurement pattern 220 and the outer edge of the semiconductor chip pattern 210 is 1.58 mm or more, the exposure accuracy measurement pattern 220 is obtained. Even when the film is exposed alone, a decrease in the exposure accuracy of the pattern can be suppressed.

  Alternatively, the exposure apparatus 10 may be a stepper having a reduced projection exposure magnification of 1/5. In this case, if the size of the exposure accuracy measurement pattern 220 exposed and formed on the wafer W is 0.04 mm × 0.04 mm, the minimum shot size is 0.20 mm × 0.20 mm. Further, in this stepper, if there is no shielding area of at least 1.5 mm around the pattern, the exposure accuracy of the pattern may be lowered. The outer size (L1 × L1) of the exposure accuracy measurement pattern 220 is equal to 0.20 mm × 0.20 mm, which is the minimum shot size of the exposure apparatus 10, and the width of the shielding region 230 around the exposure accuracy measurement pattern 220 When (Lm) is 1.5 mm, the shortest distance (L1 / 2 + Lm) between the center of the exposure accuracy measurement pattern 220 and the outer edge of the semiconductor chip pattern 210 is 1.6 mm. Therefore, in this case, if the mask 20 is designed and manufactured so that the shortest distance between the center of the exposure accuracy measurement pattern 220 and the outer edge of the semiconductor chip pattern 210 is 1.6 mm or more, the exposure accuracy measurement pattern 220 is obtained. Even when the film is exposed alone, a decrease in the exposure accuracy of the pattern can be suppressed.

  The present invention is also applicable to the case where a scanner is used as the exposure apparatus.

  The present invention is not limited to the above-described embodiments and modifications, and can be realized with various configurations without departing from the spirit thereof. For example, the technical features in the embodiments and the modifications corresponding to the technical features in each embodiment described in the summary section of the invention are to solve some or all of the above-described problems, or In order to achieve part or all of the effects, replacement or combination can be performed as appropriate. Further, if the technical feature is not described as essential in the present specification, it can be deleted as appropriate.

DESCRIPTION OF SYMBOLS 10 ... Exposure apparatus 20 ... Mask 110 ... Illumination optical system 130 ... Mask stage 140 ... Reduction projection optical system 150 ... Wafer stage 210 ... Semiconductor chip pattern on mask 220 ... Pattern for measuring exposure accuracy on mask 222 ... Shielding region 230 ... Shielding area 240 ... Pattern 242 ... Transmission area 250 ... Pattern 252 ... Shielding area 260 ... Pattern 262 ... Transmission area 310 ... Semiconductor chip pattern on wafer 320 ... Pattern for measuring exposure accuracy on wafer 420 ... Designing pattern for measuring exposure precision Upper position 520 ... Exposure accuracy measurement pattern of second layer on wafer 620 ... Design position of exposure accuracy measurement pattern W ... Wafer

Claims (16)

A method for forming a pattern on a wafer, comprising:
Preparing at least one mask on which a semiconductor chip pattern and an exposure accuracy measurement pattern capable of measuring the positional accuracy of a single layer formed on the wafer and the overlay accuracy between a plurality of layers are formed When,
A plurality of the semiconductor chip patterns are exposed on the wafer by using one mask and a reduction projection type exposure apparatus, and only in an area outside the area where the semiconductor chip patterns are exposed on the wafer. An exposure step for the first layer for exposing the exposure accuracy measurement pattern;
The first layer including a plurality of the semiconductor chip patterns and the exposure accuracy measurement pattern on the wafer by performing processing based on the pattern exposed on the wafer in the exposure step for the first layer. Forming a step;
A plurality of the semiconductor chip patterns are exposed on the wafer by using one mask and a reduction projection type exposure apparatus, and only in an area outside the area where the semiconductor chip patterns are exposed on the wafer. An exposure process for the second layer for exposing the exposure accuracy measurement pattern;
The second layer including a plurality of the semiconductor chip patterns and the exposure accuracy measurement pattern on the wafer by performing processing based on the pattern exposed on the wafer in the exposure step for the second layer. Forming a method. The method of claim 1, comprising:
In the exposure process for the first layer and the exposure process for the second layer, the semiconductor chip pattern and the exposure accuracy measurement pattern are obtained without executing unloading of the mask and the wafer, respectively. And a step of exposing. A method according to claim 1 or claim 2, wherein
In the exposure process for the first layer and the exposure process for the second layer, the exposure accuracy measurement pattern is exposed at the position of each vertex of a rectangle having at least the center of the wafer as an intersection of diagonal lines. A method comprising the steps of: A method according to any one of claims 1 to 3, comprising:
The method according to claim 1, wherein the exposure accuracy measurement pattern is at least one of a cross-shaped pattern and a rectangular pattern. A method according to any one of claims 1 to 4, comprising:
The exposure process for the first layer and the exposure process for the second layer are each performed using a stepper having a reduction projection exposure magnification of 1 / 2.5 as the reduction projection exposure apparatus. ,
The method as claimed in claim 1, wherein the shortest distance between the center of the exposure accuracy measurement pattern formed on the mask and the outer edge of the semiconductor chip pattern is 2.125 mm or more. A method according to any one of claims 1 to 4, comprising:
The exposure process for the first layer and the exposure process for the second layer are each performed using a stepper having a reduction projection exposure magnification of 1/4 as the reduction projection exposure apparatus,
The shortest distance between the center of the exposure accuracy measurement pattern formed on the mask and the outer edge of the semiconductor chip pattern is 1.58 mm or more. A method according to any one of claims 1 to 4, comprising:
The exposure process for the first layer and the exposure process for the second layer are each performed using a stepper having a reduction projection exposure magnification of 1/5 as the reduction projection exposure apparatus,
The shortest distance between the center of the exposure accuracy measurement pattern formed on the mask and the outer edge of the semiconductor chip pattern is 1.6 mm or more. A method according to any one of claims 1 to 7, comprising
The exposure accuracy measuring pattern is a pattern capable of measuring the accuracy of pattern dimensions. A mask used to expose a pattern on a wafer using a stepper having a reduced projection exposure magnification of 1 / 2.5,
A semiconductor chip pattern and an exposure accuracy measurement pattern capable of measuring the position accuracy of a single layer formed on the wafer and the overlay accuracy between a plurality of layers are formed,
2. The mask according to claim 1, wherein a shortest distance between a center of the exposure accuracy measurement pattern and an outer edge of the semiconductor chip pattern is 2.125 mm or more. A mask used to expose a pattern on a wafer using a stepper with a reduced projection exposure magnification of 1/4,
A semiconductor chip pattern and an exposure accuracy measurement pattern capable of measuring the position accuracy of a single layer formed on the wafer and the overlay accuracy between a plurality of layers are formed,
The shortest distance between the center of the exposure accuracy measurement pattern and the outer edge of the semiconductor chip pattern is 1.58 mm or more. A mask used to expose a pattern on a wafer using a stepper having a reduced projection exposure magnification of 1/5,
A semiconductor chip pattern and an exposure accuracy measurement pattern capable of measuring the position accuracy of a single layer formed on the wafer and the overlay accuracy between a plurality of layers are formed,
The mask characterized in that the shortest distance between the center of the exposure accuracy measurement pattern and the outer edge of the semiconductor chip pattern is 1.6 mm or more. A mask according to any one of claims 9 to 11, comprising:
The exposure accuracy measurement pattern is a mask that is a pattern capable of measuring the accuracy of pattern dimensions. A method of exposing a pattern on a wafer,
Preparing at least one mask on which a semiconductor chip pattern and an exposure accuracy measurement pattern capable of measuring the positional accuracy of a single layer formed on the wafer and the overlay accuracy between a plurality of layers are formed When,
A plurality of the semiconductor chip patterns are exposed on the wafer by using one mask and a reduction projection type exposure apparatus, and only in an area outside the area where the semiconductor chip patterns are exposed on the wafer. Exposing a pattern for measuring exposure accuracy. 14. A method according to claim 13, comprising:
The exposure accuracy measuring pattern is a pattern capable of measuring the accuracy of pattern dimensions. An exposure apparatus,
Using a mask formed with a semiconductor chip pattern and an exposure accuracy measurement pattern capable of measuring the position accuracy of a single layer formed on the wafer and the overlay accuracy between a plurality of layers, the wafer is formed on the wafer. An exposure apparatus that exposes the plurality of semiconductor chip patterns and exposes the exposure accuracy measurement pattern only in a region outside the region on the wafer where the semiconductor chip pattern is exposed. The exposure apparatus according to claim 15, wherein
The exposure apparatus according to claim 1, wherein the exposure accuracy measurement pattern is a pattern capable of measuring the accuracy of a pattern dimension.

Images